Digitally calibrated programmable clock phase generation circuit

Abstract

An integrated circuit is described that includes a generating circuit. In operation, the generating circuit can provide an edge clock having a target phase within a clock period of an input clock, and the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit can include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is higher than a second fundamental frequency of the input clock. It is noted that the gated ring oscillator can be programmed to adjust the first fundamental frequency to a value within a predefined range. Additionally, the generating circuit can include a control circuit that determines a reference count of a number of edges of a reference clock within a reference period of the reference clock.

Description

Technical Field

[0001] The present disclosure relates to a generation circuit that uses a digital circuit and provides one or more edge clocks within the clock period of an input clock without using a delay locked loop (DLL).

Background Art

[0002] Successive approximation register (SAR) analog-to-digital converters (ADCs) often use multiple clock reference phases within a sampling clock cycle. For example, a SAR ADC can divide an input clock using a target signal and a tracking signal based on an asymmetric clock (such as a clock having a duty cycle other than 50% i.e., 50 / 50).

[0003] Typically, complex analog circuits are often used to generate edges within the period of an input clock. For example, using a DLL, multiple clock edges such as 8, 16, or 32 clock edges can be generated within the period of an input clock. Further, it is also possible to generate additional delayed edges that track an input clock edge using combinational logic (such as set / reset latches). However, even as the process node is scaled down to smaller critical dimensions, the analog circuits used in DLLs generally do not adapt well.

Summary of the Invention

Means for Solving the Problems

[0004] An integrated circuit embodiment is described. The integrated circuit includes a generation circuit. During operation, the generation circuit provides an edge clock having a target phase within the clock period of an input clock, and the generation circuit does not include a DLL.

[0005] For example, the generation circuit can include a gate ring oscillator that provides a reference clock having a first fundamental frequency higher than a second fundamental frequency of the input clock.

[0006] Note that the gate ring oscillator can be programmed to adjust the first fundamental frequency to a value within a defined range.

[0007] Furthermore, the generation circuit may include a control circuit that determines a reference count of the number of edges of the reference clock within a reference period of the reference clock. This control circuit can provide a control signal corresponding to the target phase, at least partially based on a predefined subcount of the reference count. Note that the predefined subcount may be programmable or adjustable. Furthermore, the predefined subcount can be computed by the control circuit by digitally dividing the reference count by a predefined value. Furthermore, the generation circuit can provide an edge clock having a target phase and duty cycle, at least partially based on the control signal. In some embodiments, the duty cycle may be other than 50 / 50 and can be provided by selectively turning on and off a gate ring oscillator, at least partially based on the control signal.

[0008] It should be noted that the generation circuit can simultaneously generate multiple edge clocks having different target phases during the clock period.

[0009] Furthermore, the generation circuit can be calibrated periodically.

[0010] Furthermore, the integrated circuit may include a second generator circuit, and the generator circuit and the second generator circuit can be calibrated alternately and operated in a normal operating mode.

[0011] Furthermore, the integrated circuit may include an ADC that uses an edge clock to convert a second input signal into a quantized output. In some embodiments, the ADC may include a SAR ADC.

[0012] Another embodiment provides an electronic device including a generating circuit or integrated circuit.

[0013] Another embodiment provides a system including a generating circuit or integrated circuit.

[0014] Another embodiment provides a method for providing an edge clock. This method includes at least a portion of the operations performed by a generating circuit.

[0015] This summary is provided to illustrate several exemplary embodiments in order to provide a basic understanding of some aspects of the subject matter described herein. It should be recognized that the features described above are illustrative and should not be construed as narrowing the scope or spirit of the subject matter described herein in any way. Other features, aspects, and advantages of the subject matter described herein will become apparent from the embodiments, drawings, and claims for carrying out the invention described below. [Brief explanation of the drawing]

[0016] [Figure 1] This block diagram shows an example of a gate ring oscillator according to some embodiments of the present disclosure. [Figure 2] This figure shows examples of counting the number of reference clock cycles in an input clock cycle during calibration, according to some embodiments of the present disclosure. [Figure 3] This figure shows examples of counting the number of reference clock cycles in an input clock cycle during calibration using a reference clock having a 75 / 25 duty cycle, according to some embodiments of the present disclosure. [Figure 4] The block diagram shows an example of a generation circuit according to some embodiments of the present disclosure. [Figure 5A] This block diagram shows an example of a digitally programmable ring oscillator according to some embodiments of the present disclosure. [Figure 5B]This block diagram shows an example of a digitally programmable ring oscillator according to some embodiments of the present disclosure. [Figure 5C] This block diagram shows an example of a digitally programmable ring oscillator according to some embodiments of the present disclosure. [Figure 6] This flowchart illustrates examples of methods for providing an edge clock according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0017] Note that similar reference number notations represent the corresponding part throughout all drawings. Furthermore, multiple instances of the same part are indicated by a common prefix separated from the instance number by a dash.

[0018] An integrated circuit including a generator circuit is described. During operation, the generator circuit can provide an edge clock having a target phase within the clock period of an input clock, and the generator circuit does not include a DLL. For example, the generator circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency higher than a second fundamental frequency of the input clock. Note that the gated ring oscillator can be programmed to adjust the first fundamental frequency to a value within a predefined range. Furthermore, the generator circuit may include a control circuit that determines a reference count of the number of edges of the reference clock within the reference period of the reference clock. This control circuit can provide a control signal corresponding to the target phase within the clock period of the input clock, based at least in part on a predefined subcount of the reference count. The generator circuit can then provide an edge clock having a target phase and duty cycle, based at least in part on the control signal. In some embodiments, the duty cycle may be other than 50 / 50 and can also be provided by selectively turning on and off the gated ring oscillator, based at least in part on the control signal.

[0019] According to these circuit techniques, by providing an edge clock without using a DLL, the generation circuit can be adapted to a smaller critical dimension. Furthermore, since the generation circuit does not include a DLL, the generation circuit can respond more quickly. Additionally, the generation circuit can improve the performance of an ADC, for example, with a smaller critical dimension. Therefore, the generation circuit and / or the ADC can be used in a wide variety of systems, electronic devices, and applications.

[0020] Hereinafter, embodiments of the circuit technique and the generation circuit will be described. In the disclosed circuit technique, one or more digital circuits can be used to generate an edge. For example, an all-digital calibration delay generation circuit can use only digital standard cells. Therefore, the generation circuit may not include a DLL.

[0021] In the calibration delay generation circuit, a ring oscillator (which is a ring oscillator that can be gated on or off) can be used to generate a reference clock having a fundamental frequency higher than the input clock. For example, the input clock can have a fundamental frequency of 100 MHz. FIG. 1 shows a block diagram illustrating an example of a ring oscillator 100 according to some embodiments of the present disclosure. It should be noted that the ring oscillator 100 can provide a reference oscillator (RO) clock (which may sometimes be referred to as the "reference clock") and can be gated using an enable signal.

[0022] Next, the number of clock edges with a higher frequency that pass through the reference clock period of the reference clock or occur within the reference clock period of the reference clock is counted as a reference count and can be recorded or stored (e.g., in a non-volatile memory). For example, FIG. 2 is a diagram showing an example of counting the number of reference clock cycles during an input clock cycle in calibration according to some embodiments of the present disclosure. Further, FIG. 3 shows a diagram showing an example of counting the number of reference clock cycles during an input clock cycle in calibration using a reference clock according to some embodiments of the present disclosure. Note that in FIG. 2, there are 16 clock cycles of the reference clock within one input clock cycle. As an alternative, in FIG. 3, the reference clock has a 75 / 25 duty cycle, and there are 12 clock cycles of the reference clock within one input clock cycle.

[0023] A desired phase within the reference clock period can be generated by counting the corresponding sub-count of the reference count. Note that the sub-count can be digitally adjusted to a desired ratio of the reference clock period using digital division. Further, a ring oscillator can be used to subsequently generate the reference count, create the sub-count, and then gate off during the unused portions of the reference clock cycle to save power. Thus, the ring oscillator can be used only when needed, and a generation circuit can be used to generate multiple clocks and / or duty cycles. In some embodiments, multiple clocks can be generated simultaneously.

[0024] For example, after initialization / calibration, if a 75 / 25 duty cycle is desired, the corresponding sub-count can be obtained by dividing the reference clock period by . Then, the ring oscillator can be turned on until the reference count equals this sub-count and can subsequently be turned off for the remaining reference clock cycles, i.e., the period, thus providing a 75 / 25 duty cycle.

[0025] Figure 4 shows a block diagram illustrating an example of a generation circuit 400 according to some embodiments of the present disclosure. Notably, a gate ring oscillator 410 in the generation circuit 400 can provide a reference clock (RO-CLKOUT). A counter 412 can determine a desired reference count (COUNT), which is provided to a finite state machine (FSM) 414, i.e., control logic, which can control the gate ring oscillator 410 using an enable signal, and can also control the counter 412 using reset and enable signals, at least partially based on the input clock (CLK) and a desired phase i.e., a sub-count (corresponding to a count modifier). Furthermore, the FSM 414 can generate a given edge clock (CLK_OUT) by controlling a shift register 416 (via shift, load, and enable signals) at least partially based on the reference count, and by controlling an SR latch 418 at least partially based on a reset signal provided by a first edge detection / pulse generation circuit 420. For example, the FSM414 can load counts into a shift register, and different points in the reference clock cycle can be used as triggers for the edge clock. Note that the output of the shift register 416 can be provided to a second edge detection / pulse generation circuit 422 that sets an SR latch 418. In some embodiments, a thermometer decoder 424 (meaning logic code) or unary coding can be used to facilitate faster detection of the ring oscillator edge count. Note that at least some of the components in the generation circuit 400 can be included in the control circuit 426.

[0026] In some embodiments, calibration of the generator circuit 400 may require only a single reference clock cycle or a reference clock period of the reference clock, and several more reference clock cycles to set up the state machine. Since the generator circuit 400 does not need to include a DLL "locking loop", it can reach an operating state more quickly than a DLL-based generator circuit.

[0027] It should be noted that while the generator circuit 400 can calibrate and eliminate the effects of process variations, it may still be subject to the effects of voltage and temperature variations. In some embodiments, a programmable-length ring oscillator can be used to facilitate the maintenance of the fundamental frequency of the reference clock within the nominal range throughout the process, at the expense of additional calibration cycles. With this method, the fundamental frequency cannot be too low (which may negatively affect the resolution) nor too high relative to the FSM414, i.e., the control logic. This capability allows the generator circuit 400 to be digitally programmed to correct process variations throughout the semiconductor die or integrated circuit, thus achieving better resolution. Figures 5A–5C show block diagrams illustrating examples of digitally programmable ring oscillators according to some embodiments of the present disclosure. These types of digitally programmable ring oscillators may include variable driver strength, variable load (such as a variable capacitance on the driver), and / or variable delay (length) elements. In a generating circuit 400 (Figure 4), such as a ring oscillator having a variable delay element with individual variable loads, or a ring oscillator having a variable delay element for coarse delay and a variable load for fine delay, two or more combinations of these types of ring oscillators can be used.

[0028] Alternatively or additionally, if an electronic device or system using the generator circuit 400 (Figure 4) has a downtime, periodic recalibration can be used to track voltage or temperature. However, since the required reference clock cycles may be only a few, the length of the downtime can be minimal. In some embodiments, if no downtime exists, a dual generator circuit can be used to ping-pong between calibration and normal operating modes.

[0029] In some embodiments, the 1 / 8th of the clock input cycles provided by the generation circuit 400 (Figure 4) can be used for the SAR ADC input tracking signal. Furthermore, a rising edge target signal may be required to mark the end of the SAR conversion that occurs prior to the SAR tracking signal. Thus, the disclosed calibration delay generation circuit (which may not be limited to single clock edge generation) can be used to generate the target signal and the tracking signal.

[0030] In some embodiments, there may be 16 to 30 phases that can determine the granularity (i.e., number of bits or resolution) of the digital conversion of the SAR ADC. However, the use of more ring oscillator cycles may limit the speed of the conversion circuit. Alternatively or additionally, by including more stages in the gate ring oscillator, the number of phases in the generating circuit 400 (Figure 4), as well as process, voltage, and temperature variations, can be defined.

[0031] The above considerations regarding circuit techniques illustrate the gated ring oscillator as one that is selectively turned on or turned off, but in other embodiments, the gated ring oscillator does not need to be turned off. Instead, specific edges provided by the gated ring oscillator can be used to obtain duty cycles other than, for example, 50 / 50.

[0032] Furthermore, although the above discussion uses a SAR ADC as an example, the disclosed circuit technique can be used with other types of ADCs, such as other types of intervening ADCs or pipelined ADCs. Alternatively, in other embodiments, this circuit technique can also be used in applications (including applications without an ADC) to generate clocks with different duty cycles and phases.

[0033] In this consideration, the analog-to-digital conversion performed using the edge clock provided by the generation circuit 400 (Figure 4) can be applied to a wide range of input signals. For example, the input signal may include a frame. This frame may include an image, and one or more ADCs in the generation circuit can receive analog inputs corresponding to different spatial locations or regions. Alternatively, in some embodiments, such as a scanning system, frames can be captured progressively over a fixed time interval (e.g., several milliseconds). Thus, in these embodiments, one or more ADCs can receive analog inputs corresponding to different spatial locations or regions captured at different times.

[0034] Next, embodiments of the method will be described. Figure 6 shows a flowchart illustrating an example of method 600 for providing an edge clock using a generator circuit such as generator circuit 400 (Figure 4). During operation, the generator circuit can provide an edge clock having a target phase within the clock period of the input clock (operation 610), and the generator circuit does not include a DLL. Note that the providing step (operation 610) may include the step (operation 612) of providing a reference clock having a first fundamental frequency higher than a second fundamental frequency of the input clock using a gate ring oscillator.

[0035] In some embodiments of Method 600, additional or fewer operations may be present. Furthermore, the order of operations can be changed, and / or two or more operations can be combined into a single operation.

[0036] The disclosed generating circuits and circuit techniques may be any electronic device (or may be included in any electronic device). For example, an electronic device may include a cellular phone or smartphone, a tablet computer, a laptop computer, a notebook computer, a personal or desktop computer, a netbook computer, a media player device, an ebook device, a MiFi® device, a smartwatch, a wearable computing device, a portable computing device, a consumer electronic device, an access point, a router, a switch, communication equipment, test equipment, a vehicle, a ship, an aircraft, an automobile, a truck, a bus, a motorcycle, manufacturing equipment, agricultural equipment, construction equipment, or any other type of electronic device.

[0037] While embodiments of generator circuits and / or integrated circuits including generator circuits are described using specific components, alternative embodiments may include different components and / or subsystems within the generator circuit, integrated circuit including generator circuits, and / or one or more ADCs. Thus, embodiments of generator circuits, integrated circuits including generator circuits, and / or one or more ADCs may include fewer components, additional components, different components, two or more components may be combined into a single component, a single component may be separated into two or more components, the positions of one or more components may be changed, and / or different types of components may be present.

[0038] Furthermore, the circuits and components in the generating circuit, the integrated circuit including the generating circuit, and / or one or more embodiments of the ADC can be implemented using any combination of analog and / or digital circuit mechanisms, including bipolar, PMOS and / or NMOS gates or transistors. Furthermore, the signals in these embodiments can include digital signals having generally discrete values ​​and / or analog signals having continuous values. Additionally, the components and circuits may be single-ended or differential, and the power supply may be unipolar or bipolar. It should be noted that the electrical coupling or connection in the above embodiments may be direct or indirect. In the above embodiments, a single line corresponding to a path may represent one or more single lines or paths.

[0039] As already mentioned, integrated circuits can implement some or all of the functionality of circuit techniques. These integrated circuits may include hardware and / or software mechanisms used to implement the functionality associated with the circuit techniques.

[0040] In some embodiments, the output of a process for designing an integrated circuit or part of an integrated circuit containing one or more of the circuits described herein may be a computer-readable medium such as magnetic tape or optical disk or magnetic disk. The computer-readable medium can be encoded using data structures or other information describing circuit mechanisms that can be physically exemplified as an integrated circuit or part of an integrated circuit. Various formats can be used for such encoding, but these data structures are generally created in Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), Electronic Design Interchange Format (EDIF), OpenAccess (OA), or Open Artwork System Interchange Standard (OASIS). A person skilled in the art of integrated circuit design can develop such data structures from the types of schematic diagrams and corresponding descriptions detailed above and encode the data structures onto a computer-readable medium. A person skilled in the art of integrated circuit manufacturing can use such encoded data to manufacture an integrated circuit containing one or more of the circuits described herein.

[0041] While some of the operations in the above embodiments are implemented in hardware or software, the operations in the above embodiments can typically be implemented in a wide range of configurations and architectures. Therefore, some or all of the operations in the above embodiments can be implemented in hardware, software, or both. For example, at least some of the operations in the circuit technique can be implemented by a processor or using program instructions executed in firmware within an integrated circuit.

[0042] Furthermore, while numerical examples are provided in the above discussion, different numerical values ​​will be used in other embodiments. Therefore, the numerical values ​​provided are not intended to be limiting.

[0043] The above description refers to "several embodiments." Note that "several embodiments" describe a subset of all possible embodiments, but do not necessarily specify the same subset of embodiments.

[0044] The above detailed description is intended to enable all persons skilled in the art to construct and use the disclosure, and is provided in the context of a particular application and its requirements. Furthermore, the above description of embodiments of the disclosure is provided solely for illustrative and explanatory purposes. The above description is not intended to be exhaustive or to limit the disclosure to the disclosed forms. Thus, many variations and modifications will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the disclosure. Furthermore, the consideration of the above embodiments is not intended to limit the disclosure. Thus, the disclosure is not limited to the embodiments shown, but is intended to be consistent with the broadest scope of the principles and features disclosed herein without being inconsistent. [Explanation of Symbols]

[0045] 100 Gate Ring Oscillators 400 generation circuit 410 Gate Ring Oscillator 412 counter 414 Finite State Machine (FSM) 416 Shift Register 418 SR Latch 420 First edge detection / pulse generation circuit 422 Second edge detection / pulse generation circuit 424 Thermometer Decoder 426 Control circuits Method for providing 600 edge clocks

Claims

1. It is an integrated circuit, A generation circuit configured to provide an edge clock having the same period as the input clock and having a target phase, wherein the generation circuit does not include a delay-locked loop (DLL). The generation circuit includes a gated ring oscillator configured to provide a reference clock having a first fundamental frequency higher than the second fundamental frequency of the input clock, wherein the gated ring oscillator is a ring oscillator that can be gated on or gated off. The generation circuit includes a control circuit configured to determine a reference count of the number of edges of the reference clock within a reference period of the reference clock, The control circuit is configured to provide feedback from the control circuit to the gate ring oscillator by controlling the gate on or gate off of the gate ring oscillator based on the reference count. An integrated circuit equipped with the following features.

2. The integrated circuit according to claim 1, wherein the gate ring oscillator is configured to be programmed to adjust the first fundamental frequency to a value within a defined range.

3. The integrated circuit according to claim 1, wherein the control circuit is configured to provide a control signal corresponding to the target phase based at least in part on a predefined subcount of the reference count, the subcount being a value obtained by dividing the reference period of the reference clock by a predetermined ratio.

4. The integrated circuit according to claim 3, wherein the predefined subcount is programmable or adjustable.

5. The integrated circuit according to claim 3, wherein the control circuit is configured to compute the predefined subcount by digitally dividing the reference count by a predefined value.

6. The integrated circuit according to claim 3, wherein the generating circuit is configured to provide the edge clock having the target phase and duty cycle based at least partially on the control signal.

7. The integrated circuit according to claim 6, wherein the duty cycle is other than 50 / 50, and the generating circuit is configured to provide the edge clock having the duty cycle by selectively turning on and off the gate ring oscillator based at least partially on the control signal.

8. The integrated circuit according to claim 1, wherein the generation circuit is configured to simultaneously generate a plurality of edge clocks having different target phases during the clock period.

9. The integrated circuit according to claim 1, wherein the generation circuit is periodically calibrated.

10. The integrated circuit comprises a second generation circuit, The integrated circuit according to claim 1, wherein when the generation circuit is calibrated, the second generation circuit operates in a normal operating mode, and when the second generation circuit is calibrated, the generation circuit operates in a normal operating mode, and the second generation circuit has the same configuration as the generation circuit.

11. The integrated circuit according to claim 1, further comprising an analog-to-digital converter (ADC) configured to use the edge clock to convert a second input signal into a quantized output.

12. The integrated circuit according to claim 11, wherein the ADC comprises a successive approximation register (SAR) ADC.

13. It is a system, It is an integrated circuit, A generation circuit configured to provide an edge clock having the same period as the input clock and having a target phase, wherein the generation circuit does not include a delay-locked loop (DLL). The generation circuit includes a gated ring oscillator configured to provide a reference clock having a first fundamental frequency higher than the second fundamental frequency of the input clock, wherein the gated ring oscillator is a ring oscillator that can be gated on or gated off. The generation circuit includes a control circuit configured to determine a reference count of the number of edges of the reference clock within a reference period of the reference clock, The control circuit is configured to provide feedback from the control circuit to the gate ring oscillator by controlling the gate on or gate off of the gate ring oscillator based on the reference count. Integrated circuits equipped with A system equipped with these features.

14. The system according to claim 13, wherein the integrated circuit comprises an analog-to-digital converter (ADC) configured to use the edge clock to convert a second input signal into a quantized output.

15. The system according to claim 13, wherein the gate ring oscillator is configured to be programmed to adjust the first fundamental frequency to a value within a defined range.

16. The system according to claim 13, wherein the control circuit is configured to provide a control signal corresponding to the target phase based at least in part on a predefined subcount of the reference count, the subcount being a value obtained by dividing the reference period of the reference clock by a predetermined ratio.

17. The system according to claim 16, wherein the predefined subcount is programmable or adjustable.

18. The system according to claim 16, wherein the control circuit is configured to compute the predefined subcount by digitally dividing the reference count by a predefined value.

19. The system according to claim 16, wherein the generating circuit is configured to provide the edge clock having the target phase and duty cycle based at least in part on the control signal.

20. A method for providing an edge clock, The generation circuit, The step of providing an edge clock having the same period as the input clock and having a target phase. The generating circuit does not include a delayed-locked loop (DLL), and the steps provided are: A step of providing a reference clock having a first fundamental frequency higher than a second fundamental frequency of the input clock, using a gate ring oscillator that can be gated on or gated off; A step of using a control circuit to determine a reference count of the number of edges of the reference clock within a reference period of the reference clock, The steps include providing feedback from the control circuit to the gate ring oscillator by controlling the gate on or gate off of the gate ring oscillator based on the aforementioned reference count, Methods that include...

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