Management of voltage regulator units in field-programmable arrays

Abstract

The electronic device has power rails driven by voltage regulators to provide a rail voltage. Each voltage regulator has an output interface electrically coupled to the power rail for supplying up to a predefined regulator current to the power rail. In each voltage regulator, a voltage regulator controller has an input coupled to the output interface by a feedback path and controls a drive path coupled to the output interface. A bypass unit is coupled to the drive path and the voltage regulator controller and operates in a standby mode or an operating mode. In the standby mode, the bypass unit bypasses the feedback path and the respective voltage regulator does not supply current to the power rail, while in the operating mode, the bypass unit does not bypass the feedback path and the respective voltage regulator supplies up to a predefined regulator current to the power rail.

Description

[Technical Field]

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 237485, “Management of Voltage Regulator Units in Field Programmable Arrays,” filed on 26 August 2021, which is incorporated herein by reference in its entirety.

[0002] This application also claims priority to U.S. Patent Application No. 17 / 684215, “Management of Voltage Regulator Units in Field Programmable Arrays,” filed on 1 March 2022, which is incorporated herein by reference in its entirety. [Background technology]

[0003] Electronic devices often incorporate a system-on-a-chip (SoC) on a main logic board, which includes a power management integrated circuit (PMIC), communication ports, external memory or storage devices, and other peripheral function modules. An SoC contains one or more microprocessor or central processing unit (CPU) cores, memory, input / output ports, and secondary storage devices in a single package. The PMIC is typically located adjacent to the SoC on the main logic board and provides multiple DC power supply rails to the SoC via wires formed on the main logic board. For each type of SoC, the PMIC and the wires connecting it to the SoC must be custom-designed based on at least one microprocessor or CPU core included in that type of SoC. [Overview of the project]

[0004] The various embodiments of the systems, methods, and devices in the attached claims each have several aspects, and no single aspect of them alone carries any of the attributes described herein. After considering this disclosure without limiting the scope of the attached claims, and in particular after considering the section entitled “Modes for Carrying Out the Invention,” it will be understood how aspects of the various embodiments are used to provide a semiconductor device configured to provide a semiconductor device or system having a general-purpose PMIC that can adaptively support various different types of SoCs having different microprocessors or CPU cores. The general-purpose PMIC provides multiple power rails to power one or more clusters of processors in the SoC. The semiconductor device includes multiple voltage regulators, which are located in a field-programmable array and controlled to output power to the multiple power rails of the SoC based on load information and power state policies associated with one or more clusters of processors coupled to the power rails. In some embodiments, each voltage regulator in a field-programmable array can become a redundant or standby voltage regulator by being electrically isolated from multiple power rails without being completely power-cut off when the bypass unit (of the redundant or standby voltage regulator) operates in standby mode to disable the feedback path between the output interface and input of the redundant or standby voltage regulator.

[0005] Specifically, in one embodiment, the electronic device includes a power rail configured to provide a rail voltage, and a plurality of voltage regulators electrically coupled to the power rail and configured to collectively provide the rail voltage. Each of the plurality of voltage regulators includes an output interface, one or more drive paths, a voltage regulator controller, and a bypass unit. The output interface is coupled to the power rail and configured to provide the rail voltage and supply up to a predetermined regulator current to the power rail. One or more drive paths are coupled to the output interface and configured to operate at an operating frequency. The voltage regulator controller has outputs coupled to one or more drive paths and inputs coupled to the output interface by a feedback path, and is configured to control one or more drive paths. The bypass unit is coupled to one or more drive paths and the voltage regulator controller. Each of the plurality of voltage regulators is configured to operate in either a standby mode or an operating mode according to the control settings. In standby mode, the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller, and each voltage regulator does not supply current to the power rail. In operating mode, the bypass unit is disabled from bypassing the feedback path, and each voltage regulator supplies the power rail with a maximum of the default regulator current.

[0006] In another embodiment, a method is implemented for driving a power rail in an electronic device having a plurality of voltage regulators electrically coupled to the power rail. This method includes generating rail voltage and rail current to drive the power rail. Each voltage regulator has an output interface coupled to the power rail and is configured to provide rail voltage and supply up to a default regulator current to the power rail when the voltage regulator is in operating mode. This method further includes obtaining control settings for each of the plurality of voltage regulators. The control settings for each voltage regulator determine whether the voltage regulator is a standby voltage regulator operating in standby mode or an operating voltage regulator operating in operating mode. This method further includes, for each standby voltage regulator, enabling the standby voltage regulator's bypass unit to bypass the feedback path from the output interface to the input of the voltage regulator controller so that the standby voltage regulator does not supply current to the power rail. This method further includes, for each operating voltage regulator, disabling the bypass unit from bypassing the feedback path so that the voltage regulator supplies current to the power rail.

[0007] These exemplary embodiments and implementations are described not to limit or define the disclosure, but to provide examples to aid in its understanding. Additional embodiments are described in embodiments for carrying out the invention, and further descriptions are provided therein. Other implementations and advantages may become apparent to those skilled in the art in light of the description and drawings herein. [Brief explanation of the drawing]

[0008] [Figure 1A] This is a block diagram of an exemplary system module in a typical electronic device, according to several embodiments. [Figure 1B] This is a cross-sectional view of an integrated semiconductor device according to several embodiments. [Figure 2] Block diagrams of power management systems according to several embodiments. [Figure 3] This is a simplified block diagram of an integrated semiconductor device, including multiple voltage regulators for providing one or more power rails to an SoC, according to several embodiments. [Figure 4A] This document describes a process, according to several embodiments, of providing rail current IR at rail voltage VR using a subset of voltage regulators. [Figure 4B] The following describes a process, according to several embodiments, for providing rail current IR at rail voltage VR based on one or more redundant voltage regulators. [Figure 5A] This is a block diagram of a voltage regulator, which is one of several embodiments of a voltage regulator in a field-programmable array. [Figure 5B] This is a block diagram of a voltage regulator having a bypass unit according to several embodiments. [Figure 6] This is a circuit diagram of a voltage regulator having an auxiliary loop for controlling redundancy, according to several embodiments. [Figure 7] This is a schematic diagram of an exemplary voltage regulator having a filter-based auxiliary loop, according to several embodiments. [Figure 8] This is a schematic diagram of multiple voltage regulators in a field-programmable array of voltage regulators configured to drive a power rail, according to several embodiments. [Figure 9A] This is a circuit diagram of a multiphase driver in a voltage regulator having multiple drive paths while operating in an operating mode, according to several embodiments. [Figure 9B] This is a circuit diagram of a voltage regulator having multiple bypass paths while operating in bypass mode, according to several embodiments. [Figure 9C] This is a circuit diagram of the equivalent circuit of a voltage regulator operating in both operating mode and bypass mode, according to several embodiments. [Figure 9D] This is a circuit diagram of the equivalent circuit of a voltage regulator operating in both operating mode and bypass mode, according to several embodiments. [Figure 10] This is a flowchart illustrating a method for driving the power rails of an electronic device according to several embodiments.

[0009] For a better understanding of the various implementations described, the following "Modes for Carrying Out the Invention" should be referred to in conjunction with the following drawings, where similar reference numbers indicate corresponding parts throughout the drawings. [Modes for carrying out the invention]

[0010] Next, we will refer in detail to specific embodiments, examples of which are shown in the accompanying drawings. The following detailed description includes numerous non-limiting specific details to aid in understanding the subject matter presented herein. However, it will be apparent to those skilled in the art that various alternative forms may be used without departing from the claims, and that the subject matter may be carried out without these specific details.

[0011] Figure 1 is a block diagram of an exemplary system module 100 in a typical electronic device according to several embodiments. The system module 100 in this electronic device includes at least a system-on-a-chip (SoC) 102, a memory module 104 for storing programs, instructions, and data, an input / output (I / O) controller 106, one or more communication interfaces such as a network interface 108, and one or more communication buses 130 for interconnecting these components. In some embodiments, the I / O controller 106 enables the SoC 102 to communicate with I / O devices (e.g., keyboards, mice, or touchscreens) via a universal serial bus interface. In some embodiments, the network interface 108 includes one or more interfaces for Wi-Fi®, Ethernet®, and Bluetooth® networks, respectively, enabling the electronic device to exchange data with external sources, e.g., servers or other electronic devices. In some embodiments, the communication bus 130 includes circuitry (sometimes called a chipset) that interconnects and controls communication between the various system components included in the system module 100.

[0012] In some embodiments, the memory module 104 includes high-speed random-access memory, such as DRAM, SRAM, DDR RAM, or other random-access solid-state memory devices. In some embodiments, the memory module 104 includes non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. In some embodiments, the memory module 104, or alternatively the non-volatile memory device within the memory module 104, includes a non-transient computer-readable storage medium. In some embodiments, a memory slot is reserved on the system module 100 to receive the memory module 104. Once inserted into the memory slot, the memory module 104 is integrated into the system module 100.

[0013] In some embodiments, the system module 100 further includes one or more components selected from the following: • A memory controller 110 controls communication between the SoC 102 and memory components including the memory module 104 within the electronic device. • Applying an integrated circuit assembly for storing data in an electronic device, in many embodiments, a solid-state drive (SSD) 112 based on a NAND or NOR memory configuration, • A hard drive 114 is a conventional data storage device used to store and retrieve digital information based on an electromechanical magnetic disk. • Power supply connector 116 including one or more DC power supply interfaces, each configured to receive a separate direct current (DC) supply voltage. A power management integrated circuit (PMIC) 118 adjusts a separate DC supply voltage received via the DC power supply interface to another desired internal supply voltage (also called rail voltage), e.g., 5V, 3.3V, or 1.8V, as required by various components or circuits within the electronic device (e.g., the processor core in SoC102). A graphics module 120 that generates a feed of output images to one or more display devices according to those desired image / video formats, and • A sound module 122 that facilitates the input and output of audio signals between electronic devices under the control of a computer program.

[0014] Furthermore, it should be noted that the communication bus 130 interconnects and controls communication between various system components, including components 110 to 122.

[0015] Furthermore, those skilled in the art know that when new data storage techniques are developed for storing information in non-temporary computer-readable storage media in the memory module 104 and the SSD 112, other non-temporary computer-readable storage media may be used. These new non-temporary computer-readable storage media include, but are not limited to, those manufactured from biological materials, nanowires, carbon nanotubes and individual molecules, although the respective data storage techniques are currently under development and not yet commercialized.

[0016] In some embodiments, the SoC102 is implemented in a semiconductor package containing one or more integrated circuits, each integrated circuit incorporating a subset of one or more microprocessors or CPU cores, memory, input / output ports, and secondary storage devices on a single substrate. The PMIC118 is also implemented in a semiconductor package containing one or more integrated circuits, each formed on a single substrate. The SoC102 is configured to receive one or more internal supply voltages (also called rail voltages) provided by the PMIC118 via one or more power rails. In some embodiments, both the SoC102 and the PMIC118 are mounted on a main logic board, for example, on two separate areas of the main logic board, and are electrically coupled to each other via conductors formed in the main logic board. This arrangement introduces parasitic effects and electrical noise that can impair the performance of the SoC, for example, by causing voltage drops in the internal supply voltages. Alternatively, according to various embodiments described with reference to Figure 1B, the semiconductor dies of the SoC102 and PMIC118 are packaged vertically within an integrated semiconductor device such that they are electrically coupled to each other via electrical connections that are not formed on the main logic board. Such vertical arrangement of the semiconductor dies of the SoC102 and PMIC118 can reduce the length of the electrical connections between the SoC102 and PMIC118, thereby avoiding performance degradation caused by wiring conductors on the main logic board.

[0017] In some embodiments, a general-purpose PMIC 118 is configured to drive different types of SoC 102s for different types of electronic devices. Whether the PMIC 118 and SoC 102 are positioned side-by-side or vertically, the PMIC 118 occupies the same footprint with respect to the main circuit board, while the SoC 102 may have a separate footprint based on the electronic modules it incorporates. The PMIC 118 includes a plurality of voltage regulator units (e.g., regulator 320 in Figure 3) arranged in a field-programmable array (e.g., array 330 in Figure 3). The plurality of voltage regulator units may be identical to each other or include two or more alternative types of voltage regulator units. For a particular electronic device, the control settings are determined based on the rail voltage and rail current of the power rails required to power the SOC 102 and, if present, other electronic modules. For each of these power rails, a corresponding control setting is used to select a subset of voltage regulator units in the field-programmable array of the PMIC118, and the selected voltage regulator units collectively provide rail current at rail voltage to each power rail. Thus, the PMIC118 is reconfigured by these control settings to provide rail voltage and current to the power rails of the SoC102, and each voltage regulator unit in the multiple configurable voltage regulators within the PMIC118 is either redundant or selected by one of the control settings to drive one of the power rails.

[0018] Figure 1B is a cross-sectional view of an integrated semiconductor device 180 in which an SoC 102 and a PMIC 118 are arranged vertically, according to several embodiments. The semiconductor device 180 incorporates at least one SoC die 102 and at least one PMIC die 118 within a semiconductor package and includes at least a package substrate 124 having a first surface 124A and a second surface 124B opposite the first surface 124A. The SoC die 102 is positioned on the first surface 124A of the package substrate 124, and the PMIC die 118 is mechanically coupled to the second surface 124B of the package substrate 124.

[0019] The package substrate 124 further includes a plurality of first via interconnects 126 that pass through the body of the package substrate 124 and are exposed on both the first surface 124A and the second surface 124B. The PMIC die 118 is electrically coupled to the SoC die 102 via the plurality of first via interconnects 126 of the package substrate 124. In particular, the PMIC die 118 provides a plurality of rail voltages V to the SoC die 102 via a plurality of power rails. R The PMIC die 118 includes a plurality of DC connections 128 configured to output a certain value. When the PMIC die 118 is mounted on the second surface 124B of the package substrate 124, the DC connections 128 are electrically coupled to a plurality of first via interconnects 126 of the package substrate 124. In some embodiments, the SoC die 102 includes a plurality of power connections 132 configured to receive a plurality of rail voltages. When the SoC die 102 is mounted on the first surface 124A of the package substrate 124, the power connections 132 are electrically coupled to a plurality of first via interconnects 126 of the package substrate 124. Thus, the PMIC die 118 is configured to provide DC power (i.e., rail voltage and rail current of the power rail 206 in Figure 2) to the SoC die 102 via the DC connections 128 of the PMIC die 118, the power connections 132 of the SoC die 102, and the first via interconnects 126 of the package substrate 124. Furthermore, by using the extremely low impedance DC connection 128, the quality of the DC power supplied to the SoC die 102 by the PMIC die 118 is significantly improved compared to a system where the PMIC die 118 and the SoC die 102 are packaged separately and located next to each other on the main circuit board.

[0020] In some embodiments, the power management interface 208 on the PMIC die 118 is controlled by the master power management interface on the SoC die 102 and is configured to receive digital power control signals from the SoC die 102 (carrying load information 314 in Figure 3). A subset of the first via interconnect 126 is configured to transfer digital power control signals from the SoC die 102 to the PMIC die 118.

[0021] The SoC die 102 has a first footprint on the package substrate 124, and the PMIC 118 has a second footprint on the package substrate 124. In some embodiments, the first and second footprints overlap at least partially for the purpose of directly coupling the DC connection 128 of the PMIC die 118 and the power connection 132 of the SoC die 102 using a plurality of first via interconnects 126. In some situations, the first footprint of the SoC die 102 is larger than the second footprint of the PMIC die 118 and completely surrounds it. Alternatively, in some situations, the first footprint of the SoC die 102 is offset from the second footprint of the PMIC die 118, but at least partially overlaps with the second footprint of the PMIC die 118. The DC connection 128 of the PMIC die 118, the power connection 132 of the SoC die 102, and the first via interconnection 126 of the package substrate 124 are aligned and surrounded within the overlapping area of ​​the first and second footprints.

[0022] In addition, the PMIC die 118 includes a plurality of thin-film inductors 150 corresponding to a plurality of DC connections 128. The plurality of thin-film inductors 150 are located adjacent to or facing the second surface 124B of the package substrate 124, for example, on the upper surface of the PMIC die 118 facing the second surface 124B of the package substrate 124. In other words, the plurality of thin-film inductors 150 are arranged between the upper surface of the PMIC die 118 and the second surface 124B of the package substrate 124. In some embodiments, the PMIC die 118 is mechanically bonded to the package substrate 124, for example, via an adhesive. The height of the plurality of thin-film inductors 150 is less than a predetermined threshold height (e.g., 1 mm, 100 μm) to maintain the robustness of the mechanical bond between the PMIC die 118 and the package substrate 124. That said, the vertical arrangement of the semiconductor dies of the SoC102 and PMIC118 is facilitated in part by the integration of a thin-film inductor 150 within the limited space between the dies of the SoC102 and PMIC118. The thin-film inductor is formed and integrated on the substrate of the PMIC118 so that it can fit into the limited space between the semiconductor dies of the SoC102 and PMIC118, and has an inductor height controlled to be smaller than the height of the limited space. When the thin-film inductor is formed on the substrate of the PMIC118, the thin-film inductor can be directly connected to an internal or output node of the PMIC118, and the main logic board wires are not used to connect the thin-film inductor to an internal or output node of the PMIC118.

[0023] In some embodiments, the integrated semiconductor device 180 further includes a cover 134 coupled to a first surface 124A of a package substrate 124. The cover 134 is configured to conceal at least a portion of the SoC die 102 and the first surface 124A of the package substrate 124, thereby protecting the SoC die 102 and at least a portion of the first surface 124A. Furthermore, in some embodiments, the cover 134 is made of a conductive material and is configured to be grounded to provide electrostatic shielding to the SoC die 102 and any other circuits on the first surface 124A if the cover 134 completely conceals it, or to provide electrostatic shielding to the portion of the first surface 124A concealed by the cover 134 if the first surface 124A is only partially concealed by the cover 134. In some situations, the cover 134 is made of a thermally conductive material configured to dissipate heat generated by the SoC die 102. In some embodiments, a heat diffuser 136, or a layer of heat diffusers, is used to bond the SoC die 102 to the inner surface of the cover 134 in order to uniformly diffuse the heat generated by the SoC die 102 from the SoC die 102 to the cover 134.

[0024] In some embodiments, the semiconductor device 180 further includes a socket substrate 138. The socket substrate 138 has a third surface 138A facing a second surface 124B of the package substrate 124. The package substrate 124 is electrically coupled to the socket substrate 138 via a plurality of electrical connectors 140. In particular, in some embodiments, the second surface 124B of the package substrate 124 includes a first area (e.g., a central area) to which the PMIC die 118 is mechanically coupled, and a second area (e.g., a peripheral area) to which the plurality of electrical connectors 140 are located. In one example, the second area is adjacent to or surrounds the first area. Note that under some circumstances, the semiconductor device 180 is provided together with the socket substrate 138. However, under some circumstances, the socket substrate 138 is fixed on the circuit board of the electronic device in Figure 1A and is not part of the integrated semiconductor device 180. Rather, the semiconductor device 180 is a replaceable component provided to propose the functionality of the combination of the PMIC die 118 and the SoC die 102.

[0025] In some embodiments, the third surface 138A of the socket substrate 138 is substantially flat, and the PMIC die 118 is positioned between the second surface 124B of the package substrate 124 and the third surface 138A of the socket substrate 138. The height of the multiple thin-film inductors 150 is less than a predetermined threshold height (e.g., 1 mm, 100 μm) determined by the difference between the length of the electrical connector 140 and the thickness of the PMIC die 118. Alternatively, in some embodiments, the socket substrate 138 includes a recessed portion 142, sometimes called a cavity, configured to receive the PMIC die 118 when it is mechanically and electrically coupled to the second surface 124B of the package substrate 124. The depth of the recessed portion 142 is less than the thickness of the socket substrate 138. In some situations, the PMIC die 118 is suspended within the recessed portion 142, i.e., separated from the bottom surface of the recessed portion 142 by a gap. Alternatively, in some situations, the PMIC die 118 contacts the bottom surface of the concave portion 142 either directly or via an intermediate layer (e.g., an adhesive layer, a heat diffuser layer, or a layer that is both an adhesive and a heat diffuser).

[0026] In some embodiments not shown in Figure 1B, the depth of the recessed portion 142 is equal to the thickness of the socket substrate 138, and the recessed portion 142 is an opening or cutoff in the socket substrate 138. When the socket substrate 138 is mounted on a circuit board (e.g., a main logic board), the PMIC die 118 is suspended within the recessed portion 142 (also called the opening or cutoff) and is at least partially surrounded by the package substrate 124, the socket substrate 138, and the circuit board.

[0027] In some embodiments, the power connection 132 of the SoC die 102 is not directly coupled to the first via interconnect 126 of the package substrate 124. Rather, a first interposer 144 is located between the SoC die 102 and the first surface 124A of the package substrate 124. The first interposer 144 further includes a plurality of second via interconnects 146 configured to at least electrically couple the power connection 132 of the SoC die 102 and the first via interconnect 126 of the package substrate 124. Similarly, in some embodiments, the DC connection 128 of the PMIC die 118 is not directly coupled to the first via interconnect 126 of the package substrate 124. Rather, a second interposer 148 is located between the PMIC die 118 and the second surface 124B of the package substrate 124. The second interposer 148 further includes a plurality of third via interconnects 152 configured to at least electrically couple the DC connection 128 of the PMIC die 118 and the first via interconnect 126 of the package substrate 124. Thus, the power rail 206 of the SoC 102 includes at least the power connection 132 of the SoC die 102, the first via interconnect 126 of the package substrate 124, and the DC connection 128 of the PMIC die 118, and in some circumstances further includes the second via interconnect 146 of the first interposer 144 and / or the third via interconnect 152 of the second interposer 148.

[0028] In some embodiments, the semiconductor device 180 further includes one or more discrete electronic modules 160 (e.g., resistors, capacitors, inductors, transistors, and logic chips). The discrete electronic modules 160 may be electrically coupled in the input / output interface circuit of the SoC die 102 to control the input / output coupling of the SoC die 102. Optionally, a subset of the discrete electronic modules 160 (e.g., component 160A) is located on a first surface 124A of the package substrate 124. Each component 160A may be contained within the cover 134 or located outside the cover 134. Optionally, a subset of the discrete electronic modules 160 (e.g., component 160B) is mechanically coupled to a second surface 124B of the package substrate 124. If each component 160B has a low profile (for example, thinner than the length of the electrical connector 140), the component 160B can fit into the gap between the second surface 124B of the package substrate 124 and the third surface 138A of the socket substrate 138. Otherwise, if the component 160B does not have a low profile (for example, thicker than the length of the electrical connector 140), each component 160B may be received by the recessed portion 142 of the socket substrate 138 and positioned adjacent to the PMIC die 118.

[0029] The SoC die 102 and PMIC die 118 are arranged vertically within the semiconductor device 180. The power connections 132 of the SoC die 102 and the DC connections 128 of the PMIC die 118 are aligned and positioned close to each other, thereby reducing parasitic resistance and capacitance coupled to each power rail 206 that provides rail voltage to the SoC die 102. Note that in some implementation configurations, multiple PMIC dies 118 may be arranged in a recessed portion 142 of a socket substrate 138 and electrically coupled to one or more SoC dies 102 located on the first surface 124A of a package substrate 124. For example, two PMIC dies 118 are arranged in a recessed portion 142 of a socket substrate 138 to collectively power four SoC dies 102. One of the SoC dies 102 optionally corresponds to a microprocessor or CPU core, or a cluster of microprocessor or CPU cores.

[0030] In addition, in some embodiments, the PMIC die 118 includes a field-programmable array of voltage regulators configurable by control settings to drive different types of SoC dies 102. In some situations, multiple instances of the same PMIC die 118, package substrate 124, and socket substrate 138 are used to support different types of SoC dies 102. A recessed portion 142 formed on the socket substrate 138 has a fixed size to adapt to the same PMIC die 118, and a first via interconnect 126 passing through the body of the package substrate 124 has a fixed position. Alternatively, in some situations, the footprint sizes of the package substrate 124 and socket substrate 138 differ for different types of SoC dies 102, but the same PMIC die 118 allows the recessed portion 142 and the first via interconnect 126 of the package substrate 124 to remain constant, thereby avoiding the need for custom design of the PMIC die 118 and the entire package for each individual type of SoC die 102. Therefore, the application of a field-programmable array of voltage regulators in the PMIC die 118 simplifies the assembly process of the semiconductor device 180 and improves cost efficiency.

[0031] Figure 2 is a block diagram of a power management system 200 configured to provide power to one or more power rails 206 of an SoC such as SoC102, according to several embodiments. The power management system 200 receives one or more input DC supply voltages 202 and digital power control signals 204, converts the input DC supply voltages 202 into one or more rail voltages, which are output by one or more power rails 206A, 206B~206N and supplied to SoC102. The power management system 200 includes a power management interface 208, one or more DC-DC converters 210 (e.g., DC-DC converters 210A, 210B...210N), and one or more output filters 212 (e.g., output filters 212A, 212B,...212N). The power management interface 208 receives the input DC supply voltages 202 and digital power control signals 204. In some embodiments, the power management interface 208 is controlled by a master power management interface of a central processor unit (e.g., on an SoC 102) and is configured to receive a digital power control signal 204 from the SoC 102. The DC-DC converter 210 is coupled to the power management interface 208 and the power rail 206, and one or more rail voltages V are provided on the power rail 206 from the input DC supply voltage(s) 202. R The output is controlled by a digital power control signal 204 to generate the output. The output filter 212 is coupled to the DC-DC converter 210 and configured to reduce noise in the power rail 206 supplied to the SoC 102 and maintain its stability. In some embodiments, the output filter (e.g., any of 212A, 212B, ..., 212N) includes one or more respective output resistors 214 and one or more output capacitors 216 (e.g., 216A, 216B, ..., 216N). In some embodiments, the output filter (e.g., 212B) includes an inductor 150 and one or more output capacitors (e.g., capacitor 216B).

[0032] In some embodiments, the power management system 200 is mounted on one or more PMIC dies 118, each PMIC die 118 having a single substrate. In some embodiments, the power management interface 208 and the DC-DC converter 210 are formed on the substrate of a single PMIC die 118 and belong to the same integrated circuit fabricated on the substrate of the PMIC die 118, for example. Conversely, in some embodiments, the power management interface 208 and the DC-DC converter 210 are formed on multiple substrates of multiple PMIC dies 118. In some embodiments, in addition to the power management interface 208 and the DC-DC converter 210, each PMIC die 118 further includes a plurality of thin-film inductors fabricated or mounted on the upper surface of the substrate of the PMIC die 118. Optionally, the plurality of thin-film inductors include one or more inductors 150 used in the output filter 212. Optionally, the plurality of thin-film inductors include one or more inductors 150' used in the DC-DC converter 210A. In some embodiments, in addition to the power management interface 208, the converter 210, and the inductors 150 / 150', the PMIC die 118 further incorporates a subset of the output resistors 214 and capacitors 216 of the output filter 212. Alternatively, in some embodiments, the PMIC 118 and SoC 102 are arranged vertically within an integrated semiconductor device 180, and a subset or all of the capacitive and resistive components of the output filter 212 are formed using individual electronic modules 160 located on any surface of the package substrate 124.

[0033] In some embodiments, the power management system 200 includes a field-programmable array of voltage regulator units, an output filter 212, one or more output resistors 214, one or more output capacitors 216, and one or more inductors 150. The digital power control signal 204 is determined, for example, by the SoC 102, based on the target power capability (e.g., rail voltage and rail current) required for the power rail 206. In other words, the digital power control signal 204 is determined by the load information and power state policy of the power rail 206. The power state policy requires that the power rail meets at least one performance criterion (e.g., output ripple voltage, power supply rejection rate, load transient response, output noise, and / or power efficiency). For example, each power rail 206 is configured to power a CPU cluster, cache, or functional block of the SoC 102, each having a power demand used by the SoC 102 to indicate the target power capability of each power rail 206 controlled by the corresponding power state policy. In one embodiment, a power state policy for a particular power rail 206 requires that the corresponding rail current of that particular power rail 206 be controlled to maximize one of the power conversion efficiency and rail voltage response speed. According to the control signal 204, the voltage regulator unit in the field programmable array is divided and configured to form one or more DC-DC converters 210, e.g., DC-DC converters 210A, 210B, ..., 210N, to drive the power rails 206 according to the load information and power state policy associated with the power rails 206. For each DC-DC converter 210, additional components 212-216 and 150 may also be selected and controlled by their respective subsets of the control signal 204 to enable desirable noise performance for the corresponding power rail 206.

[0034] FIG. 3 is a simplified block diagram of an integrated semiconductor device 300 that includes a plurality of voltage regulators 320 for providing one or more power rails 206 to the SoC 102 according to some embodiments. The plurality of voltage regulators 320 are disposed within a field programmable array 330. The power array controller 302 includes a plurality of electronic modules (e.g., one or more of a SoC interface, an oscillator, a microcontroller, an LDO, and a reference generator) and is coupled to the plurality of voltage regulators 320. The power array controller 302 is configured to control the plurality of voltage regulators 320 to output power to the plurality of power rails 206. Each power rail 206 provides a respective rail current I R at a respective rail voltage V R . In the embodiment shown in FIG. 3, the field programmable array 330 of voltage regulators 320 powers four power rails 206-1, 206-2, 206-3, and 206-4, and provides rail currents I R1 , I R2 , I R3 , and I R4 at respective rail voltages V R1 , V R2 , V R3 , and V R4 respectively. For each of the plurality of power rails 206, the power array controller 302 determines a respective rail current I R associated with each respective power rail 206, selects a subset of the voltage regulators 320 according to at least the respective rail current I R , and enables the subset of voltage regulators 320 to generate a respective rail voltage V R to collectively provide the respective rail current I R . Thus, the power array controller 302 and the voltage regulators 320 implement a power management system for the SOC 102 on one or more PMIC dies 118.

[0035] The SoC102 includes a plurality of electronic components, such as one or more microprocessors or CPU cores 304, memory 306, communication module 308, timing source, peripherals (e.g., clock, counter timer), analog interface, input / output ports, and / or secondary storage. The microprocessors or CPU cores 304 are optionally arranged in a cluster. The SoC102 is implemented by one or more integrated circuits (e.g., SoC dies 102). Each SoC die 102 incorporates a subset of the electronic modules of the SoC102 on its respective semiconductor substrate. In one embodiment, the SoC102 has a main SoC die including one or more processor cores 304 and a companion SoC die including memory 306, analog interface, or other components separate from the processor cores 304.

[0036] For each power rail 206, the respective rail voltage V R This is determined by the operation of each subset of the electronic components of the SoC102, and the respective rail current I R This is determined by the load information and power state policy associated with each subset of the electronic components of the SoC102. The power array controller 302 controls at least each rail voltage V R Based on this, the control value 310 is determined, and at least each rail current I R Based on this, a selected subset of voltage regulators 320 is selected, and the determined control value 310 is provided to the selected subset of voltage regulators 320 corresponding to each power rail 206, thereby ensuring that the subset of voltage regulators 320 controls each rail voltage V R Generates the respective rail current I R It is configured to enable the collective provision of the following. Furthermore, in some embodiments, the power array controller 302 provides each rail voltage V R Generates the respective rail current I RTo provide this collectively, the power array controller 302 provides an operation enable signal 312 to a selected subset of voltage regulators corresponding to each power rail 206. Thus, the power array controller 302 provides each voltage regulator 320 with a control setting including a control value 310 and an operation enable signal 312, thereby controlling the rail voltage V R and rail current I R The system is configured to select a separate subset of voltage regulators 320 to provide power to each power rail 206.

[0037] In some embodiments, the power array controller 302 includes one or more processors and a memory that stores instructions, which, when executed by one or more processors, cause the processors to control a voltage regulator 320 to output power to a plurality of power rails 206. Optionally, a VRU grouping configuration is stored in the memory of the power array controller 302, the off-chip non-volatile memory (NVM) of the system module 100, or the basic input / output system (BIOS) of the system module 100 to associate a control value 310 and an enable signal 312 for each of the power rails 206 with a subset of the voltage regulators. In some situations, the VRU grouping configuration is loaded and implemented by the power array controller 302 when the PMIC 118 is powered on.

[0038] Each of the multiple power rails 206 is configured to power a subset of the electronic modules of the SOC 102, which constitutes the load for each power rail 206. For each power rail 206, the power array controller 302 determines load information 314 corresponding to the expected or actual load for each power rail 206, and according to the load information 314 and the power state policy, determines the respective rail current I associated with each power rail. RThe power state policy is configured to determine the power state policy, which includes at least one performance criterion (e.g., output ripple voltage, power supply rejection rate, load transient response, output noise, and / or power efficiency), and the device 300 is configured to operate according to the power state policy for each power rail. In some embodiments, a power rail 206 is coupled to a main SoC die having one or more processor cores 304 arranged in a cluster, and the load information 314 for this power rail 206 corresponds to processor load information for one or more clusters of processors 304 on the main SoC die 102 coupled to this power rail 206. Examples of processor load information include the total number and types of operations performed by one or more clusters of processors 304. Conversely, in some embodiments, one of the power rails 206 is coupled to a companion SoC die having a memory 306 and is configured to power write and read operations on the memory 306. The load information for that power rail 206 corresponds to memory load information for memory access to the memory 306 on the companion SoC die. Examples of memory load information include the memory type of memory 306, the frequency of memory write operations, and the frequency of memory read operations. Therefore, the rail current I of each power rail 206 R This is adaptively determined based on the load information 314 (e.g., processor or memory load information) of each power rail 206. Furthermore, in some embodiments, given the load information of each power rail 206, the power state policy of each power rail 206 is determined by the corresponding rail current I of the power rail 206. R It is required that the power rail be controlled to maximize either the power conversion efficiency or the rail voltage response speed. In one embodiment, according to a power state policy, the power rail 206 provides a maximum rail current at startup of the power rail 206 so that the rail voltage reaches the rail voltage VR within the transient load response time.

[0039] In addition, in some embodiments, each of the multiple voltage regulators 320 in the field-programmable array 330 corresponds to a voltage regulator type selected from a plurality of default voltage regulator types. For each power rail 206, a selected subset of voltage regulators 320 corresponds to at least one performance criterion (e.g., maximum rail current I RLM , maximum regulator current I RGM The voltage regulator type is determined based on one or more of the following: output ripple voltage, power supply rejection rate, load transient response, output noise, and power efficiency.

[0040] Referring to Figure 3, after each subset of voltage regulators 320 is selected for each power rail 206, each voltage regulator 320 within the subset is uniquely associated with each power rail 206 at a given time. For example, in a first time, power rails 206-1, 206-2, 206-3, and 206-4 are associated with four distinct sets of voltage regulators 320, as shown in Figure 3. Each voltage regulator 320 in the first row is uniquely associated with power rail 206-1 in the first time and cannot be associated with any of power rails 206-2, 206-3, and 206-4 in the same first time. However, in a second time, separate from the first time, the voltage regulators 320 in the field-programmable array 330 can be reconfigured to power a distinct power rail 206. Each voltage regulator 320 in the first row is uniquely associated with power rail 206-1 in a first time, but can be reconfigured to drive any of power rails 206-2, 206-3, and 206-4 in a second time. More generally, in some embodiments, at least several voltage regulators 320 in the field-programmable array 330 can be configured to provide power to selected power rails 206 of multiple power rails at any one time. Thus, in some embodiments, a subset of voltage regulators 320 are permanently assigned to some power rails 206, while others are configurable with respect to which power rails 206 they are connected to. In some other embodiments, all of the voltage regulators 320 in the field-programmable array 330 are configurable with respect to which power rails 206 they are connected to.

[0041] Each voltage regulator 320 has at least two modes, including an operating mode and a standby mode. In the operating mode, each voltage regulator 320 controls the rail voltage V R Each voltage regulator 320 outputs this to one of the multiple power rails 206 to which it is associated, and the maximum default regulator current I RThis supplies current to the associated power rail 206. Conversely, standby mode is applied when each voltage regulator 320 (e.g., 320RA to 320RD) is not assigned to drive any power rail 206, and when each voltage regulator 320 (e.g., 320E) is temporarily disabled from supplying current to the power rail 206 to which each voltage regulator 320 is assigned. Specifically, in the embodiment shown in Figure 3, the voltage regulators 320RA to 320RD in the field-programmable array 330 are redundant and not associated with any power rail 206. Such voltage regulators 320RA to 320RD operate in standby mode and remain in standby mode until they are reassigned to drive one or more power rails 206. With respect to each voltage regulator 320 assigned to each power rail 206, each voltage regulator 320 may be disabled from supplying current to its respective power rail 206 during a first duty cycle corresponding to the standby mode. Unlike the first duty cycle, each voltage regulator 320 may be activated to supply power and current to its respective power rail 206 during a second duty cycle corresponding to the operating mode. For example, a voltage regulator 320E associated with power rail 206-1 can operate on alternating duty cycles corresponding to a standby mode in which the voltage regulator 320 does not supply current to power rail 206-1 and an operating mode in which the voltage regulator 320 is enabled to supply current to power rail 206-1.

[0042] More specifically, in some embodiments, each voltage regulator 320 (e.g., voltage regulators 320RA to 320RD and 320E) includes a bypass unit configured to provide a dummy load component. In standby mode, the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator 320 (e.g., under the control of the operation enable signal 312), thereby preventing each voltage regulator 320 from passing any rail current I through its output interface.R It also disables contributions to the feedback path. In operating mode, the bypass unit is disabled to bypass the feedback path, and the voltage regulator is disabled so that the output interface is the rail voltage V R and rail current I R It operates in a feedback path to allow a portion of it to be output to the corresponding power rail 206. Further details regarding the bypass unit are provided below with reference to Figures 5B and 6-10.

[0043] In some embodiments, the semiconductor device 300 further includes one or more direct current (DC) power supply interfaces 316. Each DC power supply interface 316 has a separate DC supply voltage V IN It is configured to receive 202. Each voltage regulator 320 is coupled to one or more subsets of DC power supply interfaces 316, and the corresponding DC supply voltage V IN Powered by 202 and with the corresponding DC supply voltage V IN From 202, each rail voltage V R It is configured to generate.

[0044] Figure 4A shows a subset of voltage regulators 320 used to apply rail voltage V according to several embodiments. R In the rail current I R Figure 4B shows a process 400 that provides rail voltage V based on one or more redundant voltage regulators 320 according to several embodiments. R In the rail current I R Process 450 is shown, which provides rail current I. R 0 and maximum rail current I RLM It can vary between the following. Each of the subsets of voltage regulators 320 has a maximum regulator current I RGM It is configured to provide a regulator current up to a certain value. A subset of voltage regulators 320 are configured to provide a maximum rail current I RLM and maximum regulator current I RGM It has a first number of voltage regulators corresponding to the ratio with. For example, in Figure 3, the first power rail 206-1 has a maximum rail current IRLM Each voltage regulator 320 is required to output a maximum regulator current I RGM Each regulator current up to can be provided. Maximum rail current I RLM (For example, 0.6A) and maximum regulator current I RGM (For example, 80mA) According to this, the eight voltage regulators set the maximum rail current I to power rail 206-1. RLM Rail current I R They are required to provide it.

[0045] In some embodiments, the maximum rail current I RLM The rail voltage V within the transient load response time is R Applied during the startup of the power rail 206 to reach the maximum rail current I RLM It operates with an operating current smaller than that. Power rail 206 operates with a rail voltage V during the transient load response time at each start of power rail 206. R It is configured to reach the rail voltage V within the transient load response time. R Providing sufficient power to the power rail to reach the maximum regulator current I during startup RGM and maximum rail current I RLM This is enabled by providing the first number of voltage regulators 320, and therefore the first number of voltage regulators 320 is determined in part on the transient load response time required to start the power rails 206. However, in some embodiments, when ramping up the voltage on each power rail 206 in starting the power rails, the current provided by the power management system 500 is significantly smaller than the maximum rail current of that power rail, for example, to reduce system stress and avoid overshoot.

[0046] During the operation of the power rail 206 (sometimes referred to as normal operation in this specification, as opposed to starting), the operating current I supplying power to the SoC 102 R It fluctuates, and the maximum rail current I RLM It does not exceed . Conversely, in some embodiments, the rail current I is used to power the operation of the SoC102. RWhen used, the maximum rail current I RLM This is reached at least occasionally during the normal operation of the power rail 206. The operating current is between 0 and the maximum rail current I RLM It fluctuates between the following. In contrast to the starting of the power rail 206, during normal operation, the first number of the voltage regulator 320 is determined based on the operating current of the power rail 206, rather than the transient load response time of the power rail 206 at each start. The transient load response time of the power rail 206 is determined by the maximum rail current I RLM This can be achieved with a smaller transient rail current.

[0047] Referring to Figure 4A, the power rail 206, at each time interval, regardless of whether that interval corresponds to the starting or normal operation of the power rail 206, has an instantaneous rail current I R In some embodiments, the power array controller 302 has all of the voltage regulators 320 that control the instantaneous rail current I of the power rail 206. R To enable the collective provision of control settings (e.g., control value 310 and operation enable signal 312), a control setting is generated. In other words, in some embodiments, instantaneous rail I R When the maximum rail current I is 0 RLM When the voltage fluctuates between 0.5I, none of the subsets of the voltage regulator 320 will operate in standby mode. For example, the first power rail 206-1 (Figure 3) is 0.5I at a given time. RLM Instantaneous rail current I equal to R Outputs the maximum rail current I RLM All eight voltage regulators configured to provide 0.5I RLM It is enabled while being controlled by the power array controller 302 to provide only the collectively. Therefore, in this embodiment, only a portion of the power capacity of each voltage regulator 320 is utilized. In some situations, the instantaneous rail current I R Related rail voltage V R The maximum rail current I RLM Related rail voltage V RIt only differs by the first rail voltage error. The power array controller 302 and / or the voltage regulator 320 maintain (e.g., limit or control) the first rail voltage error within the rail drift tolerance V RT configured to be maintained (e.g., limited or controlled).

[0048] Furthermore, in some embodiments, a subset of the voltage regulators 320 is controlled to contribute substantially equally to the instantaneous rail current I R For example, each voltage regulator 320 provides its respective portion to the instantaneous rail current I R and this portion varies by less than 5% (or 10%, 20%, or other predefined margin) among the voltage regulators 320 configured to provide power to the same power rail 206. Each voltage regulator 320 balances the portion of the respective rail current I R provided by that respective voltage regulator 320 with at least another portion of the respective rail current I R provided by a separate voltage regulator 320 within the subset of voltage regulators 320. In some implementations, the inter-regulator balance circuit can be within each voltage regulator 320 and uses negative feedback to control the portion of the respective rail current I R provided by that respective voltage regulator 320 internally and independently of the other voltage regulators configured to provide power to the same power rail 206 for the portion of the respective rail current I R provided by that respective voltage regulator 320.

[0049] Referring to FIG. 4B, in some embodiments, one or more voltage regulators 320 are disabled within a subset of the voltage regulators 320 and operate in standby mode, for example, under the control of the operation enable signal 312, while the remainder of the subset of voltage regulators 320 is enabled to collectively provide the instantaneous rail current I R for the corresponding power rail. One or more voltage regulators 320 have a second number of voltage regulators 320, and the second number is related to the instantaneous rail current I R and the maximum regulator current I RGMDetermined according to a comparison with (e.g., their ratio), or equivalently, the instantaneous rail current I R and the maximum rail current I RLM Determined according to a comparison with (e.g., their ratio). For example, a subset of the voltage regulators 320 has eight voltage regulators, and the second number is equal to a value between 1 and 7. The instantaneous rail current I R is in a first range, e.g.,

[0050]

Number

[0051]

Number

[0052] In some situations, when one or more voltage regulators 320 are operating in standby mode, the rail voltage V R associated with the instantaneous rail current I R is the rail voltage V RLM associated with the maximum rail current IR The only difference is the second rail voltage error. The second rail voltage error is the rail drift tolerance V. RT It is controlled to be maintained within (e.g., limited or controlled) (e.g., by the power array controller 302 and / or voltage regulator 320). The same rail current I R When provided with at least one redundant regulator (Figure 4B) or without a redundant regulator (Figure 4A), the second rail voltage error is smaller than the first rail voltage error, and the involvement of a redundant regulator (one or more) 320 allows for more precise rail voltage control using more complex regulator control. R It will be provided.

[0053] As explained above, each power rail 206 corresponds to a first number of voltage regulators 320, and each second number of voltage regulators 320 are enabled at one time to operate in standby mode, and each second number corresponds to the instantaneous rail current I R The second number changes dynamically according to the following. The second number is determined based on load information 314 and a power state policy configured to satisfy at least one performance criterion (e.g., output ripple voltage, power supply rejection rate, load transient response, output noise, and / or power efficiency). In one embodiment, the second number of voltage regulators 320 are dynamically adjusted to maximize power conversion efficiency for driving the power rails. In other words, in some embodiments, at any point while the electronic device is powered on and supplying power to one or more other semiconductor devices (e.g., SoC 102) via the power rail 206, a first subset of voltage regulators 320 is in operating mode and a second subset of voltage regulators 320 is in bypass mode, as specified by the control setting (e.g., operation enable signal 312) of each voltage regulator. The control setting is determined by the power array controller 302 based on load information 314 and the power state policy.

[0054] During the regulator adjustment process 402, the additional voltage regulators 320D and 320E switch from standby mode to operating mode. The internal voltage regulator controllers of the voltage regulators 320A~320E that drive the power rail 206 control the instantaneous rail current I R The associated rail voltage V R To compensate for the rail voltage error, the operating points of these voltage regulators 320A-320E are dynamically adjusted. This regulator adjustment process 402 is relatively slow due to the time constant of the loop control filters included in voltage regulators 320A-320E. In particular, the control loops of the additional voltage regulators 320D and 320E, which switch between modes, interfere with the operation of the remaining control loops of voltage regulators 320A-320C that drove the power rail 206 in the operating mode, affecting the rail voltage V of the power rail 206. R This can cause a deviation. Therefore, in some embodiments, one of the redundant voltage regulators 320B-320H operating in standby mode may have the same operating point (e.g., rail voltage V) as the other operating voltage regulators on the same power rail 206. R It is biased to the same output voltage (including the same output voltage) of the operating voltage regulator 320 when the redundant voltage regulator(s) 320 drive the power rail 206. R This helps to reduce disturbances to the power rail 206. Given the same operating point, each voltage regulator 320 associated with the power rail 206 is configured to transition from standby mode to operating mode and provide a predetermined regulator current to the power rail 206 within a predetermined period, for example, within 1, 2, 5, or 10 microseconds.

[0055] Figure 5A is a block diagram of a voltage regulator 320, which is one of several voltage regulators in a field programmable array 330. In the field programmable array 330, the power rail 206 has a rail voltage V corresponding to the power rail 206. RMultiple voltage regulators 320 are electrically coupled to provide the rail voltage V. Each voltage regulator 320 includes an output interface 502, one or more drive paths 504, and a voltage regulator controller 506. The output interface 502 provides the rail voltage V R It is electrically coupled to the power rail 206 to output. One or more drive paths 504 are coupled in parallel between the voltage regulator controller 506 and the output interface 502, and each drive path 504 supplies its respective path current I to the power rail 206. P It is configured to operate at the operating frequency during each phase to provide the respective path current I P This is the rail current I introduced into power rail 206. R It becomes part of the power array controller 506. The voltage regulator controller 506 is configured to receive control settings (e.g., control value 310 and operation enable signal 312) from the power array controller 302 and generate path control signals 508 for controlling one or more drive paths 504.

[0056] The voltage regulator 320 includes a feedback path 522 that connects the output interface 502 to the voltage regulator controller 506. However, the voltage regulator controller 506 has a feedback input 540 configured to receive the output voltage of the output interface 502. The voltage regulator controller 506 dynamically adjusts the path control signal 508 based on the output voltage of the output interface 502 to the rail voltage V as defined by the control value 310. R It is configured to generate a rail voltage V defined by the control value 310. In particular, in some embodiments, the path control signal 508 is configured to generate a rail voltage V defined by the control value 310. R The duty cycle is defined by the voltage regulator controller 506, which is dynamically adjusted according to a comparison of the output voltages of the output interface 502.

[0057] In some embodiments, the voltage regulator 320 includes a buck converter, i.e., a DC-DC switch-mode converter, that operates based on an integrated switch. Each drive path 504 includes a switch component 510 and a pulse width modulation (PWM) driver 512. The PWM driver 512 is coupled between the voltage regulator controller 506 and the switch component 510. The PWM driver 512 receives a periodic signal 514 (e.g., having a sine wave, square wave, triangular wave, or sawtooth wave) and a path control signal 508 to control the switch component 510. In particular, the path control signal 508 defines a duty cycle, and the periodic signal 514 has a frequency equal to the operating frequency of one or more drive paths 504. The PWM driver 512 is configured to modify the periodic signal 514 with the path control signal 508 to generate a switching signal 516. The switch component 510 is controlled by the switching signal 516 to turn on and off according to the duty cycle at the operating frequency. The switch component 510 is also coupled to the DC power supply interface 316 and the corresponding DC supply voltage V IN It is configured to be powered by a DC supply voltage V IN This is then output to the switch output 518 of the switch component 510 at the operating frequency according to the duty cycle. The switch output 518 of the switch component 510 receives the rail voltage V R To generate the rail voltage V, it is further adjusted (e.g., filtered) by the passive load component 520. R The output is sent to the power rail 206 via the output interface 502. In some implementations, the rail voltage V R The DC supply voltage V is substantially constant (for example, has an output ripple voltage smaller than the ripple tolerance) IN It has an average magnitude equal to the product of the duty cycle and the conversion efficiency of the switch component 510.

[0058] Figure 5B is a block diagram of a voltage regulator 320 that further includes a bypass unit 528 inside the voltage regulator 320. In some embodiments, each individual voltage regulator 320 controls its current output using the bypass unit 528, independently of any other voltage regulators 320 configured to drive the same power rail 206. The bypass unit 528 controls the rail current I of the corresponding power rail 206 when the voltage regulator 320 is controlled. R It is used to enable standby mode, which is disabled from contributing to the power rail 206. Standby mode is optionally applied when a voltage regulator 320 (e.g., 320E in Figure 3) is applied to drive a power rail 206, or when a voltage regulator 320 (e.g., 320RA-320RD in Figure 3) is not applied to drive any of the power rails 206. The bypass unit 528 is coupled to one or more drive paths 504 and the voltage regulator controller 506 and is configured to provide a dummy load component (including, for example, a passive RC filter or an active filter) in place of the load coupled to the power rail 206 when the voltage regulator 320 is in standby mode.

[0059] In standby mode, the bypass unit 528 is enabled to bypass the feedback path 522 from the output interface 502 to the input of the voltage regulator controller 506, thereby allowing the voltage regulator 320 to control each rail current I RThis disables contribution to the switch. In an embodiment as shown in Figure 5B, a first switch 530A is inserted into the interconnection carrying the switching signal 516 in each drive path 504, blocking it, and a switch 530B is inserted into the feedback path 522, blocking it. In some implementations, each of switches 530A and 530B includes a multiplexer and is controlled by an operation enable signal 312 received by a voltage regulator 320. A bypass unit 528 is coupled between switches 530A and 530B in each drive path 504, intercepting the switching signal 516 and is configured to isolate the power rail 206 and the feedback path 522 from the voltage regulator controller 506. Thus, the bypass unit 528 enables the auxiliary path 532 to bypass the feedback path 522 in standby mode. An example of an implementation of the bypass unit 528 is shown in Figure 6, which is described below.

[0060] Figure 6 is a schematic diagram of a voltage regulator 320 having an auxiliary loop 602 to facilitate a fast transition between the operation of the voltage regulator in bypass mode and the operation of the voltage regulator in operating mode, according to several embodiments. The voltage regulator controller 506 is coupled to each of the drive paths 504A to 504B and provides them with a path control signal 508. A feedback path 522 connects the output interfaces 502 of the drive paths 504A to 504B to the feedback input 540 of the voltage regulator controller 506. In some embodiments, the voltage regulator controller 506 includes a digital-to-analog converter (DAC) 608, an error amplifier 610, and an amplifier feedback circuit configured to enable pulse width modulation for the drive paths 504A to 504B. The control value 310 is applied by the DAC 608 to generate a reference voltage (e.g., reference voltage 704, Figure 7) which is received at the input of the error amplifier 610. The amplifier feedback circuit and feedback path 522 are configured to match the reference voltage, and the rail voltage V output at the output interface 502 is also matched. RIt dynamically controls the rail voltage V. In particular, the path control signal 508 controls the rail voltage V. R The voltage regulator controller 506 controls the duty cycle of the drive paths 504A~504B to match the reference voltage. In some situations, the power array controller 302 also controls the respective rail voltage V R and the respective rail currents I R To enable the generation of these, an operation enable signal 312 is provided to each voltage regulator 320. In some embodiments, the operation enable signal 312 is optionally applied to control (e.g., enable and disable) the error amplifier 610 and / or DAC 608, thereby disabling the entire voltage regulator 320 when the voltage regulator 320 is a redundant voltage regulator not associated with any power rail 206 (e.g., 320RA to 320RD in Figure 3).

[0061] As explained above, the voltage regulator 320 is not enabled to supply power to any of the power rails 206, or the voltage regulator 320 (e.g., 320RA to 320RD) is coupled to the power rail 206, but the corresponding rail current I RIt has a standby mode in which its contribution to the power supply is temporarily disabled. In some embodiments, whether the voltage regulator 320 is coupled to any of the power rails 206, the voltage regulator 320 includes one or more drive paths 504 and a bypass unit 528. The voltage regulator controller 506 of the voltage regulator 320 has an output 508 coupled to one or more drive paths 504 and a feedback input 540 coupled to the output interface 502 by a feedback path 522. The bypass unit 528 is coupled to one or more drive paths 504 and the voltage regulator controller 506 and is configured to provide a dummy load component 604. In standby mode, when the bypass unit 528 is enabled, an auxiliary loop 602 is formed, bypassing the feedback path 522 from the output interface 502 to the input of the voltage regulator controller 506 and driving the dummy load component 604 with one or more switching components 606. Therefore, the auxiliary loop 602 includes a bypass unit 528, and in standby mode, the voltage regulator 320 controls the corresponding rail current I of the power rail 206. R To disable its contribution, it is enabled instead of the feedback path 522. When the auxiliary loop 602 is enabled, the voltage regulator 320 is in standby mode, so the feedback path 522 is disabled.

[0062] In particular, in standby mode, the bypass unit 528 is enabled to bypass the switch component 510 and the passive load component 520 of each drive path 504. Each drive path 504 further includes a PWM driver 512 and a multiplexer 530A coupled to the switch component 510 and the bypass unit 528. The multiplexer 530A is configured to select the bypass unit 528, deselect the switch component 510, and electrically couple the PWM driver 512 to the bypass unit 528 in standby mode. The voltage regulator 320 further includes a multiplexer 530B coupled between the feedback input 540 and the output interface 502 of the voltage regulator controller 506. The multiplexer 530B is configured to operate simultaneously with the multiplexer 530A of each drive path 504 to select the bypass unit 538 and deselect the output interface 502 for input to the voltage regulator controller 506. In some embodiments, the operation enable signal 312 is used to simultaneously control multiplexer 530A and multiplexer 530B to enable standby mode. These means that in standby mode, the switching components 510 and passive load components 520 of each drive path 504 are skipped by the bypass unit 528, while the voltage regulator controller 506 and the PWM drivers 512 of each drive path 504 continue to operate together with the dummy load components 604 and switching components 606 in the bypass unit 528.

[0063] In summary, when the voltage regulator 320 is in standby mode, the auxiliary loop 602 is formed (or enabled) to isolate the output interface 502 without completely shutting down the voltage regulator 320. The voltage regulator controller 506 and the PWM driver 512 of the drive path 504 remain operational in standby mode, and the voltage regulator 320 is able to wake up quickly and maintain a desired transient response time when it recovers from standby mode and resumes operation in operational mode. For example, in some situations, the voltage regulator controller 506 and the PWM driver 512 of the drive path 504 operate at the same operating point (e.g., rail voltage V at feedback input 540) in both standby and operational modes. R By maintaining this, a rapid switch to the operating mode is possible. Furthermore, the switching component 510 of the drive path 504 is isolated and disabled, and the dummy load component 604 and the switching component 606 are designed to consume less power than the switching component 510 and the load component 520 of the drive path 504. In one embodiment, the voltage regulator 320 drives the power rail 206 with a rail current of 1.5A in the operating mode and consumes less than 100mA while driving the dummy load component 604 and the switching component 606 in the standby mode. This efficiently saves power consumption of the voltage regulator 320 in the standby mode.

[0064] Conversely, in some embodiments or situations, each voltage regulator 320 (for example, any of the voltage regulators 320RA to 320RD in Figure 3) may not be assigned to drive any power rail 206 and may be completely stopped or operate in standby mode. In standby mode, the voltage regulator controller 506 and the PWM driver 512 of the drive path 504 are operational, and the bypass unit 528 is enabled to bypass the switching components 510 and load components 520 of the drive path 504. When coupled to the power rail 206, such redundant voltage regulators 320 will not operate on the rail voltage V during the transition from standby mode to operational mode. R Outputs the corresponding rail current I of power rail 206. R This allows current to be contributed quickly (e.g., in transient response time). However, if the voltage regulator 320 is stopped, the voltage regulator controller 506 and the PWM driver 512 of the drive path 504 are disabled under the control of the operation enable signal 312. When coupled to the power rail 206, such a redundant voltage regulator 320 will cause the corresponding rail current I of the power rail 206 to be affected. R Before it can contribute to the operation, it must be restarted when transitioning from standby mode to operating mode. The restart process is often slow and impairs the relatively long transient response time when the voltage regulator 320 recovers from a completely stopped state, but the application of a bypass unit 528 with an operating voltage regulator controller 506 and a PWM driver 512 enables both rapid mode switching and low power consumption.

[0065] Figure 7 is a schematic diagram of an exemplary voltage regulator 320 having a filter-based auxiliary loop 602 according to several embodiments. The compensator 702 is coupled to the drive path 504 and provides it with a path control signal 508. A feedback path 522 connects the output interface 502 of the voltage regulator 320 to the feedback input 540 of the compensator 702. The compensator 702 is coupled to the DAC 608 and configured to enable pulse width modulation of the drive path 504. A control value 310 is applied by the DAC 608 to generate a reference voltage 704 received at the reference input of the compensator 702. The compensator 702 outputs a rail voltage V at the output interface 502. R The rail voltage V is dynamically controlled to match the reference voltage 704 output by the DAC608. In particular, the path control signal 508 controls the rail voltage V R The compensator 702 generates the respective rail voltage V to control the duty cycle of the drive path 504 so that it matches the reference voltage 704. In some situations, the power array controller 302 also controls the respective rail voltage V R and the respective rail currents I R To enable the generation of the voltage regulators, an operation enable signal 312 is provided to each voltage regulator 320, and the operation enable signal 312 controls a switch 530 to enable one of the standby mode and operation mode for each voltage regulator 320. In some embodiments, the compensator 702 is one of a type II compensator and a type III compensator. In some embodiments, a type III compensator is used in implementations where a phase margin exceeding a threshold phase margin is required to keep both the feedback loop and the auxiliary loop 602 corresponding to the feedback path 522 stable, for example.

[0066] The switch component 510 of the drive path 504 includes an upper switching transistor 706A and a lower switching transistor 706B. The upper switching transistor 706A is supplied with a DC voltage V INThe lower switching transistor 706B is coupled between the 202 and the passive load component 520 and controlled by the upper level shifter 708A, which receives and converts the switching signal 516 generated by the PWM driver 512. The lower switching transistor 706B is coupled between the low DC supply voltage (e.g., ground, sometimes called circuit ground) and the passive load component 520 and controlled by the lower level shifter 708B, which receives and converts the switching signal 516 generated by the PWM driver 512.

[0067] The voltage regulator 320 further includes a bypass unit 528 coupled to switches 530A and 530B at the input and output of the bypass unit 528. Switch 530A' is inserted into an interconnection carrying a switching signal 516 in the drive path 504 and interrupts it, and switch 530A' is inserted into a feedback path 522 and interrupts it. The bypass unit 528 is coupled in parallel to the switch components 510 and passive load components 520 of the drive path 504 via switches 530A, 530A', 530B, and 530B'. Switches 530A and 530A' are two separate switches, optionally coupled to each other or integrated into a single-input two-output multiplexer. Switches 530B and 530B' are two separate switches, optionally coupled to each other or integrated into a two-input one-output multiplexer. In standby mode, switches 530A and 530B are enabled, and switches 530A' and 530B' are disabled, resulting in the activation of auxiliary path 532, which bypasses the feedback path 522 from output interface 502 to the feedback input of compensator 702. Thus, the voltage regulator 320 controls the respective rail currents I of the power rails 206 that are assigned to be driven by the voltage regulator 320. R Contribution to is disabled. In operating mode, switches 530A' and 530B' are enabled, switches 530A and 530B are disabled, and as a result, the auxiliary path 532 is disabled, and the switch component 510 and the passive load component 520 are enabled, and the rail voltage V RThe output is sent to the power rail 206. Each of the switches 530A, 530A', 530B, and 530B' is controlled by the operation enable signal 312 or its complementary signal.

[0068] Bypass unit 528 includes a bypass switching component 606 having an upper switching transistor 714A and a lower switching transistor 714B. The upper switching transistor 714A is supplied with a DC voltage V IN The lower switching transistor 714B is coupled between 202 and the dummy load component 604 and controlled by an upper level shifter 716A that receives and converts the switching signal 516 generated by the PWM driver 512 in standby mode. The lower switching transistor 714B is coupled between a low DC supply voltage (e.g., ground) and the dummy load component 604 and controlled by a lower level shifter 716B that receives and converts the switching signal 516 generated by the PWM driver 512 in standby mode. In some embodiments not shown, the dummy load component 604 includes an inductor-capacitor (LC) tank. In some embodiments, the dummy load component 604 includes an active filter 720 to mimic the LC tank. The active filter 720 is coupled to the bypass output 722 of the bypass unit 528 and includes an operational amplifier and a passive feedback component. In one embodiment, the active filter 720 is a second-order Sallen-Key filter. Through these means, the auxiliary loop 602 is established based on the replicated power stage and active filter 720, enabling closed-loop control of the voltage regulator 320 without involving the output interface 502 of the voltage regulator 320.

[0069] In operating mode, switches 530A and 530B are disabled, and switches 530A' and 530B' are enabled. Control loop control is formed by a feedback path 522 from the output interface 502 to the feedback input of compensator 702. Compensator 702 supplies the rail voltage V to the power rail 206. RA path control signal 508 is generated to control the drive path 504 to produce the power stage. Conversely, in standby mode, the path control signal 508 is configured to replicate the power stage while reducing the power stage to reduce power consumption. When driven by the switching signal 516, the active filter 720 can serve the purpose of reducing the power stage and saving power consumption. In particular, given a reference voltage 704, the output voltages at the output interface 502 and bypass output 722 are low-pass filtered by the compensator 702.

[0070] In some embodiments, the bypass voltage output at the bypass output 722 of the voltage regulator 320 in standby mode is the rail voltage V output at the output interface 502 of the voltage regulator 320 in operating mode. R It is substantially equal to (for example, within a default error margin). Alternatively, in some embodiments, the bypass voltage output at the bypass output 722 of the voltage regulator 320 in standby mode is the rail voltage V R Rail voltage V is not equal to and is less than the threshold voltage difference. R It has a deviation from. In some embodiments, the output interface 502 and bypass output 722 of the voltage regulator 320 are physically close to each other on the PMIC die 118. By means of these, when the standby mode is changed to the operating mode, the voltage regulator 320 sets a default regulator current I within a predetermined period (e.g., within 10 microseconds). R and rail voltage V R This can be supplied to the power rail 206.

[0071] Referring to Figure 7, in some embodiments, the voltage regulator 320 includes only one drive path 504, and the bypass unit 528 includes only one bypass path 724 configured to bypass a portion of the one drive path 504 of the voltage regulator 320 in standby mode. Alternatively, in some embodiments, the voltage regulator 320 includes multiple drive paths 504, and the bypass unit 528 includes multiple bypass paths 724 configured to bypass the multiple drive paths 504 of the voltage regulator 320. The bypass paths 724 have the same number of paths as the drive paths 504, or a different number of paths. Additionally and alternatively, in some embodiments, the voltage regulator 320 includes multiple drive paths 504, and the bypass unit 528 includes only one bypass path 724 configured to bypass the multiple drive paths 504 of the voltage regulator 320 in standby mode.

[0072] Figure 8 is a schematic diagram of a plurality of voltage regulators 800 in a field-programmable array of voltage regulators configured to drive a power rail 206, according to several embodiments. The plurality of voltage regulators 800 includes a first voltage regulator 800A, a second voltage regulator 800B, and a third voltage regulator 800C. Voltage regulators 800A to 800C are identical to each other. In this embodiment, each voltage regulator 800 has the same circuit configuration as the voltage regulator 320 described above with reference to Figure 7. Specifically, each voltage regulator 800 includes a compensator 702 coupled to a drive path 504 and a bypass path 724. The compensator 702 provides a path control signal 508 to the drive path 504. A feedback path 522 connects an output interface 502 coupled to the drive path 504 to a feedback input 540 of the compensator 702. The reference input of compensator 702 is coupled to DAC608 and is configured to receive a reference voltage 704 generated by DAC608 according to the control value 310. Compensator 702 receives the rail voltage V output at output interface 502. R By dynamically controlling the pulse width modulation of the drive path 504, it is made to match the reference voltage 704. In particular, the path control signal 508 controls the rail voltage V RA compensator 702 generates a voltage to control the duty cycle of the drive path 504 so that it matches the reference voltage 704. A bypass unit 528 is coupled onto the bypass path 724, and a switch 530 is applied to couple the bypass unit 528 in parallel with the PWM driver 512 and the compensator 702, thereby allowing a portion of the drive path 504, including the output interface 502 coupled to the power rail 206, to be bypassed in standby mode.

[0073] The output interfaces 502 of voltage regulators 800A to 800C are electrically coupled to the same power rail 206. However, each of the voltage regulators 800A to 800C is independently controlled to drive the power rail 206 by a separate corresponding operation enable signal 312. In each voltage regulator 800, its operation enable signal 312 controls switch 530 to selectively enable only one of the feedback path 522 and auxiliary path 532. Furthermore, the same DC supply voltage V is coupled to the switch component 510 and the bypass switching component 606 of the voltage regulators 800A to 800C. IN 202 and a low DC supply voltage (e.g., ground) are shared. In some embodiments, the control values ​​310 of the voltage regulators 800A to 800C are identical to each other, and as a result, the PWM driver 512 of the voltage regulators 800A to 800C generates switching signals 516 with the same duty cycle in the different voltage regulators 800A to 800C. Alternatively, in some embodiments, the control values ​​310 of the voltage regulators 800A to 800C are independently controlled by the operation enable signals 312 of the voltage regulators 800A to 800C.

[0074] In some situations, each of the first and second voltage regulators 800A and 800B operates to drive the power rail 206 in operating mode. The feedback paths 522 of each voltage regulator 800A and 800B are enabled between the output interfaces 502 and the feedback input 540 of each voltage regulator 800A and 800B in operating mode. Conversely, the third voltage regulator 800C is electrically isolated from the power rail 206 in standby mode, where the bypass unit 528 of the third voltage regulator 800C is enabled to bypass the feedback path 522 of the third voltage regulator 800C.

[0075] Alternatively, in some situations, each of the first and second voltage regulators 800A and 800B operates in standby mode, and the bypass units 528 of each voltage regulator 800A and 800B are enabled to bypass the feedback path 522 between the output interface 502 and the feedback input 540 of each voltage regulator 800A and 800B. Conversely, the third voltage regulator 800C operates in an operating mode in which the feedback path 522 of voltage regulator 800C is enabled between the output interface 502 and the feedback input 540 of voltage regulator 800C. Alternatively and additionally, in some situations, all three voltage regulators 800A-880C operate in an operating mode in which the feedback path 522 of each and every voltage regulator 800A-800C is enabled between the output interface 502 and the feedback input 540 of each voltage regulator 800A-800C.

[0076] Referring to Figure 8, the multiple voltage regulators 800 are configured to drive the power rail 206 in a configurable manner. In some embodiments, each voltage regulator 800 is trimmed to minimize relative mismatches (e.g., offset errors, gain errors, and / or bandwidth errors) with other voltage regulators 800. In situation and parallel trimming mechanisms are optionally applied to the fully integrated or assembled SoC 102 and PMIC 118 as shown in Figure 1B. During in situation and parallel trimming, each voltage regulator 800 enables its respective auxiliary loop 602 and disables its respective feedback path 522. These means adjust the gain and offset errors of each voltage regulator 800 without causing power sequencing problems.

[0077] Under certain circumstances, multiple voltage regulators 800 are powered on. When the DC supply voltage (e.g., voltage 202) is first applied, the rail voltage V output by the feedback-based voltage regulator 800 is R The large voltage difference between them causes the voltage regulators 800 to clash with each other, slowing down the power-up process of the voltage regulators 800. This is undesirable for rapid power state transitions. To avoid this condition, in some embodiments, voltage regulators 800 coupled to the same power rail are pre-regulated at the analog signal level before being coupled to the power rail 206. Specifically, in some situations, the output interface 502 of the voltage regulator 800 is electrically isolated from the power rail 206 when the DC supply voltage is first applied. Standby mode and operating mode are applied sequentially during the power-up process of each voltage regulator 800. The auxiliary loop 602 of each voltage regulator 800 is bypassed at the rail voltage V R Initially enabled during power-up operation until outputting, the feedback path 522 is then enabled to couple each voltage regulator 800 to the power rail 206.

[0078] Alternatively, during power-up operation, each voltage regulator 800 starts in operating mode. The output voltage at the output interface 502 of each voltage regulator 800 is monitored and compared to the threshold start voltage. For each voltage regulator 800, according to the determination that the output voltage exceeds the threshold start voltage, the output interface 502 of the voltage regulator 800 is electrically coupled to the power rail 206. More specifically, in one embodiment, the threshold start voltage is 1V and the rail voltage is V R The voltage is 1.8V. Voltage regulators 800A to 800C are powered on separately to avoid reaction between regulators. For each voltage regulator 800A to 800C, according to the determination that the output voltage reaches 1V at the output interface 502 of that voltage regulator (e.g., 800A), the output interface 502 of that voltage regulator (e.g., 800A) is electrically coupled to the power rail 206, for example, using a switch coupled between the output interface 502 of the voltage regulator (e.g., 800A) and the power rail 206.

[0079] During the power-up test, the normal loop of each voltage regulator 800 on the PMIC118 is the rail voltage V for driving the SoC102. R It operates to ramp up. In some situations, one of the SoC102 and PMIC118 may fail, causing a hardware failure condition. For field fault diagnosis, the fault location needs to be identified among the different voltage regulators 800 of the SoC102 and PMIC118. Therefore, each of the SoC102 and voltage regulators 800 may be isolated and monitored separately, i.e., each SoC102 or voltage regulator 800 can operate independently of any other SoC102 or voltage regulator 800. In one embodiment, each voltage regulator 800 is isolated from the SoC102 or other voltage regulators (one or more) 800 by entering a standby mode in which a bypass unit 528 is enabled to bypass the feedback path 522 from the output interface 502 to the feedback input 540 of the compensator 702.

[0080] Figure 9A is a schematic diagram of a portion 900 of a voltage regulator 320 having multiple drive paths 504, according to several embodiments, referred to herein as the multiphase drive section 900, and Figure 9B is a schematic diagram of another portion 920 of a voltage regulator 320 having multiple bypass paths 724, according to several embodiments, referred to herein as the multiphase bypass section 920. The drive section 900 corresponds to portions of two parallel drive paths 504A and 504B, and the bypass section 920 corresponds to two parallel bypass paths 724A and 724B. Each portion of the drive path 504A or 504B of the drive section 900, and each bypass path 724 of the bypass section 920, are coupled in parallel to each other via a switch 530. Referring to Figure 5B, the switch 530 selects either the drive section 900 or the bypass section 920 (for example, one of them) which is electrically coupled to the PWM driver 512 and the feedback input 540 of the voltage regulator controller 506. In addition to the drive paths 504, the drive unit 900 further includes an output interface 502 to which each drive path 504 is coupled. As shown in the complete schematic diagram of the voltage regulator (e.g., Figure 6), the output interface 502 is coupled to the feedback input 540 of the voltage regulator controller 506. The output interface 502 is also coupled to the power rail 206 and the rail voltage V generated by the voltage regulator 320. R It is configured to provide and supply a maximum default regulator current to the power rail 206.

[0081] Each drive path 504 (e.g., 504A or 504B) includes a switch component 510 (as shown in Figure 6), a passive load component 520, and a PWM driver 512, and is arranged in parallel with other drive paths 504 (one or more) in the same voltage regulator 320. Each drive path 504 has its own path current I P To provide power to the power rail 206, it is configured to operate at the operating frequency during each phase. Each path current I P This is the rail current I introduced into power rail 206. RThis becomes part of the drive unit 900 (Figure 9A) includes a first number of drive paths 504, and the bypass unit 920 (Figure 9B) has a second number of bypass paths 724. Optionally, the second number is equal to the first number such that each bypass path 724 is configured to bypass the switch components 510 and passive load components 520 of each single drive path 504. The same PWM driver 512 that drives each single drive path 504 in operating mode is configured to drive the corresponding bypass path 724 in standby mode. Thus, in standby mode, each bypass path 724 is configured to operate at the operating frequency during its respective phase, and different bypass paths 724 have different phases under the control of different PWM drivers 512, optionally.

[0082] In some embodiments, the bypass section 920 functions as a bypass unit 528 of a voltage regulator 320 (for example, in Figure 5B). In some embodiments, the bypass section 920 includes a plurality of bypass switching components (for example, components 606 in Figure 6, or components 714A and 714B in Figures 9B and 9D) and a single dummy load component 604 coupled between the plurality of bypass switching components 606 and the bypass output 722 of the bypass unit 528. In this embodiment, the dummy load component 604 includes an active filter 720 (for example, a second-order Sallen-Key filter), and the plurality of bypass paths 724 of the bypass unit 528 share the same active filter 720. From this viewpoint, the active filter 720 functions as an additive filter having a plurality of inputs from the parallel bypass switching components 606. Conversely, in some embodiments not shown in Figures 9B and 9D, the bypass unit 528 has a plurality of bypass paths 724, each bypass path 724 having a separate bypass switch component 606 coupled to a separate active filter 720. The bypass outputs 722 of the different active filters 720 are optionally coupled to or isolated from each other.

[0083] Each bypass switching component 606 corresponds to a respective drive path 504 and is configured to bypass a portion of the corresponding drive path 504 in standby mode. Specifically, the switch component 510 of the drive path 504 is configured to bypass the DC supply voltage V IN It includes an upper switching transistor 706A configured to generate a current path to 202 and a lower switching transistor 706B configured to generate a current path to a low DC supply voltage (e.g., ground). The bypass switching component 606 of the bypass path 724 also includes a DC supply voltage V IN The circuit includes an upper switching transistor 714A configured to generate a current path to 202 and a lower switching transistor 714B configured to generate a low DC supply voltage (e.g., ground). In some embodiments, the upper switching transistor 714A of the bypass path 724 has a smaller transistor size than the upper switching transistor 706A of the drive path 504, and the lower switching transistor 714B of the bypass path 724 has a smaller transistor size than the lower switching transistor 706B of the drive path 504.

[0084] Figures 9C and 9D are schematic diagrams of equivalent circuits 940 and 960 of a voltage regulator 320 operating in operating mode and bypass mode, respectively, according to several embodiments. The voltage regulator 320 is a two-phase buck converter. In standby mode (Figure 9D), the bypass unit 528 is enabled to bypass the feedback path 522 from the output interface 502 to the feedback input 540 of the voltage regulator controller 506 (specifically, the compensator 702 therein), and the voltage regulator 320 does not supply current to the power rail 206. The voltage regulator 320 has a first alternating current (AC) loop response in standby mode. The first AC loop response has a first low-frequency gain, a first cutoff frequency, and a first phase margin. In operating mode (Figure 9C), the bypass unit 528 is disabled to bypass the feedback path 522, and the voltage regulator 320 supplies at most a predetermined regulator current to the power rail 206. The voltage regulator 320 has a second AC loop response in its operating mode. The second AC loop response has a second low-frequency gain, a second cutoff frequency, and a second phase margin. The first and second low-frequency gains are substantially equal to each other and have a first gain difference less than, for example, a first threshold. The first and second cutoff frequencies are substantially equal to each other and have a second frequency difference less than, for example, a second threshold (e.g., 5 kHz). The first and second phase margins are substantially equal to each other and have a third phase margin difference less than, for example, a third threshold (e.g., 5°).

[0085] The voltage regulator 320 applies an active filter 720 in the bypass unit 528. The active filter 720 provides an LC filter frequency response with a sufficient quality factor (e.g., greater than the quality factor threshold). In standby mode, the auxiliary loop 602 is stabilized based on phase margin and gain margin. The phase margin is greater than the phase margin threshold, and the gain margin is greater than the gain margin threshold. The active filter 720 includes an operational amplifier 902 with sufficient driving capability for large loads (e.g., loads greater than the threshold load). In addition, in operating mode, the bypass output 722 is isolated from the power rail 206 and therefore does not interfere with the operation of the SoC 102 coupled to the power rail 206.

[0086] In some embodiments (for example, Figure 9C), a bypass unit 528 having one or more bypass paths 724 is applied to bypass a feedback path 522 in a buck converter. It should be noted that in some embodiments, a bypass unit 528 having one or more bypass paths 724 is similarly applied to bypass a feedback path 522 in a boost converter or a buck boost converter.

[0087] Figure 10 is a flowchart of a method 1000 for driving a power rail 206 of an electronic device according to several embodiments. In some embodiments, the electronic device includes an integrated semiconductor device 180 in which an SoC 102 and a PMIC 118 are vertically integrated. In some embodiments, the electronic device includes an SoC 102 and a PMIC 118 mounted on a circuit board. The power rail 206 is provided by the PMIC 118 to drive the operation of the SoC 102. The electronic device is electrically coupled to the power rail 206 and the rail voltage V R and rail current I R It has multiple voltage regulators 320 configured to supply power to one of the power rails 206.

[0088] Electronic devices use rail voltage V R and rail current I RThe voltage is generated and supplied to the power rail 206 (1002). Each voltage regulator 320 has an output interface coupled to the power rail 206, and when each voltage regulator 320 is in operating mode, the rail voltage V R The device provides and is configured to supply a default regulator current to the power rail 206 at best (1004). The electronic device obtains control settings for each of the multiple voltage regulators 320 (1006). The control settings for each voltage regulator 320 determine whether each voltage regulator 320 is a standby voltage regulator operating in standby mode or an operating voltage regulator operating in operating mode (1008). Each standby voltage regulator 320 (e.g., regulator 800C in Figure 8) enables the standby voltage regulator bypass unit 528 to bypass the feedback path 522 from the output interface 502 to the input 540 of the voltage regulator controller 506 so that the standby voltage regulator 320 does not supply current to the power rail 206 (1010). Each operating voltage regulator 320 (for example, regulator 800A or 800B in Figure 8) disables the bypass unit 528 from bypassing the feedback path 522 so that each voltage regulator 320 supplies current to the power rail 206 (1012).

[0089] In some embodiments, each voltage regulator 320 of a plurality of voltage regulators is configured to transition from standby mode to operating mode in accordance with a change in control settings and to provide a default regulator current to the power rail 206 within a predetermined period (e.g., within 1, 2, 5, or 10 microseconds). That said, in some situations, the default period is in the range of 0.1 to 10 microseconds. If each voltage regulator 320 is not completely stopped in standby mode, each voltage regulator 320 can quickly switch from standby mode to operating mode and provide a default regulator current to the power rail 206.

[0090] In some embodiments, for each voltage regulator 320, the control setting includes a control value 310 and an operation enable signal 312. The control value 310 is the rail voltage V R The magnitude of the rail voltage V is defined, and the operation enable signal 312 is configured to control each voltage regulator 320 to operate in either a standby mode in which the bypass unit 528 is enabled to bypass the feedback path 522, or an operating mode in which the bypass unit 528 is disabled to bypass the feedback path 522, thereby controlling the rail voltage V R In connection with this, the total current introduced into the power rail 206 is controlled. Specifically, the operation enable signal 312 is applied to the control switch 530 to select one of the bypass unit 528 and the feedback path 522, which are electrically coupled to the voltage regulator controller 506 and the PWM driver 512.

[0091] In some embodiments, each voltage regulator 320 includes one or more drive paths 504 coupled to an output interface 502 and is configured to operate at an operating frequency. The voltage regulator controller 506 of each voltage regulator 320 has an output 508 coupled to one or more drive paths 504 and an input 540 coupled to the output interface 502 by a feedback path 522. The voltage regulator controller 506 is configured to control one or more drive paths 504 and a bypass unit 528.

[0092] In some embodiments, the electronic device dynamically and in real time determines control settings for each voltage regulator 320 coupled to the power rail 206 based on the load state and power state policy associated with the power rail 206 (1014).

[0093] In some embodiments, referring to Figure 5B, each voltage regulator includes one or more drive paths 504 coupled to an output interface 502 and a voltage regulator controller 506. Each drive path 504 further includes a passive load component 520 coupled to the output interface 502, a driver 512 configured to receive a periodic signal 514 having an operating frequency and modulate the periodic signal 514 to give a distinct phase to a switching signal 516, and a power switch component 510 coupled to the driver 512 and the passive load component 520. The power switch component 510 controls the passive load component 520 under the control of the switching signal 516 by supplying one or more DC voltages V IN It is configured to be coupled to the power switch component 510 and the passive load component 520 of each drive path 504. In addition, in some embodiments, in standby mode, the bypass unit 528 is enabled to bypass the power switch component 510 and the passive load component 520 of each drive path 504, and each drive path 504 further includes a driver 512, a power switch component 510, and a first multiplexer 530A coupled to the bypass unit 528. The first multiplexer 530A is configured to be controlled by a control setting (specifically, an operation enable signal 312) to enable standby mode, i.e., to select access to the bypass unit 528 and deselect access to the power switch component 510 which is electrically coupled to the driver 512 of the drive path 504. In addition, each voltage regulator 320 further includes a second multiplexer 530B coupled to the input 540 of the voltage regulator controller 506, the output interface 502 of the power rail 206, and the bypass output 722 of the bypass unit 528. The second multiplexer 530B is configured to be controlled by a control setting (specifically, an operation enable signal 312) simultaneously with the first multiplexer 530A, to enable standby mode, i.e., to select the bypass output 722 of the bypass unit 528 and deselect the output interface 502 of the power rail 206 which is coupled to the input 540 of the voltage regulator controller 506.

[0094] In some embodiments, referring to Figures 6 and 7, the bypass unit 538 includes one or more bypass paths 724, each bypass path 724 including a bypass switching component 606 having a first-size bypass switching transistor 714. The switch component 510 of each driver path 504 has a path switching transistor 706 having a second size. The second size of the path switching transistor 706 is larger than the first size of the bypass switching transistor 714.

[0095] In some embodiments, multiple voltage regulators 320 are electrically coupled to a power array controller 506. The power array controller 506 is configured to determine control settings for each voltage regulator 320 coupled to the power rail 206. Furthermore, in some embodiments, for each voltage regulator 320, the control settings are dynamically and in real time adjusted by the power array controller 506 based on the load state and power state policy associated with the power rail 206. For example, the power state policy may require that the control settings maximize the power conversion efficiency of the multiple voltage regulators, or that the quality factor of the voltage regulator 320 is greater than a quality factor threshold.

[0096] In various embodiments of this application, the PMIC has a field-programmable array of voltage regulators configured to provide rail voltages to multiple power rails. Each power rail is associated with multiple identical voltage regulators in the field-programmable array, although in some embodiments the field-programmable array further includes one or more redundant voltage regulators that are not used to drive any power rail. For each power rail, all of the identical voltage regulators are coupled to drive their respective power rails to provide maximum drive capability in some situations, while a subset of standby voltage regulators may be isolated from their respective power rails during standby duration in some other situations. During standby duration, standby mode is enabled to convert the voltage regulators that drive the power rails in operating mode to redundant or standby voltage regulators. In this standby mode, the voltage regulator bypass units are enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller, and the voltage regulators do not supply current to the corresponding power rails. The voltage regulator is not completely shut down in standby mode, but can transition to operating mode to quickly (e.g., within a few microseconds) supply the default regulator current to the power rail.

[0097] Implementation examples will be described in at least the following numbered clauses. Clause 1: An electronic device comprising: a power rail configured to provide rail voltage; and a plurality of voltage regulators electrically coupled to the power rail and configured to collectively provide rail voltage, each of the plurality of voltage regulators having an output interface coupled to the power rail and configured to provide rail voltage and supply up to a default regulator current to the power rail; one or more drive paths coupled to the output interface and configured to operate at an operating frequency; an input coupled to the output interface by outputs and feedback paths coupled to one or more drive paths and configured to control one or more drive paths; and a bypass unit coupled to one or more drive paths and the voltage regulator controller, wherein each voltage regulator of the plurality of voltage regulators is configured to operate in either a standby mode in which the bypass unit is enabled to bypass a feedback path from the output interface to the input of the voltage regulator controller and each voltage regulator does not supply current to the power rail, or an operating mode in which the bypass unit is disabled to bypass the feedback path and each voltage regulator supplies up to a default regulator current to the power rail.

[0098] Clause 2: The electronic device described in Clause 1, wherein each of the multiple voltage regulators is configured to transition from standby mode to operating mode in accordance with a change in control settings and to provide a predetermined regulator current to the power rail within a predetermined period.

[0099] Clause 3: The electronic device described in Clause 1, wherein for each voltage regulator, the control setting includes a control value and an operating enable signal, the control value defining the magnitude of the rail voltage, and the operating enable signal controlling each voltage regulator to operate in either a standby mode in which the bypass unit is enabled to bypass the feedback path, or an operating mode in which the bypass unit is disabled to bypass the feedback path.

[0100] Clause 4: The electronic device according to Clause 1, wherein each of one or more drive paths further comprises a passive load component coupled to an output interface; a driver configured to receive a periodic signal having an operating frequency and modulate the periodic signal to give a distinct phase to a switching signal; and a power switching component coupled to the driver and the passive load component, the power switching component configured to couple the passive load component to one or more DC supply voltages under the control of a switching signal.

[0101] Clause 5: The electronic device according to Clause 4, wherein in standby mode, a bypass unit is enabled to bypass the power switching components and passive load components of each drive path, and each of one or more drive paths further comprises a driver, a power switching component, and a first multiplexer coupled to the bypass unit, wherein the first multiplexer is controlled by a control setting to enable a standby mode in which the first multiplexer selects access to the bypass unit and deselects access to the power switching component electrically coupled to the driver of the drive path.

[0102] Clause 6: The electronic device according to Clause 5, wherein each voltage regulator further comprises a second multiplexer coupled to the input of a voltage regulator controller, the output interface of a power rail, and the output of a bypass unit, the second multiplexer being controlled by a control setting, simultaneously with the first multiplexer, to enable a standby mode in which the second multiplexer selects the output of a bypass unit and deselects the output interface of a power rail coupled to the input of a voltage regulator controller.

[0103] Clause 7: The electronic device according to Clause 4, wherein the bypass unit includes one or more bypass paths, each bypass path includes a bypass switching component having a bypass switching transistor of a first size, and each driver path's power switching component has a path switching transistor of a second size, the second size of the path switching transistor being greater than the first size of the bypass switching transistor.

[0104] Clause 8: An electronic device as described in any one of Clauses 1 to 7, wherein multiple voltage regulators are electrically coupled to a power array controller, and the power array controller is configured to determine the control settings of each voltage regulator coupled to the power rail.

[0105] Clause 9: For each voltage regulator, the control settings are dynamically and in real time adjusted by the power array controller based on the load conditions and power condition policies associated with the power rail, as described in Clause 8.

[0106] Clause 10: The electronic device according to any one of Clauses 1 to 6, wherein the bypass unit includes one or more bypass paths, each bypass path having its own bypass switching component and its own dummy load component coupled between the bypass switching component and the output of the bypass unit, and each bypass path is configured to bypass its respective drive path of the feedback path in standby mode.

[0107] Clause 11: For each bypass path, each dummy load component includes an active filter, as described in Clause 10.

[0108] Clause 12: The electronic device described in Clause 11, wherein the active filter is a second-order Sallen-Key filter.

[0109] Clause 13: For each voltage regulator, a bypass unit is configured to be electrically isolated from the power rail in standby mode, to output the rail voltage in standby mode, and to provide the rail voltage to the input of the voltage regulator controller, and when the standby mode is changed to operating mode, each voltage regulator is able to provide a predetermined regulator current to the power rail within a predetermined period, as described in any one of Clauses 1 to 12.

[0110] Clause 14: The electronic device according to Clause 1, wherein the bypass unit includes one or more bypass switching components and a dummy load component coupled between the one or more bypass switching components and the output of the bypass unit, and each bypass switching component is coupled to its respective drive path in standby mode.

[0111] Clause 15: The electronic device described in Clause 14, wherein the dummy load component includes one of the active filters, and the active filter is a Sallen-Key filter.

[0112] Clause 16: An electronic device according to any one of Clauses 1 to 15, wherein the plurality of voltage regulators include a first voltage regulator, a second voltage regulator, and a third voltage regulator, each of the first and second voltage regulators operating to drive a power rail in operating mode, the feedback path of each voltage regulator being enabled between the output interface and input of each voltage regulator in operating mode, and the third voltage regulator being electrically isolated from the power rail in standby mode, such that the bypass unit of the third voltage regulator is enabled to bypass the feedback path of the third voltage regulator.

[0113] Clause 17: Multiple voltage regulators coupled to a power rail are identical to the electronic devices described in any one of Clauses 1 to 16.

[0114] Clause 18: An electronic device according to any one of Clauses 1 to 17, wherein each voltage regulator has a first alternating current (AC) loop response in standby mode, the first AC loop response having a first low-frequency gain, a first cutoff frequency, and a first phase margin; each voltage regulator has a second AC loop response in operating mode, the second AC loop response having a second low-frequency gain, a second cutoff frequency, and a second phase margin; a first difference between the first low-frequency gain and the second low-frequency gain is less than a first threshold; a second difference between the first cutoff frequency and the second cutoff frequency is less than a second threshold; and a third difference between the first phase margin and the second phase margin is less than a third threshold.

[0115] Clause 19: A method for driving a power rail, in an electronic device having a plurality of voltage regulators electrically coupled to a power rail, comprising generating rail voltage and rail current to drive the power rail, wherein each voltage regulator has an output interface coupled to the power rail, and is configured to provide rail voltage and supply a maximum default regulator current to the power rail when the voltage regulator is in operating mode; obtaining a control setting for each of the plurality of voltage regulators, which determines whether each voltage regulator is a standby voltage regulator operating in standby mode or an operating voltage regulator operating in operating mode; enabling a bypass unit of the standby voltage regulator to bypass a feedback path from the output interface to the input of the voltage regulator controller so that the standby voltage regulator does not supply current to the power rail; and disabling a bypass unit to bypass a feedback path so that the voltage regulator supplies current to the power rail, in each operating voltage regulator.

[0116] Clause 20: The method according to Clause 19, wherein each voltage regulator includes one or more drive paths coupled to an output interface and configured to operate at an operating frequency, and the voltage regulator controller of each voltage regulator is configured to control one or more drive paths, having an output coupled to one or more drive paths and an input coupled to the output interface by a feedback path, and a bypass unit is coupled to one or more drive paths and the voltage regulator controller.

[0117] Clause 21: The method according to Clause 19, further comprising dynamically and in real time determining control settings for each voltage regulator coupled to a power rail based on the load conditions and power condition policies associated with the power rail.

[0118] Clause 22: A non-temporary computer-readable storage medium storing one or more programs configured to be executed by an electronic device having a plurality of voltage regulators electrically coupled to a power rail, wherein the one or more programs, when executed by the electronic device, include instructions causing the electronic device to perform the method described in any one of Clauses 19 to 22.

[0119] Clause 23: An apparatus for driving a power rail in an electronic device having a plurality of voltage regulators electrically coupled to the power rail, comprising at least one means for performing the method described in any one of Clauses 19 to 22.

[0120] The above description is provided in relation to a specific implementation. However, the above illustrative description is not intended to be exhaustive or to limit to the exact form disclosed. Many modifications and variations are possible in relation to the above teaching. The implementations have been selected and described in order to best illustrate the disclosed principles and their practical applications, thereby enabling others to best utilize this disclosure and various implementations with various modifications suitable for the specific intended use.

[0121] The terms used in the descriptions of the various implementations described herein are intended solely to describe, and not to limit, specific implementations. The singular forms “a,” “an,” and “the” used in the descriptions of the various implementations and in the accompanying claims are intended to include the plural form unless the context otherwise clearly indicates. Furthermore, the terms “and / or” as used herein will be understood to refer to and encompass all possible combinations of one or more of the related enumerated items. Moreover, the terms “includes,” “including,” “comprises,” and / or “comprising” as used herein will be understood to indicate the presence of a described feature, integer, step, operation, element, and / or component, but not to exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, while terms such as “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another.

[0122] As used herein, the term “if” shall optionally be interpreted, depending on the context, to mean “when,” “upon,” “in response to having determined,” “in response to having detected,” or “according to the determination that.” Similarly, the phrase “if it is determined that” or “if ‘the stated condition or event’ is detected” shall optionally be interpreted, depending on the context, to mean “when it is determined that,” “in response to having determined,” “when ‘the stated condition or event’ is detected,” “in response to having detected ‘the stated condition or event’,” or “according to the determination that ‘the stated condition or event’ has been detected.”

[0123] While various drawings show several logical stages in a specific order, stages that are not order-dependent may be rearranged, and other stages may be combined or separated. Several reorderings or other groupings are specifically described, but others will be obvious to those skilled in the art, and therefore the orderings and groupings presented herein are not an exhaustive list of alternatives. Furthermore, it should be noted that stages can be implemented in hardware, firmware, software, or any combination thereof.

Claims

1. It is an electronic device, A power rail configured to provide rail voltage, A plurality of voltage regulators configured to be electrically coupled to the power rail and to collectively provide the rail voltage, wherein each of the plurality of voltage regulators is An output interface coupled to the power rail and configured to provide the rail voltage and supply a maximum default regulator current to the power rail, One or more drive paths configured to be coupled to the output interface and operate at an operating frequency, wherein each of the one or more drive paths is A passive load component coupled to the output interface, A driver configured to receive a periodic signal having an operating frequency, modulate the periodic signal, and give a separate phase to a switching signal, A power switching component coupled to the driver and the passive load component, configured to couple the passive load component to one or more DC supply voltages under the control of the switching signal, A drive circuit comprising one or more, A voltage regulator controller having outputs coupled to one or more drive paths and inputs coupled to the output interface by a feedback path, and configured to control one or more drive paths, The one or more drive paths and the bypass unit coupled to the voltage regulator controller, Includes multiple voltage regulators, It is equipped with, Each of the plurality of voltage regulators is configured to operate in one of the following modes, according to the control settings: the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller and to bypass the power switching components and passive load components of each drive path, and each voltage regulator operates in a standby mode in which it does not supply current to the power rail; or the bypass unit is disabled to bypass the feedback path and to bypass the power switching components and passive load components of each drive path, and each voltage regulator operates in an operating mode in which it supplies up to the default regulator current to the power rail. Electronic devices.

2. The electronic device according to claim 1, wherein each of the plurality of voltage regulators is configured to transition from the standby mode to the operating mode in accordance with a change in the control setting and to provide the default regulator current to the power rail within a predetermined period.

3. The electronic device according to claim 1, wherein for each voltage regulator, the control setting includes a control value and an operation enable signal, the control value defining the magnitude of the rail voltage, and the operation enable signal controlling each voltage regulator to operate in either the standby mode in which the bypass unit is enabled to bypass the feedback path, or the operation mode in which the bypass unit is disabled to bypass the feedback path.

4. Each of the one or more drive paths is The system further comprises the driver, the power switching component, and a first multiplexer coupled to the bypass unit, wherein the first multiplexer is controlled by the control setting to enable the standby mode, which selects access to the bypass unit and deselects access to the power switching component electrically coupled to the driver in the drive path. Each voltage regulator, The electronic device according to claim 1, further comprising a second multiplexer coupled to the input of the voltage regulator controller, the output interface of the power rail, and the output of the bypass unit, wherein the second multiplexer is configured to be controlled by the control setting in parallel with the first multiplexer, such that the second multiplexer selects the output of the bypass unit and deselects the standby mode which is used to deselect the output interface of the power rail coupled to the input of the voltage regulator controller.

5. The bypass unit includes one or more bypass paths, each bypass path includes a bypass switching component having a bypass switching transistor of a first size, Each driver path has a path switching transistor having a second size, The second size of the path switching transistor is larger than the first size of the bypass switching transistor. The electronic device according to claim 1.

6. The plurality of voltage regulators are electrically coupled to a power array controller, and the power array controller is configured to determine the control settings of each voltage regulator coupled to the power rail. The electronic device according to claim 1, wherein for each voltage regulator, the control settings are dynamically and in real time adjusted by the power array controller based on the load state and power state policy associated with the power rail.

7. The bypass unit includes one or more bypass paths, each bypass path having a bypass switching component and a dummy load component coupled between the bypass switching component and the output of the bypass unit, and each bypass path is configured to bypass each drive path of the feedback path in the standby mode. For each bypass path, each of the dummy load components includes an active filter, The electronic device according to claim 1, wherein the active filter is a second-order Sallen-Key filter.

8. The electronic device according to claim 1, wherein for each voltage regulator, the bypass unit is configured to be electrically isolated from the power rail in the standby mode, to output the rail voltage in the standby mode, and to provide the rail voltage to the input of the voltage regulator controller, and when the standby mode is changed to the operating mode, each voltage regulator is configured to provide the predetermined regulator current to the power rail within a predetermined period.

9. The bypass unit includes one or more bypass switching components and a dummy load component coupled between the one or more bypass switching components and the output of the bypass unit. Each bypass switching component is coupled to its respective drive path in the standby mode. The electronic device according to claim 1, wherein the dummy load component includes one of the active filters, and the active filter is a Sallen-Key filter.

10. The plurality of voltage regulators include a first voltage regulator, a second voltage regulator, and a third voltage regulator. Each of the first and second voltage regulators operates to drive the power rail in the operating mode, and the feedback path of each voltage regulator is enabled between the output interface and the input of each voltage regulator in the operating mode. The third voltage regulator is electrically isolated from the power rail in the standby mode in which the bypass unit of the third voltage regulator is enabled to bypass the feedback path of the third voltage regulator. The electronic device according to claim 1.

11. The electronic device according to claim 1, wherein the plurality of voltage regulators coupled to the power rail are identical to one another.

12. Each voltage regulator has a first AC loop response in the standby mode, and the first AC loop response has a first low-frequency gain, a first cutoff frequency, and a first phase margin. Each voltage regulator has a second AC loop response in the operating mode, and the second AC loop response has a second low-frequency gain, a second cutoff frequency, and a second phase margin. The first difference between the first low-frequency gain and the second low-frequency gain is less than the first threshold, The second difference between the first cutoff frequency and the second cutoff frequency is less than the second threshold, The third difference between the first phase margin and the second phase margin is less than the third threshold. The electronic device according to claim 1.

13. A method for driving electric rails, An electronic device having a plurality of voltage regulators electrically coupled to the power rail, wherein each of the plurality of voltage regulators includes one or more drive paths configured to be coupled to an output interface and operate at an operating frequency, and each of the one or more drive circuits is A passive load component coupled to the output interface, A driver configured to receive a periodic signal having an operating frequency, modulate the periodic signal, and give a separate phase to a switching signal, A power switching component coupled to the driver and the passive load component, configured to couple the passive load component to one or more DC supply voltages under the control of the switching signal, In an electronic device having, Generating rail voltage and rail current to drive the power rail, wherein each voltage regulator has an output interface coupled to the power rail, and is configured to provide the rail voltage and supply a maximum predetermined regulator current to the power rail when the respective voltage regulator is in operating mode. Obtaining control settings for each of the plurality of voltage regulators, and determining whether each of the control settings for each voltage regulator is a standby voltage regulator operating in standby mode or an operating voltage regulator operating in operating mode, In each standby voltage regulator, the standby voltage regulator's bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller and to bypass the power switching components and passive load components of each drive path, so that the standby voltage regulator does not supply current to the power rail. In each operating voltage regulator, the bypass unit is disabled from bypassing the feedback path and from bypassing the power switching components and passive load components of each drive path, so that each voltage regulator supplies current to the power rail. Methods that include...

14. The voltage regulator controller of each of the voltage regulators has an output coupled to one or more drive paths and an input coupled to the output interface by a feedback path, and is configured to control one or more drive paths, and the bypass unit is coupled to one or more drive paths and the voltage regulator controller, The method according to claim 13, further comprising dynamically and in real time determining the control settings for each voltage regulator coupled to the power rail based on the load conditions and power condition policies associated with the power rail.

15. A computer-readable storage medium for storing one or more programs configured to be executed by an electronic device having a plurality of voltage regulators electrically coupled to a power rail, wherein, when the one or more programs are executed by the electronic device, the one or more programs include instructions causing the electronic device to perform the method according to any one of claims 13 or 14.

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