Method for reducing standby power consumption of AC / DC power supplies

Abstract

A standby method for a switching power supply, a switching power supply, a primary side and a secondary side control circuit, which relates to the technical field of secondary side feedback control technology. The method is applied to a switching power supply provided with an opto-coupling circuit. When a mode control signal indicating that the power supply demand of a load device is higher than a preset value is detected, the switching power supply enters the first mode, and the output of the switching power supply is controlled by the opto-coupling circuit. When a mode control signal indicating that the power supply demand of the load device is less than or equal to the preset value is detected, the switching power supply enters the second mode, and the bias current of the opto-coupling circuit is turned off, and the output of the switching power supply is controlled by a drive pulse signal, so as to reduce the bias currents on the primary side and the secondary side of the switching power supply and reduce the standby power consumption of the switching power supply. At this time, since the bias current of the opto-coupling circuit is turned off, the bias currents on both the primary side and the secondary side become 0, so the bias current decreases and the static loss is reduced, and the standby power consumption becomes even lower.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, particularly to the standby method of switching power supplies, switching power supplies, primary side and secondary side control circuits.

Background Art

[0002] FIG. 1 is a structural diagram of a conventional switching power supply. As shown in FIG. 1, specifically, it is an Alternating Current / Direct Current Secondary Side Regulation (AC / DC SSR). A conventional AC / DC SSR generally utilizes a current signal flowing through an optical coupler (OC) through a voltage control loop (CV) or a current control loop (CC) to keep the switching power supply in a stable state under a constant voltage and constant current control mode. In the application of switching power supplies, generally, it is necessary to connect a load and perform corresponding operation control based on the load. When the switching power supply is in the standby state, usually, there are situations where the switching power supply is connected to the load and where the switching power supply is not connected to the load. When a conventional switching power supply is in the standby situation, regardless of whether the load is connected to the switching power supply or not, the burst mode (BM) of the switching power supply is used to reduce standby power consumption. At this time, the bias current flowing through the optical coupler on both the primary side and the secondary side of the switching power supply reaches the maximum value, so the standby power consumption of the switching power supply at this time becomes very large, and the standby power consumption cannot be further reduced by the large bias current.

[0003] In view of the above problems that exist, how to avoid the influence of the bias current and further reduce the standby power consumption of the switching power supply is an issue that those skilled in the art should strive to solve.

Summary of the Invention

[0004] The object of the present invention is to provide a standby method for a switching power supply, a switching power supply, and primary and secondary control circuits for use in avoiding the effects of bias current and further reducing the standby power consumption of the switching power supply.

[0005] To solve the above technical problems, the present invention provides a standby method for a switching power supply that is applied to a switching power supply equipped with an optical coupling circuit. When a mode control signal indicating that the power supply demand of the load device is higher than a preset value is detected, the switching power supply enters the first mode, and the output of the switching power supply is controlled by the optical coupling circuit. The system includes detecting a mode control signal indicating that the power supply demand of the load device is below a preset value, which causes the switching power supply to enter a second mode, turn off the bias current of the optical coupling circuit, and control the output of the switching power supply with a drive pulse signal to reduce the bias currents on the primary and secondary sides of the switching power supply and to reduce the standby power consumption of the switching power supply.

[0006] Furthermore, entering the second mode means To generate a notification signal indicating that the switching power supply enters the second mode based on the bias current of the optical coupling circuit, This includes controlling the secondary control chip based on a notification signal that maintains a first preset time length, and entering a second mode.

[0007] Furthermore, entering the second mode means The primary-side control chip, upon detecting that an inversion has occurred in the level signal of the voltage signal output by the optical coupling circuit, and that the holding time length of the inverted level signal has reached a time threshold, controls the primary-side control chip to enter a second mode. Of these, the time threshold is greater than the maximum duration of the level signal under the first mode, and the duration of the mode control signal, which is controlled by the secondary control chip and indicates that the power supply demand of the load device is less than or equal to a preset value, is greater than the time threshold.

[0008] Furthermore, by turning off the bias current of the optical coupling circuit and controlling the output of the switching power supply with a drive pulse signal, When the primary control chip collects an output voltage deficiency signal indicating that the output voltage is in a deficiency state, the primary control chip outputs a drive pulse signal. This includes putting the switching power supply into a second mode by adjusting the output of the switching power supply based on a drive pulse signal.

[0009] Furthermore, the primary control chip collects an output voltage deficiency signal indicating that the output voltage is in a deficiency state. Determine whether the output voltage in the secondary control chip is less than the first preset output voltage. If the value is small, an output voltage deficiency signal is transmitted to the primary control chip. If the output voltage is not small, this includes not outputting an insufficient output voltage signal.

[0010] Furthermore, This also includes blocking detection by the primary control chip if the primary control chip is within a preset resonance time.

[0011] Furthermore, after controlling the output of the switching power supply with the drive pulse signal, the following steps are taken: The secondary control chip, upon receiving a mode control signal indicating that the power supply demand of the load device is higher than a preset value, outputs a wake-up signal at a preset frequency through a transformer, indicating that the second mode should be exited, and controls the secondary control chip to stop outputting the wake-up signal, and controls the secondary control chip to exit the second mode based on the wake-up signal.

[0012] Furthermore, after outputting a wake-up signal representing the exit of the second mode at a preset frequency through a transformer, This includes controlling the primary control chip to exit the second mode if it is determined that the preset frequency of the wake-up signal is lower than the frequency threshold.

[0013] Furthermore, by turning off the bias current of the optical coupling circuit and controlling the output of the switching power supply with a drive pulse signal, When adjusting the input voltage of the primary auxiliary winding to fall within a preset range, the primary control chip outputs a drive pulse signal. This includes setting the switching power supply to a second mode by adjusting the output of the switching power supply based on the drive pulse signal and the relationship between the input voltage and the output voltage.

[0014] Furthermore, the output of the switching power supply is adjusted based on the drive pulse signal and the relationship between the input voltage and the output voltage. The output voltage is adjusted based on the turns ratio relationship between the input voltage and the output voltage. The turns ratio is the ratio of the number of turns in the secondary winding of the secondary transformer to the number of turns in the primary auxiliary winding.

[0015] Furthermore, after controlling the output of the switching power supply with the drive pulse signal, The primary control chip collects a level signal from the voltage signal output by the optical coupling circuit, and when this inversion occurs in the level signal, and the holding time of the inverted level signal reaches a second preset time length, the secondary control chip is controlled to stop outputting a wake-up signal, and the primary control chip is controlled based on the wake-up signal to exit the second mode.

[0016] Furthermore, This includes the secondary control chip exiting the second mode based on the control of a notification signal that maintains a third preset time length.

[0017] To solve the above technical problems, the present invention further provides a switching power supply in which an optical coupling circuit is coupled between the primary and secondary sides, and the switching power supply further... A mode signal generation circuit is used to detect the power supply demand of a load device of a switching power supply, and generates a second mode control signal when the power supply demand of the load device is below a preset value, A photocoupling control circuit that controls to turn off the bias current of the photocoupling circuit based on the second-mode control signal, A switching power supply output control circuit that generates a first-mode control signal when the power supply demand of the load device is higher than a preset value, controls the switching power supply based on the first-mode control signal to enter the first mode, and controls the output of the switching power supply by the photocoupling circuit. The switching power supply output control circuit controls the switching power supply to enter the second mode based on the second-mode control signal, and controls the output of the switching power supply by a drive pulse signal, thereby reducing the bias current on the primary side and the secondary side of the switching power supply and reducing the standby power consumption of the switching power supply.

[0018] Also, when the switching power supply enters the first mode, the stability of the output of the switching power supply is controlled by adjusting the bias current of the photocoupling circuit.

[0019] Also, the switching power supply output control circuit After receiving the second-mode control signal, generates a notification signal and uses it to notify the primary-side control chip to enter or exit the second mode, so as to control the output of the switching power supply by a drive pulse signal in the switching power supply, reduce the bias current on the primary side and the secondary side of the switching power supply, and reduce the standby power consumption of the switching power supply. A notification signal control circuit; Receives the notification signal and includes a primary-side mode control circuit for controlling the primary-side control chip based on the notification signal to change the operating mode including the first mode or the second mode. Among them, when the power supply demand of the load device is higher than the preset value, the switching power supply enters the first mode, and the output of the switching power supply is controlled by the photocoupling circuit.

[0020] Also, the notification signal control circuit Based on the bias current of the optical coupling circuit, a notification signal indicating that the switching power supply enters the second mode is generated, and a first second-mode entry control circuit for controlling the secondary control chip to enter the second mode based on the notification signal maintaining a first preset time length is included.

[0021] Also, the notification signal control circuit further includes a second second-mode entry control circuit for controlling the primary control chip to enter the second mode when the primary control chip collects that an inversion occurs in the level signal of the voltage signal output by the optical coupling circuit and the holding time length of the inverted level signal reaches a time threshold, wherein the time threshold is greater than the maximum value of the duration of the level signal in the first mode, and the duration of the mode control signal indicating that the power supply demand of the load device controlled by the secondary control chip is below a preset value is greater than the time threshold.

[0022] Also, the primary side mode control circuit includes a first second-mode maintenance control circuit for outputting a drive pulse signal in the primary control chip and adjusting the output of the switching power supply based on the drive pulse signal to make the switching power supply enter the second mode when the primary control chip collects an output voltage shortage signal indicating that the output voltage is in a voltage shortage state.

[0023] Also, the primary side mode control circuit further includes a first judgment circuit for judging whether the output voltage in the secondary control chip is smaller than a first preset output voltage, and if the output voltage is smaller than the first preset output voltage, transmitting an output voltage shortage signal to the primary control chip.

[0024] Also, further includes a first shielding circuit for blocking the detection of the primary control chip when the primary control chip is within a preset resonance time.

[0025] Also, the notification signal control circuit further The secondary side includes a first secondary side second mode exit control circuit for controlling the secondary side control chip to exit the second mode based on the wake-up signal, which is a wake-up signal of a preset frequency, through a transformer, when the secondary side control chip has collected a mode control signal indicating that the power supply demand of the load device is higher than a preset value, and for controlling the secondary side control chip to stop outputting the wake-up signal, and for controlling the secondary side control chip to exit the second mode based on the wake-up signal.

[0026] Furthermore, the notification signal control circuit is further described as follows: The system includes a first primary-side second-mode exit control circuit for controlling the primary-side control chip to exit the second mode if it is determined that the preset frequency of the wake-up signal is lower than a frequency threshold.

[0027] Furthermore, the primary mode control circuit is further: The circuit includes a second second-mode maintenance control circuit that, when the input voltage of the primary-side auxiliary winding is adjusted to be within a preset range, outputs a drive pulse signal at the primary-side control chip and adjusts the output of the switching power supply based on the drive pulse signal and the relationship between the input voltage and the output voltage, thereby putting the switching power supply into second mode.

[0028] Furthermore, the primary mode control circuit is further: It includes a first adjustment circuit for adjusting the output voltage based on the turns ratio relationship between the input voltage and the output voltage, where the turns ratio relationship is the ratio of the number of turns of the secondary winding of the secondary transformer to the number of turns of the auxiliary winding on the primary side.

[0029] Furthermore, the notification signal control circuit is further described as follows: The system includes a second primary-side second-mode exit control circuit for controlling the secondary-side control chip to stop outputting a wake-up signal when an inversion occurs in the level signal of the voltage signal output by the optical coupling circuit, collected by the primary-side control chip, and the holding time length of the inverted level signal reaches a second preset time length, and for controlling the primary-side and secondary-side control chips to exit the second mode based on the wake-up signal.

[0030] Furthermore, the notification signal control circuit is further described as follows: The system includes a second secondary second-mode exit control circuit for the secondary control chip to exit the second mode based on the control of a notification signal that maintains a third preset time length.

[0031] Furthermore, the mode signal generation circuit includes at least a mode control signal interface and a second mode control unit. The mode control signal interface is used to transmit a mode control signal, which indicates that the power supply demand of a load device is higher than a preset value, in correspondence with the second mode control unit.

[0032] Furthermore, the optical coupling control circuit includes at least a secondary-side first switch tube and a secondary-side second switch tube. The first end of the secondary first switch tube is connected to the optical coupling circuit, the second end of the secondary first switch tube is grounded, the control end of the secondary first switch tube is connected to the first end of the secondary second switch tube, the second end of the secondary second switch tube is grounded, and the control end of the secondary second switch tube is connected to the second mode unit.

[0033] To solve the above technical problems, the present invention further provides a secondary control circuit for a switching power supply, wherein an optical coupling circuit is coupled between the primary and secondary sides of the switching power supply, and the secondary control circuit is A mode signal generation circuit is used to detect the power supply demand of a load device of a switching power supply, and generates a second mode control signal when the power supply demand of the load device is below a preset value, An optical coupling control circuit that controls the bias current of the optical coupling circuit to be turned off based on the second mode control signal, The circuit includes a notification signal control circuit that, after receiving a second-mode control signal, generates a notification signal and uses it to notify the primary-side control chip that it has entered or exited the second mode, thereby causing the switching power supply to control its output with a drive pulse signal, reducing the bias currents on the primary and secondary sides of the switching power supply, and reducing the standby power consumption of the switching power supply.

[0034] Furthermore, the notification signal control circuit is The system includes a third second-mode entry control circuit that generates a notification signal indicating that the switching power supply is entering a second mode based on the bias current of the optical coupling circuit, and controls a secondary-side control chip to enter the second mode based on the notification signal which maintains a first preset time length.

[0035] Furthermore, the notification signal control circuit is further described as follows: The primary-side control chip includes a fourth second-mode entry control circuit to control the primary-side control chip to enter the second mode when it detects that an inversion has occurred in the level signal of the voltage signal output by the optical coupling circuit and that the holding time length of the inverted level signal has reached a time threshold. Of these, the time threshold is greater than the maximum duration of the level signal under the first mode, and the duration of the mode control signal, which is controlled by the secondary control chip and indicates that the power supply demand of the load device is less than or equal to a preset value, is greater than the time threshold.

[0036] Furthermore, the notification signal control circuit is further described as follows: The secondary side includes a mode control circuit that, when the secondary side control chip collects a mode control signal indicating that the power supply demand of the load device is higher than a preset value, outputs a wake-up signal through a transformer at a preset frequency indicating exit from the second mode, and controls the secondary side control chip to stop outputting the wake-up signal, and controls the secondary side control chip to exit from the second mode based on the wake-up signal.

[0037] Furthermore, the notification signal control circuit is further described as follows: The system includes a third primary-side second-mode exit control circuit for controlling the primary-side control chip to exit the second mode if it is determined that the preset frequency of the wake-up signal is lower than a frequency threshold.

[0038] Furthermore, the notification signal control circuit is further described as follows: The system includes a fourth primary-side second-mode exit control circuit for controlling the secondary-side control chip to stop outputting a wake-up signal when an inversion occurs in the level signal of the voltage signal output by the optical coupling circuit, collected by the primary-side control chip, and the holding time length of the inverted level signal reaches a second preset time length, and for controlling the primary-side and secondary-side control chips to exit the second mode based on the wake-up signal.

[0039] Furthermore, the notification signal control circuit is further described as follows: The system includes a fourth secondary second-mode exit control circuit for the secondary control chip to exit the second mode based on the control of a notification signal that maintains a third preset time length.

[0040] To solve the above technical problems, the present invention further provides a primary-side control circuit for a switching power supply, wherein an optical coupling circuit is coupled between the primary and secondary sides of the switching power supply, and the primary-side control circuit is A drive pulse signal generation circuit, coupled to the power switch of a switching power supply, controls the conduction and disconnection of the power switch by generating a drive pulse signal, It includes a primary mode control circuit for receiving notification signals, controlling a primary control chip based on the notification signals, and changing the operating mode.

[0041] Furthermore, the primary mode control circuit is The primary-side control chip includes a third second-mode maintenance control circuit to put the switching power supply into a second mode by outputting a drive pulse signal in the primary-side control chip when it collects an output voltage deficiency signal indicating that the output voltage is in a deficiency state, and adjusting the output voltage of the switching power supply based on the drive pulse signal.

[0042] Furthermore, the primary mode control circuit is further: The system includes a second determination circuit that determines whether the output voltage in the secondary control chip is lower than a first preset output voltage, and if the output voltage is lower than the first preset output voltage, transmits an output voltage shortage signal to the primary control chip.

[0043] Furthermore, The system includes a second shielding circuit to block detection of the primary side control chip when the primary side control chip is within a preset resonance time.

[0044] Furthermore, the primary mode control circuit is further: The circuit includes a fourth second mode maintenance control circuit for putting the switching power supply into second mode by adjusting the input voltage of the primary auxiliary winding to be within a preset range, outputting a drive pulse signal at the primary control chip, and adjusting the output of the switching power supply based on the drive pulse signal and the relationship between the input voltage and the output voltage.

[0045] Furthermore, the primary mode control circuit is further: It includes a second adjustment circuit for adjusting the output voltage based on the turns ratio relationship between the input voltage and the output voltage, where the turns ratio relationship is the ratio of the number of turns of the secondary winding of the secondary transformer to the number of turns of the auxiliary winding on the primary side.

[0046] The standby method for a switching power supply provided in this invention is applied to a switching power supply equipped with an optical coupling circuit. When a mode control signal indicating that the power supply demand of the load device is higher than a preset value is detected, the switching power supply enters a first mode and the output of the switching power supply is controlled by the optical coupling circuit. When a mode control signal indicating that the power supply demand of the load device is less than or equal to a preset value is detected, the switching power supply enters a second mode, the bias current of the optical coupling circuit is turned off, and the output of the switching power supply is controlled by a drive pulse signal. This reduces the bias current on both the primary and secondary sides of the switching power supply and reduces the standby power consumption of the switching power supply. At this time, since the bias current of the optical coupling circuit is turned off, both the primary and secondary bias currents become 0, so the bias current is reduced and static losses are reduced, resulting in even lower standby power consumption.

[0047] The present invention further provides a standby method for a switching power supply, a switching power supply, and primary and secondary control circuits, the effects of which are as described above.

[0048] To more clearly illustrate embodiments of the present invention, the following briefly introduces the drawings necessary for use in the embodiments. However, the drawings in the following description represent only some embodiments of the present invention, and it will be obvious to those skilled in the art that other drawings can be obtained based on these drawings without any creative work. [Brief explanation of the drawing]

[0049] [Figure 1] Figure 1 shows the structure of a conventional switching power supply. [Figure 2] Figure 2 is a structural diagram of the OC device. [Figure 3] Figure 3 shows the waveform of a conventional switching power supply in burst mode. [Figure 4] Figure 4 is a flowchart of the standby method for the switching power supply provided in an embodiment of the present invention. [Figure 5] Figure 5 is a structural diagram of the first switching power supply provided in an embodiment of the present invention. [Figure 6] Figure 6 is a waveform diagram of sleep mode entry corresponding to the first switching power supply provided in an embodiment of the present invention. [Figure 7] Figure 7 is a waveform diagram of sleep mode exit corresponding to the first switching power supply provided in an embodiment of the present invention. [Figure 8] Figure 8 is a structural diagram of a second switching power supply provided in an embodiment of the present invention. [Figure 9] Figure 9 is a waveform diagram of sleep mode entry corresponding to the second switching power supply provided in an embodiment of the present invention. [Figure 10] Figure 10 is a waveform diagram of sleep mode exit corresponding to the second switching power supply provided in an embodiment of the present invention. [Modes for carrying out the invention]

[0050] The following describes the technical methods in embodiments of the present invention clearly and completely, in conjunction with the drawings of the embodiments; however, it is clear that the embodiments described are only a part of the embodiments of the present invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention, without any creative work, fall within the scope of the present invention.

[0051] The core of the present invention is to provide a standby method for a switching power supply, a switching power supply, and primary and secondary control circuits that can further reduce the standby power consumption of the switching power supply by avoiding the effects of bias current.

[0052] To help those skilled in the art better understand the method of the present invention, the present invention is described in more detail below, linking the drawings with specific embodiments.

[0053] Figure 1 shows the structure of a conventional switching power supply. As shown in Figure 1, the primary and secondary sides of the transformer T1 are defined in the switching power supply. The primary side of the switching power supply generally consists of an AC power supply, a rectifier bridge DB, an input capacitor Cbulk, a starting resistor R3, the primary coil of the transformer T1 (also called the primary winding), an NMOS transistor Qp (also called a power switch, coupled to the primary winding of the transformer T1), a current sampling resistor R4, a control chip Controller, a rectifier diode D1, and the triode portion of the OC device. It should be noted that in a more preferred embodiment, a voltage divider resistor R1, a voltage divider resistor R2, a constant voltage capacitor Cvcc, and an auxiliary winding Rf are also installed. The control chip has six additional pins, which are represented as DEM, HV, VCC, COMP, GATE, and CS. The secondary side of a switching power supply generally consists of a voltage divider resistor R5, a voltage divider resistor R6, a constant voltage capacitor Cout, a resistor R7 connected to the output terminal, the diode portion of the OC device, a compensation capacitor Ccomp, a triode Q1, an amplifier U1, a Bais module, a rectifier diode D2, and the secondary coil (also called the secondary winding) of the transformer T1. Of these, the triode Q1, amplifier U1, and Bais module constitute the secondary OC controller OCRDV. Generally, OCRDV is called the secondary controller (secondary control chip), and the Controller is called the primary controller (primary control chip). Figure 2 is a structural diagram of an OC device. As shown in Figure 2, the left side of the OC device is the triode portion, and the right side is the diode portion. At the same time, the triode portion is usually located on the primary side, and the diode portion is usually located on the secondary side. When applied to actual production, the OC device is a single device, but it can be understood that it is represented separately when creating a schematic diagram within the circuit domain for ease of description. It should be further explained that the triode in the OC device is generally an NPN transistor. At the same time, the bias current flowing through the OC device on the primary side is represented as IOC_C, and the bias current flowing through the OC device on the secondary side is represented as IOC_LED.Since the OC device is an optical coupling element, the secondary diode is an LED lamp, and when current flows, the diode emits light. The description of the OC device mentioned above is only one of many embodiments, and its specific embodiment will be determined based on the implementation scenario, so it should be understood that the present invention is not limited thereto.

[0054] For output terminals where the switching power supply is in standby mode, there are typically two types of load conditions. One is when the load is connected to the switching power supply (in this case, the power supply demand of the load device is higher than the preset value). For ease of understanding, this can be understood as the situation when charging a mobile phone with a switching power supply, where the phone is fully charged but the connection between the mobile phone and the switching power supply is not disconnected. When the mobile phone and the switching power supply are connected, there are further light load (generally expressed as Light Load) and heavy load (generally expressed as Heavy Load) conditions. Specifically, the load condition can be determined by setting preset values ​​for the load, and of course, the embodiment can be determined based on the actual implementation scenario. The other is when the load and the switching power supply are disconnected (in this case, the power supply demand of the load device is below the preset value). For ease of understanding, this can be understood as the situation when charging a mobile phone with a switching power supply, where the phone is fully charged but the connection between the mobile phone and the switching power supply is disconnected. In this case, the example is whether or not the mobile phone is connected to the switching power supply, but in actual production processes, it can be applied to other scenarios as well, and specifically, it can be determined based on the embodiment, so the present invention is not limited to this. Under no-load conditions, the preset value is 0. Similarly, if the preset value is 5 (or another value determined based on a specific implementation scenario), a load between 0 and 5 is considered a light load, and a load of 5 or more is considered a heavy load.

[0055] Conventional switching power supplies use a CV or CC control loop to feed back the secondary bias current of the OC device to the primary side. In such switching power supplies, as the load at the secondary output terminal decreases, the secondary bias current IOC_LED increases. In a steady state, IOC_C = CTR × IOC_LED, where CTR is the current transmission ratio of the OC. At this time, regardless of how the load conditions change, the switching power supply always uses the first mode (burst mode) to keep the switching power supply in standby mode. At this time, both IOC_C and IOC_LED are at their maximum values, so it is not possible to further reduce standby losses. It should be further explained that in actual application processes, the burst mode can be further divided into shallow burst mode and deep burst mode.

[0056] When using burst mode for power standby, specifically, As the load decreases, the secondary output voltage (Vout) increases, the secondary bias current IOC_LED increases, the primary bias current IOC_C increases at the same rate, the voltage received by the COMP pin decreases, and when the COMP voltage falls below BML (low threshold reference voltage for burst mode), the primary enters burst mode, the GATE stops outputting drive pulses, and after energy transmission stops, the secondary output voltage (Vout) begins to decrease, and as the secondary output voltage (Vout) decreases, the secondary bias current IOC_LED decreases, the primary bias current IOC_C decreases at the same rate, the primary COMP voltage increases, and when the COMP voltage exceeds BMH (high threshold reference voltage for burst mode), the primary control chip exits burst mode, the GATE outputs a periodic drive pulse signal, energy is recovered and transmitted from the primary to the secondary, and the secondary output voltage (Vout) begins to increase.

[0057] Figure 3 shows the waveform of a conventional switching power supply under burst mode. As shown in Figure 3, as the load at the secondary output terminal decreases, the voltage at the COMP pin of the primary control chip decreases. When the COMP voltage falls below BML, the system enters a shallow burst mode, with a larger proportion of pulse output time and a smaller proportion of no-pulse time. When the load and power supply are disconnected, the system enters a deep burst mode, with a smaller proportion of pulse output time and a larger proportion of no-pulse time. At this time, the corresponding maximum bias current appears on both the primary and secondary sides of the OC device. When COMP drops from being higher than BMH to being between BML and BMH, the GATE outputs an output, some modules recover, and ICCP increases (ICCP is 2mA at this time). When COMP rises from being lower than BML to being between BML and BMH, the GATE stops outputting an output, some modules shut down, and ICCP decreases (ICCP is 300uA at this time). When COMP is between BML and BMH, whether or not the GATE outputs an output depends on the state of COMP before it was in operation.

[0058] When burst mode is used and a 100uA level bias current IOC_C is required for the OC on the primary side, the ICC is generally not less than 300uA. Under normal operation, the control chip's DEM pin detects a resonant waveform (which is caused by the capacitance between the primary coil and the Qp drain), and when Qp is driven by this, the output voltage turns on and / or is detected at the bottom of the resonant waveform. When entering burst mode, the GATE does not output a drive pulse, so any signal detected by the DEM pin is not considered at this time, and the detection function of the DEM pin may be turned off to reduce losses.

[0059] Figure 4 is a flowchart of a standby method for a switching power supply provided in an embodiment of the present invention. As shown in Figure 4, this method is applied to a switching power supply equipped with an optical coupling element. S40: When a mode control signal indicating that the power supply demand of the load device is higher than a preset value is detected, the switching power supply enters the first mode, and the output of the switching power supply is controlled by the optical coupling circuit. S41: When a mode control signal indicating that the power supply demand of the load device is below a preset value is detected, the switching power supply enters the second mode, the bias current of the optical coupling circuit is turned off, and the output of the switching power supply is controlled by a drive pulse signal, including the following: At this time, it is possible to reduce the bias current on the primary and secondary sides of the switching power supply, and to reduce the standby power consumption of the switching power supply.

[0060] First, it must be explained that the first mode is burst mode, the second mode is sleep mode, and simultaneously, the mode control signals C1 and C2 represent the relationship between the power supply demand of the load device and a preset value, and the mode control signal that activates sleep mode is any combination of C1 and C2. For example, if the mode control signal indicating that the power supply demand of the load device is higher than the preset value is set to be represented by both C1 and C2 signals being high-level signals, both being low-level signals, or four sets of 2-bit binary data (00, 01, 10, 11), then if the data after combining C1 and C2 is 00 or 01, it indicates that the mode control signal indicates that the power supply demand of the load device is higher than the preset value. Of course, if the data after combining C1 and C2 could also be 10 or 11, then the specific embodiment of the mode control signal indicating that the power supply demand of the load device is higher than the preset value can be determined based on the specific implementation scenario, and it should be understood that this embodiment does not limit it.

[0061] From this, it can be seen that in this embodiment, since the bias current of the optical coupling circuit is turned off, both the primary and secondary bias currents become 0, thereby reducing the bias current and simultaneously reducing static losses, and further lowering standby power consumption.

[0062] Among these, the embodiment in which the secondary side enters the second mode based on the standby method of the switching power supply mentioned above is: A notification signal is generated indicating that the switching power supply enters the second mode based on the bias current of the optical coupling circuit. The system controls the secondary control chip based on a notification signal that maintains the first preset time length, and then enters the second mode.

[0063] Among these, the notification signal that indicates the switching power supply is entering the second mode, which is generated based on the bias current of the optical coupling circuit, is denoted as the Iting signal. It should be explained that the Iting signal is part of the bias current of the optical coupling circuit, and the first preset time length maintained by the notification signal is denoted as T1, with a preferred embodiment being T1 = 240 ms.

[0064] In an embodiment where the primary side enters the second mode, The primary control chip detects that an inversion has occurred in the level signal of the voltage signal output by the optical coupling circuit, and that the duration of the inverted level signal has reached a time threshold. In this case, the primary control chip is controlled to enter the second mode. Of these, the time threshold is greater than the maximum duration of the level signal under the first mode, and the duration of the mode control signal, which is controlled by the secondary control chip and indicates that the power supply demand of the load device is less than or equal to a preset value, is greater than the time threshold.

[0065] To maintain the switching power supply in the second mode, the present invention provides two types of embodiments, which are specifically as follows.

[0066] Among these, the first embodiment, which maintains the switching power supply in the second mode, When the primary control chip collects an output voltage deficiency signal indicating that the output voltage is in a deficiency state, the primary control chip outputs a drive pulse signal. This method involves adjusting the output of the switching power supply based on the drive pulse signal, thereby putting the switching power supply into a second mode.

[0067] Furthermore, the primary control chip collects an output voltage undervoltage signal indicating that the output voltage is in an undervoltage state. Determine whether the output voltage in the secondary control chip is less than the first preset output voltage. If the value is small, an output voltage deficiency signal is transmitted to the primary control chip. If the output voltage is not small, this includes not outputting an insufficient output voltage signal.

[0068] In this embodiment, the first preset output voltage is set to 4V, the output voltage in the secondary control chip is defined as Vout, and by detecting within the secondary control chip, the relationship between Vout and 4V is compared in the comparator U2 to determine whether or not there is an output voltage deficiency signal. If Vout is greater than 4V, no output voltage deficiency signal is output, and there is no drive pulse signal at the GATE pin. If Vout is less than 4V, an output voltage deficiency signal is transmitted, and there is a drive pulse signal at the GATE pin. When the drive pulse signal is output, the output of the switching power supply is controlled by the power switch Qp and the transformer T1. In this embodiment, the drive pulse signal is labeled Idrive.

[0069] Furthermore, when the GATE pin outputs a drive pulse signal, it may generate a resonant signal with the internal capacitance of the power switch Qp. To avoid the self-excited condition that may arise from this resonant signal, detection of the primary side control chip is blocked when the primary side control chip is within a preset resonant time.

[0070] In response to this, the first embodiment in which the secondary control chip exits the second mode specifically describes the following: After controlling the output of the switching power supply with the drive pulse signal, further, The secondary control chip, upon receiving a mode control signal indicating that the power supply demand of the load device is higher than a preset value, outputs a wake-up signal at a preset frequency through a transformer, indicating that the second mode should be exited, and controls the secondary control chip to stop outputting the wake-up signal, and controls the secondary control chip to exit the second mode based on the wake-up signal.

[0071] In response to this, the first embodiment in which the primary control chip exits the second mode specifically describes the following: After outputting a wake-up signal representing the exit of the second mode at a preset frequency through a transformer, This includes controlling the primary control chip to exit the second mode if it is determined that the preset frequency of the wake-up signal is lower than the frequency threshold.

[0072] In a second embodiment in which the switching power supply is maintained in the second mode, By turning off the bias current of the optical coupling circuit and controlling the output of the switching power supply with a drive pulse signal, When adjusting the input voltage of the primary auxiliary winding to fall within a preset range, the primary control chip outputs a drive pulse signal. This includes setting the switching power supply to a second mode by adjusting the output of the switching power supply based on the drive pulse signal and the relationship between the input voltage and the output voltage.

[0073] At this time, the input voltage of the primary auxiliary winding is denoted as VCC, and whether or not the switching power supply remains in the second mode is determined based on whether or not VCC is within a preset range. In this process, the relationship between VCC and 7.6V and 8.1V is detected, and if VCC falls below 7.6V, the GATE pin outputs a drive pulse signal, and if VCC exceeds 8.1V, no drive pulse signal is output to the GATE pin.

[0074] Furthermore, adjusting the output of a switching power supply based on the relationship between the input voltage and the output voltage is possible. This involves adjusting the output voltage based on the turns ratio relationship between the input voltage and the output voltage. The turns ratio relationship is the ratio of the number of turns in the secondary winding of the secondary transformer to the number of turns in the auxiliary winding on the primary side, and can be expressed by the formula Vout = VCC * Ns / Na, where Na represents the number of turns in the auxiliary winding coil and Ns represents the number of turns in the secondary coil.

[0075] In response to this, a second embodiment in which the primary control chip exits the second mode specifically describes the following: After controlling the output of the switching power supply with the drive pulse signal, further, The primary control chip collects a level signal from the voltage signal output by the optical coupling circuit, and when this inversion occurs in the level signal, and the holding time of the inverted level signal reaches a second preset time length, the secondary control chip is controlled to stop outputting a wake-up signal, and the primary control chip is controlled based on the wake-up signal to exit the second mode.

[0076] Of these, the second pre-set time length is denoted as T2.

[0077] In response to this, a second embodiment in which the secondary control chip exits the second mode specifically describes the following: This includes controlling the secondary control chip to exit the second mode based on a notification signal that maintains a third preset time length.

[0078] Of these, the third pre-set time length is denoted as T3.

[0079] Based on the above, it should be further explained that the switching power supply provided in the embodiment of the present invention generally has three operating processes, specifically as follows: First, the normal operating mode, which, according to the above embodiment relating to mobile phone charging, is the normal charging state of the mobile phone. Second, when charging a mobile phone with a switching power supply, it can be understood as a situation where the phone is fully charged but the connection between the mobile phone and the switching power supply is not broken. Third, when charging a mobile phone with a switching power supply, it can be understood as a situation where the phone is fully charged but the connection between the mobile phone and the switching power supply is broken. When the relationship between the switching power supply and the load is in the second state, the first mode is used to reduce the power consumption of the switching power supply, and in this case, two methods, magnetic coupling and optical coupling, are used. When the relationship between the switching power supply and the load is in the third state, the second mode is used to reduce the power consumption of the switching power supply, and in this case, only the magnetic coupling method is used.

[0080] The standby method for a switching power supply provided in this invention is applied to a switching power supply equipped with an optical coupling circuit. When a mode control signal indicating that the power supply demand of the load device is higher than a preset value is detected, the switching power supply enters a first mode and controls the output of the switching power supply by the optical coupling circuit. When a mode control signal indicating that the power supply demand of the load device is less than or equal to a preset value is detected, the switching power supply enters a second mode, the bias current of the optical coupling circuit is turned off, and the output of the switching power supply is controlled by a drive pulse signal, thereby reducing the bias current on both the primary and secondary sides of the switching power supply and reducing the standby power consumption of the switching power supply. At this time, since the bias current of the optical coupling circuit is turned off, both the primary and secondary bias currents become 0, so the bias current is reduced, static losses are reduced, and standby power consumption is further reduced.

[0081] It is understandable that the standby method for switching power supplies applies to power supply systems that use OC within a CV or CC control loop, including but not limited to topological structures such as Flyback and LLC, where the switching power supply may be an AC / DC SSR power supply. The switching power supply provided in this embodiment has an optical coupling circuit coupled between the primary and secondary sides, and the switching power supply further... A mode signal generation circuit is used to detect the power supply demand of a load device of a switching power supply, and generates a second mode control signal when the power supply demand of the load device is below a preset value, An optical coupling control circuit that controls the bias current of the optical coupling circuit to be turned off based on the second mode control signal, A switching power supply output control circuit for generating a first mode control signal when the power supply demand of a load device is higher than a preset value, controlling a switching power supply to enter the first mode based on the first mode control signal, and controlling the output of the switching power supply by an optical coupling circuit, the switching power supply output control circuit for controlling the switching power supply to enter the second mode based on a second mode control signal, and controlling the output of the switching power supply by a drive pulse signal, thereby reducing the bias currents on the primary and secondary sides of the switching power supply and reducing the standby power consumption of the switching power supply. When the switching power supply enters the first mode, the stability of the output of the switching power supply is controlled by adjusting the bias current of the optical coupling circuit.

[0082] In some embodiments, the switching power supply output control circuit is A notification signal control circuit generates a notification signal after receiving a second-mode control signal and uses it to notify the primary-side control chip that it has entered or exited the second mode, thereby causing the switching power supply to control its output with a drive pulse signal, reducing the bias current on the primary and secondary sides of the switching power supply, and reducing the standby power consumption of the switching power supply. Includes a primary mode control circuit that receives a notification signal and controls a primary control chip based on the notification signal to change the operating mode, including a first mode or a second mode, If the power supply demand of the load device is higher than a preset value, the switching power supply enters the first mode, and the output of the switching power supply is controlled by the optical coupling circuit.

[0083] In some embodiments, the notification signal control circuit is The system includes a first second-mode entry control circuit that generates a notification signal indicating that the switching power supply is entering a second mode based on the bias current of the optical coupling circuit, and controls a secondary-side control chip to enter the second mode based on the notification signal which maintains a first preset time length.

[0084] In some embodiments, the notification signal control circuit is further modified. The primary-side control chip includes a second second-mode entry control circuit to control the primary-side control chip to enter the second mode when it detects that an inversion has occurred in the level signal of the voltage signal output by the optical coupling circuit and that the holding time length of the inverted level signal has reached a time threshold. Of these, the time threshold is greater than the maximum duration of the level signal under the first mode, and the duration of the mode control signal, which is controlled by the secondary control chip and indicates that the power supply demand of the load device is less than or equal to a preset value, is greater than the time threshold.

[0085] In some embodiments, the primary mode control circuit is: The primary-side control chip includes a first second-mode maintenance control circuit to put the switching power supply into a second mode by, upon receiving an output voltage deficiency signal indicating that the output voltage is in a deficiency state, outputting a drive pulse signal at the primary-side control chip and adjusting the output of the switching power supply based on the drive pulse signal.

[0086] In some embodiments, the primary mode control circuit is further, The system includes a first determination circuit for determining whether the output voltage in the secondary control chip is lower than a first preset output voltage, and for transmitting an output voltage shortage signal to the primary control chip if the output voltage is lower than the first preset output voltage.

[0087] In some embodiments, a first shielding circuit is further included to block detection of the primary side control chip when the primary side control chip is within a preset resonance time.

[0088] In some embodiments, the notification signal control circuit is further modified. The secondary side includes a first secondary side second mode exit control circuit for controlling the secondary side control chip to exit the second mode based on the wake-up signal, which is a wake-up signal of a preset frequency, through a transformer, when the secondary side control chip has collected a mode control signal indicating that the power supply demand of the load device is higher than a preset value, and for controlling the secondary side control chip to stop outputting the wake-up signal, and for controlling the secondary side control chip to exit the second mode based on the wake-up signal.

[0089] In some embodiments, the notification signal control circuit is further modified. The system includes a first primary-side second-mode exit control circuit for controlling the primary-side control chip to exit the second mode if it is determined that the preset frequency of the wake-up signal is lower than a frequency threshold.

[0090] In some embodiments, the primary mode control circuit is further, The circuit includes a second second-mode maintenance control circuit that, when the input voltage of the primary-side auxiliary winding is adjusted to be within a preset range, outputs a drive pulse signal at the primary-side control chip and adjusts the output of the switching power supply based on the drive pulse signal and the relationship between the input voltage and the output voltage, thereby putting the switching power supply into second mode.

[0091] In some embodiments, the primary mode control circuit is further, It includes a first adjustment circuit for adjusting the output voltage based on the turns ratio relationship between the input voltage and the output voltage, where the turns ratio relationship is the ratio of the number of turns of the secondary winding of the secondary transformer to the number of turns of the auxiliary winding on the primary side.

[0092] In some embodiments, the notification signal control circuit is further modified. The primary side control chip collects a level signal from the output voltage of the optical coupling circuit, and when an inversion occurs in the level signal, and the holding time length of the inverted level signal reaches a second preset time length, the primary side control chip controls the secondary side control chip to stop outputting a wake-up signal, and the primary side control chip controls the primary side and secondary side control chips based on the wake-up signal to exit the second mode.

[0093] In some embodiments, the notification signal control circuit is further modified. The system includes a second secondary second-mode exit control circuit for the secondary control chip to exit the second mode based on the control of a notification signal that maintains a third preset time length.

[0094] Figure 5 is a structural diagram of a first switching power supply provided in an embodiment of the present invention. As shown in Figure 5, in some embodiments, the mode signal generation circuit includes at least a mode control signal interface (C1, C2) and a second mode control unit (Sleep Mode). The mode control signal interface is used to transmit a mode control signal, which indicates that the power supply demand of the load device is higher than a preset value, to the second mode control unit. The optical coupling control circuit includes at least a secondary first switch tube Q2 and a secondary second switch tube Q3. The first end of the secondary first switch tube is connected to the optical coupling circuit, the second end of the secondary first switch tube is grounded, the control end of the secondary first switch tube is connected to the first end of the secondary second switch tube, the second end of the secondary second switch tube is grounded, and the control end of the secondary second switch tube is connected to the second mode unit.

[0095] The secondary control chip further includes the following circuit structures, specifically: The second mode control unit, Sleep Mode, is installed inside the secondary control chip where the mode control signal interfaces (C1, C2) are located. The relationship between Vout and 4V is compared to determine whether or not there is an output voltage deficiency signal. If Vout is greater than 4V, the output voltage deficiency signal is not sent, and the GATE pin does not output a drive pulse signal. If Vout is less than 4V, the output voltage deficiency signal is sent, and the GATE pin outputs a drive pulse signal. If there is an output of a drive pulse signal, the power switch Qp and transformer T1 control the output of the switching power supply with a secondary amplifier U2. The output terminal of the secondary amplifier U2 is connected to the first terminal of the oscillator OSC, the second terminal of the oscillator OSC is connected to the control terminal of the secondary drive switch tube Q4, the first terminal of the secondary drive switch tube Q4 is connected to the secondary winding of the transformer T1, and the second terminal of the secondary drive switch tube Q4 is grounded. Furthermore, a DC bias circuit Bias2 is installed, which is connected to both OSC and Sleep Mode. The control terminal of the secondary second switch tube Q3 is connected to the DC bias circuit Bias2, the first terminal of the secondary second switch tube Q3 is connected to the output terminal of comparator U6, and the second terminal of the secondary second switch tube Q3 is grounded. The control terminal of the secondary first switch tube Q2 is connected to the output terminal of comparator U6, the first terminal of the secondary first switch tube Q2 is connected to the optically coupled switch tube, and the second terminal of the secondary first switch tube Q2 is grounded. The positive-sequence input terminal of comparator U6 is connected to Ccomp, and the negative-sequence input terminal of comparator U6 (a voltage of 2.5V is input) is connected to the DC bias circuit Bias2, which is also connected to R5.

[0096] In response to this, the primary control chip further includes the following circuit structure, specifically: The DC bias circuit Bias1, located inside the primary control chip, has four input and output ports labeled VDD, UVLO, PSL, and Vref. Of these, the UVLO port is connected to the output terminal of comparator U4, the output terminal of comparator U5 receives the Hold signal, and comparator U4 controls the voltage passing through it between 18V and 6.7V. Comparator U5 controls the voltage passing through it between 18V and 7.6V and is connected to the output pin HV of the primary control chip via diode D3, parallel switch tubes for receiving signals corresponding to UVLO and Hold, and a constant current source H.First, let's describe the two input terminals of the primary-side first amplifier U3. The positive-sequence input terminal must be connected to a voltage of 50mV, and the negative-sequence input terminal must be connected to the output pin DEM of the primary-side control chip. The output terminal of the primary-side first amplifier U3 is connected to the Valley Lock OSC module, and then sequentially to the DFF module. The Valley Lock OSC module has multiple pins, which are COMP and Pulse, respectively. The Pulse pin is connected to the output terminal of the primary-side first amplifier U3. Similarly, the DFF module has multiple pins, which are D (for external power input, and the value is VDD), CLK, RB, and Q. The DFF module is connected to the Valley Lock OSC module via the CLK pin. The Q pin is connected to the AND gate, and the output terminal of the AND gate is connected to the drive amplifier Driver. The AND gate has two input terminals, one of which is connected to the Valley Lock The output terminal of the OSC module is connected, and the other input terminal is connected to the Q pin of the DFF module. The output terminal of the drive amplifier Driver outputs a drive pulse signal as the GATE of the pin, and this drive pulse signal is used to drive Qp. The RB pin of the Driver is also connected to a NAND gate, the first output terminal of the NAND gate is connected to the output terminal of comparator U7, and the second output terminal of the NAND gate is connected to the output terminal of comparator U8. The positive-sequence input terminal of comparator U7 has a voltage of 0.8V. The reverse-phase input terminal of comparator U7 is connected to the COMP pin, the positive-phase input terminal of comparator U8 is connected to the common terminals of R9 and R10, the other end of R10 is grounded, the other end of R9 is connected to the cathode of diode D4, the anode of diode D4 is connected to one end of R8, the other end of R8 is connected to the second end of switch tube PSL, the first end of switch tube PSL is connected to the external power supply VDD, the reverse-phase input terminal of comparator U7 is connected to the CS pin, and resistor R4 is externally connected to the CS pin, with the other end of R4 grounded.Furthermore, in the primary control chip, the signals that control the second mode control unit Sleep Mode are Brust, Pulse, and PSL, respectively. Of these, Brust is the signal at the output terminal of comparator U7, PSL is the signal at the control terminal of switch tube PSL, and Pulse is the signal at the output terminal of primary side first amplifier U3.

[0097] It should be explained that in this structure, the connection status between the load and the power supply is detected by signals C1 and C2 on the USB interface connected to the load. In a specific embodiment, if both signals C1 and C2 are at a high level (i.e., the mode control signal is 11), it indicates that the load and the switching power supply are disconnected, and at this time, Sleep Mode (SM) is activated. Reconnection to the peripheral circuit of the OCDRV is performed, and modules corresponding to Sleep Mode, OSC modules, amplifiers, etc. are installed. Of these, it should be explained in detail that the secondary amplifier U2 is used to detect whether or not the output voltage is insufficient, and the set voltage insufficiency threshold is 4V. Of course, the voltage insufficiency threshold includes 4V, but it is not limited to this value, and other values ​​may be used, and can be determined based on the specific implementation scene. Further explanation should be given to the module corresponding to Sleep Mode. This module also has an Itring signal drive installed, and when the secondary bias current is set to 0, the corresponding secondary first switch tube Q2 also turns off. The internal circuitry of the primary control chip also needs to be reconnected. Of course, there can be various connection methods for the internal circuitry of the control chip, and Figure 5 shows only one of many embodiments. It should be understood that the specific embodiment should be determined based on the concrete implementation scenario.

[0098] If it is determined that the load and switching power supply are disconnected, sleep mode is activated. Specifically, this is done as follows:

[0099] By setting the OC bias current to 0 (IOC_LED=0), the secondary current loss can be reduced by an order of magnitude to the 100uA level. Vout is controlled by magnetic coupling, monitored, and if a voltage deficiency occurs, an excitation pulse signal (IDrive) is output and transmitted to the primary side via the transformer. At this time, the GATE outputs a drive pulse signal, transmitting energy to the secondary side to maintain the stability of the output voltage. This voltage deficiency signal is unrelated to the resonant waveform and represents only a voltage deficiency at Vout.

[0100] When the secondary OC bias current is set to 0 (IOC_LED=0), the OC characteristics cause the primary OC bias current (IOC_C) to synchronously drop to 0, stopping the operation of the CV or CC control loop based on OC feedback. This reduces both primary and secondary current losses by an order of magnitude, and system standby losses can be reduced to 5mW or less.

[0101] The output voltage (Vout) can be controlled by a CV control loop based on magnetic coupling. After the secondary side enters sleep mode, the output voltage (Vout) is detected, and the OC bias current (IOC_LED) is turned off. If Vout is undervoltage, an undervoltage signal IDrive is sent and transmitted to the primary side DEM pin by the transformer; if Vout is not undervoltage, the undervoltage signal is not sent.

[0102] After the primary side enters sleep mode, it monitors the DEM pin signal and pulls down the ICC. When it detects a voltage deficiency signal transmitted by the secondary side at the DEM pin, the GATE outputs a drive pulse signal to maintain the secondary side output voltage.

[0103] The output voltage Vout can also be indirectly controlled by controlling the primary side VCC. After the primary side enters sleep mode, the VCC voltage is monitored and the ICC is lowered. If a VCC voltage deficiency is detected, the GATE outputs a drive pulse signal to maintain the VCC voltage within a certain range. The output voltage Vout maintains the relationship between the VCC voltage and the turns ratio (Na / Ns).

[0104] It should be explained at the beginning that if the load is connected to the power supply at this time (Attached), the standby of the power supply will continue to be maintained in burst mode. However, if the load is disconnected from the power supply (which can be represented by Detached), the standby of the power supply will be maintained in sleep mode. When the sleep mode is activated, the high-level drive of the SSL signal indicating the activation of the sleep mode is used.

[0105] Figure 6 is a waveform diagram of the entry into sleep mode corresponding to the first switching power supply provided in an embodiment of the present invention. As shown in Figure 6, when the secondary side enters the sleep mode (SSL = H), IOC_LED is set to 0 (at this time, this signal can also be represented by the Iopto signal). At the same time, the Itrig signal is set to 2 mA and held for a T1 time (240 ms). After the elapse of the T1 time, the Itrig signal becomes 0 A. The quiescent current at this time drops to 150 μA. When the 2 mA Itrig signal makes the primary side COMP lower than BML, the primary side enters burst mode. At this time, GATE does not output a drive pulse signal. After the burst mode on the primary side lasts for a T2 time (180 ms, T2 < T1), the primary side enters the sleep mode. After the T1 time, the bias current (IOC_C) on the primary side decreases synchronously to 0. At this time, the quiescent current drops to 30 μA.

[0106] In sleep mode, the standby power consumption of the power supply can be reduced to 5 mW or less, and the secondary side directly monitors the output voltage Vout. When Vout < 4V, a voltage shortage signal IDrive (a 30 mA current pulse with a width of 1 μs and a period of 300 μs) is transmitted and transmitted to the primary side DEM pin through the transformer. When Vout ≥ 4V, no voltage shortage signal is transmitted.

[0107] After the primary side enters burst mode or sleep mode, the signal of the DEM pin is detected. When the DEM pin detects the voltage shortage signal transmitted by the secondary side, GATE outputs a drive pulse signal to maintain the secondary side output voltage. If the DEM pin does not detect the voltage shortage signal, GATE does not output a drive pulse signal.

[0108] During the process of the primary side entering sleep mode, it enters burst mode during the T2 time zone. In this process, the constant voltage control loop based on OC feedback stops operating, and at this time, the GATE does not output a drive pulse signal. When energy transmission stops, the output voltage Vout continues to drop, potentially falling below the minimum operating voltage of the secondary side, causing a voltage shortage at the secondary side chip. If a voltage shortage occurs, the secondary side will stop operating, and the power supply system will not be able to function properly. Therefore, in burst mode, the primary side also needs to detect and respond to the voltage shortage signal at the DEM pin.

[0109] Since a resonant signal may appear at the DEM pin after the primary side outputs the drive pulse signal, the primary side needs to block detection of the DEM pin during the resonant time period to avoid self-excitation.

[0110] Figure 7 shows the waveform diagram of sleep mode exit corresponding to the first switching power supply provided in an embodiment of the present invention. As shown in Figure 7, when the load is reconnected, the secondary side exits sleep mode and transmits a wake-up signal IDrive (a 30mA current pulse with a width of 1us and a period of 200us), which is transmitted to the DEM pin via the transformer. At this time, the quiescent current returns to normal. Specifically, the following occurs: In sleep mode, if the primary side detects that the pulse period of the DEM pin signal is less than 250us, the primary side exits sleep mode, the primary side COMP returns to normal bias, the voltage is determined by the loop, and at this time, the quiescent current returns to normal.

[0111] Based on the above embodiments, the present invention further provides the following embodiments, and Figure 8 is a structural diagram of a second switching power supply provided in an embodiment of the present invention. As shown in Figure 8, compared to the structure shown in Figure 5, the secondary control chip further includes the following circuit structure, specifically, This is the second mode control unit, Sleep Mode, located inside the secondary control chip, where the mode control signal interfaces (C1, C2) are installed. The output terminal of the second mode control unit Sleep Mode outputs an SSL signal and is connected to the first terminal of the DC bias circuit Bias2. The control terminal of the secondary second switch tube Q3 is connected to the DC bias circuit Bias2. The first terminal of the secondary second switch tube Q3 is connected to the output terminal of comparator U6. The second terminal of the secondary second switch tube Q3 is grounded. The control terminal of the secondary first switch tube Q2 is connected to the output terminal of comparator U6. The first terminal of the secondary first switch tube Q2 is connected to the optical coupling switch tube. The second terminal of the secondary first switch tube Q2 is grounded. The positive-sequence input terminal of comparator U6 is connected to Ccomp. The negative-sequence input terminal of comparator U6 (a voltage of 2.5V is input) is connected to the DC bias circuit Bias2, which is also connected to R5.

[0112] In response to this, the primary control chip further includes the following circuit structure, specifically: The DC bias circuit Bias1, located inside the primary control chip, has four input and output ports labeled VDD, UVLO, PSL, and Vref. Of these, the UVLO port is connected to the output terminal of comparator U4. Comparator U4 controls the voltage passing through it between 18V and 6.7V and is connected to the output pin HV of the primary control chip via diode D3, switch tube UVLO, and constant current source H. First, let's describe the two input terminals of the primary first amplifier U3. The positive-sequence input terminal must receive a voltage of 50mV, and the negative-sequence input terminal must be connected to the output pin DEM of the primary control chip. The output terminal of the primary first amplifier U3 is connected to the Valley Lock OSC module, and then sequentially to the DFF module. The OSC module has multiple pins, each labeled COMP and Pulse. The Pulse pin is connected to the output terminal of the primary-side first amplifier U3. Similarly, the DFF module has multiple pins, each labeled D (for external power input, with a value of VDD), CLK, RB, and Q. The DFF module is connected to the Valley Lock OSC module via the CLK pin. The Q pin of the DFF module is connected to the AND gate, and the output terminal of the AND gate is connected to the drive amplifier Driver. The AND gate has two input terminals, one of which is connected to the Valley Lock. The OSC module's output terminal is connected to the Q pin of the DFF module, and the other input terminal is connected to the Q pin of the DFF module. The output terminal of the drive amplifier Driver outputs a drive pulse signal as the GATE of the pin, and this drive pulse signal is used to drive Qp. The RB pin of the DFF module is also connected to the AND gate, of which the first output terminal of the AND gate is connected to the input terminal of the NOA gate, the second output terminal of the AND gate is connected to the output terminal of comparator U8, the first output terminal of the NOA gate is connected to the output terminal of comparator U7, and the second output terminal of the NOA gate is connected to the output terminal of comparator U9. Comparator U9 has three input terminals, and the voltage values ​​of the three input terminals are 8.1V and 7.The voltage is 6V, VCC. Comparator U7 has three input terminals, two of which have voltage values ​​BMH and BML, respectively, and the other input terminal is connected to the COMP pin. The positive-sequence input terminal of comparator U8 is connected to the common terminals of R9 and R10, the other end of R10 is grounded, the other end of R9 is connected to the second terminal of switch tube PSL, the first terminal of switch tube PSL is connected to the cathode of diode D4, the anode of diode D4 is connected to one end of R8, the other end of R8 is connected to the external power supply VDD, the negative-sequence input terminal of comparator U8 is connected to the CS pin, and resistor R4 is externally connected to the CS pin, with the other end of R4 being grounded. In addition, on the primary side control chip, the signals that control the second mode unit Sleep Mode are Brust and PSL, of which Brust is the signal from the output terminal of comparator U7, and PSL is the signal from the control terminal of switch tube PSL. .

[0113] It should be noted first that if a load is attached to the power supply at this time, the standby of the power supply continues to be maintained in burst mode. Only when the load and the power supply are detached, the standby of the power supply is maintained in sleep mode. When the sleep mode is activated, a high-level drive of the SSL signal indicating the activation of the sleep mode is used. Fig. 9 is a waveform diagram of the entry into sleep mode corresponding to the second switching power supply provided in the embodiment of the present invention. As shown in Fig. 9, when the secondary side enters the sleep mode (SSL = H), the secondary side bias current at this time is 0A, Itrig is 2mA, and it is maintained for a T1 time (240ms). After the T1 time, Itrig becomes 0A. At this time, the quiescent current drops to 150uA. When the Itrig signal is 2mA, if the primary side COMP is made lower than BML, the primary side enters burst mode and GATE does not output a drive pulse signal. When the primary side persists in burst mode for a T2 time (180ms, T2 < T1), the primary side enters sleep mode. After the T1 time, the primary side COMP rises to VDD, but the bias current IOC_C is 0. At this time, the quiescent current drops to 30uA. In sleep mode, the standby power consumption of the power supply can be reduced to 5mW or less, and the primary side indirectly controls the output voltage by adjusting VCC. If VCC < 7.6V, GATE outputs a periodic drive pulse signal and the VCC voltage rises. If VCC > 8.1V, GATE stops outputting the drive pulse signal and the VCC voltage drops. The output voltage Vout at this time is approximately equal to VCC * Ns / Na.

[0114] FIG. 10 is a waveform diagram of the sleep mode exit corresponding to the second switching power supply provided in the embodiment of the present invention. As shown in FIG. 10, when the load is reconnected, the secondary side exits the sleep mode. If the Itrig signal is set to 2 mA and held for the T3 time (1 ms), the Itrig signal after the T3 time becomes 0 A. At this time, the quiescent current returns to normal. In the sleep mode, when the primary side chip detects the falling edge of COMP and the low level of COMP lasts for the T4 time (0.5 ms, T4 < T3), the primary side exits the sleep mode. The primary side COMP after the T3 time is determined by the loop. At this time, the quiescent current returns to normal.

[0115] In addition, in the present invention, a secondary side control circuit and a primary side control circuit of the switching power supply are provided respectively. Specifically, A secondary side control circuit of the switching power supply, wherein an opto-coupling circuit is coupled between the primary side and the secondary side of the switching power supply, and the secondary side control circuit includes A mode signal generation circuit used to detect the power supply demand of the load device of the switching power supply, and generate a second mode control signal when the power supply demand of the load device is below a preset value; An opto-coupling control circuit that controls to turn off the bias current of the opto-coupling circuit based on the second mode control signal; After receiving the second mode control signal, a notification signal is generated and used to notify the primary side control chip to enter or exit the second mode, so as to control the output of the switching power supply by a drive pulse signal in the switching power supply, reduce the bias currents of the primary side and the secondary side of the switching power supply, and reduce the standby power consumption of the switching power supply. The notification signal control circuit.

[0116] In some embodiments, the notification signal control circuit includes The system includes a third second-mode entry control circuit that generates a notification signal indicating that the switching power supply is entering a second mode based on the bias current of the optical coupling circuit, and controls a secondary-side control chip to enter the second mode based on the notification signal which maintains a first preset time length.

[0117] In some embodiments, the notification signal control circuit is further modified. The primary-side control chip includes a fourth second-mode entry control circuit to control the primary-side control chip to enter the second mode when it detects that an inversion has occurred in the level signal of the voltage signal output by the optical coupling circuit and that the holding time length of the inverted level signal has reached a time threshold. Of these, the time threshold is greater than the maximum duration of the level signal under the first mode, and the duration of the mode control signal, which is controlled by the secondary control chip and indicates that the power supply demand of the load device is less than or equal to a preset value, is greater than the time threshold.

[0118] In some embodiments, the notification signal control circuit is further modified. The secondary side includes a mode control circuit that, when the secondary side control chip collects a mode control signal indicating that the power supply demand of the load device is higher than a preset value, outputs a wake-up signal through a transformer at a preset frequency indicating exit from the second mode, and controls the secondary side control chip to stop outputting the wake-up signal, and controls the secondary side control chip to exit from the second mode based on the wake-up signal.

[0119] In some embodiments, the notification signal control circuit is further modified. The system includes a third primary-side second-mode exit control circuit for controlling the primary-side control chip to exit the second mode if it is determined that the preset frequency of the wake-up signal is lower than a frequency threshold.

[0120] In some embodiments, the notification signal control circuit is further modified. The primary side control chip collects a level signal from the output voltage of the optical coupling circuit, and when an inversion occurs in the level signal, and the holding time length of the inverted level signal reaches a second preset time length, the primary side control chip controls the secondary side control chip to stop outputting a wake-up signal, and a fourth primary side second mode exit control circuit controls the primary side and secondary side control chips based on the wake-up signal to exit the second mode.

[0121] In some embodiments, the notification signal control circuit is further modified. The system includes a fourth secondary second-mode exit control circuit for the secondary control chip to exit the second mode based on the control of a notification signal that maintains a third preset time length.

[0122] This is a primary-side control circuit for a switching power supply, wherein an optical coupling circuit is connected between the primary and secondary sides of the switching power supply, and the primary-side control circuit is A drive pulse signal generation circuit, coupled to the power switch of a switching power supply, controls the conduction and disconnection of the power switch by generating a drive pulse signal, It includes a primary mode control circuit for receiving notification signals, controlling a primary control chip based on the notification signals, and changing the operating mode.

[0123] In some embodiments, the primary mode control circuit is: The primary-side control chip includes a third second-mode maintenance control circuit to put the switching power supply into a second mode by outputting a drive pulse signal in the primary-side control chip when it collects an output voltage deficiency signal indicating that the output voltage is in a deficiency state, and adjusting the output voltage of the switching power supply based on the drive pulse signal.

[0124] In some embodiments, the primary mode control circuit is further, The system includes a second determination circuit for determining whether the output voltage in the secondary control chip is lower than a first preset output voltage, and for transmitting an output voltage shortage signal to the primary control chip if the output voltage is lower than the first preset output voltage.

[0125] In some examples, further, The system includes a second shielding circuit to block detection of the primary side control chip when the primary side control chip is within a preset resonance time.

[0126] In some embodiments, the primary mode control circuit is further, The circuit includes a fourth second mode maintenance control circuit for putting the switching power supply into second mode by adjusting the input voltage of the primary auxiliary winding to be within a preset range, outputting a drive pulse signal at the primary control chip, and adjusting the output of the switching power supply based on the drive pulse signal and the relationship between the input voltage and the output voltage.

[0127] In some embodiments, the primary mode control circuit is further, It includes a second adjustment circuit for adjusting the output voltage based on the turns ratio relationship between the input voltage and the output voltage, where the turns ratio relationship is the ratio of the number of turns of the secondary winding of the secondary transformer to the number of turns of the auxiliary winding on the primary side.

[0128] As described above, the standby method for the switching power supply, the switching power supply, and the primary and secondary control circuits provided by the present invention have been introduced in detail. Each embodiment of the specification is described in a gradual manner, but each embodiment focuses on explaining the differences from other embodiments, and parts that are the same or similar between embodiments can be referred to from one another. The apparatus disclosed in the embodiments corresponds to the method disclosed in the embodiments and is described relatively simply, so for relevant points, please refer to the explanation in the method section. Those skilled in the art may make some improvements and modifications to the present invention, provided that they do not depart from the principles of the present invention, but it should be noted that such improvements and modifications are also included within the scope of protection of the claims of the present invention.

[0129] It should be further explained that, in this specification, relational terms such as "first," "second," etc., are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any substantial relationship or order between these entities or operations. Furthermore, the terms "encompassing," "including," or any other variations of the terms cover non-exclusive inclusion, so that a process, method, article, or equipment containing a set of elements may not only include those elements, but also other elements not explicitly listed, or elements specific to that kind of process, method, article, or equipment. In circumstances without further restriction, the element limited by the phrase "including one..." does not preclude the existence of another identical element in a process, method, article, or equipment containing the aforementioned element.

Claims

1. In a standby method for switching power supplies, this method is applied to switching power supplies equipped with an optical coupling circuit. When a mode control signal indicating that the power supply demand of the load device is higher than a preset value is detected, the switching power supply enters a first mode, and the output of the switching power supply is controlled by the optical coupling circuit. When the mode control signal indicating that the power supply demand of the load device is less than or equal to the preset value is detected, the switching power supply enters a second mode, the bias current of the optical coupling circuit is turned off, and the output of the switching power supply is controlled by a drive pulse signal, thereby reducing the bias currents on the primary and secondary sides of the switching power supply and reducing the standby power consumption of the switching power supply. Entering the second mode means Based on the bias current of the optical coupling circuit, a notification signal is generated indicating that the switching power supply enters the second mode. This includes controlling the secondary control chip based on the notification signal that maintains a first preset time length, and entering the second mode. How to keep a switching power supply in standby mode.

2. Entering the second mode means The primary control chip is controlled to enter the second mode when it detects that an inversion has occurred in the level signal of the voltage signal output by the optical coupling circuit, and that the holding time length of the inverted level signal has reached a time threshold. The time threshold is greater than the maximum duration of the level signal under the first mode, and the duration of the mode control signal, which is controlled by the secondary control chip and indicates that the power supply demand of the load device is less than or equal to the preset value, is greater than the time threshold. A method for standbying a switching power supply according to claim 1.

3. By turning off the bias current of the optical coupling circuit and controlling the output of the switching power supply with a drive pulse signal, When the primary control chip collects an output voltage deficiency signal indicating that the output voltage is in a voltage deficiency state, the primary control chip outputs the drive pulse signal. The invention is characterized by including adjusting the output of the switching power supply based on the drive pulse signal to put the switching power supply into the second mode, A method for standbying a switching power supply according to claim 1.

4. The primary control chip collects an output voltage deficiency signal indicating that the output voltage is in a voltage deficiency state. This involves determining whether the output voltage in the secondary control chip is less than the first preset output voltage, If the value is small, the output voltage deficiency signal is transmitted to the primary control chip. The following features include: not outputting the output voltage deficiency signal if the output voltage is not small, A method for standbying a switching power supply according to claim 3.

5. The present invention further includes blocking detection of the primary side control chip when the primary side control chip is within a preset resonance time. A standby method for a switching power supply according to any one of claims 1 to 4.

6. After controlling the output of the switching power supply with the aforementioned drive pulse signal, further, The secondary control chip, upon receiving a mode control signal indicating that the power supply demand of the load device is higher than the preset value, outputs a wake-up signal at a preset frequency through a transformer, indicating that the second mode should be exited; controls the secondary control chip to stop the output of the wake-up signal; and controls the secondary control chip based on the wake-up signal to exit the second mode. A method for standbying a switching power supply according to claim 1.

7. After outputting the wake-up signal, which indicates the exit of the second mode at a preset frequency, through the transformer, The method is characterized by including controlling the primary control chip to exit the second mode when it is determined that the preset frequency of the wake-up signal is smaller than a frequency threshold. The standby method for a switching power supply according to claim 6.

8. By turning off the bias current of the optical coupling circuit and controlling the output of the switching power supply with a drive pulse signal, When adjusting the input voltage of the primary auxiliary winding to fall within a preset range, the primary control chip outputs the drive pulse signal. The method is characterized by including adjusting the output of the switching power supply based on the drive pulse signal and the relationship between the input voltage and the output voltage to put the switching power supply into the second mode. A method for standbying a switching power supply according to claim 1.

9. The output of the switching power supply is adjusted based on the relationship between the drive pulse signal, the input voltage, and the output voltage. This includes adjusting the output voltage based on the turns ratio relationship between the input voltage and the output voltage, wherein the turns ratio relationship is the ratio of the number of turns of the secondary winding of the secondary transformer to the number of turns of the auxiliary winding on the primary side. The standby method for a switching power supply according to claim 8.

10. After controlling the output of the switching power supply with the aforementioned drive pulse signal, further, The primary control chip collects the level signal of the voltage signal output by the optical coupling circuit, and when an inversion occurs in the level signal and the holding time length of the inverted level signal reaches a second preset time length, the secondary control chip is controlled to stop the output of the wake-up signal, and the primary control chip is controlled based on the wake-up signal to exit the second mode. The standby method for a switching power supply according to claim 6.

11. The third mode is further characterized by controlling the secondary control chip based on the notification signal that maintains a preset time length, and exiting the second mode. A method for standbying a switching power supply according to claim 1.

12. In a switching power supply in which an optical coupling circuit is coupled between the primary and secondary sides, the switching power supply further comprises: A mode signal generation circuit is used to detect the power supply demand of the load device of the switching power supply, and generates a second mode control signal when the power supply demand of the load device is less than or equal to a preset value, An optical coupling control circuit that controls the bias current of the optical coupling circuit to be turned off based on the second mode control signal, A switching power supply output control circuit for generating a first mode control signal when the power supply demand of the load device is higher than the preset value, controlling the switching power supply to enter a first mode based on the first mode control signal, and controlling the output of the switching power supply by the optical coupling circuit, comprising: a switching power supply output control circuit for controlling the switching power supply to enter a second mode based on a second mode control signal, and controlling the output of the switching power supply by a drive pulse signal, thereby reducing the bias currents on the primary and secondary sides of the switching power supply and reducing the standby power consumption of the switching power supply, When the switching power supply enters the first mode, the stability of the output of the switching power supply is controlled by adjusting the bias current of the optical coupling circuit. Switching power supply.

13. The aforementioned switching power supply output control circuit is A notification signal control circuit for reducing the standby power consumption of a switching power supply, which, after receiving the second mode control signal, generates a notification signal and uses it to notify the primary side control chip that it has entered or exited the second mode, thereby causing the switching power supply to control the output of the switching power supply with the drive pulse signal, reducing the bias current on the primary and secondary sides of the switching power supply, and reducing the standby power consumption of the switching power supply, Includes a primary mode control circuit for receiving the notification signal and controlling the primary control chip based on the notification signal to change the operating mode, including the first mode or the second mode, The switching power supply enters the first mode and controls the output of the switching power supply by the optical coupling circuit when the power supply demand of the load device is higher than the preset value. The switching power supply according to claim 12.

14. The notification signal control circuit, The circuit is characterized by including a first second mode entry control circuit for generating a notification signal indicating that the switching power supply enters the second mode based on the bias current of the optical coupling circuit, and for controlling the secondary side control chip to enter the second mode based on the notification signal which maintains a first preset time length. The switching power supply according to claim 13.

15. The notification signal control circuit further, The primary-side control chip includes a second second-mode entry control circuit for controlling the primary-side control chip to enter the second mode when it detects that an inversion has occurred in the level signal of the voltage signal output by the optical coupling circuit and that the holding time length of the inverted level signal has reached a time threshold. The time threshold is greater than the maximum duration of the level signal under the first mode, and the duration of the second mode control signal, which is controlled by the secondary control chip and indicates that the power supply demand of the load device is less than or equal to the preset value, is greater than the time threshold. The switching power supply according to claim 13.

16. The primary side mode control circuit, The primary side control chip collects an output voltage deficiency signal indicating that the output voltage is in a voltage deficiency state, and the primary side control chip outputs the drive pulse signal, and the first second mode maintenance control circuit is included which adjusts the output of the switching power supply based on the drive pulse signal to put the switching power supply into the second mode. The switching power supply according to claim 13.

17. The primary side mode control circuit further, The invention includes a first determination circuit for determining whether the output voltage in the secondary control chip is smaller than a first preset output voltage, and if the output voltage is smaller than the first preset output voltage, for transmitting an output voltage shortage signal to the primary control chip. The switching power supply according to claim 16.

18. The invention further includes a first shielding circuit for blocking detection of the primary side control chip when the primary side control chip is within a preset resonance time, The switching power supply according to claim 12.

19. The notification signal control circuit further, The secondary control chip collects a mode control signal indicating that the power supply demand of the load device is higher than the preset value, and outputs a wake-up signal at a preset frequency, indicating that the second mode should be exited, through a transformer, and controls the secondary control chip to stop the output of the wake-up signal, and includes a first secondary second mode exit control circuit for controlling the secondary control chip to exit the second mode based on the wake-up signal. The switching power supply according to claim 14.

20. The notification signal control circuit further, The system is characterized by including a first primary-side second-mode exit control circuit for controlling the primary-side control chip to exit the second mode when it is determined that the preset frequency of the wake-up signal is smaller than a frequency threshold, The switching power supply according to claim 19.

21. The primary side mode control circuit further, When the input voltage of the primary auxiliary winding is adjusted to be within a preset range, the primary control chip outputs the drive pulse signal, and the output of the switching power supply is adjusted based on the drive pulse signal and the relationship between the input voltage and the output voltage, thereby including a second second mode maintenance control circuit for putting the switching power supply into the second mode. The switching power supply according to claim 13.

22. The primary side mode control circuit further, The system includes a first adjustment circuit for adjusting the output voltage based on the turns ratio relationship between the input voltage and the output voltage, wherein the turns ratio relationship is the ratio of the number of turns of the secondary winding of the secondary transformer to the number of turns of the auxiliary winding on the primary side. The switching power supply according to claim 21.

23. The notification signal control circuit further, The primary side control chip collects the level signal of the voltage signal output by the optical coupling circuit, and when an inversion occurs in the level signal and the holding time length of the inverted level signal reaches a second preset time length, the primary side control chip controls the secondary side control chip to stop the output of the wake-up signal, and the primary side and secondary side control chips control the wake-up signal to exit the second mode, and the primary side control chip controls the second side and secondary side control chips based on the wake-up signal, and the control chip is characterized by including a second primary side second mode exit control circuit for exiting the second mode. The switching power supply according to claim 19.

24. The notification signal control circuit further, The invention is characterized by including a second secondary second mode exit control circuit for the secondary control chip to exit the second mode based on the control of a notification signal that maintains a third preset time length, The switching power supply according to claim 13.

25. The mode signal generation circuit includes at least a mode control signal interface and a second mode control unit. The mode control signal interface is used to transmit a mode control signal, corresponding to the second mode control unit, indicating that the power supply demand of the load device is higher than the preset value. The switching power supply according to claim 12.

26. The optical coupling control circuit includes at least a secondary first switch tube and a secondary second switch tube. The first end of the secondary first switch tube is connected to the optical coupling circuit, the second end of the secondary first switch tube is grounded, the control end of the secondary first switch tube is connected to the first end of the secondary second switch tube, the second end of the secondary second switch tube is grounded, and the control end of the secondary second switch tube is connected to the second mode control unit. The switching power supply according to claim 12.

27. In a secondary control circuit of a switching power supply in which an optical coupling circuit is coupled between the primary and secondary sides, A mode signal generation circuit is used to detect the power supply demand of the load device of the switching power supply, and generates a second mode control signal when the power supply demand of the load device is less than or equal to a preset value, An optical coupling control circuit that controls the bias current of the optical coupling circuit to be turned off based on the second mode control signal, The notification signal control circuit includes, after receiving the second mode control signal, generating a notification signal and using it to notify the primary side control chip that it has entered or exited the second mode, thereby causing the switching power supply to control its output with a drive pulse signal, reducing the bias currents on the primary and secondary sides of the switching power supply, and reducing the standby power consumption of the switching power supply, The notification signal control circuit, The circuit includes a third second mode entry control circuit that generates a notification signal indicating that the switching power supply enters the second mode based on the bias current of the optical coupling circuit, controls the secondary side control chip based on the notification signal which maintains a first preset time length, and enters the second mode. Secondary control circuit of a switching power supply.

28. The notification signal control circuit further, The primary-side control chip includes a fourth second-mode entry control circuit for controlling the primary-side control chip to enter the second mode when it detects that an inversion has occurred in the level signal of the voltage signal output by the optical coupling circuit and that the holding time length of the inverted level signal has reached a time threshold. The secondary control circuit of the switching power supply according to claim 27.

29. The notification signal control circuit further, The secondary control chip, upon receiving a mode control signal indicating that the power supply demand of the load device is higher than the preset value, outputs a wake-up signal at a preset frequency through a transformer indicating that the second mode should be exited, and controls the secondary control chip to stop the output of the wake-up signal, and includes a third secondary second mode exit control circuit for controlling the secondary control chip to exit the second mode based on the wake-up signal. The secondary control circuit of the switching power supply according to claim 27.

30. The notification signal control circuit further, The system is characterized by including a third primary-side second-mode exit control circuit for controlling the primary-side control chip to exit the second mode when it is determined that the preset frequency of the wake-up signal is smaller than a frequency threshold, The secondary control circuit of the switching power supply according to claim 29.

31. The notification signal control circuit further, The primary side control chip collects a level signal from the optical coupling circuit, and when an inversion occurs in the level signal of the voltage signal output by the optical coupling circuit, and the holding time length of the inverted level signal reaches a second preset time length, the primary side control chip controls the secondary side control chip to stop the output of the wake-up signal, and the primary side control chip controls the wake-up signal to exit the second mode, and the primary side control chip controls the wake-up signal to exit the second mode, and the control chip is further controlled to exit the second mode. The secondary control circuit of the switching power supply according to claim 29.

32. The notification signal control circuit further, The invention is characterized by including a fourth secondary second mode exit control circuit for the secondary control chip to exit the second mode based on the control of a notification signal that maintains a third preset time length, The secondary control circuit of the switching power supply according to claim 27.

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