Display boards and display devices

Abstract

To provide a display substrate and display device.SOLUTION: A display substrate provided herein comprises a base substrate and sub-pixels provided on the base substrate, where each sub-pixel has a pixel circuit comprising a data write-in sub-circuit, a storage sub-circuit, a drive sub-circuit and a resistor that is connected between a light-emitting element and the drive sub-circuit. The resistor and a control electrode of the drive sub-circuit are insulatively arranged on the same layer. Resistivity of the resistor is higher than that of the control electrode of the drive sub-circuit. The display substrate has a good effect in solving the problem of pixel circuit failure.SELECTED DRAWING: Figure 2A

Description

Technical Field

[0001] This application is a divisional application of the invention patent application with the application number 2022-503870 and the invention title "display substrate and display device". Embodiments of the present disclosure relate to a display substrate and a display device.

Background Art

[0002] Micro OLED (Micro Organic Light Emitting Diode) displays relate to the combination of organic light emitting diode (OLED) technology and CMOS technology, are related to the mutual integration of the optoelectronics industry and the microelectronics industry, promote the development of next-generation microdisplay technology, and promote the research and development of organic electronics on silicon and even molecular electronics on silicon.

[0003] Micro OLED (Micro Organic Light Emitting Diode) displays have excellent display characteristics such as high resolution, high brightness, rich colors, low drive voltage, high response speed, and low power consumption, and are expected to have future potential.

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of the present disclosure provides a display substrate comprising a base substrate and subpixels on the base substrate, wherein the subpixels include a pixel circuit comprising a data writing subcircuit, a recording subcircuit, a driving subcircuit, and a resistor. The data writing subcircuit is electrically connected to a first terminal of the recording subcircuit and configured to transmit a data signal to the first terminal of the recording subcircuit in response to a control signal; the driving subcircuit includes a control electrode, a first electrode, and a second electrode, wherein the control electrode of the driving subcircuit is electrically connected to the first terminal of the recording subcircuit and configured to receive a first power supply voltage; the second electrode of the driving subcircuit is electrically connected to a first terminal of a resistor and the second terminal of the resistor is used to electrically connect to a first electrode of a light-emitting element; the driving subcircuit is configured to drive the light-emitting element to emit light in response to a voltage at the first terminal of the recording subcircuit; the resistor is insulated and installed on the same layer as the control electrode of the driving subcircuit, and the resistivity of the resistor is higher than the resistivity of the control electrode of the driving subcircuit.

[0005] In some examples, both the resistor and the control electrode of the drive subcircuit are made of polycrystalline silicon.

[0006] In some examples, the control signal includes a first control signal, the data writing subcircuit includes a first data writing transistor, the drive subcircuit includes a drive transistor, the first data writing transistor is a P-type metal-oxide-semiconductor field-effect transistor, the drive transistor is an N-type metal-oxide-semiconductor field-effect transistor, the gate of the first data writing transistor is configured to receive the first control signal, the first pole of the first data writing transistor is configured to receive the data signal, the second pole of the first data writing transistor is electrically connected to the first terminal of the recording subcircuit and the control electrode of the drive subcircuit, and the gate, first pole, and second pole of the drive transistor are the control electrode, first electrode, and second electrode of the drive subcircuit, respectively.

[0007] In some examples, a PN junction is formed between the second electrode of the drive subcircuit and the base substrate, and the resistance value of the resistor is set so that the PN junction turns off when the drive transistor operates in the saturation region.

[0008] In some examples, the resistance value of the resistor is

number

[0009] In some examples, the recording subcircuit includes a storage capacitor, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second capacitor electrode are the first and second terminals of the recording subcircuit, respectively, and the first capacitor electrode is insulated and installed on the same layer as the resistor.

[0010] In some examples, the first data writing transistor and the drive transistor are located on opposite sides of the storage capacitor in a direction parallel to the substrate surface of the base substrate.

[0011] In some examples, the resistor and the first data writing transistor are located on the same side of the first capacitor electrode in a direction parallel to the substrate surface of the base substrate.

[0012] In some examples, the resistor has a U-shaped structure, the opening of the U-shaped structure faces the first capacitor electrode, and the first and second terminals of the resistor are located at the two ends of the U-shaped structure, respectively.

[0013] In some examples, the second terminal of the resistor is closer to the drive transistor in a direction parallel to the substrate surface of the base substrate.

[0014] In some examples, the subpixel further includes a first connecting electrode that electrically connects the first terminal of the resistor to the second pole of the drive transistor.

[0015] In some examples, the first connecting electrode is electrically connected to the first terminal of the resistor via a first via and to the second pole of the drive transistor via a second via, and the first and second vias are located on opposite sides of the first capacitor electrode in a direction parallel to the substrate surface of the base substrate.

[0016] In some examples, the storage capacitor further includes a third capacitor electrode, which is located on the side of the first capacitor electrode away from the second capacitor electrode and is configured to be electrically connected to the second capacitor electrode in a direction perpendicular to the base substrate.

[0017] In some examples, the third capacitor electrode and the first connecting electrode are insulated and made of the same material in the same layer.

[0018] In some examples, the third capacitor electrode includes a first and second spaced portion, the first and second portions respectively located on either side of the first connecting electrode and each electrically connected to the second capacitor electrode.

[0019] In some examples, the second capacitor electrode of the storage capacitor is in the first region of the base substrate and overlaps with the first capacitor electrode in a direction perpendicular to the base substrate.

[0020] In some examples, the first capacitor electrode of the storage capacitor and the gate of the drive transistor are located on the same layer and form an integrated structure.

[0021] In some examples, the control signal further includes a second control signal, the data writing sub-circuit further includes a second data writing transistor, the second data writing transistor is an N-type metal-oxide semiconductor field effect transistor, a gate of the second data writing transistor is configured to receive the second control signal, a first pole of the second data writing transistor is electrically connected to a first pole of the first data writing transistor, and a second pole of the second data writing transistor is electrically connected to a second pole of the first data writing transistor.

[0022] In some examples, gates of the first data writing transistor and the second data writing transistor are arranged in parallel along a first direction and are symmetric with respect to a symmetry axis along a second direction, and the first direction intersects with the second direction.

[0023] In some examples, the sub-pixel further includes a second connection electrode including a first terminal, a second terminal, and a third terminal, the first terminal of the second connection electrode is electrically connected to the second pole of the first data writing transistor, the second terminal of the second connection electrode is electrically connected to the second pole of the second data writing transistor, and the third terminal of the second connection electrode is electrically connected to the first terminal of the recording sub-circuit.

[0024] In some examples, the display substrate includes the four sub-pixels constituting one pixel unit group, the four sub-pixels are arranged as an array along a first direction and a second direction, the first direction intersects with the second direction, and a positive projection of the resistor of the four sub-pixels on the base substrate is located within the same N-type well region on the base substrate.

[0025] In some examples, resistors of sub-pixels adjacent along the first direction are symmetric with respect to a symmetry axis along the second direction, and resistors of sub-pixels adjacent along the second direction are symmetric with respect to a symmetry axis along the first direction.

[0026] In some examples, the recording sub-circuit includes a storage capacitor, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second capacitor electrode are respectively the first terminal and the second terminal of the recording sub-circuit, the first capacitor electrodes of two adjacent sub-pixels in the first direction are symmetric with respect to the symmetry axis along the second direction, and the first capacitor electrodes of two adjacent sub-pixels in the second direction are symmetric with respect to the symmetry axis along the first direction.

[0027] In some examples, the orthographic projection of the first capacitor electrode in the four sub-pixels on the base substrate is located outside the N-type well region and surrounds the N-type well region.

[0028] In some examples, the storage capacitor further includes a third capacitor electrode. In a direction perpendicular to the base substrate, the third capacitor electrode is located on the side away from the second capacitor electrode of the first capacitor electrode, and is configured to be electrically connected to the second capacitor electrode. The third capacitor electrodes of two adjacent sub-pixels in the first direction are symmetric with respect to the symmetry axis along the second direction, and the third capacitor electrodes of two adjacent sub-pixels in the second direction are symmetric with respect to the symmetry axis along the first direction.

[0029] In some examples, the third capacitor electrode includes a first portion and a second portion spaced apart in the first direction. The first portion and the second portion are each configured to be electrically connected to the second capacitor electrode, and the first portions of the third capacitor electrodes of two adjacent sub-pixels in the first direction are connected as an integral structure.

[0030] In some examples, the display substrate includes a plurality of pixel unit groups arranged along the first direction. In each pixel unit group, the second portion of the third capacitor electrode of its sub-pixel is connected to the second portion of the third capacitor electrode of the sub-pixel adjacent to this sub-pixel in the pixel unit group adjacent to this pixel unit group to form an integral structure.

[0031] In some examples, the control signal includes a first control signal and a second control signal, the data writing subcircuit includes a first data writing transistor and a second data writing transistor, the gate of the first data writing transistor is configured to receive the first control signal, the gate of the second data writing transistor is configured to receive the second control signal, the first pole of the first data writing transistor is electrically connected to the first pole of the second data writing transistor and configured to receive the data signal, the second pole of the first data writing transistor is electrically connected to the second pole of the second data writing transistor and is electrically connected to the first terminal of the recording subcircuit and the control electrode of the driving subcircuit, and the second data writing transistors of the four subpixels are all located in the same N-type well region.

[0032] In some examples, the gates of the second data writing transistors in adjacent subpixels in the first direction are connected as a single, symmetrical structure with respect to the axis of symmetry along the second direction, and the gates of the second data writing transistors in two adjacent subpixels in the second direction are symmetrical with respect to the axis of symmetry along the first direction.

[0033] In some examples, the first poles of the second data writing transistors of two adjacent subpixels in the second direction are connected as a symmetrical and integrated structure along the first direction, and the first poles of the second data writing transistors of two adjacent subpixels in the first direction are symmetrical with respect to the axis of symmetry along the second direction.

[0034] In some examples, the pixel circuit further includes a bias subcircuit, the bias subcircuit includes a control terminal, a first terminal and a second terminal, the control terminal of the bias subcircuit is configured to receive a bias signal, the first terminal of the bias subcircuit and the second terminal of the recording subcircuit are both configured to receive a second power supply voltage, and the second terminal of the bias subcircuit is electrically connected to the second electrode of the drive subcircuit and the first terminal of the resistor.

[0035] At least one embodiment of the present disclosure further provides a display device comprising a display substrate and a light-emitting element on the display substrate, wherein the first electrode of the light-emitting element is electrically connected to the second terminal of the resistor.

[0036] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings of the embodiments are briefly described below, and as will be apparent, the drawings described below relate only to some embodiments of this disclosure and do not limit this disclosure. [Brief explanation of the drawing]

[0037] [Figure 1A] Figure 1A is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 1B] Figure 1B is a pixel circuit diagram 1 according to at least one embodiment of the present disclosure. [Figure 1C] Figure 1C is a schematic diagram of the pixel circuit structure. [Figure 2A] Figure 2A is a pixel circuit diagram 2 according to at least one embodiment of the present disclosure. [Figure 2B] Figure 2B is a pixel circuit diagram 3 according to at least one embodiment of the present disclosure. [Figure 2C] Figure 2C is a signal timing diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 3A] Figure 3A is a schematic diagram 2 of a display substrate according to at least one embodiment of the present disclosure. [Figure 3B] Figure 3B is a schematic diagram of the display board shown in Figure 3A, along the cross-sectional line I-I'. [Figure 4A] Figure 4A is a schematic diagram 3 of a display board according to at least one embodiment of the present disclosure. [Figure 4B] Figure 4B is a magnified schematic diagram of one subpixel of a display substrate according to at least one embodiment of the present disclosure. [Figure 5A] Figure 5A shows the steps for manufacturing the display board shown in Figure 4A. [Figure 5B] Figure 5B shows the steps for manufacturing the display board shown in Figure 4A. [Figure 5C] Figure 5C shows the steps for manufacturing the display board shown in Figure 4A. [Figure 5D] Figure 5D shows a diagram illustrating the manufacturing steps for the display board shown in Figure 4A. [Figure 5E] Figure 5E shows a diagram illustrating the manufacturing steps for the display board shown in Figure 4A. [Figure 6A] Figure 6A is a schematic diagram of the first conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 6B] Figure 6B is a schematic diagram of the first conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 6C] Figure 6C shows a cross-sectional view along the section line IV-IV' in Figure 6B. [Figure 7A] Figure 7A is a schematic diagram of the second conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 7B] Figure 7B is a schematic diagram of the second conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 8A] Figure 8A is a schematic diagram of the third conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 8B] Figure 8B is a schematic diagram of the third conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 9A] Figure 9A is a schematic diagram of the fourth conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 9B] Figure 9B is a schematic diagram of the fourth conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 10A]Figure 10A is a schematic diagram of a display board according to at least one embodiment of the present disclosure. [Figure 10B] Figure 10B is an enlarged schematic diagram of the area of ​​the display board shown by the dashed line in Figure 10A. [Figure 10C] Figure 10C is a cross-sectional view along the cross-sectional line V-V' in Figure 10B. [Figure 11A] Figure 11A is a schematic diagram of a display board according to at least one embodiment of the present disclosure. [Figure 11B] Figure 11B is a schematic diagram of a display board according to at least one embodiment of the present disclosure. [Figure 11C] Figure 11C is a cross-sectional view of the display board shown in Figure 11B along the cross-sectional line II-II'. [Figure 11D] Figure 11D is a cross-sectional view of the display board shown in Figure 11B along the cross-sectional line III-III'. [Figure 12] Figure 12 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0038] To further clarify the objectives, technical solutions, and advantages of the embodiments of this disclosure, the technical solutions of the embodiments of this disclosure will be described clearly and completely below with reference to the drawings of the embodiments of this disclosure. Of course, the embodiments described are only some embodiments of this disclosure, not all embodiments. All other embodiments that a person skilled in the art can obtain without inventive work based on the embodiments of this disclosure described are within the scope of this disclosure.

[0039] Unless otherwise defined, technical or scientific terms used in this disclosure have their ordinary meanings as understood by those skilled in the art. The terms “first,” “second,” and similar words used in this disclosure do not indicate order, number, or importance, but are used solely to distinguish different components. Similarly, similar words such as “one,” “one,” or “the” do not limit a quantity, but mean that there is at least one. Similar words such as “includes” or “equipped” mean that the element or part indicated before the word includes, but does not exclude, the elements or parts and their equivalents listed after the word. Similar words such as “connected” or “linked” are not limited to physical or mechanical connections, but may also include direct or indirect electrical connections. “Up,” “down,” “left,” “right,” etc., are used solely to indicate relative positional relationships, and such relative positional relationships may change as the absolute position of the object being described changes.

[0040] In the field of OLED (Organic Light-Emitting Diode) displays, the rapid development of high-resolution products has led to increased demands on the structural design of the display substrate, such as the arrangement of pixels and signal lines. For example, compared to a 4K resolution OLED display, a large 8K resolution OLED display doubles the number of sub-pixel units required for installation, and consequently doubles the pixel density. On the one hand, the line width of the signal lines becomes smaller, resulting in increased resistance of the signal lines themselves. On the other hand, the overlap between signal lines increases, resulting in increased parasitic capacitance of the signal lines. These factors lead to increased resistive-capacitive load on the signal lines. Consequently, phenomena such as signal delay (RC delay), voltage drop (IR drop), and voltage rise (IR rise) due to resistive-capacitive load become more severe. These phenomena seriously impair the display quality of the display product.

[0041] Micro OLED displays generally have a size smaller than 100 micrometers, for example, smaller than 50 micrometers, and involve a combination of organic light-emitting diode (OLED) technology and CMOS technology, where an OLED array is fabricated on a silicon-based substrate containing CMOS circuits.

[0042] Micro-OLEDs are widely applied in the AR and VR fields, and as the technology continues to develop, higher resolution is required, leading to increased demands on the structural design of the display substrate, such as the arrangement of pixels and signal lines.

[0043] A display substrate according to at least one embodiment of the present disclosure can achieve a sub-pixel area of ​​5.45 μm × 13.6 μm through optimized layout and wiring design processes in the design, achieving high resolution (PPI) and optimized arrangement of the pixel circuit array, while also having a relatively good display effect.

[0044] Figure 1A is a block diagram of a display board according to at least one embodiment of the present disclosure. As shown in Figure 1A, the display board 10 includes a plurality of sub-pixels 100, a plurality of scan lines 11, and a plurality of data lines 12 distributed in an array. Each sub-pixel 100 includes a light-emitting element and a pixel circuit that drives the light-emitting element. The plurality of scan lines 11 and the plurality of data lines 12 intersect each other to define a plurality of pixel regions distributed in an array in the display area, and a pixel circuit of one sub-pixel 100 is installed in each pixel region. The pixel circuit is, for example, a normal pixel circuit, such as a 2T1C (i.e., two transistors and one capacitor) pixel circuit, or an nTmC (n, m are positive integers) pixel circuit such as 4T2C, 5T1C, 7T1C, etc. In different embodiments, the pixel circuit may further include a compensation subcircuit including an internal compensation subcircuit or an external compensation subcircuit, and the compensation subcircuit may include transistors, capacitors, etc. For example, if necessary, the pixel circuit may further include a reset circuit, a light emission control subcircuit, and a detection circuit, etc. For example, the display board may further include a gate drive sub-circuit 13 and a data drive sub-circuit 14 located in a non-display area. The gate drive sub-circuit 13 is connected to the pixel circuit via scan lines 11 to provide various scanning signals, and the data drive sub-circuit 14 is connected to the pixel circuit via data lines 12 to provide data signals. The positional relationship between the gate drive sub-circuit 13 and the data drive sub-circuit 14 on the display board, and the positional relationship between the scan lines 11 and the data lines 12 on the display board shown in Figure 1A, are merely examples, and the actual arrangement can be designed as needed.

[0045] For example, the display board 10 may further include a control circuit (not shown). For example, the control circuit is configured to control a data drive subcircuit 14 to apply the data signal and to control a gate drive subcircuit to apply the scan signal. An example of such a control circuit is a timing control circuit (T-con). The control circuit may take various forms, for example, including a processor and memory, the memory containing executable code, and the processor executing the executable code to perform the detection method.

[0046] For example, the processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may include, for example, a microprocessor, a programmable logic controller (PLC), and the like.

[0047] For example, the recording device may include one or more computer program products, and the computer program products may include various forms of computer-readable recording media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions can be stored on the computer-readable recording media, and the processor can execute the functions desired by the program instructions. The computer-readable recording media can further store various application programs and various data.

[0048] The pixel circuit may optionally include a drive subcircuit, a data writing subcircuit, a compensation subcircuit, and a recording subcircuit, and may further optionally include a light emission control subcircuit, a reset circuit, and the like.

[0049] Figure 1B shows a schematic diagram of a pixel circuit. As shown in Figure 1B, the pixel circuit includes a data writing subcircuit 111, a driving subcircuit 112, and a recording subcircuit 113.

[0050] The data writing subcircuit 111 is electrically connected to the first terminal of the recording subcircuit 113 and is configured to transmit a data signal Vd to the first terminal of the recording subcircuit 113 in response to a control signal (first control signal SEL). The second terminal of the recording subcircuit 113 is configured to receive, for example, a second power supply voltage VSS.

[0051] The drive subcircuit 112 includes a control electrode (control terminal) 150, a first electrode (first terminal) 151, and a second electrode (second terminal) 152. The control electrode 150 of the drive subcircuit is electrically connected to the first terminal of the recording subcircuit, the first electrode 151 of the drive subcircuit 112 is configured to receive a first power supply voltage VDD, and the second electrode 152 of the drive subcircuit 112 is electrically connected to a first node S and is also connected to the first electrode 121 of the light-emitting element 120. The drive subcircuit 112 is configured to drive the light-emitting element 120 to emit light in response to the voltage at the first terminal of the recording subcircuit. The second electrode 122 of the light-emitting element 120 is configured to receive, for example, a first common voltage Vcom1.

[0052] In at least some embodiments of this disclosure, the pixel circuit further includes a bias subcircuit 114, as shown in Figure 1B. The bias subcircuit 114 includes a control terminal, a first terminal and a second terminal, the control terminal of the bias subcircuit 114 is configured to receive a bias signal, the first terminal of the bias subcircuit 114 is configured to receive, for example, a second power supply voltage VSS, and the second terminal of the bias subcircuit 114 is electrically connected to a first node S. For example, the bias signal is a second common voltage Vcom2. For example, the bias signal Vcom2 is a constant voltage signal, for example, 0.8V-1V, and the bias subcircuit 114 is configured to be normally open in the action of the bias signal and to provide a constant current, thereby creating a linear relationship between the voltage applied to the light-emitting element 120 and the data signal, contributing to high-precision control of the grayscale, thereby improving the display effect. Further explanation follows with reference to specific circuits.

[0053] For example, when the data signal (voltage) Vd changes from high to low, the grayscale voltage of the first electrode 121 of the writing light-emitting element 120 needs to change rapidly, and the bias subcircuit 114 can also allow the first electrode 121 of the light-emitting element 120 to rapidly release charge, thereby achieving good dynamic contrast.

[0054] The transistors used in the embodiments of this disclosure may be thin-film transistors, field-effect transistors, or other switching devices having the same characteristics. In the embodiments of this disclosure, metal-oxide-semiconductor field-effect transistors are described as examples. The source and drain of the transistors used here may be structurally symmetrical, and therefore, the source and drain do not need to be structurally distinguished. In the embodiments of this disclosure, in order to distinguish the two poles other than the gate of the transistor, one pole is directly described as the first pole and the other pole as the second pole. Also, depending on the characteristics of the transistor, it can be divided into N-type transistors and P-type transistors. If the transistor is a P-type transistor, the on-voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage) and the off-voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). If the transistor is an N-type transistor, the on-voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage) and the off-voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0055] The display substrates according to the embodiments of this disclosure may use rigid substrates such as glass substrates or silicon substrates, or they may be formed from flexible materials having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cycloolefin polymer (COP), and cycloolefin copolymer (COC). The embodiments of this disclosure are described using silicon substrates as examples, that is, the pixel structures are fabricated on silicon substrates, but the embodiments of this disclosure are not limited to this.

[0056] For example, the pixel circuit includes a complementary metal-oxide-semiconductor (CMOS) circuit, meaning the pixel circuit is fabricated on a single-crystal silicon-based substrate. Due to the mature CMOS integrated circuit technology, silicon-based processes can achieve high precision (for example, PPI can reach 6500, and even over 10000).

[0057] For example, process variations in the display board can cause a short circuit between the first electrode 121 and the second electrode 122 of the light-emitting element 120 in a subpixel. This can result in the voltage of the first electrode 121 of the light-emitting element 120 being either too high (e.g., the first common voltage Vcom1 being at a high potential) or too low (e.g., the first common voltage Vcom1 being at a low potential). This can cause the PN junction formed between the second electrode of the drive subcircuit and the base substrate to turn on, leading to a failure in the CMOS circuit and causing defects such as dark lines appearing on the display board.

[0058] In some examples, the data writing subcircuit includes a first data writing transistor P1, and the driving subcircuit includes a driving transistor N2. For example, the first data writing transistor is a P-type metal-oxide-semiconductor field-effect transistor (PMOS), and the driving transistor N2 is an N-type metal-oxide-semiconductor field-effect transistor (NMOS), with the gate, first electrode, and second electrode of the driving transistor N2 being the control electrodes 150, first electrode 151, and second electrode 152 of the driving subcircuit 112, respectively. In such a case, for example, if the first common voltage Vcom1 provided to the second electrode 122 of the light-emitting element 120 is at a low potential, and the first electrode 121 and the second electrode 122 of the light-emitting element 120 are short-circuited, it will cause the potential of the second electrode of the driving transistor directly connected to the first electrode 121 to be too low.

[0059] Figure 1C shows a schematic diagram of a transistor failure in the pixel circuit. The N-type active region (e.g., second pole) of the drive transistor N2, the P-type silicon-based base, the N-type well region where the first data writing transistor P1 is located, and the P-type active region (e.g., first pole) of the first data writing transistor P1 are interconnected to form two parasitic transistors Q1 and Q2, constituting an NPNP structure. The potential of the second pole (i.e., the first node S) of the drive transistor N2 is too low, causing a forward bias in the PN junction (emitter junction) between the second pole (N-type high-concentration doping region) of the drive transistor N2 and the P-type base. This causes Q1 to conduct, providing sufficient current to conduct the parasitic transistor Q2, and conversely, feeding current back to the parasitic transistor Q1, creating a vicious cycle. Ultimately, most of the current is not controlled by the transistor's gate voltage and flows directly from VDD through the parasitic transistor to VSS, leading to a failure in the CMOS pixel circuit. When this circuit fails, the parasitic transistor Q2 constantly draws current from the emitter, i.e., the data line, causing a row of subpixels connected to that data line to fail, resulting in defects such as dark lines on the display board and significantly impairing the display effect.

[0060] In at least some embodiments of the present disclosure, at least one sub-pixel further includes a resistor connected between the second electrode 152 of the drive sub-circuit 112 and the first electrode 121 of the light-emitting element 120 to raise or lower the potential of the first node S, thereby mitigating or avoiding circuit failure, improving circuit reliability, and enhancing the display effect.

[0061] Figure 2A is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. As shown in Figure 2A, the pixel circuit further includes a resistor 130, the first terminal 131 of which is electrically connected to the second electrode 152 of the drive subcircuit 112, and the second terminal 132 is electrically connected to the first electrode 121 of the light-emitting element 120. That is, the second electrode 152 of the drive subcircuit 112 is electrically connected to the first electrode 121 of the light-emitting element 120 by the resistor 130.

[0062] For example, the resistor 130 may be a constant resistor or a variable resistor, or it may be an equivalent resistor formed by another device (e.g., a transistor).

[0063] For example, the resistor 130 is insulated and installed on the same layer as the control electrode 150 of the drive sub-circuit 112, and the resistivity of the resistor is higher than the resistivity of the control electrode of the drive sub-circuit. That is, the conductivity of the control electrode of the drive sub-circuit is higher than the conductivity of the resistor. For example, the resistivity of the resistor is 10 times or more the resistivity of the control electrode.

[0064] In this disclosure, "installed in the same layer" refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process, and their materials may be the same or different. For example, the precursor materials forming multiple structures installed in the same layer may be the same, and the materials of the final formed structures may be the same or different. In this disclosure, "integrated structure" refers to an interconnected structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process, and their materials may be the same or different.

[0065] By installing them in this way, the control electrodes and resistors of the drive sub-circuit can be formed in the same patterning process, thereby saving process time.

[0066] For example, both the resistor and the control electrode of the drive subcircuit are made of polycrystalline silicon, and the doping concentration for the resistor is lower than that for the control electrode, so that the resistor has a higher resistivity than the control electrode. For example, the resistor may be intrinsic polycrystalline silicon or polycrystalline silicon doped at a low concentration, and the control electrode may be polycrystalline silicon doped at a high concentration.

[0067] In some other examples, the materials of the control electrodes and resistors may differ. For example, the materials of the control electrodes and resistors may each include metals and metal oxides corresponding to those metals. For example, the metals may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloys of these materials.

[0068] In at least one embodiment of the present disclosure, the data writing subcircuit 111 may include a transmission gate circuit formed by connecting two complementary transistors in parallel, and the control signal includes two control signals that are in opposite phase. By using a circuit with a transmission gate structure, the data writing subcircuit 111 can contribute to transmitting the data signal to the first terminal of the recording subcircuit 113 without loss.

[0069] For example, the data writing subcircuit includes a first control electrode, a second control electrode, a first terminal, and a second terminal, wherein the first and second control electrodes of the data writing subcircuit are configured to receive a first control signal and a second control signal, respectively, the first terminal of the data writing subcircuit is configured to receive a data signal, and the second terminal of the data writing subcircuit is electrically connected to the first terminal of the recording subcircuit and is configured to transmit the data signal to the first terminal of the recording subcircuit in response to the first and second control signals.

[0070] However, in the description of the embodiments of this disclosure, the first node S does not necessarily represent an actual existing component, but rather indicates a junction point in the circuit diagram where related circuits are connected.

[0071] In the description of the embodiments of this disclosure, the symbol Vd can represent both the data signal terminal and the data signal level; similarly, the symbol SEL can represent both the control signal and the control signal terminal; the symbols Vcom1 and Vcom2 can represent the first common voltage and the second common voltage, and can also represent the first common voltage terminal and the second common voltage terminal; the symbol VDD can represent both the first voltage terminal and the first power supply voltage; and the symbol VSS can represent both the second voltage terminal and the second power supply voltage. The following embodiments are the same as these, and their descriptions are omitted.

[0072] Figure 2B shows a circuit diagram of a specific implementation example of the pixel circuit shown in Figure 2A. As shown in Figure 2B, the data writing subcircuit 111 includes a first data writing transistor P1 and a second data writing transistor N1 connected in parallel to each other. The first data writing transistor P1 and the second data writing transistor N1 are a P-type metal-oxide semiconductor field-effect transistor (PMOS) and an N-type metal-oxide semiconductor field-effect transistor (NMOS), respectively. The control signal includes a first control signal SEL and a second control signal SEL_B which are in opposite phases to each other. The gate of the first data writing transistor P1 is configured to receive the first control signal SEL as the first control electrode of the data writing subcircuit, and the gate of the second data writing transistor N1 is configured to receive the second control signal SEL_B as the second control electrode of the data writing subcircuit. The first pole of the second data writing transistor N1 and the first pole of the first data writing transistor P1 are electrically connected and configured to receive the data signal Vd as the first terminal of the data writing subcircuit, and the second pole of the second data writing transistor N1 and the second pole of the first data writing transistor P1 are electrically connected and configured to receive the control electrode 150 of the drive subcircuit 112 as the second terminal of the data writing subcircuit.

[0073] For example, the first data writing transistor P1 and the second data writing transistor N1 are the same size and have the same channel aspect ratio.

[0074] The data writing subcircuit 111 utilizes the complementary electrical characteristics of transistors, resulting in low on-state resistance in both high-level and low-level transmissions. This gives it the advantage of completely transmitting electrical signals, and allows the data signal Vd to be transmitted to the first terminal of the recording subcircuit 113 without loss.

[0075] For example, as shown in Figure 2B, the drive subcircuit 112 includes a drive transistor N2, which is, for example, an NMOS transistor. The gate, first electrode, and second electrode of the drive transistor N2 are the control electrode, first electrode, and second electrode of the drive subcircuit 112, respectively.

[0076] For example, the recording subcircuit 113 includes a storage capacitor Cst, the storage capacitor Cst includes a first capacitor electrode 141 and a second capacitor electrode 142, and the first capacitor electrode 141 and the second capacitor electrode 142 are the first and second terminals of the recording subcircuit 113, respectively.

[0077] For example, the resistor 130 includes a resistor R. For example, a PN junction is formed between the second electrode 152 of the drive subcircuit 112 and the base substrate, and the resistance value of the resistor 130 is set so that the PN junction turns off when the drive transistor N2 operates in the saturation region, that is, when the pixel circuit operates and drives the light-emitting element 120 to emit light. In such a case, even if a short circuit occurs between the two electrodes of the light-emitting element 120, a voltage drop exists across the resistor 130, which protects the potential of the second electrode 152 and thereby avoids circuit failure.

[0078] For example, the resistance value of resistor 130 is

number

number

[0079] For example, the light-emitting element 120 is specifically implemented as an organic light-emitting diode (OLED). For example, the light-emitting element 120 may be an OLED with an upper light-emitting structure, and can emit red light, green light, blue light, or white light. For example, the light-emitting element 120 is a micro OLED. The embodiments of this disclosure do not limit the specific structure of the light-emitting element. For example, the first electrode 121 of the light-emitting element 120 is the anode of the OLED, and the second electrode 122 is the cathode of the OLED, that is, the pixel circuit has a common cathode structure. However, the embodiments of this disclosure do not limit this, and the pixel circuit may have a common anode structure depending on the circuit structure.

[0080] For example, the bias subcircuit 114 includes a bias transistor N3, and the gate, first pole, and second pole of the bias transistor N3 are the control terminal, first terminal, and second terminal of the bias subcircuit 114, respectively.

[0081] Figure 2C shows the signal timing diagram of the pixel circuit shown in Figure 2B, and the operating principle of the pixel circuit shown in Figure 2C will be explained below with reference to the signal timing diagram shown in Figure 2B. For example, the second data writing transistor, the driving transistor, and the bias transistor are all N-type transistors, and the first data writing transistor is a P-type transistor, but the embodiments of this disclosure are not limited to these.

[0082] Figure 2C shows the waveforms of each signal in two consecutive display periods T1 and T2, for example, the data signal Vd is a high grayscale voltage in display period T1 and a low grayscale voltage in display period T2.

[0083] For example, as shown in Figure 2C, the image display process for each frame includes a data writing stage 1 and a light emission stage 2. The operation process of the pixel circuit includes a data writing stage 1 in which both the first control signal SEL and the second control signal SEL_B are ON signals, the first data writing transistor P1 and the second data writing transistor N1 conduct, and the data signal Vd is transmitted to the gate of the drive transistor N2 via the first data writing transistor P1 and the second data writing transistor N1; and a light emission stage 2 in which both the first control signal SEL and the second control signal SEL_B are OFF signals, the voltage across the storage capacitor Cst does not change due to the bootstrap phenomenon of the storage capacitor Cst, the drive transistor N2 operates in a saturated state with no change in current, and the light-emitting element 120 is driven to emit light. When the pixel circuit transitions from display cycle T1 to display cycle T2, the data signal Vd changes from a high grayscale voltage to a low grayscale voltage. The bias transistor N3 generates a stable drain current by controlling the second common voltage Vcom2, which can rapidly discharge the charge stored in the OLED anode when the OLED's display grayscale needs to change rapidly. For example, since this discharge process occurs in the data writing stage 1 of display cycle T2, the voltage of the OLED anode rapidly decreases in the light emission stage 2 of display cycle T2, thereby achieving high dynamic contrast and improving the display effect.

[0084] As shown in Figure 2B, for example, during the light-emitting stage, the light-emitting current when the light-emitting OLED writes grayscale data is on the order of nanoamperes (e.g., several nanoamperes), but the bias transistor N3 is controlled by the bias signal, i.e., the second common voltage Vcom2, and operates in the saturation region, and the resulting current is on the order of microamperes (e.g., 1 microampere). Therefore, almost all of the current flowing through the drive transistor N2 flows into the bias transistor N3, and both can be treated in the same way, i.e.,

number

number

number

number

number

[0085] For example, bias transistor N3 is controlled by bias signal Vcom2 and operates in the saturation region, and the voltage difference between the gate and source of bias transistor N3 is

number

[0086] For example, if the first node S is electrically connected directly to the light-emitting element 120, the voltage V0 is applied directly to the first electrode 121 of the light-emitting element 120, and is, for example, the anode voltage of the OLED. If the first node S is electrically connected to the light-emitting element 120 via a resistor 130, the current flowing through the light-emitting element 120 is very small, so the voltage at the first node S may be approximately equal to the voltage at the first electrode 121 of the light-emitting element 120. In other words, by making the voltage at the first electrode 121 of the light-emitting element 120 and the data signal (data voltage) Vd linear, it is possible to control the grayscale with high precision and improve the display effect.

[0087] For example, the first control signal SEL and the second control signal SEL_B are differential complementary signals, having the same amplitude and opposite phase. This contributes to improving the interference prevention performance of the circuit. For example, since the first control signal SEL and the second control signal SEL_B can be output from the same gate drive circuit unit (e.g., a GOA unit), the circuit is simplified.

[0088] For example, as shown in Figure 1A, the display board 10 may further include a data driving circuit 13 and a scanning driving circuit 14. The data driving circuit 13 is configured to transmit a data signal, for example, the data signal Vd, as needed (for example, an image signal input to a display device). The scanning driving circuit 14 is configured to output various scanning signals, for example, the first control signal SEL and the second control signal SEL_B, and is, for example, a gate driving circuit (GOA) fabricated directly on an integrated circuit chip (IC) or the display board.

[0089] For example, the display substrate can use a silicon substrate as the base substrate 101, and the pixel circuit, data driving circuit 13, and scanning driving circuit 14 can all be integrated on the silicon substrate. In this case, since silicon-based circuits can achieve high precision, the data driving circuit 13 and scanning driving circuit 14 are not necessarily located in the non-display area, but may be formed, for example, in an area corresponding to the display area of ​​the display substrate.

[0090] For example, the display board 10 further includes a control circuit (not shown). For example, the control circuit is configured to control a data drive circuit 13 to apply the data signal Vd and to control a gate drive circuit 13 to apply various scanning signals. An example of the control circuit is a timing control circuit (T-con). The control circuit may take various forms, for example, including a processor and a memory, the memory containing executable code, and the processor executing the executable code to perform the detection method.

[0091] For example, the processor may be a central processing unit (CPU) or other forms of processing equipment having data processing capability and / or instruction execution capability, and may include, for example, a microprocessor, a programmable logic controller (PLC), etc.

[0092] For example, the recording device may include one or more computer program products, and the computer program products may include various forms of computer-readable recording media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions can be recorded on the computer-readable recording media, and the processor 121 can execute the functions desired by the program instructions. Various application programs and various data, such as electrical characteristic parameters obtained by the detection method described above, can also be recorded on the computer-readable recording media.

[0093] In the following, a display substrate according to at least one embodiment of the present disclosure will be described illustratively using the pixel circuit shown in Figure 2B as an example, but the embodiments of the present disclosure are not limited thereto.

[0094] Figure 3A is a schematic diagram of a display substrate 10 according to at least one embodiment of the present disclosure. For example, as shown in Figure 3A, the display substrate 10 includes a base substrate 101, and a plurality of subpixels 100 are located on the base substrate 101. The plurality of subpixels 100 are arranged as a subpixel array, the row direction of the subpixel array is a first direction D1, and the column direction is a second direction D2, and the first direction D1 and the second direction D2 intersect, for example, orthogonal. Figure 3A exemplifies a 2x6 subpixel arrangement, i.e., two pixel rows 20 and six pixel columns 30, and shows three pixel column regions spaced apart from each other with dashed frame lines.

[0095] For example, the base substrate 101 may be a rigid substrate, such as a glass substrate or a silicon substrate, or it may be formed from a flexible material having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cycloolefin polymer (COP), and cycloolefin copolymer (COC). In all the examples of this disclosure, the base substrate 101 is described as a silicon substrate as an example, but the examples of this disclosure are not limited thereto.

[0096] For example, the base substrate 101 includes single-crystal silicon or high-purity silicon. The pixel circuit is formed on the base substrate 10 by a CMOS semiconductor process. For example, the active region of the transistor (including the channel region, first pole, and second pole of the transistor) is formed on the base substrate 101 by a doping process, and each insulating layer is formed by a silicon oxidation process or chemical vapor deposition (CVD) process, and a wiring structure is formed by forming multiple conductive layers by a sputtering process. The active region of each transistor is located inside the base substrate 101.

[0097] Figure 3B shows a cross-sectional view along the cross-sectional line I-I' in Figure 3A. For clarity, Figure 3B omits wiring or electrode structures that do not have a direct connection relationship.

[0098] For example, as shown in Figure 3B, the display substrate 10 includes a base substrate 101, a first insulating layer 201 located sequentially on the base substrate 101, a polycrystalline silicon layer 102, a second insulating layer 202, a first conductive layer 301, a third insulating layer 203, a second conductive layer 302, a fourth insulating layer 204, a third conductive layer 303, a fifth insulating layer 205, and a fourth conductive layer 304. The structure of the display substrate 10 will be described layer by layer below, with reference to Figure 3B.

[0099] For clarity and convenience of explanation, Figure 4A shows the portion of the display substrate 10 located beneath the first conductive layer 301, namely the base substrate 101 and the first insulating layer 201 and polycrystalline silicon layer 102 thereon, including each transistor (P1, N1-N3), storage capacitor Cst and resistor 130, and Figure 4B is an enlarged schematic of one subpixel 100 in Figure 4A, and for clarity, Figure 4A also shows the corresponding cross-sectional line I-I' in Figure 3A. Figures 5A-5E show the formation process of the substrate structure shown in Figure 4A.

[0100] As shown in Figure 4B, for example, in a direction parallel to the substrate surface of the base substrate 101, the first data writing transistor P1 and the drive transistor N2 are located on opposite sides of the storage capacitor Cst, and for example, in a second direction D2, they are located on opposite sides of the storage capacitor Cst.

[0101] As can be seen in conjunction with Figure 1C, this configuration increases the distance between the first data writing transistor P1 and the drive transistor N2, thereby increasing the resistance of the parasitic circuit and further reducing the risk of failure in the CMOS circuit.

[0102] For example, the material of the second capacitor electrode 142 of the storage capacitor 140 is a conductor or a semiconductor. For example, as shown in Figures 3B and 4B, the second capacitor electrode 142 of the storage capacitor 140 is the first region 401 of the base substrate 101, for example, the base substrate 101 is a P-type silicon-based substrate, and the material of the second capacitor electrode 142 is P-type single-crystal silicon. When a voltage is applied to the first capacitor electrode 141, the first region 401, which is a semiconductor located below the first capacitor electrode 141 in the base substrate 101, forms an inversion region and becomes a conductor, and is electrically connected to the contact hole regions on both sides of the first region 401 (contact hole regions 145a and 145b shown in Figure 4B). In such a case, no separate treatment such as doping is performed on the first region 401.

[0103] In another example, the first region 401 is, for example, a conductive region in the base substrate 101, such as a highly doped region, thereby enabling the second capacitor electrode 142 to obtain stable and high conductivity.

[0104] For example, the base substrate 101 further includes a second region 402, which is an N-type well region in the base substrate 101. As shown in Figure 4B, for example, the first data writing transistor P1 and the resistor 130 are installed in parallel in the second region 402 in the second direction D2. Installing the resistor 130 made of polycrystalline silicon material on an N-type base reduces parasitic phenomena and contributes to improving the characteristics of the circuit.

[0105] For example, in a direction parallel to the substrate surface of the base substrate 101, the resistor (R) 130 and the first data writing transistor P1 are located on the same side of the second capacitor electrode 142. For example, in a direction parallel to the substrate surface of the base substrate 101, the drive transistor N2 and the bias transistor N3 are located on the same side of the second capacitor electrode 142.

[0106] For example, as shown in Figure 4B, the first data writing transistor P1 and the second data writing transistor P1 are installed in parallel in the first direction D1 and are symmetric with respect to the axis of symmetry along the second direction D2. For example, the gate 160 of the first data writing transistor P1 and the gate 170 of the second data writing transistor N1 are installed in parallel in the first direction D1 and are symmetric with respect to the axis of symmetry along the second direction D2.

[0107] For example, resistor 130 has a U-shaped structure, for example, an asymmetrical U-shaped structure, for example, the lengths of the two branches of the U-shaped structure are not equal. For example, as shown in Figure 4B, the second terminal 132 of resistor 130 is closer to the drive transistor N2.

[0108] By arranging the resistor 130 in a U-shape, the area occupied by the resistor is saved, thereby increasing the space utilization rate and contributing to an improved resolution of the display board. For example, in the same space, a U-shaped resistor allows for an increase in the length of the resistor, thereby achieving the desired resistance value.

[0109] Furthermore, designing the resistor 130 as an asymmetric structure is also for the rational use of the placement space. For example, as shown in Figure 4B, a contact hole region 411a is placed above the shorter branch of the U-type resistor, and the contact hole region 411a is in parallel with the second terminal 132 of the resistor 130 in the first direction D1. For example, the contact hole region 411a is an N-type high-concentration doping region (N+). For example, the contact hole region 411 is for biasing the well region 401 where the first data writing transistor P1 is located, thereby avoiding threshold voltage changes due to parasitic phenomena such as base bias and improving circuit stability. For example, as shown in Figure 3B, by applying a low voltage bias to the P-type base 101 and a high voltage bias to the N-type well region 402, the parasitic PN junction between the two is reverse-biased, electrically isolating the devices and reducing parasitic phenomena between devices, thereby improving circuit stability.

[0110] For example, the opening of the U-shaped structure faces the first capacitor electrode 141, and the first terminal 131 and second terminal 132 of the resistor 130 are located at the two ends of the U-shaped structure, respectively. As shown in the figure, the first terminal 131 of the resistor 130 is provided with a contact hole region 133 for electrical connection to the gate 150 of the drive transistor N2, and the second terminal 132 of the resistor 130 is provided with a contact hole region 134 for electrical connection to the first electrode 121 of the light-emitting element 120.

[0111] For example, the material of the resistor 130 includes a polycrystalline silicon material, the contact hole regions 133 and 134 are doping regions for reducing contact resistance, and the body region of the resistor 130 other than the contact hole regions is, for example, an intrinsic region or a low-concentration doping region, thereby obtaining a desired resistance value.

[0112] For example, the first capacitor electrode 141 of the storage capacitor 140 and the resistor 130 are insulated and installed in the same layer, both containing polycrystalline silicon material, and the doping concentration to the first capacitor electrode 141 of the storage capacitor 140 is higher than the doping concentration to the main body region of the resistor 130. For example, the main body region of the resistor 130 is made of intrinsic polycrystalline silicon material.

[0113] For example, the gates 160, 170, 150, and 180 of each transistor P1, N1-N3 and the first capacitor electrode 141 of the storage capacitor 140 are located in the same layer and all contain polycrystalline silicon material. For example, as shown in Figure 4B, the gate 150 of the drive transistor N2 and the first capacitor electrode 141 are interconnected to form an integrated structure.

[0114] Figure 4B further shows the active regions P1a, N1a, N2a, and N3a of each transistor P1, N1-N3, and also shows the first pole 161 and second pole 162 of the first data writing transistor P1, the first pole 171 and second pole 172 of the second data writing transistor N1, the first pole 151 and second pole 152 of the drive transistor N2, and the first pole 181 and second pole 182 of the bias transistor N3.

[0115] Figure 4B further shows the gate contact region 165, first contact region 163, and second pole contact region 164 of the first data writing transistor P1, the gate contact region 175, first contact region 173, and second pole contact region 174 of the second data writing transistor N1, the gate contact region 155, first contact region 153, and second pole contact region 154 of the drive transistor N2, and the gate contact region 185, first contact region 183, and second pole contact region 184 of the bias transistor N3. For example, each first pole contact region is a region for forming an electrical contact with the corresponding first pole, each second pole contact region is a region for forming an electrical contact with the corresponding second pole, and each gate contact region is a region for forming an electrical contact with the corresponding gate.

[0116] For example, the active region P1a of the first data writing transistor P1 and the active region N1a of the second data writing transistor N1 are arranged in parallel in the first direction D1 and are symmetric with respect to the axis of symmetry along the second direction D2.

[0117] As shown in Figure 4B, the area of ​​the active region N2a of the driving transistor N2 is larger than the area of ​​the active regions of the other transistors, which allows for a larger aspect ratio, contributing to an improved driving capability of the driving transistor N2 and thereby improving the display effect.

[0118] As shown in Figure 4B, transistors with large active regions, such as the drive transistor N2 and the bias transistor N3, have sufficient space to accommodate at least two contact hole regions on their first and second poles, respectively. This allows for sufficient contact with the structure to be connected and the formation of a parallel connection structure, thereby reducing contact resistance.

[0119] Figure 4B further shows the contact hole region 144 of the first capacitor electrode 141 and contact hole regions 145a and 145b configured to be electrically connected to the second capacitor electrode 142. As shown in Figure 4B, the contact resistance is reduced by providing at least two corresponding contact hole regions for each of the first capacitor electrode 141 and the second capacitor electrode 142.

[0120] As can be seen in conjunction with Figure 4A, the distribution of transistors (including, for example, the shape and size of each transistor), storage capacitors, and resistors in two adjacent subpixels 100 in the first direction D1 is symmetric with respect to the axis of symmetry along the second direction D2; that is, the corresponding structures in the two subpixels are symmetric with respect to the axis of symmetry along the second direction D2. The distribution of transistors in two adjacent subpixels 100 in the second direction D2 is symmetric with respect to the axis of symmetry along the first direction D1.

[0121] By arranging the elements symmetrically in this manner, the uniformity of process errors can be improved as much as possible, thereby improving the uniformity of the display substrate. Furthermore, by arranging them symmetrically in this manner, several structures that are installed on the same layer of the substrate and can be interconnected can be integrally formed, allowing for a more compact pixel arrangement compared to individual placement, increasing space utilization and thereby improving the resolution of the display substrate.

[0122] For example, as shown in Figure 4A, the second region 402 of two adjacent subpixels 100 in the first direction D1 is a single integrated structure, and the second region 402 of two adjacent subpixels 100 in the second direction D2 is also a single integrated structure; that is, the first data writing transistor N1 and resistor 130 in the four adjacent subpixels 100 are located in the same well region. Compared to individually installing independent well regions, this arrangement allows for a more compact pixel arrangement while satisfying design rules, contributing to an improved resolution of the display board.

[0123] For example, as shown in Figure 4A, the active regions P1a of two adjacent subpixels in the second direction D2 are interconnected to form an integrated structure. That is, the active regions P1a of the two first data writing transistors P1 are located in the same doping region A1 (P-well) of the same second region 402, and the first poles of the two first data transistors P1 are interconnected to form an integrated structure so as to receive the same data signal Vd.

[0124] For example, as shown in Figure 4A, the active regions N1a of two adjacent subpixels in the second direction D2 are interconnected to form an integrated structure. That is, the active regions N1a of the two second data writing transistors N1 are located in the same doping region A2 (N well) of the base substrate 101, and the first poles of the two second data writing transistors N1 are interconnected to form an integrated structure so as to receive the same data signal Vd.

[0125] For example, as shown in Figure 4A, the gates of the first data writing transistor P1 or the second data writing transistor N2 of two adjacent subpixels 100 in the first direction D1 are connected to each other to form an integrated structure.

[0126] In each row of pixels, the gates of the first data writing transistors P1 are configured to receive the same first control signal SEL, and the gates of the second data writing transistors N1 are configured to receive the same second control signal SEL_B. Furthermore, the transistors of two adjacent sub-pixels in the first direction D1 are mirror-symmetric, and in the first direction D1, the cases where the first writing transistors P1 of two sub-pixels are adjacent and the cases where the second writing transistors N1 are adjacent occur alternately. Therefore, the gates of two adjacent first data writing transistors P1 can be directly connected to form a single integrated structure that forms the first control electrode group 191, and the gates of adjacent second data writing transistors N1 can be directly connected to form a single integrated structure that forms the second control electrode group 192. This arrangement allows for a more compact pixel arrangement while satisfying design rules, contributing to an improvement in the resolution of the display board.

[0127] As shown in Figure 4A, in two adjacent subpixels 100 in the first direction D1, when their drive transistors N2 are adjacent, the active regions N2a of the two drive transistors N2 are interconnected to form an integrated structure. That is, the active regions N2a of the two drive transistors N2 are located in the same doping region B (N well) of the base substrate 101, and the first poles of the two drive transistors N2 are interconnected to form an integrated structure that receives the same first power supply voltage VDD, thereby forming the third control electrode group 193. When the bias transistors N3 are adjacent, the gates of the two bias transistors N3 are connected to each other to form an integrated structure so that they receive the same second common voltage Vcom2, and the active regions N3a of the two bias transistors N3 are connected to each other to form an integrated structure, that is, the active regions N3a of the two bias transistors N3 are located in the same doping region C (N well) of the base substrate 101, and the first poles of the two bias transistors N3 are connected to each other to form an integrated structure so that they receive the same second power supply voltage VSS.

[0128] This installation method allows for a more compact arrangement of pixels while still meeting design regulations, contributing to improved resolution of the display board.

[0129] Figures 5A-5D illustrate the formation process of the substrate structure shown in Figure 4A. For clarity, the figures show only two rows and two columns of subpixels, i.e., four adjacent subpixels 100, which constitute one pixel unit group. Figure 4A schematically shows this pixel unit group 420 with a dashed frame. For example, the display substrate includes a plurality of pixel unit groups arranged along a first direction D1 and a second direction D2.

[0130] The following describes the process of forming a display substrate according to an embodiment of the present disclosure with reference to Figures 5A-5D, but this is not intended to limit the present disclosure.

[0131] For example, a silicon-based substrate is provided, for instance, a P-type single-crystal silicon. An N-type transistor (e.g., a driver transistor) can be fabricated directly on the P-type silicon base. That is, by using the P-type base as the channel region of the N-type transistor, it is advantageous to leverage the high-speed capabilities of NMOS devices and improve circuit performance.

[0132] As shown in Figure 5A, for example, an N-type well region, i.e., a second region 402, is formed by N-type doping on a P-type silicon base substrate to serve as the base for the first data writing transistor P1 and resistor 130.

[0133] For example, the second regions 402 of two adjacent subpixels in the first direction D1 may be interconnected, and the second regions 402 of two adjacent subpixels in the second direction D2 may be interconnected. For example, when performing N-type doping, the undoped region of the base substrate 101 is blocked.

[0134] As shown in Figures 4B and 5B, for example, a first insulating layer 201 is formed on the base substrate 101, and then a polycrystalline silicon layer 102 is formed on the first insulating layer 201.

[0135] The first insulating layer 201 includes the gate insulating layer of each transistor and further includes the dielectric layer 104 of the storage capacitor Cst. The polycrystalline silicon layer 102 includes the first capacitor electrode 141, the resistor 130 and the gates 150, 160, 170, and 180 of each transistor (P1, N1-N3).

[0136] The gate of the first data writing transistor P1 is located in the second region 402, and the N-type well region serves as the channel region of the P-type transistor. The resistor 130 is also formed in the second region 402; that is, the orthographic projection of the resistor 130 on the base substrate is located within the second region. Forming the resistor 130 of polycrystalline silicon material on an N-type base reduces parasitic phenomena and contributes to improving the circuit characteristics. Each N-type transistor is formed directly on a P-type base outside the N-type well region.

[0137] For example, as shown in Figure 5B, the orthographic projection of the first capacitor electrodes 141 of the four subpixels in each pixel unit group on the base substrate lies outside the second region 402 and encloses the second region 402. For example, the second region 402 is rectangular, and the orthographic projection of the first capacitor electrodes 141 of each subpixel on the base substrate encloses one corner of the rectangle. For example, each first capacitor electrode 141 includes a recessed structure with an L-shaped contour, and one corner of the rectangle extends into the orthographic projection of the recessed structure and conforms to the L-shaped contour.

[0138] As shown in Figure 5B, the pattern of the polycrystalline silicon layer in two adjacent subpixels in the first direction D1 is symmetric with respect to the axis of symmetry along the second direction D2, and the pattern of the polycrystalline silicon layer in two adjacent subpixels in the second direction D2 is symmetric with respect to the axis of symmetry along the first direction D1; that is, the pattern of the polycrystalline silicon layer is a symmetric pattern. For example, as shown in Figure 5B, the resistor of an adjacent subpixel in the first direction is symmetric with respect to the axis of symmetry along the second direction, and the resistor of an adjacent subpixel in the second direction is symmetric with respect to the axis of symmetry along the first direction. For example, the first capacitor electrode of an adjacent subpixel in the first direction is symmetric with respect to the axis of symmetry along the second direction, and the first capacitor electrode of an adjacent subpixel in the second direction is symmetric with respect to the axis of symmetry along the first direction.

[0139] For example, the gates of the first data writing transistor P1 and the second data writing transistor N1 of two adjacent subpixels in the first direction D1 are symmetric with respect to the axis of symmetry along the second direction. For example, the gates of the first data writing transistor P1 or the second data writing transistor N1 of two adjacent subpixels in the first direction D1 are integrally molded.

[0140] For example, in the second direction D2, the gates of the first data writing transistor P1 and the second data writing transistor N1 of two adjacent subpixels are symmetric with respect to the axis of symmetry along the first direction.

[0141] For example, the first insulating layer is formed on the base substrate by a thermal oxidation method. For example, the material of the first insulating layer is silicon nitride, oxide, or nitrogen oxide.

[0142] For example, a polycrystalline silicon material layer is formed on the first insulating layer by a chemical vapor deposition (PVD) process, and then a lithography process is performed on the polycrystalline silicon material layer to form the polycrystalline silicon layer 102.

[0143] Figure 5C shows the doping window region 103 of the base substrate (left), and Figure 5B shows the doping window region in the substrate structure shown (right). For example, the doping is high-concentration doping to form contact hole regions for electrical connection to the base substrate. For example, the doping window region includes the source and drain regions of each transistor. For example, the doping window region further includes each contact hole region in the base and the contact hole regions in the resistor 130, for example, contact hole regions 400a, 400b, 411a, 411b, 145a, 145b, 133, and 134 shown in Figure 4B. For example, since the gate of the transistor is formed of polycrystalline silicon material, it is also necessary to dope the polycrystalline silicon gate. When doping, it is necessary to form a barrier layer to block the undoped region so that only the corresponding doping window region and amorphous silicon region are exposed.

[0144] Note that Figure 5C only shows the doping window regions; when actually performing the doping process, the corresponding barrier layer / mask layer should be installed to expose the corresponding doping window region and polycrystalline silicon region for doping. For example, the material of the barrier layer / mask layer may be a photoresist or an oxide material.

[0145] As shown in Figure 5D, a barrier layer 135 is formed corresponding to the resistor 130. In order to protect the resistance value of the resistor 130, it is necessary to shield the resistor 130 during the doping process to prevent it from being damaged by the doping. The barrier layer 135 shields the main body of the resistor 130, exposing only the contact hole regions 133 and 134 at both ends of the resistor 130.

[0146] For example, the barrier layer 135 may be a silicon nitride, oxide, or nitrogen oxide, or it may be a photoresist material. After the doping process is complete, the barrier layer 135 may remain on the display substrate or may be removed.

[0147] In some other examples, the barrier layer 135 of the resistor 130 may be formed together with the barrier / mask layers of other regions during doping, and the embodiments of this disclosure are not limited thereto.

[0148] For example, in the doping process, it is necessary to perform N-type doping and P-type doping, respectively, to form the source and drain regions of an N-type transistor and a P-type transistor. When performing the N-type doping process, it is necessary to form a barrier layer that blocks the regions that are not doped with N-type doping, and when performing the P-type doping process, it is necessary to form a barrier layer that blocks the regions that are not doped with P-type doping.

[0149] Figure 5E shows the N-type doping region SN and the P-type doping region SP with different shade patterns (left), and Figure 5D shows the N-type doping region SN and the P-type doping region SP on the substrate shown (right). The N-type doping region SN and the P-type doping region SP are also shown in Figure 4B, which may also be referred to.

[0150] For example, performing an N-type doping process involves forming a barrier layer that covers the P-type doping region SP and the regions of the N-type doping region SN other than the doping window region and the polycrystalline silicon region, leaving only the doping window region and the polycrystalline silicon region of the N-type doping region SN, i.e., the superposition region of the SN region and the doping window region 103 and the polycrystalline silicon region shown in Figure 5C, and then performing the N-type doping process. In contrast to Figure 4B, the N-type doping process can form the gates and first and second poles of transistors N1-N3, as well as the contact hole regions 411a, 411b, 145a, and 145b. The N-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, boron.

[0151] For example, performing a P-type doping process involves forming a barrier layer that covers the N-type doping region SN and the regions of the P-type doping region SP other than the doping window region and the polycrystalline silicon region, leaving only the doping window region and the polycrystalline silicon region of the P-type doping region SP, i.e., the superposition region of the SP region and the doping window region 103 and the polycrystalline silicon region shown in Figure 5C, and then performing the P-type doping process. In contrast to Figure 4B, the P-type doping process can form the gate, first and second poles, and contact holes 400a, 400b, 133, and 134 of transistor P1. The P-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, phosphorus.

[0152] In the doping process, for example, an ion implantation process is used, and by using a polycrystalline silicon pattern as a mask, ions are implanted into the silicon-based base precisely on both sides of the polycrystalline silicon, thereby forming the first and second electrodes of each transistor and achieving self-alignment. Furthermore, the resistivity of polycrystalline silicon, which originally has high resistance, is reduced by the doping process, allowing for the formation of the gate and the first capacitor electrode of each transistor. Therefore, using polycrystalline silicon material as the material for resistors and gates has multiple beneficial effects and saves process costs.

[0153] In this way, the structure of the display board, including each transistor P1, N1-N3, resistor 130, and storage capacitor Cst, as shown in Figure 4A, is formed.

[0154] For example, in the first direction D1, the corresponding transistors, resistors, and storage capacitors Cst in two adjacent subpixels are symmetric with respect to the axis of symmetry along the second direction D2, and in the second direction D2, the corresponding transistors, resistors, and storage capacitors Cst in two adjacent subpixels are symmetric with respect to the axis of symmetry along the first direction D1.

[0155] In this embodiment, the storage capacitor Cst is a capacitor formed by the field effect. After applying a voltage to the first capacitor electrode 141, a reversal charge is generated in the region located below the first capacitor electrode 141 on the base substrate 101, causing the lower electrode plate of the storage capacitor Cst, i.e., the second capacitor electrode 142, to become a conductor.

[0156] In some other embodiments, a conductive treatment (e.g., doping treatment) may be performed on a region of the base substrate 101 located below the first capacitor electrode 141 in order to form the second capacitor electrode 142. The embodiments of this disclosure are not limited thereto.

[0157] The display substrate shown in Figure 3A is formed by sequentially forming a second insulating layer 202, a first conductive layer 301, a third insulating layer 203, a second conductive layer 302, a fourth insulating layer 204, a third conductive layer 303, a fifth insulating layer 205, and a fourth conductive layer 304 on the substrate shown in Figure 4A.

[0158] Figures 6A and 6B show the pattern of the first conductive layer 301 and the case in which the first conductive layer 301 is installed on the substrate structure shown in Figure 4A, respectively. Figure 6C shows a cross-sectional view cut along the cross-sectional line IV-IV' in Figure 6B. Figure 6B also shows vias in the second insulating layer 202, which correspond one-to-one with each contact region in Figure 4B and are used to electrically connect each contact hole region to the pattern in the first conductive layer 301. For clarity, the figures show only 2x6 subpixels, and the dashed frame indicates the region of one subpixel 100. Furthermore, Figure 6B corresponds to the location of the cross-sectional line I-I' in Figure 3A.

[0159] As shown in Figure 6A, the pattern of the first conductive layer in two adjacent subpixels in the first direction D1 is symmetric with respect to the axis of symmetry along the second direction D2, and the pattern of the first conductive layer in two adjacent subpixels in the second direction D2 is symmetric with respect to the axis of symmetry along the first direction D1. Below, the pattern of the first conductive layer will be explained illustratively using one subpixel as an example.

[0160] As shown in Figure 6A, the first conductive layer 301 includes a connecting electrode 313 (an example of the first connecting electrode in this disclosure) for electrically connecting the first terminal 131 of the resistor 130 to the second electrode 152 of the drive subcircuit 112.

[0161] For example, as shown in conjunction with Figure 6B, the first terminal of the connecting electrode 313 is electrically connected to the first terminal 131 of the resistor 130 by via 225 (an example of the first via in this disclosure) in the second insulating layer 202, and the second terminal of the connecting electrode 313 includes a first branch 331 and a second branch 332, as shown in conjunction with Figure 3B, the first branch 331 is electrically connected to the first pole 151 of the drive transistor N2 by via 226a (an example of the second via in this disclosure) in the second insulating layer 202, and the second branch 332 is electrically connected to the first pole 181 of the bias transistor N3 by via 226b in the second insulating layer 202.

[0162] For example, as shown in Figure 6B, in the second direction D2, vias 225 and 226a are located on opposite sides of the first capacitor electrode 141, that is, the orthographic projection of the connecting electrode 313 on the base substrate 101 passes through the orthographic projection of the first capacitor electrode 141 on the base substrate 101 in the second direction D2.

[0163] For example, to reduce contact resistance, at least two vias 226a and 226b may be provided.

[0164] For example, as can be seen in conjunction with Figures 6A and 6B, the first conductive layer 301 further includes a connecting electrode 314, which is electrically connected to the second terminal 132 of the resistor 130 by vias 229 in the second insulating layer 202, and is used to electrically connect to the first electrode 121 of the light-emitting element 120.

[0165] For example, the connecting electrode 314 is L-shaped, and one branch is electrically connected to the second terminal 132 of the resistor 130, while the other branch is electrically connected to the first electrode 121 of the light-emitting element 120.

[0166] For example, as shown in Figures 6B and 6C, the first conductive layer 301 further includes a third capacitor electrode 315 that overlaps with the first capacitor electrode 141 in a direction perpendicular to the base substrate. The third capacitor electrode 315 is located on the side of the first capacitor electrode 141 away from the second capacitor electrode 142 and is configured to be electrically connected to the second capacitor electrode 142. That is, in a direction perpendicular to the base substrate, the second capacitor electrode 142 and the third capacitor electrode 315 are located on either side of the first capacitor electrode 141 and are electrically connected to each other, thereby forming a parallel capacitor structure that increases the capacitance value of the storage capacitor Cst.

[0167] For example, as shown in Figures 6B and 6C, the third capacitor electrode 315 includes a first portion 315a and a second portion 315b, with the first portion 315a and the second portion 315b spaced apart from each other in a first direction D1. For example, the third capacitor electrode 315 of the first portion 315a is electrically connected to the contact hole region 145b by vias 228 in the second insulating layer 202 so as to be electrically connected to the second capacitor electrode 142, and the second portion 315b is electrically connected to the contact hole region 145a by vias 227 in the second insulating layer 202 so as to be electrically connected to the second capacitor electrode 142.

[0168] For example, the first portion 315a and the second portion 315b of the third capacitor electrode 315 are located on both sides of the connecting electrode 313 in the first direction D1, and are each installed with a gap between them and the connecting electrode 313.

[0169] For example, the third capacitor electrodes 315 of two adjacent subpixels in the first direction D1 are symmetric with respect to the axis of symmetry along the second direction D2, and the third capacitor electrodes 315 of two adjacent subpixels in the second direction D2 are symmetric with respect to the axis of symmetry along the first direction D1.

[0170] For example, as shown in Figure 6B, the first portion 315a or the second portion 315b of the third capacitor electrode 135 of two adjacent subpixels in the first direction D1 are integrally molded.

[0171] For example, as shown in Figure 6B, for each pixel unit group 420, the first portions 315a of the third capacitor electrodes 315 of two adjacent subpixels in the first direction D1 are interconnected to form an integrated structure.

[0172] For example, as shown in Figure 6B, the second portion 315b of the third capacitor electrode 315 of a subpixel in each pixel unit group 420 is interconnected with the second portion 315b of the third capacitor electrode 315 of a subpixel adjacent to that subpixel in a pixel unit group adjacent to the pixel unit group 420, forming an integrated structure.

[0173] For example, as shown in Figure 6A, adjacent third capacitor electrodes 315 in two adjacent subpixels in the first direction D1 may be integrally formed so as to receive the same second power supply voltage VSS.

[0174] For example, to reduce contact resistance, at least two vias 227 and 228 may be provided. For example, the at least two vias 227 may be arranged along the second direction D2, and the at least two vias 228 may be arranged along the second direction D2.

[0175] For example, the first conductive layer 301 further includes a connecting electrode 317 (an example of a second connecting electrode in this disclosure), which is used to electrically connect the second terminal of the data writing subcircuit to the first terminal of the recording subcircuit, that is, to electrically connect the second pole 161 of the first data writing transistor P1, the second pole 171 of the second data writing transistor N1, and the first capacitor electrode 141.

[0176] As shown in conjunction with Figures 6A and 6B, the connecting electrode 317 includes three ends and has, for example, a T-shaped structure. As shown in conjunction with Figure 3B, the first terminal of the connecting electrode 317 is electrically connected to the second pole of the first data writing transistor P1 by via 261a in the second insulating layer 202, the second terminal of the connecting electrode 317 is electrically connected to the second pole of the second data writing transistor N1 by via 261b in the second insulating layer 202, and the third terminal of the connecting electrode 317 is electrically connected to the first capacitor electrode 141 by via 261c in the second insulating layer 202.

[0177] For example, as shown in Figure 6B, in the second direction D2, the connecting electrode 314 at least partially overlaps with the third terminal of the connecting electrode 317. This arrangement makes the pixel arrangement more compact, thereby increasing the space utilization rate of the display board and improving the resolution of the display board.

[0178] As can be seen in conjunction with Figures 6A and 6B, the first conductive layer 301 further includes a first scan line connection 311 and a second scan line connection 312, the first scan line connection 311 being used to electrically connect to the first scan line so that the gate of the first data writing transistor P1 receives the first control signal SEL, and the second scan line connection 312 being used to electrically connect to the second scan line so that the gate of the second data writing transistor N1 receives the first control signal SEL_B.

[0179] For example, the first scan line connection portion 311 is electrically connected to the gate of the first data writing transistor P1 by via 221 in the second insulating layer 202, and the second scan line connection portion 312 is electrically connected to the gate of the second data writing transistor N1 by via 222 in the second insulating layer 202.

[0180] For example, as shown in Figure 6A, adjacent subpixels in the first direction D1 share either the first scan line connection 311 or the second scan line connection 312.

[0181] For a detailed explanation of the first scan line connection and the second scan line connection, please refer to the explanation in Figures 10A-10B below.

[0182] As shown in Figure 6A, the first conductive layer 301 further includes a data line connection portion 245, which is used to electrically connect to the data line so that the first pole of the first data writing transistor P1 and the first pole of the second data writing transistor N1 receive the data signal Vd transmitted over the data line.

[0183] As shown in Figure 6B, the data line connection portion 245 is electrically connected to the first pole 161 of the first data writing transistor P1 by via 223 in the second insulating layer 202, and is electrically connected to the first pole 171 of the second data writing transistor N1 by via 224 in the second insulating layer 202.

[0184] For example, as shown in Figure 6A, multiple data line connections 245 are spaced apart in the first direction D1, and are located, for example, at the boundary between two sub-pixel rows. For example, two adjacent sub-pixels in the second direction D2 share one data line connection 245.

[0185] For a detailed explanation of the data line connection section, please refer to the explanation of the second data line connection section in Figures 8A-8D below.

[0186] As shown in Figures 6A and 6B, the first conductive layer 301 further includes a connecting electrode 318, which is electrically connected to the first pole of the drive transistor N2 by a via 230 in the second insulating layer 202.

[0187] As shown in Figures 4A and 6B, the first conductive layer 301 further includes connecting electrodes 319a, 319b, and 319c, all of which are installed to bias the base of the transistor. For example, they are used to connect an N-type base to the first power supply voltage terminal to receive a first power supply voltage VDD (high voltage), or to connect a P-type base to the second power supply voltage terminal to receive a second power supply voltage VSS (low voltage), thereby avoiding parasitic phenomena such as base bias and improving circuit stability.

[0188] As shown in conjunction with Figure 4B, the connecting electrodes 319a and 319b are electrically connected to contact hole regions 411a and 411b in the second region (N-well region) 402 of the base substrate 101 by vias 262a and 262b in the second insulating layer 202, respectively, and are used to connect to the first voltage terminal VDD to bias the N-type base of the first data writing transistor P1. The connecting electrode 319c is electrically connected to the contact hole region 400a in the base substrate 101 by via 262c in the second insulating layer 202, and is used to connect to the second voltage terminal VSS to bias the P-type base on which the second data writing transistor N1 is located.

[0189] As shown in conjunction with Figures 6A-6B, the first conductive layer 301 further includes a bias voltage line 250 which extends along a first direction D1 to provide a second common voltage Vcom2 and is electrically connected to the gate of the bias transistor N3 by vias 263 in the second insulating layer 202.

[0190] As can be seen in conjunction with Figures 4B and 6A-6B, the first conductive layer 301 further includes a power line 260 which extends along a first direction D1 and is used to transmit a second power supply voltage VSS. The power line 260 is electrically connected to the first pole of a bias transistor N3 by via 264a in the second insulating layer 202 to provide the second power supply voltage VSS, and is electrically connected to a contact hole region 400b in the base substrate 101 by via 264b in the second insulating layer 202 to bias the P-type base on which the second data writing transistor N1 is located.

[0191] Figure 7A shows a schematic diagram of the second conductive layer 302, and Figure 7B shows the second conductive layer 302 based on the first conductive layer 301. Figure 7B also shows vias in the third insulating layer 203, which are used to connect the pattern in the first conductive layer 301 and the pattern in the second conductive layer 302. For clarity, the figures show only 4 rows and 6 columns of subpixels, and the boundary lines between two subpixel rows are indicated by dashed lines. Furthermore, Figure 7B shows the corresponding location of the cross-sectional line I-I' in Figure 3A.

[0192] As shown in Figure 7A, the pattern of the second conductive layer in two adjacent subpixels in the first direction D1 is symmetric with respect to the axis of symmetry along the second direction D2, and the pattern of the second conductive layer in two adjacent subpixels in the second direction D2 is symmetric with respect to the axis of symmetry along the first direction D1. Below, the pattern of the second conductive layer will be explained illustratively using one subpixel as an example.

[0193] As shown in Figure 7A, the second conductive layer 302 includes power lines 270a, 270b, 280a, and 280b extending along the first direction D1, with power lines 270a and 270b used to transmit the second power supply voltage VSS and power lines 280a and 280b used to transmit the first power supply voltage VDD. The power lines 270a, 280a, 270b, and 280b are arranged alternately one by one in the second direction D2.

[0194] As can be seen in conjunction with Figures 3B, 7A, and 7B, the power line 270a is electrically connected to the power line 260 in the first conductive layer 301 by a plurality of vias 235 arranged along a first direction D1 in the third insulating layer 203, thereby forming a parallel connection structure that effectively reduces the resistance of the wiring. For example, the power line 270b is electrically connected to the third capacitor electrode 315 by vias 236 arranged along a second direction D2 in the third insulating layer 203, for example, to provide the second power supply voltage VSS. For example, the power line 270b is further electrically connected to the third capacitor electrode 315 (315b) by vias 267 arranged along a second direction D2 in the third insulating layer 203, for example, to provide the second power supply voltage VSS.

[0195] For example, the power line 270b has a large width because both the first and second portions of the third capacitor electrode 315, which is electrically connected to the power line 270b, have a large surface area. Therefore, in the second direction D2, the width of the power line 270b is greater than the width of the power line 270a. By being installed with a large width, the power line 270b contributes to forming multiple connection holes 236, 267 between itself and the third capacitor electrode 315, thereby effectively reducing contact resistance.

[0196] As shown in conjunction with Figures 7A and 7B, the power line 280a is electrically connected to a connecting electrode 318 in the first conductive layer 301 by via 237 in the third insulating layer 203 to provide a first power supply voltage VDD, and is connected to the first pole of the drive transistor N2. The power line 280b is electrically connected to a connecting electrode 319a in the first conductive layer 301 by via 238 in the third insulating layer 203 to provide a high voltage bias to a second region (N-well region) 402 in the base substrate 101, for example, with multiple vias 238 arranged along a second direction D2.

[0197] For example, the power line 280b has a width greater than the width of the power line 280a in the second direction D2, because the connecting electrode 319a electrically connected to the power line 280b has a relatively large size in the second direction D2. By installing the power line 280b to have a relatively large width, it contributes to forming multiple connection holes 238 between it and the connecting electrode 319a, thereby increasing the contact area with the connecting electrode 319a and effectively reducing contact resistance.

[0198] For example, the second conductive layer 302 further includes a plurality of first scan lines 210 and a plurality of second scan lines 220 extending along the first direction D1. For example, the scan line 11 shown in Figure 1A may be the first scan line 210 or the second scan line 220.

[0199] As can be seen in conjunction with Figures 6A and 6B, the first scan line 210 is electrically connected to the first scan line connection 311 by via 231 in the third insulating layer 203, and the second scan line 220 is electrically connected to the second scan line connection 312 by via 232 in the third insulating layer 203.

[0200] For a detailed explanation of the first and second scan lines, please refer to the explanation in Figures 10A-10B below.

[0201] For example, as can be seen in conjunction with Figures 3B, 7A, and 7B, the second conductive layer 302 further includes a connecting electrode 323, which is electrically connected to a connecting electrode 314 in the first conductive layer 301 by vias 239 in the third insulating layer 203, and then connected to the second terminal 132 of the resistor 130. The connecting electrode 323 is used to electrically connect to the first electrode 121 of the light-emitting element 120. For example, there are at least two vias 239.

[0202] For example, as can be seen in conjunction with Figures 7A and 7B, the second conductive layer 302 further includes a connecting electrode 324, which is electrically connected to the connecting electrode 319b in the first conductive layer 301 by vias 265 in the third insulating layer 203, so as to be electrically connected to the contact hole region 411b of the second region (N-well region) 402 in the base substrate 101.

[0203] For example, as can be seen in conjunction with Figures 7A and 7B, the second conductive layer 302 further includes a connecting electrode 325, which is electrically connected to the connecting electrode 319c in the first conductive layer 301 by vias 266 in the third insulating layer 203, so as to be electrically connected to a contact hole region 400a in the base substrate 101.

[0204] For example, the connecting electrode 325 has a cross-shaped structure. For example, the connecting electrode 324 and the connecting electrode 325 are alternately distributed in the first direction D1 and are located at the boundary between two sub-pixel rows.

[0205] For example, as shown in Figure 7A, the second conductive layer 302 further includes a data line connection 244. As shown in conjunction with Figure 7B, the data line connection 244 is electrically connected to a data line connection 245 in the first conductive layer 301 by vias 233.

[0206] For example, as shown in Figure 7A, multiple data line connection points 244 are spaced apart in the first direction D1, and one connection electrode 324 or connection electrode 325 is installed between every two adjacent data line connection points 244.

[0207] For example, the data line connection portion 244 is located at the boundary between two sub-pixel rows. For example, two adjacent sub-pixels in the second direction D2 share one data line connection portion 244.

[0208] For example, as can be seen in conjunction with Figures 7A and 7B, in the second direction D2, the data line connection portions 244 in each subpixel of each column are alternately located on both sides of the data line connection portion 245, and are electrically connected to the first and second terminals of the data line connection portion 245 by vias 233 and 234, respectively, thereby connecting the data line connection portion 245 to different data lines.

[0209] For a detailed explanation of the data line connection section, please refer to the explanation of the first data line connection section in Figure 11A-11D below.

[0210] Figure 8A shows a schematic diagram of the third conductive layer 303, and Figure 8B shows the third conductive layer 303 based on the second conductive layer 302. Figure 8B also shows vias in the fourth insulating layer 204, which are used to connect the pattern in the second conductive layer 302 and the pattern in the third conductive layer 303. For clarity, the figures show only the conductive patterns corresponding to 4 rows and 6 columns of subpixels, and Figure 8A shows the boundary line of 2 rows of subpixels with a dashed line. Furthermore, Figure 8B shows the corresponding position of the cross-sectional line I-I' in Figure 3A.

[0211] For example, the third conductive layer 303 includes a plurality of data lines extending along a second direction D2, which are used to connect to a first terminal of a data writing subcircuit in a subpixel to provide a data signal Vd. For example, as shown in Figure 8A, the plurality of data lines include a plurality of first data lines 241 and a plurality of second data lines 242 arranged alternately one by one in the first direction D1. For example, the data line 12 shown in Figure 1A may be either a first data line 241 or a second data line 242.

[0212] For example, the data line is divided into multiple data line groups, each data line group containing one first data line 241 and one second data line 242. For example, each sub-pixel row is connected to one data line group, i.e., connected to one first data line 241 and one second data line 242, i.e., one row of sub-pixels is driven by two data lines. In this way, it contributes to reducing the load on each data line, thereby improving the driving capability of the data lines, reducing signal delay, and improving the display effect.

[0213] As shown in Figure 8B, the first data line 241 is electrically connected by via 403 in the fourth insulating layer 204 to a data line connection 244 located between the first row of subpixels and the second row of subpixels in the second conductive layer 302 shown in Figure 7B, thereby providing data signals to the first and second rows of subpixels, and the second data line 242 is electrically connected by via 404 in the fourth insulating layer 204 to a data line connection 244 located between the third row of subpixels and the fourth row of subpixels in the second conductive layer 302 shown in Figure 7B, thereby providing data signals to the third and fourth rows of subpixels.

[0214] For a detailed explanation of the first and second data lines, refer to the following explanation of Figures 11A-11D. To facilitate comparison, Figure 8B shows the positions corresponding to the cross-sectional lines II-II' and III-III' in Figure 11B.

[0215] For example, the third conductive layer 303 includes power lines 330 and 340 extending along the second direction D2. Power line 330 is used to transmit a first power supply voltage VDD, and power line 340 is used to transmit a second power supply voltage VSS. As shown in Figure 8A, power lines 330 and 340 are arranged alternately one at a time in the first direction D1.

[0216] As shown in Figure 8B, the power lines 330 are electrically connected to the power lines 280a and 280b in the second conductive layer 302 by vias 405 and 406 in the fourth insulating layer 204, respectively, thereby forming a mesh-like power line structure for transmitting the first power supply voltage. Such a structure contributes to reducing the resistance in the power lines, thereby reducing the voltage drop in the power lines and contributing to the uniform transmission of the first power supply voltage VDD to each subpixel of the display board. The power lines 330 are further electrically connected to the contact electrode 324 (see Figure 7A) in the second conductive layer 302 by via 407 in the fourth insulating layer, thereby biasing the N-type base on which the first data writing transistor P1 and resistor 130 are located, and are electrically connected to the contact hole region 411b in the second region (N-well region) 402 of the base board 101.

[0217] As shown in Figure 8B, the power lines 340 are electrically connected to power lines 270a and 270b in the second conductive layer 302 by vias 408 and 409 in the fourth insulating layer 204, respectively, thereby forming a mesh-like power line structure for transmitting the second power supply voltage. Such a structure contributes to reducing resistance in the power lines, thereby reducing voltage rise in the power lines and contributing to the uniform transmission of the second power supply voltage VSS to each subpixel of the display substrate. The power lines 340 are further electrically connected to the contact electrode 325 in the second conductive layer 302 (see Figures 3B and 6A) by via 412 in the fourth insulating layer, thereby biasing the P-type base on which transistors N1-N3 are located, and electrically connected to the contact hole region 400a in the base substrate 101.

[0218] As shown in Figure 8A, the third conductive layer 303 further includes a connecting electrode 333 located between the first data line 241 and the second data line 242 in a data line group. As shown in Figure 7B, the connecting electrode 333 is electrically connected to the power line 270b in the second conductive layer by vias 413 in the fourth insulating layer, for example, there are at least two vias 413, so that the connecting electrode 333 can make sufficient contact with the power line 270b and reduce contact resistance. By providing the connecting electrode 333 connected in parallel with the power line 270b, it is possible to reduce the resistance in the power line 270b, thereby reducing the voltage rise in the power line and contributing to the uniform transmission of the second power supply voltage VSS to each subpixel of the display board.

[0219] As shown in Figures 3B, 8A, and 8B, the third conductive layer 303 further includes a connecting electrode 334, which is electrically connected to a connecting electrode 323 in the second conductive layer 302 by vias 414 in the fourth insulating layer, and then connected to the second terminal 132 of the resistor 130. The connecting electrode 334 is used to electrically connect to the first electrode 121 of the light-emitting element 120. For example, there are at least two vias 414.

[0220] As shown in Figures 8A and 8B, the third conductive layer 303 further includes a shielding electrode 341, for example, extending along a second direction D2 and located between a first data line 241 and a second data line 242 in a group of data lines, for example, the first data line 241 and the second data line 242 are symmetrically positioned on both sides of the shielding electrode 341 of the second data line. The shielding electrode 341 is positioned between the two data lines and performs a shielding function to prevent the signals on the two data lines from interfering with each other. For example, the shielding electrode 341 receives a constant voltage to improve its shielding capability. In this embodiment, the shielding electrode 341 is used to receive a second power supply voltage VSS.

[0221] For example, the display board includes multiple shielding electrodes 341 that are installed in one-to-one correspondence with multiple data line groups, and each shielding electrode is located between the first data line and the second data line in the corresponding data line group.

[0222] As shown in Figure 8A, the connecting electrodes 333, 334, and shielding electrode 341 are positioned in the second direction D2 and between the first data line 241 and the second data line 242. The connecting electrodes 333, 334, and shielding electrode 341 form a single shielding wall, which provides a shielding function over the entire range in which the first data line 241 and the second data line 242 extend, preventing interference between the signals on the two data lines.

[0223] For example, as shown in Figure 8A, the connecting electrode 333 and the shielding electrode 341 are located on both sides of the connecting electrode 334 and are spaced apart from it. One end of the connecting electrode 333 that is close to the connecting electrode 334 has a projection 333a, which is L-shaped, with its first branch extending along the first direction D1 and connected to the main body of the connecting electrode 333, and its second branch extending along the second direction D2, which is close to the connecting electrode 334, and overlapping with the gap between the connecting electrode 333 and the connecting electrode 334 in the first direction D1, thereby improving the shielding capability and thus avoiding signal interference between the two data lines.

[0224] Similarly, one end of the shielding electrode 341 adjacent to the connecting electrode 334 has an L-shaped projection 341a to further block the gap between the shielding electrode 341 and the connecting electrode 334, thereby improving the shielding ability.

[0225] In this way, the shielding wall achieves complete shielding in the second direction D2, and the first data line 241 and the second data line 242 do not have any areas directly facing each other in the first direction D1, thus performing an excellent signal shielding function, resulting in good stability of the displayed data and improved display effect.

[0226] Figure 9A shows a schematic diagram of the fourth conductive layer 304, and Figure 9B shows the fourth conductive layer 304 based on the third conductive layer 303. Figure 9B also shows vias in the fifth insulating layer 205, which are used to connect the pattern in the third conductive layer 303 and the pattern in the fourth conductive layer 304. For clarity, the figures show only 4 rows and 6 columns of subpixels, and the boundary lines of 2 rows of subpixels are indicated by dashed lines. Furthermore, Figure 9B shows the corresponding positions of the cross-sectional lines I-I' in Figure 3A.

[0227] For example, the fourth conductive layer 304 includes power lines 350 and 360 extending along the second direction D2. Power line 350 is used to transmit a first power supply voltage VDD, and power line 360 ​​is used to transmit a second power supply voltage VSS. As shown in Figure 9A, power lines 350 and 360 are arranged alternately one at a time in the first direction D1.

[0228] For example, multiple power lines 350 and multiple power lines 330 are installed in a one-to-one correspondence, and multiple power lines 360 and multiple power lines 340 are installed in a one-to-one correspondence. In a direction perpendicular to the base board 101, each power line 350 overlaps with and is electrically connected (e.g., in parallel) to its corresponding power line 330, and each power line 360 ​​overlaps with and is electrically connected (e.g., in parallel) to its corresponding power line 340. This reduces resistance in the power lines and improves the uniformity of the display.

[0229] As shown in Figure 9B, power line 350 is electrically connected to the corresponding power line 330 by via 251 in the fifth insulation layer 205, and power line 360 ​​is electrically connected to the corresponding power line 340 by via 252 in the fifth insulation layer. For example, there are at least two vias 251 and 252.

[0230] As can be seen in conjunction with Figures 9A and 9B, the fourth conductive layer 304 further includes a connecting electrode 342, which is electrically connected to a connecting electrode 333 in the third conductive layer 303 by vias 253 in the fifth insulating layer, for example, there are at least two vias 253, so that the connecting electrode 342 makes sufficient contact with the connecting electrode 333 and reduces contact resistance. The installation of the connecting electrode 342 contributes to further reducing the resistance in the power line 270b, thereby reducing the voltage rise in the power line and contributing to the uniform transmission of the second power supply voltage VSS to each subpixel of the display board.

[0231] As can be seen in conjunction with Figures 3B, 9A, and 9B, the fourth conductive layer 304 further includes a connecting electrode 343, which is electrically connected to a connecting electrode 334 in the third conductive layer 303 by vias 254 in the fifth insulating layer, and then connected to the second terminal 132 of the resistor 130. The connecting electrode 343 is used to electrically connect to the first electrode 121 of the light-emitting element 120. For example, there are at least two vias 254.

[0232] As shown in conjunction with Figures 9A and 9B, the fourth conductive layer 304 further includes a connecting electrode 344, which is electrically connected to a shielding electrode 341 in the third conductive layer 303 by a via 255 in the fifth insulating layer. As shown in Figure 9A, the fourth conductive layer 304 further includes a connection portion 345 that connects the connecting electrode 344 to a power line 360 ​​directly adjacent to the connecting electrode 344.

[0233] For example, as shown in Figure 9A, the connecting electrodes 344 located on both sides of the power line 360 ​​are installed symmetrically with respect to the power line 360. The power line 360, the connecting electrodes 344 located on both sides thereof, and the connecting portions 345 corresponding to the connecting electrodes are interconnected to form an integrated structure. In this way, the power line 360 ​​can provide the shielding electrode 341 with a second power supply voltage VSS to improve the shielding capability of the shielding electrode.

[0234] For example, conductivity can be achieved by further filling each via with a conductive material (e.g., tungsten).

[0235] Figure 9B also shows the contact hole region 256 of the connecting electrode 343, which is used to electrically connect to the first electrode 121 of the light-emitting element 120.

[0236] Note that, along the cross-sectional line I-I', the portion of the connecting electrode 343 located in the contact hole region 256 is not continuous with the portion of the connecting electrode 343 corresponding to the via 254 (region F shown in Figure 9B). However, for the sake of simplicity, the cross-sectional view shown in Figure 3B shows the continuous connecting electrode 343, the contact hole region 256 and the via 254, i.e., it matches the actual situation. For example, the display substrate 10 further includes a sixth insulating layer 206, as shown in Figure 3B, in which a via 257 is formed corresponding to the contact hole region 256 of the connecting electrode 343, the via 257 is filled with a conductive material (e.g., tungsten), and a flat surface is formed by a polishing process (e.g., chemical mechanical polishing) to form the light-emitting element 120.

[0237] For example, the number of vias 257 is at least two.

[0238] For example, as shown in Figure 3B, the number of contact hole regions for electrical connection in the connecting electrodes 314, 323, 334, and 343 connected to the first electrode 121 of the light-emitting element 120 is at least two, thereby reducing the contact resistance between the connecting electrodes and, consequently, the connection resistance between the resistor 130 and the first electrode 121 of the light-emitting element 120. This reduces the voltage drop in the transmission path through which the data signal is transmitted from the resistor 130 to the first electrode 121, mitigating problems such as color cast and display unevenness caused by anode potential loss (grayscale loss) due to the voltage drop, and improving the display effect.

[0239] For example, as shown in Figure 3B, vias 257, 254, and 414 corresponding to the first electrode 121 of the light-emitting element 120 do not overlap each other in the direction perpendicular to the base substrate 101. When vias are stacked in the direction perpendicular to the substrate, connection problems, disconnections, and unevenness are likely to occur in the areas where the vias are located. Therefore, installing them as described above improves the quality of the electrical connection of the first electrode 121 of the light-emitting element 120 and improves the display effect.

[0240] As shown in Figure 3B, the light-emitting element 120 includes a first electrode 121, a light-emitting layer 123, and a second electrode 122, which are sequentially arranged on the sixth insulating layer 206. For example, the first electrode 121 and the second electrode 122 are the anode and cathode of the OLED, respectively. For example, multiple first electrodes 121 are spaced apart on the same layer and correspond one-to-one with multiple subpixels. For example, the second electrode 122 is a common electrode, and its entire surface is arranged within the display substrate 10.

[0241] For example, as shown in Figure 3B, the display substrate further includes a first package layer 124, a color filter layer 125, and a cover plate 126 located on the side away from the base substrate 101 of the light-emitting element 120.

[0242] For example, the first package layer 124 is configured to seal the light-emitting element to prevent damage to the device due to the intrusion of external moisture and oxygen into the light-emitting element and pixel circuit. For example, the package layer 124 includes an organic thin film or a structure in which organic thin films and inorganic films are alternately laminated. For example, a water-absorbing layer may be further placed between the package layer 124 and the light-emitting element, configured to absorb water vapor and sols remaining in the light-emitting element during the manufacturing process in the earlier stages. The cover plate 126 is, for example, a glass cover plate.

[0243] For example, as shown in Figure 3B, the display substrate may further include a second package layer 127 located between the color filter layer 125 and the cover plate 126, the second package layer 127 being able to protect the color filter layer 125.

[0244] For example, the light-emitting element 120 is configured to emit white light and, in combination with the color filter layer 124, achieves full-color display.

[0245] In some other examples, the light-emitting element 120 is configured to emit light of the three primary colors, in which case the color filter layer 124 is not essential. The embodiments of this disclosure do not limit the method by which the display substrate 10 achieves full-color display.

[0246] Table A below shows exemplary thickness ranges and exemplary values ​​for the first to sixth insulating layers; Table B shows exemplary thickness ranges and exemplary values ​​for the first to fourth conductive layers; Table C shows exemplary sizes and exemplary values ​​for via VIA2 in the second insulating layer, via VIA3 in the third insulating layer, via VIA4 in the fourth insulating layer, via VIA5 in the fifth insulating layer, and via VIA6 in the sixth insulating layer; and Table D shows exemplary values ​​for the channel width, length, and aspect ratio of each transistor (N1-N4, P1), but this does not limit the present disclosure.

[0247] [Table 1]

[0248] [Table 2]

[0249] [Table 3]

[0250] [Table 4]

[0251] For example, as shown in Table A, among the first to sixth insulating layers, the thickness of the first insulating layer 201 is the smallest, and the thickness of the second insulating layer 202 is the largest. This is because the first insulating layer 201 includes the gate insulating layer of each transistor and further includes the dielectric layer 104 of the storage capacitor Cst. Setting the thickness of the first insulating layer 201 to be small contributes to improving the gate control ability of the transistor and also contributes to obtaining a large storage capacity. In addition, the second insulating layer 202 is used as a field oxide layer, and setting its thickness to be large contributes to the electrical separation between each transistor. For example, the thicknesses of the third insulating layer 203, the fourth insulating layer 204, the fifth insulating layer 205, and the sixth insulating layer 206 are the same or close. For example, the thickness of the second insulating layer 202 is 1.5 - 2 times the thickness of the third insulating layer 203 / the fourth insulating layer 204 / the fifth insulating layer 205 / the sixth insulating layer 206.

[0252] For example, the planar shape of the via may be rectangular (e.g., square) or circular, and the size in Table C indicates the average side length of the rectangle or the hole diameter. For example, as shown in Table C, the sizes of the plurality of vias in each insulating layer are the same. For example, among the second to sixth insulating layers, the size of the via in the sixth insulating layer 206 is the largest. This is because the sixth insulating layer 206 is closest to the light-emitting element, and in the driving process of the light-emitting element, the current converges from the bottommost transistor upward to the light-emitting element. Therefore, the size of the via in the sixth insulating layer 206 is made the largest to transmit a large converging current.

[0253] For example, the range of the distance between the first data writing transistor P1 and the second data writing transistor N1 is 0.4 - 0.45 micrometers, for example, 0.42 micrometers, thereby contributing to improving the pixel density. As shown in FIG. 4B, the distance D0 is the distance between the closest sides of the gate 160 of the first data writing transistor P1 and the gate 170 of the second data writing transistor N1.

[0254] For example, as shown in FIG. 4B, the equivalent length of the resistor 130 is 4.4 micrometers, and the average width is 0.42 micrometers.

[0255] For example, as shown in FIG. 4B, the effective capacitance area of the storage capacitor Cst is 20 square micrometers, that is, the effective area of the polycrystalline silicon layer 102 for forming the storage capacitor Cst is 20 square micrometers. For example, the ratio of the area of the storage capacitor Cst to each sub-pixel is 20%-35%, for example, 27%. The display substrate according to the embodiments of the present disclosure can effectively increase the area ratio of the storage capacitor through reasonable arrangement, thereby improving the capacitance value.

[0256] For example, the thickness of the polycrystalline silicon layer 102 is 200 nanometers.

[0257] At least one embodiment of the present disclosure further provides a pixel structure comprising a base substrate and a pixel row, a first scan line, and a second scan line located on the base substrate. The pixel row comprises a plurality of sub-pixels located on the base substrate and arranged along a first direction, the first scan line and the second scan line extending along the first direction, and each sub-pixel comprises a pixel circuit comprising a data writing subcircuit, a recording subcircuit, and a driving subcircuit. The data writing subcircuit comprises a first control electrode, a second control electrode, a first terminal, and a second electrode, the first and second control electrodes of the data writing circuit configured to receive a first control signal and a second control signal, respectively, the first terminal of the data writing subcircuit configured to receive a data signal, the second terminal of the data writing circuit electrically connected to the first terminal of the recording subcircuit and configured to transmit the data signal to the first terminal of the recording subcircuit in response to the first and second control signals, the driving subcircuit comprises a control terminal, a first terminal, and a second terminal, the control terminal of the driving subcircuit electrically connected to the first terminal of the recording subcircuit The drive subcircuit is connected such that the first terminal of the drive subcircuit is configured to receive a first power supply voltage, the second terminal of the drive subcircuit is used to connect to a light-emitting element, the drive subcircuit is configured to drive the light-emitting element to emit light in response to a voltage at the first terminal of the recording subcircuit, the first scan line is electrically connected to a first control electrode of the data writing circuit of the plurality of subpixels to provide the first control signal, the second scan line is electrically connected to a second control electrode of the data writing circuit of the plurality of subpixels to provide the second control signal, the first scan line and the second scan line have the same resistance and the same orthographic area on the base substrate.

[0258] In some examples, for instance, the first and second scan lines are portions of the wiring in the display area that transmit the corresponding control signals from the scanning drive circuit to each sub-pixel, and therefore, when comparing resistance values ​​and areas, portions of the wiring located outside the display area are not considered.

[0259] In some other examples, the first and second scan lines may represent all portions of the wiring that transmits the corresponding control signals from the scan drive circuit to each subpixel, that is, portions of the wiring that are located in the display and non-display areas, for example, portion S shown in Figure 1A. For example, the first control signal SEL and the second control signal SEL_B can be output from the same gate drive circuit unit (e.g., the GOA unit).

[0260] This configuration ensures that the resistive capacitance (RC) loads on the first and second scan lines are the same. As shown in Figure 1A, during the transmission of control signals from the scanning drive circuit 14 to each sub-pixel, the proportion of the scan line 11 (e.g., the first and second scan lines) located outside the display area (shown in the dashed frame) is small. Therefore, by setting the resistive capacitance loads on the portion of the scan line 11 located within the display area to be the same, the synchronization of the first control signal SEL and the second control signal SEL_B can be improved. As shown in conjunction with Figure 2C, for example, when moving from data writing stage 1 to light emission stage 2, this configuration allows the rising edge of the first control signal SEL and the falling edge of the second control signal SEL_B to occur at the same time. This improves the interference prevention performance of the pixel circuit.

[0261] The disclosure further provides a display substrate comprising a plurality of pixel structures, wherein a plurality of pixel rows in the plurality of pixel structures are arranged along a second direction, and the first direction and the second direction intersect, thereby arranging a plurality of subpixels in the plurality of pixel rows as a plurality of pixel columns.

[0262] Furthermore, the pixel structure according to the embodiments of this disclosure can be applied to the display substrate 10 according to any one of the embodiments described above. However, the pixel structure according to the embodiments of this disclosure is not limited to silicon-based display substrates, but can also be applied to glass substrates or flexible substrates, for example. In such cases, the light-emitting element may have a structure that emits light from the bottom or from both sides.

[0263] Figure 10A shows a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. For clarity, the figure shows a 2x6 subpixel, i.e., includes only two of the above pixel structures. Compared to the display substrate described in Figure 3A, this display substrate omits the third and fourth conductive layers. The following describes, with reference to Figure 10A, the arrangement of the first and second scan lines in the display substrate and pixel structure according to embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0264] For example, as shown in Figure 10A, each sub-pixel row is connected to one first scan line 210 and one second scan line 220, respectively, but this is not limited to the present disclosure.

[0265] For example, the display board 10 further includes a plurality of first scan line connection units 311 electrically connected to a first scan line 210 and a plurality of second scan line connection units 312 electrically connected to a second scan line 220, wherein the first scan line 210 is electrically connected by the plurality of first scan line connection units 311 to a first control electrode (i.e., the gate of the first data writing transistor) of a data writing circuit for a row of subpixels, and the second scan line 220 is electrically connected by the plurality of second scan line connection units 312 to a second control electrode (i.e., the gate of the second data writing transistor) of a data writing circuit for a row of subpixels.

[0266] For example, the first scanning line 210 and the second scanning line 220 are insulated and installed on the same layer and are made of the same material.

[0267] For example, the plurality of first scan line connection portions 311 and the plurality of second scan line connection portions 312 are installed in the same layer at intervals, made of the same material, and located in a different conductive layer from the first scan line 210 and the second scan line 220.

[0268] Figure 10B shows an enlarged schematic diagram of the dashed frame region E in Figure 10A. For clarity, the figure shows only the gates of the first data writing transistor P1 and the second data writing transistor N1, the first scan line 210, the second scan line 220, and the first scan line connection 311 and the second scan line connection 312. To facilitate comparison, Figure 7B also shows the corresponding location of region E. Figure 10C shows a cross-sectional view along the cross-sectional line V-V' in Figure 10B.

[0269] For example, the first scan line 210 and the second scan line 220 have the same length and line width.

[0270] For example, the first scan line connection portion 311 and the second scan line connection portion 312 are arranged alternately in the first direction D1, and their extension direction is different from the first direction D1, with the first scan line connection portion 311 intersecting both the orthographic projections of the first scan line 210 and the second scan line 220 on the base substrate, and the second scan line connection portion 312 intersecting both the orthographic projections of the first scan line 210 and the second scan line 220 on the base substrate. For example, both the first scan line connection portion 311 and the second scan line connection portion 312 are linear structures and extend along the second direction D2.

[0271] For example, the total orthographic area of ​​the multiple first scan line connection sections 311 on the base substrate is the same as the total orthographic area of ​​the multiple second scan line connection sections 312 on the base substrate. Therefore, the parasitic capacitances of the multiple first scan line connection sections 311 and the multiple second scan line connection sections 312 are the same.

[0272] When installed in this manner, the load due to parasitic capacitance in the wiring (including the corresponding scan lines and connections) when the first and second control signals are transmitted from the first and second scan lines to the data writing subcircuit is kept the same, thereby further improving the synchronization of the first and second control signals.

[0273] For example, the sizes of the first data writing transistor P1 and the second data writing circuit N1 electrically connected to the first scanning line and the second scanning line respectively are also the same. Therefore, the loads on the scanning lines to which they are respectively connected are also the same, further improving the synchronization between the first control signal and the second control signal, thereby improving the interference prevention performance of the circuit.

[0274] For example, each of the plurality of first scanning line connection portions 311 has the same length along the second direction D2, and the line widths of each of the plurality of first scanning line connection portions 311 are the same. Each of the plurality of second scanning line connection portions 312 has the same length along the second direction D2, and the line widths of each of the plurality of second scanning line connection portions 312 are the same.

[0275] For example, the first scanning line 210 is electrically connected to the first scanning line connection portion 311 by a via 231, the second scanning line 220 is connected to the second scanning line connection portion 312 by a via 232, and both the via 231 and the via 232 are located in the third insulating layer 203.

[0276] For example, as shown in FIG. 10B, the first control electrode group 191 composed of the first control electrodes of two adjacent sub-pixels in the first direction D1 is alternately arranged one by one in the first direction D1 with the second control electrode group 192 of two adjacent sub-pixels.

[0277] For example, as shown in FIG. 10B, the first scanning line connection portion 311 is electrically connected to the first control electrode group 191 or the first control electrode by a via 221, and the second scanning line connection portion 312 is electrically connected to the second control electrode group 192 or the second control electrode by a via 222. For example, the plurality of first scanning line connection portions 311 and the plurality of first control electrode groups 191 are electrically connected in a one-to-one correspondence, and the plurality of second scanning line connection portions 312 and the plurality of second control electrode groups 192 are electrically connected in a one-to-one correspondence.

[0278] For example, the first scan line 210313 and the second scan line 220 are located on the same side of the plurality of first control electrode groups 191 and the plurality of second control electrode groups 192, and the first scan line 210 is closer to the plurality of first control electrode groups 191 and the second control electrode groups 192.

[0279] For example, as shown in Figure 10B, in a direction perpendicular to the base substrate, the first scan line 210 intersects both the first scan line connection 311 and the second scan line connection 312, and the second scan line 220 intersects both the first scan line connection 311 and the second scan line connection 312. Via 231 is located where the first scan line 210 and the first scan line connection 311 intersect, and via 232 is located where the second scan line 220 and the second scan line connection 312 intersect.

[0280] For example, as shown in Figure 10B, vias 231 and 232 are arranged alternately in the first direction D1 and offset in the second direction, with via 231 being closer to the plurality of first control electrode groups 191 and second control electrode groups 192 than via 232.

[0281] As shown in Figure 10B, one end of the second scan line connection section 312 is electrically connected to the second scan line 220 by via 232, and the other end is electrically connected to the second control electrode or group of second control electrodes to be connected by via 222. The first scan line 210 passes between via 232 and via 222.

[0282] For example, as shown in Figure 10B, the first scan line connection section 311 includes a main body section 321 and an extension section 322, the extension section 322 being the portion of the main body section 321 that extends away from the first scan line 20 along a second direction. The main body section 321 is used to electrically connect the first scan line connection section 311 to a first control electrode or a group of first control electrodes, and is located between the first scan line 210 and the first control electrode or group of first control electrodes connected thereto in the second direction D2, while the extension section 322 is located on the side of the first scan line 210 away from the first control electrode or group of first control electrodes to which it is connected in the second direction D2.

[0283] Here, the extension 322 is a virtual structure and therefore cannot actually perform the function of electrical connection. With the extension 322 installed, the first scan line connection 311 and the second scan line connection 312 have the same length, the same area, and form the same capacitive load.

[0284] For example, as shown in Figure 10B, via 221 is located in the middle of the first control electrode group 191, and via 222 is located in the middle of the second control electrode group 192. The two first control electrodes in the first control electrode group 191 are axially symmetric with respect to the first scan line connection portion 311 and its extension, which are connected to the first control electrode group, and the two second control electrodes in the second control electrode group 192 are axially symmetric with respect to the second scan line connection portion 312 and its extension, which are connected to the second control electrode group.

[0285] As shown in Figure 10A, the first scan line 210, which is connected to two adjacent pixel rows, is symmetric with respect to the axis of symmetry along the first direction D1, and the second scan line 220, which is connected to two adjacent pixel rows, is symmetric with respect to the axis of symmetry along the first direction D1.

[0286] The display board 10 includes a plurality of data lines extending along a second direction D2, which are used to connect to a first terminal of a data writing subcircuit in a subpixel to provide a data signal Vd.

[0287] Figure 11A shows a schematic diagram of a display board according to several other embodiments of the present disclosure, and the figure shows a schematic diagram of data lines on a display board according to at least one embodiment of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0288] As can be seen in conjunction with Figure 8A, the data line is divided into several data line groups, each data line group containing one first data line 241 and one second data line 242. The multiple data line groups are electrically connected in a one-to-one correspondence with multiple pixel rows to provide the data signal Vd. Each sub-pixel row is electrically connected to one first data line 241 and one second data line 242, i.e., one row of sub-pixels is driven by two data lines.

[0289] For example, as shown in Figure 11A, each sub-pixel column is connected to two data lines, namely the first data line 241 and the second data line 242. For each sub-pixel in each column, two sub-pixels located in adjacent pixel rows, the nth and the (n+1)th, constitute one pixel group 240, sharing one data line, where n is an odd or even number greater than 0. For each sub-pixel in each column, in the second direction D2, the Nth pixel group 240 is connected to the first data line 241, and the (n+1)th pixel group 240 is connected to the second data line 242, where N is a natural number, i.e., in the second direction D2, the pixel groups 240 are alternately connected to the first data line 241 and the second data line 242, with odd-numbered pixel groups sharing one data line and even-numbered pixel groups sharing the other data line.

[0290] By using two data lines to drive one sub-pixel row, the load on each data line can be reduced, thereby improving the driving capability of the data lines, reducing signal delay, and improving display performance.

[0291] Since the display board according to the embodiment of this disclosure has structural symmetry, the arrangement of signal lines can be matched with the data line driving method, thereby achieving the effect of design optimization.

[0292] For example, as shown in conjunction with Figure 4A, the first poles of two first data writing transistors P1 in one pixel group 240 are interconnected to form an integrated structure (see area A1), and the first poles of two second data writing transistors N1 are interconnected to form an integrated structure (see area A2). Therefore, in combination with the data line driving method described above, the data line can be electrically connected to the two first data writing transistors P1 or the two second data writing transistors N2 in the pixel group 240 by providing connection vias for connecting to the data line on the first pole of the integrated structure within a limited contact area, without having to provide connection vias for connecting to the data line on each of the two transistors. This not only saves process time but also makes the layout design more compact and improves the resolution of the display board, even when limited by design rules.

[0293] Figure 11B shows the data line connection structure in two adjacent pixel groups 240. For clarity, only the sub-diagrams where the first and second data lines are connected to subpixels in each pixel group are selectively shown. The sub-diagrams corresponding to the two pixel groups are connected to represent the continuity relationship of the signal lines, and the dashed line indicates the boundary line between the two pixel groups.

[0294] As shown in Figure 11B, in a direction perpendicular to the base substrate, the first data line 241 overlaps with the first data writing transistor P1 and is electrically connected to the first poles of two adjacent first data writing transistors P1 in one pixel row 240, and the second data line 242 overlaps with the second data writing transistor N1 and is electrically connected to the first poles of two adjacent second data writing transistors N1 in one pixel group 240.

[0295] For example, as shown in Figure 11B, in the direction perpendicular to the base substrate, the first data line 241 overlaps with the gate 160 of the first data writing transistor P1, and the second data line 242 overlaps with the gate 170 of the second data writing transistor N1. That is, both the first data line 241 and the second data line 242 pass through the pixel region, thereby increasing space utilization without occupying additional pixel space.

[0296] Figures 11C and 11D show cross-sectional views along the cross-sectional lines II-II' and III-III' of Figure 11B, respectively, which are, for example, along the first direction D1. For clarity, the figures show only the structures electrically connected to the data lines and omit other structures. As shown in Figures 11C and 11D, the first data line 241 and the second data line 242 are located in the third conductive layer 303 and are electrically connected, respectively, to the corresponding first data line connectors 244 in the second conductive layer 302 by vias 403 and 404 in the fourth insulating layer 204. In a direction perpendicular to the base substrate, the first data line connectors 244 overlap with the corresponding first data line 241 or second data line 242. The first data line connection portion 244 is electrically connected to the second data line connection portion 245 in the first conductive layer 301 by vias 233 and 234 in the third insulating layer 203, and the second data line connection portion 245 is electrically connected to the first pole 161 of the first data writing transistor P1 and the first pole 171 of the second data writing transistor N1, respectively, by vias 223 and 224 in the second insulating layer 202, thereby transmitting data signals to the transistors.

[0297] In one pixel row, the first poles of two adjacent first data writing transistors P1 and the first poles of two second data writing transistors N1 are connected to form an integrated structure. Furthermore, the second data line connection section 245 electrically connects the first pole of the first data writing transistor P1 and the first pole of the second data writing transistor N1 in one subpixel. Thus, the second data line connection section 245 electrically connects the first poles 161 of the two first data writing transistors P1 and the first poles 171 of the two second data writing transistors N1 of two adjacent subpixels in the second direction D2 within one subpixel group, and connects to the corresponding first data line 241 or second data line 242 by the corresponding first data line connection section 244. As can be seen from this, the first poles of the four transistors can be electrically connected to the data lines by simply installing one via each in the third and fourth insulating layers, significantly saving layout space and increasing space utilization.

[0298] As shown in Figures 11B-11D, for example, the first data line 241 and the second data line 242 are installed symmetrically on both sides of the second data line connection 245.

[0299] For example, as shown in Figures 11C and 11D, the third conductive layer further includes a shielding electrode 341 located between a first data line 241 and a second data line 242, for example, the first data line 241 and the second data line 242 are symmetrically positioned on either side of the shielding electrode 341 of the second data line. The shielding electrode 341 is positioned between the two data lines and performs a shielding function to prevent the signals on the two data lines from interfering with each other. For example, the shielding electrode 341 is configured to receive a constant voltage to improve its shielding capability, for example, the shielding electrode 341 is configured to receive a second power supply voltage.

[0300] For example, as shown in Figure 4A, the first poles 161 of the first data writing transistor P1 of two adjacent subpixels 100 in the second direction D2 are interconnected to form an integrated structure, and the first poles 171 of the second data writing transistor N1 of two adjacent subpixels 100 in the second direction D2 are interconnected to form an integrated structure.

[0301] For example, the materials for the first to fourth conductive layers are metallic materials, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials combining these metals. For example, the materials for the first to fourth conductive layers may also be conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and zinc aluminum oxide (AZO).

[0302] For example, the material of the first to sixth insulating layers is, for example, an inorganic insulating layer, which is an insulating material containing silicon oxides such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride, or silicon nitrogen oxide, or metallic nitrogen oxides such as aluminum oxide or titanium nitride.

[0303] For example, the light-emitting element 120 has an upper light-emitting structure, the first electrode 121 is reflective, and the second electrode 122 is transmissive or semi-transmissive. For example, the first electrode 121 is made of a material with a high work function, such as an ITO / Ag / ITO stacked structure, to serve as the anode, and the second electrode 122 is made of a material with a low work function, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material, to serve as the cathode.

[0304] At least one embodiment of the present disclosure further provides a display panel, each including one display substrate 10. The display substrate 10 according to at least one embodiment of the present disclosure may include a light-emitting element 120, but may not include the light-emitting element 120, that is, the light-emitting element 120 can be formed in the panel factory after the display substrate 10 is completed. If the display substrate 10 itself does not include the light-emitting element 120, the display panel according to the embodiment of the present disclosure further includes the light-emitting element 120 in addition to the display substrate 10.

[0305] At least one embodiment of the present disclosure further provides a display device 40, as shown in Figure 12, which includes any one of the above-described display substrates 10 or display panel, and the display device in this embodiment may be any product or component having a display function, such as a display, OLED panel, OLED television, electronic paper, mobile phone, tablet PC, notebook computer, digital photo frame, navigator, etc.

[0306] The above description is merely a specific embodiment of the present disclosure, but does not limit the scope of protection of the present disclosure, and the scope of protection of the present disclosure should be in accordance with the claims described above.

Claims

1. A display board, The system includes a base substrate and subpixels on the base substrate, and each subpixel includes a pixel circuit comprising a data writing subcircuit, a recording subcircuit, and a driving subcircuit. The data writing subcircuit is electrically connected to the first terminal of the recording subcircuit and is configured to transmit a data signal to the first terminal of the recording subcircuit in response to a control signal. The drive subcircuit includes a control electrode, a first electrode, and a second electrode, the control electrode of the drive subcircuit is electrically connected to the first terminal of the recording subcircuit, the first electrode of the drive subcircuit is configured to receive a power supply voltage, and the drive subcircuit is configured to control a drive current that flows from the first electrode to the second electrode and drives the light emission of the light-emitting element in response to the voltage at the first terminal of the recording subcircuit. The base substrate is provided with a contact hole region that provides a power supply voltage to the pixel circuit, and the display substrate further includes a power line connection electrode electrically connected to the contact hole region, the power line connection electrode includes a main body portion and a first extension portion and a second extension portion extending from the main body portion, Both the first extension portion and the second extension portion extend along the first direction, and the main body portion extends along the second direction, and the first direction and the second direction intersect. The subpixel has a size in the second direction that is larger than the size in the first direction, and the length of the main body is greater than the length of the first extension and greater than the length of the second extension. The power line connection electrode is located between two adjacent subpixels in the first direction and is shared by the two adjacent subpixels. The aforementioned power line connection electrodes are island-shaped electrodes on the display board.

2. The display substrate according to claim 1, wherein the first extended portion and the second extended portion each extend in opposite directions along the first direction from both ends of the main body portion.

3. The display substrate according to claim 1, wherein the pattern of the power line connection electrodes is an axially symmetric pattern, and the axis of symmetry is parallel to the second direction.

4. The display substrate according to claim 1, wherein the contact hole region is located between two adjacent subpixels in the first direction and is shared by the two adjacent subpixels.

5. The display substrate according to claim 1, wherein the first extended portion and the second extended portion each extend toward the two adjacent subpixels and each overlap the corresponding subpixels.

6. The material further includes an insulating layer located between the base substrate and the power line connection electrode, The display substrate according to claim 1, wherein the power line connection electrode is electrically connected to the contact hole region via a via in the insulating layer.

7. Further including a first power line extending along the first direction, The display board according to claim 1, wherein the first power line is located on the side of the power line connection electrode away from the base substrate and is electrically connected to the power line connection electrode.

8. Further including a second power line extending along the second direction, The display board according to claim 7, wherein the second power line is located on the side of the first power line away from the base board and is electrically connected to the first power line.

9. Further including a third power line extending along the second direction, The display board according to claim 8, wherein the third power line and the second power line overlap and are electrically connected in a direction perpendicular to the base board.

10. The recording subcircuit includes a storage capacitor, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, and the first capacitor electrode and the second capacitor electrode are the first terminal and the second terminal of the recording subcircuit, respectively. The display board according to claim 1, wherein the contact hole region is used to be electrically connected to the second capacitor electrode of the storage capacitor.

11. The display substrate according to claim 10, wherein the second capacitor electrode is a first region in the base substrate.

12. The power line connection electrode further includes a polycrystalline silicon layer located on the side closer to the base substrate, The display substrate according to claim 10, wherein the first capacitor electrode is located in the polycrystalline silicon layer and at least a portion of it overlaps with the second capacitor electrode in a direction perpendicular to the base substrate.

13. The display substrate according to claim 12, wherein the contact hole region is located outside the orthographic projection of the first capacitor electrode on the base substrate.

14. The display substrate according to claim 1, wherein the base substrate is a silicon substrate, and the contact hole region is a high-concentration doping region within the silicon substrate.

15. A display device, A display device comprising a display substrate according to any one of claims 1 to 14 and the light-emitting element, wherein the light-emitting element is configured to be connected to the second electrode of the drive subcircuit.

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