Signal transmission circuit and method for manufacturing a signal transmission circuit

Abstract

To provide a clock transfer circuit capable of forming a clock tree traversing a plurality of circuit regions having the identical circuit pattern.SOLUTION: A clock transfer circuit 80 includes a plurality of circuit regions 81 having a mutually common circuit pattern, arranged along a direction D1. The circuit pattern of each of the plurality of circuit regions 81 has: circuit elements E0 to E6 capable of switching between a high-impedance state and a passage state; and wiring connected to a circuit pattern of an adjacent circuit region 81. A clock tree traversing the plurality of circuit regions 81 is configured by controlling a state of the circuit elements E0 to E6 of the plurality of circuit regions 81 to a predetermined state defined for each circuit region 81.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a clock transmission circuit, an image sensor, and a method for manufacturing a clock transmission circuit. [Background technology]

[0002] Patent Document 1 discloses a buffering technique using structured delay skew. This Patent Document 1 describes a tree structure routing method. Patent Document 2 discloses a technique for an exposure apparatus that forms a desired pattern on a substrate by overlapping and splicing exposure of a portion of the projected image of a pattern formed on a reticle. Patent Document 3 describes splicing exposure when manufacturing display devices for large display devices. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2007-060036 [Patent Document 2] Japanese Patent Publication No. 2001-110708 [Patent Document 3] Japanese Patent Publication No. 2001-154371 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] When a clock signal propagates within a semiconductor device, a delay occurs in the clock signal depending on the length of the clock wiring and the load. Therefore, when it is necessary to input a clock signal to multiple circuits at the same timing, a clock tree is used. In a clock tree, it is desirable to repeatedly branch the clock signal symmetrically with respect to the center position of the group of circuits to which the clock is supplied.

[0005] On the other hand, in the photography process for manufacturing large-area semiconductor devices, multiple shots with a common exposure pattern are sometimes joined together to form a single device. This technique is called sequential exposure. When manufacturing semiconductor devices by sequential exposure, multiple circuit regions with the same circuit pattern are arranged side by side, making it easy to form a clock tree within each circuit region, but difficult to form a clock tree that spans multiple circuit regions. Therefore, there is a problem in that a delay occurs in the clock signal between multiple circuit regions.

[0006] This disclosure aims to provide a clock transmission circuit that enables the formation of a clock tree traversing multiple circuit regions having the same circuit pattern, and a method for manufacturing the clock transmission circuit. Furthermore, this disclosure aims to provide an image sensor with low clock signal delay. [Means for solving the problem]

[0007] The clock transmission circuit according to this disclosure is a clock transmission circuit including a clock tree provided on a single substrate. This clock transmission circuit comprises a plurality of circuit regions having a common circuit pattern and arranged in one direction. Each of the plurality of circuit regions has a circuit pattern having at least two circuit elements that can switch between a high impedance state and a pass-through state, and wiring that connects to the circuit pattern of an adjacent circuit region. By controlling the state of the at least two circuit elements in the plurality of circuit regions to a predetermined state determined for each circuit region, at least a portion of the clock tree traversing the plurality of circuit regions is formed.

[0008] The present disclosure provides a method for manufacturing a clock transmission circuit, which includes a clock tree provided on a single substrate. This manufacturing method includes the step of forming a plurality of circuit regions having common circuit patterns and aligned in one direction by performing sequential exposure using a common exposure pattern. Each of the plurality of circuit regions has at least two circuit elements that can switch between a high impedance state and a pass-through state, and wiring connected to the circuit patterns of adjacent circuit regions. By controlling the state of the at least two circuit elements in the plurality of circuit regions to a predetermined state determined for each circuit region, at least a portion of a clock tree traversing the plurality of circuit regions is formed.

[0009] These clock transmission circuits and methods for manufacturing them allow for the formation of a clock tree that traverses multiple circuit regions having the same circuit pattern. Therefore, the delay of the clock signal between multiple circuit regions can be reduced.

[0010] In the clock transmission circuit described above, the circuit pattern may include multiple stages of circuit configuration, each configured to handle multiple stages of branching in the clock tree. In this case, each stage of circuit configuration can suitably realize each stage of branching in the clock tree.

[0011] In the above clock transmission circuit, one of the multiple circuit stages may include first and second circuit elements, which are included in at least two of the above circuit elements and have their output terminals connected to each other. The wiring may include a first wiring portion for connecting the input terminal of the first circuit element to the input terminal of the second circuit element in an adjacent circuit region on one side, and a second wiring portion for connecting the input terminal of the second circuit element to the input terminal of the first circuit element in an adjacent circuit region on the other side. When a clock signal propagates through the circuit, the circuit can receive the clock signal from the first wiring portion or the second wiring portion and output the clock signal from a first node between the output terminal of the first circuit element and the output terminal of the second circuit element. Thus, the circuit can be easily implemented.

[0012] In the above clock transmission circuit, at least one of the multiple circuit stages may include third, fourth, and fifth circuit elements included in the at least two circuit elements described above. The output terminal of the third circuit element, the input terminal of the fourth circuit element, and the input terminal of the fifth circuit element may be connected to the second node, and the input terminal of the third circuit element and the output terminal of the fourth circuit element may be connected to the third node. The wiring may include a third wiring portion for connecting the second node to the third node in an adjacent circuit region on one side, and a fourth wiring portion for connecting the third node to the second node in an adjacent circuit region on the other side. When a clock signal propagates through the circuit, the circuit receives the clock signal at the third node and can output the clock signal from the output terminal of the fifth circuit element as needed. Furthermore, the propagation direction of the clock signal can be controlled by controlling the state of the third and fourth circuit elements. Thus, the first or middle stage circuit can be easily implemented.

[0013] In the clock transmission circuit described above, at least two of the circuit elements may be of the tristate (registered trademark) type. In this case, each of the at least two circuit elements can be simply configured with a single functional part. Furthermore, since the output resistance value when the circuit element is in transit can be kept low, the delay of the clock signal caused by the resistance value of the circuit element can be reduced.

[0014] In the above clock transmission circuit, at least one of the two circuit elements, at least one of which constitutes the final stage, may be of the tristate type, and the output terminal of this circuit element may be connected to a pull-up resistor or a pull-down resistor. Alternatively, in the above clock transmission circuit, at least one of the two circuit elements, at least one of which constitutes the final stage, may include a logic circuit. Either of these configurations can suppress the signal level to the clock supply destination from becoming undefined, thereby preventing malfunction of the clock supply destination.

[0015] The image sensor according to the present disclosure includes a pixel array including a plurality of pixels arranged in one dimension or two dimensions, an analog / digital converter array including a plurality of analog / digital converters that convert each of a plurality of analog signals output from each of the plurality of pixels into a digital signal, a memory array having a plurality of storage areas that store each of the plurality of digital signals output from the analog / digital converter array, and a horizontal scanning circuit that sequentially outputs the plurality of digital signals stored in the memory array as a serial signal. At least one of the analog / digital converter array and the horizontal scanning circuit receives the supply of a clock signal via any one of the clock transmission circuits. According to this image sensor, the delay of the clock signal among the plurality of digital signals can be reduced. Therefore, the frequency of errors when reading out the serial signal can be reduced.

Effects of the Invention

[0016] According to the present disclosure, it is possible to provide a clock transmission circuit and a method for manufacturing the clock transmission circuit that enable the formation of a clock tree that crosses a plurality of circuit regions having the same circuit pattern. Further, according to the present disclosure, it is possible to provide an image sensor with less delay of a clock signal.

Brief Description of the Drawings

[0017] [Figure 1] It is a side view schematically showing the configuration of an exposure apparatus used for manufacturing an image sensor according to one embodiment. [Figure 2] It is a plan view schematically showing the reticle pattern of a photomask. [Figure 3] (a) It is a plan view showing the circuit formation surface of a wafer after exposure and development. (b) It is a view showing an enlargement of a part of (a). (c) It is a view showing a cross section along line IIIc-IIIc of (b). [Figure 4] [[ID=?]] [Figure 5] It is a view schematically showing the configuration of a clock tree. [Figure 6] It is a circuit diagram showing the configuration of a clock transmission circuit. [Figure 7] It is a circuit diagram showing the circuit patterns of each circuit region. [Figure 8] It is a circuit diagram showing another example of the circuit patterns of each circuit region. [Figure 9] It is a circuit diagram showing an example of a circuit for controlling circuit elements in each circuit region. [Figure 10] It is a diagram showing another control example of the clock transmission circuit. [Figure 11] It is a flowchart showing a manufacturing method of a clock transmission circuit according to an embodiment. [Figure 12] It is a diagram schematically showing a clock transmission circuit as a reference example. [Figure 13] It is a diagram for explaining the influence of the delay of a clock signal. (a) shows a clock signal input to one end of a series circuit. (b) shows an example of a serial signal output from a circuit driven by a clock signal output from a circuit region close to one end of the series circuit. (c) shows an example of a serial signal output from a circuit driven by a clock signal output from a circuit region far from one end of the series circuit. [Figure 14] (a) to (c) are circuit diagrams showing configuration examples of circuit elements.

Embodiments for Carrying Out the Invention

[0018] Hereinafter, embodiments of a clock transmission circuit, an imaging device, and a manufacturing method of a clock transmission circuit according to the present disclosure will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and redundant descriptions are omitted.

[0019] Figure 1 is a schematic side view showing the configuration of an exposure apparatus 1 used for manufacturing an image sensor according to one embodiment of the present disclosure. As shown in Figure 1, the exposure apparatus 1 is an apparatus for exposing a resist R coated on a wafer W, and comprises a light source 10, a photomask 20, and a lens 30. The light source 10 outputs light L of a wavelength to which the resist R is sensitive. The photomask 20 has a reticle pattern (exposure pattern) for forming an image sensor 40 (see Figure 3), which will be described later. The photomask 20 is positioned opposite the light source 10. The lens 30 is positioned between the photomask 20 and the wafer W. The light L output from the light source 10 passes through the photomask 20 and is then focused by the lens 30 to reach the resist R on the wafer W. The resist R may be either positive or negative type.

[0020] Figure 2 is a schematic plan view showing the reticle pattern 21 of the photomask 20. The reticle pattern 21 includes at least a first portion 211, a second portion 212, and a third portion 213. The first portion 211 is a portion for forming the light-receiving portion of the image sensor 40 and includes an exposure pattern corresponding to a circuit pattern common to each of the multiple circuit regions when the light-receiving portion of the image sensor 40 is divided into multiple circuit regions. The second portion 212 is a portion for forming a circuit region 42 (see Figure 3) that is aligned on one side of the light-receiving portion of the image sensor 40. The third portion 213 is a portion for forming a circuit region 43 (see Figure 3) that is aligned on the other side of the light-receiving portion of the image sensor 40. The second portion 212 and the third portion 213 include an exposure pattern corresponding to a circuit for supplying a bias power supply to the light-receiving portion, etc.

[0021] Figure 3(a) is a plan view showing the circuit formation surface of the wafer W after exposure and development. Figure 3(b) is an enlarged view of a part of Figure 3(a). As shown in Figure 3(a), multiple image sensors 40 are formed on the wafer W by exposure by the exposure apparatus 1 and subsequent development. The multiple image sensors 40 are arranged along a direction D2 that intersects direction D1, with direction D1 being the longitudinal direction. As shown in Figure 3(b), each of the multiple image sensors 40 has a circuit region group 44 consisting of multiple circuit regions 41 arranged along direction D1, a circuit region 42 located on one end of the circuit region group 44 in direction D1, and a circuit region 43 located on the other end of the circuit region group 44 in direction D1. The circuit region group 44 includes a light-receiving portion.

[0022] Each of the multiple circuit regions 41 is a region formed by successive exposure using the first portion 211 shown in Figure 2. That is, the multiple circuit regions 41 are regions formed by exposing the resist R while moving the first portion 211 along direction D1. At this time, adjacent regions exposed by the first portion 211 may overlap each other in some parts. The multiple circuit regions 41 have the same circuit pattern. Circuit region 42 is a region formed by exposure using the second portion 212 shown in Figure 2. Circuit region 43 is a region formed by exposure using the third portion 213 shown in Figure 2. Circuit region 42 has a different circuit pattern from circuit region 41. Circuit region 43 has a different circuit pattern from circuit regions 41 and 42.

[0023] Figure 3(c) is a cross-section along the line IIIc-IIIc in Figure 3(b). As shown in Figure 3(c), the circuit region group 44, circuit region 42, and circuit region 43 are provided on a single substrate 62 cut from the wafer W. The length of the substrate 62 in direction D1 is, for example, 20 mm to 300 mm.

[0024] Figure 4 is a diagram showing specific configuration examples for each of the multiple image sensors 40. As shown in Figure 4, the circuit region group 44 includes a pixel array 45, an amplifier array 46, an analog-to-digital (A / D) converter array 47, a memory array 48, a horizontal scanning circuit group 49, an output circuit group 50, a clock transmission circuit 80A for the A / D converter, and a clock transmission circuit 80B for the horizontal scanning circuit and the output circuit. The pixel array 45 is made up of multiple regions 451, each contained within multiple circuit regions 41, arranged in a line along direction D1. The amplifier array 46 is made up of multiple regions 461, each contained within multiple circuit regions 41, arranged in a line along direction D1. The A / D converter array 47 is made up of multiple regions 471, each contained within multiple circuit regions 41, arranged in a line along direction D1. The memory array 48 is made up of multiple regions 481, each contained within multiple circuit regions 41, arranged in a line along direction D1. The horizontal scanning circuit group 49 consists of multiple regions 491, each contained within a plurality of circuit regions 41, arranged in a line along direction D1. The output circuit group 50 consists of multiple regions 501, each contained within a plurality of circuit regions 41, arranged in a line along direction D1. In Figure 4, only some of the circuit regions 41 located near both ends of the circuit region group 44 in direction D1 are shown, and the other circuit regions 41 are omitted from the illustration.

[0025] The pixel array 45 includes a plurality of pixels arranged in one or two dimensions. The plurality of pixels are aligned along at least one direction D1. Each of the plurality of regions 451 contains two or more pixels. Therefore, for example, if each of P regions 451 contains Q pixels, the total number of pixels in the pixel array 45 is (P × Q) (P and Q are integers greater than or equal to 2). The Q pixels are arranged in an n column × m row configuration (n × m = Q, where n and m are natural numbers). Each pixel generates an amount of charge corresponding to the intensity of light incident on it. Each pixel includes an in-pixel amplifier and may perform current-voltage conversion within the pixel. Each pixel can be formed, for example, by ion implantation onto the surface of the wafer W. Wiring connected to each pixel can be formed, for example, by etching on the surface of the wafer W. The plurality of regions 451 have the same circuit pattern as each other, and the exposure patterns during ion implantation and etching are common to the plurality of regions 451.

[0026] The amplifier array 46 may include multiple amplifiers that convert each of the multiple analog signals output from each of the multiple pixels of the pixel array 45 into a current-voltage, or, if current-voltage conversion is performed within each pixel, it may include multiple amplifiers that multiply each of the multiple analog signals. Each of the multiple amplifiers corresponds to each of the multiple pixel rows of the pixel array 45. Each of the multiple regions 461 includes two or more amplifiers. For example, if each of the P regions 451 includes n pixel rows, then each of the P regions 461 includes n amplifiers. Therefore, the total number of amplifiers in the amplifier array 46 is at least (P × n). Each of the multiple amplifiers may be composed of an amplification circuit including, for example, a transistor. The drain and source regions of the transistor may be formed, for example, by ion implantation onto the surface of the wafer W. The gate of the transistor, and the wiring connected to the drain and source regions, may be formed on the surface of the wafer W by, for example, a lift-off method. The multiple regions 461 have the same circuit pattern as each other, and the exposure patterns during ion implantation and lift-off are common to the multiple regions 461.

[0027] The A / D converter array 47 includes multiple A / D converters that convert each of the multiple analog signals output from each of the multiple pixels of the pixel array 45 into a digital signal. Each of the multiple A / D converters corresponds to each of the multiple amplifiers of the amplifier array 46. Each of the multiple regions 471 contains two or more A / D converters. For example, if each of the P regions 461 contains n amplifiers, then each of the P regions 471 contains n A / D converters. Therefore, the total number of A / D converters in the A / D converter array 47 is at least (P × n). The multiple regions 471 have the same circuit pattern as each other, and the exposure pattern used to form the A / D converters is common to all of the multiple regions 471.

[0028] The memory array 48 has multiple memory cells (storage areas) that store each of the multiple digital signals output from the A / D converter array 47. Each of the multiple memory cells corresponds to each of the multiple A / D converters. Each of the multiple areas 481 contains two or more memory cells. For example, if each of the P areas 471 contains n A / D converters, then each of the P areas 481 contains n memory cells. Therefore, the total number of memory cells in the memory array 48 is (P × n). The multiple areas 481 have the same circuit pattern as each other, and the exposure pattern used to form the memory cells is common to all of the multiple areas 481.

[0029] The horizontal scanning circuit group 49 sequentially outputs multiple digital signals stored in the memory array 48 as serial signals. The horizontal scanning circuit group 49 has multiple regions 491. Each of the multiple regions 491 contains two or more horizontal scanning circuits. In one example, each of the multiple regions 491 contains 2 horizontal scanning circuits. In that case, if, for example, each of the P regions 481 contains n memory cells, then (n / 2) memory cells correspond to one horizontal scanning circuit. Each horizontal scanning circuit sequentially outputs the digital signals from these (n / 2) memory cells as serial signals to the corresponding region 501 of the output circuit group 50. The multiple regions 491 have the same circuit pattern as each other, and the exposure pattern when forming the horizontal scanning circuits is common to all of the multiple regions 491.

[0030] The output circuit group 50 has multiple regions 501. Each of the multiple regions 501 is connected to each of the multiple regions 491 of the horizontal scanning circuit group 49. Each region 501 includes an output circuit corresponding to a horizontal scanning circuit included in each region 491 of the horizontal scanning circuit group 49, and each output circuit receives digital signals sequentially output as serial signals from the corresponding horizontal scanning circuit. The output circuit of each region 501 generates output data Dout from these digital signals and outputs the output data Dout to the outside of the image sensor 40.

[0031] Circuit region 42 includes, for example, a timing control circuit 421. The timing control circuit 421 transmits a common clock signal to the pixel array 45, the amplifier array 46, the clock transmission circuit 80A for the A / D converter, and the clock transmission circuit 80B for the horizontal scanning circuit.

[0032] The circuit region 43 includes, for example, a bias voltage generation circuit 431. The bias voltage generation circuit 431 is connected via wiring (not shown) to each of the multiple pixels of the pixel array 45, each of the multiple amplifiers of the amplifier array 46, and each of the multiple A / D converters of the A / D converter array 47, and supplies a bias voltage to the multiple pixels of the pixel array 45, the multiple amplifiers of the amplifier array 46, and the multiple A / D converters of the A / D converter array 47.

[0033] Next, the configurations of the clock transmission circuits 80A and 80B will be described in detail. The clock transmission circuits 80A and 80B include a clock tree provided on a single circuit board 62 (see Figure 3(c)). Figure 5 is a schematic diagram showing the configuration of a clock tree 70 as an example. The clock tree 70 has multiple stages of branching between the wiring 76 that receives the clock signal and the circuit 77 that uses the clock signal. Each branch splits one clock wiring into at least two. Figure 5 shows, as an example, a total of three stages of branching: the first stage C1, the second stage C2, and the third stage (final stage) C3. Repeater buffers 78 are provided in the wiring between the first stage C1 and the second stage C2, between the second stage C2 and the third stage C3, and between the third stage C3 and the circuit 77.

[0034] Figure 6 is a circuit diagram showing the configuration of the clock transmission circuit 80. The clock transmission circuits 80A and 80B shown in Figure 4 have the same configuration as this clock transmission circuit 80. The circuit 77 in Figure 6 includes all A / D converters in the multiple regions 471 in the A / D converter array 47, all horizontal scanning circuits in the multiple regions 491 in the horizontal scanning circuit group 49, and all output circuits in the multiple regions 501 in the output circuit group 50.

[0035] The clock transmission circuit 80 comprises multiple circuit regions 81. Each of the multiple circuit regions 81 is contained within each of the multiple circuit regions 41 (see Figures 3 and 4). The multiple circuit regions 81 share a common circuit pattern and are aligned along direction D1. Each circuit region 81 is adjacent to and continuous with the adjacent circuit region 81.

[0036] Figure 7 is a circuit diagram showing the circuit patterns of each circuit region 81. As shown in Figure 7, the circuit pattern of each circuit region 81 has at least two (nine in this embodiment) circuit elements E0 to E8 and wiring W1 to W6. At least the circuit elements E0 to E6 (circuit elements E0 to E8 in this embodiment) are circuit elements that can switch between a high impedance state and a pass-through state, and are, for example, tri-state (registered trademark) type circuit elements. A tri-state type is also called a three-state type. A high impedance state refers to a state in which the circuit is in an isolated state or has a resistance value close to that of an isolated state. A pass-through state refers to a state in which the circuit outputs a signal that follows the logic of the input signal. In one example, the circuit elements E0 to E8 are a tri-state buffer or a tri-state inverter. The circuit elements E0 to E8 function as repeater buffers in a clock tree. Wiring W1 to W6 is wiring that connects to the circuit patterns of adjacent circuit regions 81. The circuit pattern of each circuit region 81 includes a clock supply section 82, a first stage circuit section 83, a second stage circuit section 84, and a third stage circuit section 85.

[0037] The clock supply section 82 is the part that supplies the clock signal input from outside the clock transmission circuit 80 to the clock tree. The clock supply section 82 includes circuit elements E0 and E1 and wirings W5 and W6. One end of wiring W5 is connected to wiring W6 of the adjacent circuit region 81 on one side (left side in the figure). The other end of wiring W5 is connected to the input terminal of circuit element E0. Circuit element E0 receives the clock signal input from outside the clock transmission circuit 80 via the adjacent circuit region 81 at its input terminal. One end of wiring W6 is connected to the output terminal of circuit element E0. The other end of wiring W6 is connected to wiring W5 of the adjacent circuit region 81 on the other side (right side in the figure). Also, the input terminal of circuit element E1 is connected to wiring W6.

[0038] If circuit element E0 is in a pass-through state, the clock signal propagates from wiring W5 to wiring W6. If circuit element E0 is in a high-impedance state, the clock signal does not propagate from wiring W5 to wiring W6. If both circuit elements E0 and E1 are in a pass-through state, the clock signal propagates from wiring W5 to the first stage circuit section 83. If circuit element E0 is in a pass-through state and circuit element E1 is in a high-impedance state, the clock signal propagates through wirings W5 and W6 but does not propagate to the first stage circuit section 83.

[0039] The first stage circuit section 83 is the section for branching the clock signal supplied from the clock supply section 82. Circuit section 83 includes circuit element E2 (third circuit element), circuit element E3 (fourth circuit element), and circuit element E4 (fifth circuit element). In addition, circuit section 83 includes wiring W3 (third wiring section) and wiring W4 (fourth wiring section).

[0040] The output terminal of circuit element E2, the input terminal of circuit element E3, and the input terminal of circuit element E4 are connected to node N2 (the second node). The input terminal of circuit element E2 and the output terminal of circuit element E3 are connected to node N3 (the third node). In other words, circuit elements E2 and E3 are connected in parallel to each other between nodes N2 and N3, but in opposite directions. The input terminal of circuit element E4 is connected to one end of this parallel circuit. Wiring W3 is the wiring portion for connecting node N2 to node N3 in the adjacent circuit region 81 on one side (the left side of the figure). Wiring W4 is the wiring portion for connecting node N3 to node N2 in the adjacent circuit region 81 on the other side (the right side of the figure). Node N3 is connected to the clock supply wiring from outside the clock transmission circuit 80, i.e., the output terminal of circuit element E1 of the clock supply portion 82.

[0041] If circuit element E2 is in a pass-through state and circuit element E3 is in a high-impedance state, the clock signal propagates from node N3 to node N2. Conversely, if circuit element E2 is in a high-impedance state and circuit element E3 is in a pass-through state, the clock signal propagates from node N2 to node N3. Circuit elements E2 and E3 cannot be in a pass-through state simultaneously. If both circuit elements E2 and E3 are in a high-impedance state, the clock signal does not propagate between node N2 and node N3. If circuit element E4 is in a pass-through state, the clock signal propagates from node N2 to the second stage circuit section 84. If circuit element E4 is in a high-impedance state, the clock signal does not propagate from node N2 to the second stage circuit section 84.

[0042] When a clock signal propagates through circuit section 83, circuit section 83 receives the clock signal at node N3 and can output the clock signal from the output terminal of circuit element E4 as needed. Furthermore, the direction of clock signal propagation can be controlled by controlling the state of circuit elements E2 and E3. Note that the clock tree has branches that span multiple circuit regions 81 and branches that occur within each circuit region 81, and this circuit section 83 is responsible for the first and middle stages of the branches that span multiple circuit regions 81.

[0043] The second stage circuit section 84 is for further branching the clock signal supplied from the first stage circuit section 83. Circuit section 84 includes circuit element E5 (first circuit element) and circuit element E6 (second circuit element). In addition, circuit section 84 includes wiring W1 (first wiring section) and wiring W2 (second wiring section).

[0044] The output terminals of circuit elements E5 and E6 are connected to each other. In other words, the output terminals of circuit elements E5 and E6 are connected to node N1. Wiring W1 is the portion of the wiring that connects the input terminal of circuit element E5 to the input terminal of circuit element E6 in the adjacent circuit region 81 on one side (left side of the diagram). Wiring W1 is connected to wiring W2 in the adjacent circuit region 81 on one side. Furthermore, wiring W1 is connected to the output terminal of circuit element E4. Wiring W2 is the portion of the wiring that connects the input terminal of circuit element E6 to the input terminal of circuit element E5 in the adjacent circuit region 81 on the other side (right side of the diagram). Wiring W2 is connected to wiring W1 in the adjacent circuit region 81 on the other side.

[0045] If circuit element E5 is in a pass-through state and circuit element E6 is in a high-impedance state, the clock signal propagates from wiring W1 to node N1. If circuit element E5 is in a high-impedance state and circuit element E6 is in a pass-through state, the clock signal propagates from wiring W2 to node N1. Circuit elements E5 and E6 cannot be in a pass-through state simultaneously. If both circuit elements E5 and E6 are in a high-impedance state, the clock signal does not propagate to node N1.

[0046] When the clock signal propagates through circuit section 84, circuit section 84 receives the clock signal at wiring W1 or wiring W2 and can output the clock signal from node N1. As mentioned above, the clock tree has branches that span multiple circuit regions 81 and branches that occur within each circuit region 81, and this circuit section 84 is responsible for the final branch among the branches that span multiple circuit regions 81.

[0047] The third stage circuit section 85 is responsible for branching within each circuit region 81. Circuit section 85 includes circuit elements E7 and E8. The input terminals of circuit elements E7 and E8 are connected to node N1 and are also connected to each other. The output terminals of circuit elements E7 and E8 are branched into multiple wires 87, as shown in Figure 6, and then connected to each of the multiple clock supply targets included in the clock-using circuit 77 (for example, multiple A / D converters in the A / D converter array 47, multiple horizontal scanning circuits in the horizontal scanning circuit group 49, or multiple output circuits in the output circuit group 50). Alternatively, the output terminals of circuit elements E7 and E8 may be connected to a common wire provided across multiple circuit regions 81, and connected to the multiple clock supply targets of circuit 77 via this wire.

[0048] To rephrase the above configuration, in the clock supply section 82, as shown in Figure 6, the circuit elements E0 of multiple circuit regions 81 are connected in series with their orientations aligned. The input terminal of the circuit element E1 of each circuit region 81 is connected to the node between adjacent circuit elements E0. In the first stage circuit section 83, the circuit elements E2 of multiple circuit regions 81 are connected in series with their orientations aligned, and the circuit elements E3 of multiple circuit regions 81 are connected in series with their orientations aligned, but in the opposite direction to the circuit elements E2. The nodes between adjacent circuit elements E2 are common to the nodes between adjacent circuit elements E3. The nodes between circuit elements E2 are alternately connected to the output terminal of circuit element E1 and the input terminal of circuit element E4. In the second stage circuit section 84, the circuit elements E5 and E6 are alternately connected in series, with circuit element E6 facing the opposite direction to circuit element E5. The output terminal of circuit element E4 is connected to the node between the input terminal of circuit element E5 and the input terminal of circuit element E6.

[0049] The clock propagation path F1 shown in Figure 6 represents an example of a clock tree that can be realized by multiple circuit regions 81 having the above configuration. Circuit elements located along the clock propagation path F1 are in a pass-through state (shown in white in the figure), and circuit elements located outside the clock propagation path F1 are in a high-impedance state (shown in halftone in the figure). A detailed explanation follows below.

[0050] First, in the clock supply section 82, the circuit elements E0 of two circuit regions 81A and 81B on one side of the four circuit regions 81 shown in Figure 6 are set to a pass-through state, while the circuit elements E0 of the two circuit regions 81C and 81D on the opposite side are set to a high-impedance state. In addition, the circuit element E1 of circuit region 81B is set to a pass-through state, while the circuit elements E1 of the other circuit regions 81A, 81C, and 81D are set to a high-impedance state. As a result, the clock signal supplied from outside the clock transmission circuit 80 passes through the circuit elements E0 of circuit regions 81A and 81B and the circuit element E1 of circuit region 81B to reach the top of the clock tree (clock input terminal) located in circuit region 81B.

[0051] Next, in the first stage circuit section 83, circuit element E2 in circuit region 81B is set to pass-through state, while circuit element E2 in the other circuit regions 81A, 81C, and 81D is set to high impedance state. Circuit element E3 in circuit region 81C is set to pass-through state, while circuit element E3 in the other circuit regions 81A, 81B, and 81D is set to high impedance state. Furthermore, circuit element E4 in circuit regions 81B and 81D is set to pass-through state, while circuit element E4 in the other circuit regions 81A and 81C is set to high impedance state. As a result, the clock signal is split into a clock signal that passes through circuit elements E2 and E4 in circuit region 81B, and a clock signal that passes through circuit element E3 in circuit region 81C and circuit element E4 in circuit region 81D.

[0052] Next, in the second stage circuit section 84, the circuit elements E5 in circuit regions 81B and 81D are set to a pass-through state, while the circuit elements E5 in the other circuit regions 81A and 81C are set to a high-impedance state. Also, the circuit elements E6 in circuit regions 81A and 81C are set to a conduction state, while the circuit elements E6 in the other circuit regions 81B and 81D are set to a high-impedance state. The clock signal that has passed through the circuit element E4 in circuit region 81B is thus split into a clock signal that passes through the circuit element E6 in circuit region 81A and a clock signal that passes through the circuit element E5 in circuit region 81B. The clock signal that has passed through the circuit element E4 in circuit region 81D is thus split into a clock signal that passes through the circuit element E6 in circuit region 81C and a clock signal that passes through the circuit element E5 in circuit region 81D.

[0053] Next, in the third stage circuit section 85 of each circuit region 81A to 81D, the clock signal that has passed through circuit element E5 or E6 is split into a clock signal that passes through circuit element E7 and a clock signal that passes through circuit element E8. The eight clock signals thus split are supplied to the circuits 77 that use the clock via branch wiring 87.

[0054] In this embodiment, the case where there is only one stage of circuit section 83 is described, but as shown in Figure 8, the circuit section 83 may be provided in multiple stages. In that case, the node N3 of the circuit section 83 provided in the later stage of circuit section 83 is connected to the output terminal of the circuit element E4 of the preceding circuit section 83. This makes it possible to increase the number of intermediate branches among the branches that span multiple circuit regions 81 of the clock tree to any number.

[0055] Furthermore, in the above example, the A / D converter array 47, the horizontal scanning circuit group 49, and the output circuit group 50 all receive a clock signal via the clock transmission circuit 80. However, only one or two of the A / D converter array 47, the horizontal scanning circuit group 49, and the output circuit group 50 may receive a clock signal via the clock transmission circuit 80.

[0056] Here, we will describe the circuits that control the circuit elements E0 to E8 in each circuit region 81. Figure 9 is a circuit diagram showing an example of a circuit that controls the circuit elements E0 and E1 in each circuit region 81. Note that the control circuits for the other circuit elements E2 to E8 have a similar configuration, so they are not shown.

[0057] Each circuit region 81 further contains multiple flip-flops 88, each corresponding to a circuit element E0 to E8. The flip-flops 88 corresponding to circuit element E0 are cascaded across multiple circuit regions 81. The flip-flops 88 corresponding to circuit element E1 are also cascaded across multiple circuit regions 81. Similarly, the flip-flops 88 corresponding to circuit elements E2 to E8 are cascaded across multiple circuit regions 81.

[0058] One end of the above cascade circuit corresponding to circuit element E0 receives a binary signal S. E0 The following is input: Binary signal S E0 This is a signal that takes on / off values ​​in synchronization with the clock CLK supplied to the cascaded circuit. In the example shown in the figure, four periods of clock CLK are shown. The binary signal S in the first period E0 According to the value of , the output value of the flip-flop 88 in circuit region 81D, located at the innermost part of the cascaded circuit, is controlled, and the circuit element E0 in circuit region 81D is controlled. The binary signal S in the second period E0 According to the value of , the output value of the flip-flop 88 in circuit region 81C is controlled, and the circuit element E0 in circuit region 81C is controlled. The binary signal S in the third period E0 According to the value of , the output value of the flip-flop 88 in circuit region 81B is controlled, and the circuit element E0 in circuit region 81B is controlled. Then, the binary signal S in the fourth period E0 According to the value of , the output value of the flip-flop 88 in circuit region 81A is controlled, and the circuit element E0 in circuit region 81A is controlled. In this way, the binary signal S E0By setting the value of to an arbitrary value for each period of the clock CLK, the circuit elements E0 of multiple circuit regions 81 can be controlled individually. The circuit elements E1 of the multiple circuit regions 81 also control the binary signal S E1 The value can be individually controlled by setting it to an arbitrary value for each period of the clock CLK. The same applies to the other circuit elements E2 to E8.

[0059] Figure 10 shows another control example of the clock transmission circuit 80. In this example, the control state of circuit elements E0 and E1 of the clock supply section 82 (see Figure 7) is the same as in the example shown in Figure 6, but in circuit regions 81A, 81C, and 81D, all circuit elements E2 to E8 included in the first stage circuit section 83, the second stage circuit section 84, and the third stage circuit section 85 are in a high impedance state. And only in circuit region 81B, circuit elements E2 to E8 are controlled in the same way as in the control state shown in Figure 6. In this way, a clock tree may be constructed using only some of the circuit regions 81 out of multiple circuit regions 81. If some of the multiple clock supply targets included in the circuit 77 that uses the clock are not used, power consumption can be reduced by constructing a clock tree limited to some of the circuit regions 81 in this way.

[0060] Figure 11 is a flowchart showing the method for manufacturing the clock transmission circuit 80 according to this embodiment. When manufacturing the clock transmission circuit 80, first, for example, a common exposure pattern for the circuit region 81 is formed on the first portion 211 of the reticle pattern 21 shown in Figure 2, and this exposure pattern is used to perform sequential exposure on the resist R (see Figure 1) (step S1). Next, the resist R is developed and cured to form a mask (step S2). Then, ion implantation, semiconductor etching, or metal lift-off is performed through the mask to produce the components of the circuit elements E0 to E8 or wiring W1 to W6 (step S3). Steps S1 to S3 are repeated the number of times required to manufacture the clock transmission circuit 80 (step S4). After that, the wafer is cut into individual pieces (step S5). Through the above steps, a clock transmission circuit 80 having a plurality of circuit regions 81 having a common circuit pattern and arranged along the direction D1 can be manufactured on a single substrate.

[0061] The effects obtained by the clock transmission circuit 80, image sensor 40, and manufacturing method of the clock transmission circuit 80 of this embodiment described above will now be explained. Figure 12 is a schematic diagram showing a clock transmission circuit 100 as a reference example. In this clock transmission circuit 100, each of the multiple circuit regions 110 arranged along direction D1 has repeater buffers 101 to 104. Repeater buffers 101 and 102 are alternately connected in series across the multiple circuit regions 110. The input terminals of repeater buffers 103 and 104 are connected to the node between repeater buffer 101 and repeater buffer 102. The clock signal is input from one end of the series circuit consisting of repeater buffers 101 and 102, propagates through this series circuit, and is branched to repeater buffers 103 and 104 in each circuit region 110.

[0062] In such a clock transmission circuit 100, the longer the distance the clock signal propagates in the series circuit consisting of repeater buffers 101 and 102, the greater the delay in the clock signal. Therefore, the clock signal is delayed further in the circuit region 110 that is farther from one end of the series circuit to which the clock signal is input. Figure 13 illustrates the effect of clock signal delay. Figure 13(a) shows a clock signal input to one end of the series circuit. Figure 13(b) shows an example of a serial signal output from a circuit driven by a clock signal output from a circuit region 110 that is close to one end of the series circuit. Figure 13(c) shows an example of a serial signal output from a circuit driven by a clock signal output from a circuit region 110 that is farther from one end of the series circuit. If a delay occurs in some of the circuit regions 110, a delay T occurs between the serial signals. Therefore, the signal recognition accuracy in the circuit that reads the serial signal may decrease.

[0063] Therefore, clock trees are used to input clock signals to multiple circuits at the same timing. However, when performing sequential exposure in the photography process for manufacturing large-area semiconductor devices, multiple circuit regions with the same circuit pattern are lined up. While it is easy to form a clock tree within each circuit region, it is difficult to form a clock tree that spans multiple circuit regions. It is possible to form a clock tree by using different circuit patterns for each circuit region, but in that case, it is necessary to prepare many different exposure patterns, which increases manufacturing costs and complicates the manufacturing process.

[0064] In this embodiment, each of the multiple circuit regions 81 has a circuit pattern comprising circuit elements E0 to E6 that can switch between a high-impedance state and a pass-through state, and wiring W1 to W6 connected to the circuit pattern of an adjacent circuit region 81. The state of the circuit elements E0 to E6 in the multiple circuit regions 81 is controlled to a predetermined state determined for each circuit region 81, for example, as shown in Figure 6, thereby forming a clock tree that traverses the multiple circuit regions 81. This makes it possible to form a clock tree that traverses multiple circuit regions 81 having the same circuit pattern. Therefore, the delay of the clock signal between the multiple circuit regions 81 can be reduced. Furthermore, since it is not necessary to have different circuit patterns for each circuit region, it is not necessary to prepare many different exposure patterns, which reduces manufacturing costs and simplifies the manufacturing process.

[0065] As in this embodiment, the circuit pattern of each circuit region 81 may include multiple stages of circuit parts 83, 84 configured to each be responsible for multiple stages of branching in the clock tree. In this case, each stage of circuit parts 83, 84 can suitably realize each stage of branching in the clock tree.

[0066] As in this embodiment, the circuit section 84 may include circuit elements E5 and E6 whose output terminals are connected to each other. The wirings W1 to W6 may include wiring W1 for connecting the input terminal of circuit element E5 to the input terminal of circuit element E6 in the adjacent circuit region 81 on one side, and wiring W2 for connecting the input terminal of circuit element E6 to the input terminal of circuit element E5 in the adjacent circuit region 81 on the other side. The circuit section 84 through which the clock signal propagates can receive the clock signal from wiring W1 (or wiring W2) and output the clock signal from node N1 between the output terminal of circuit element E5 and the output terminal of circuit element E6. Thus, a circuit section 84 responsible for a single branch can be easily realized.

[0067] As in this embodiment, the circuit section 83 may include circuit elements E2, E3, and E4. The output terminal of circuit element E2, the input terminal of circuit element E3, and the input terminal of circuit element E4 may be connected to node N2, and the input terminal of circuit element E2 and the output terminal of circuit element E3 may be connected to node N3. Wirings W1 to W6 may include wiring W3 for connecting node N2 to node N3 of the adjacent circuit area 81 on one side, and wiring W4 for connecting node N3 to node N2 of the adjacent circuit area 81 on the other side. The circuit section 83 through which the clock signal propagates receives the clock signal at node N3 and can output the clock signal from the output terminal of circuit element E4 as needed. Furthermore, the propagation direction of the clock signal can be controlled by controlling the state of circuit elements E2 and E3. Thus, a circuit section 83 responsible for the first or middle stage branching can be easily realized.

[0068] As in this embodiment, the circuit elements E0 to E6 may be of the tristate type. In this case, each of the circuit elements E0 to E6 can be simply configured with a single functional part. Furthermore, since the output resistance value in the pass-through state of the circuit elements E0 to E6 can be kept low, the clock signal delay caused by the resistance values ​​of the circuit elements E0 to E6 can be reduced.

[0069] In the image sensor 40 of this embodiment, at least one of the A / D converter array 47, the horizontal scanning circuit group 49, and the output circuit group 50 receives a clock signal via a clock transmission circuit having a configuration similar to that of the clock transmission circuit 80. This image sensor 40 reduces the delay of the clock signal between multiple digital signals. Therefore, the frequency of errors when reading serial signals can be reduced.

[0070] The clock transmission circuit, image sensor, and method for manufacturing the clock transmission circuit according to this disclosure are not limited to the embodiments described above, and various other modifications are possible. For example, in the above embodiments, an example was described in which each circuit region 81 has nine circuit elements E0 to E8, but a clock tree spanning two circuit regions 81 can be realized as long as each circuit region 81 has at least one circuit portion 84. In other words, each circuit region 81 only needs to have at least two circuit elements E5 and E6.

[0071] Furthermore, although the above embodiment illustrates the case where circuit elements E0 to E6 are of the tristate type, the circuit elements E0 to E6 are not limited to this, as long as they can switch between a high-impedance state and a pass-through state. For example, the circuit elements E0 to E6 may be configured to include a repeater buffer and a switch connected in series with each other. Even in that case, the high-impedance state and the pass-through state can be switched by controlling the switch.

[0072] Furthermore, it is desirable that the circuit elements E7 and E8 constituting the final stage circuit section 85 have a configuration that avoids the potential of the clock signal supplied to circuit 77 becoming undefined. Figures 14(a) to (c) are circuit diagrams showing examples of such circuit element configurations.

[0073] The circuit elements shown in Figures 14(a) and (b) are composed of logic circuits. Specifically, the circuit element shown in Figure 14(a) is composed of a logical AND (AND) element 91. In one example, the circuit element consists only of the AND element 91. One of the two input terminals of the AND element 91 receives the clock signal CLK from the preceding circuit section 84, and the other input terminal receives the control signal Scrl from the cascaded flip-flop 88 (see Figure 9). The AND element 91 outputs the logical AND of the clock signal Scrk and the control signal Scrl to the circuit 77. The circuit element shown in Figure 14(b) is composed of a logical OR (OR) element 92 and a logical NOT (NOT) element 93. In one example, the circuit element consists only of the OR element 92 and the NOT element 93. One of the two input terminals of the OR element 92 receives the clock signal Scrk from the preceding circuit section 84. The other input terminal of the OR element 92 is connected to the output terminal of the NOT element 93. The control signal Sctrl from the cascaded flip-flop 88 (see Figure 9) is input to this other input terminal via the NOT element 93. The OR element 92 outputs the logical OR of the clock signal Sclk and the inverted signal of the control signal Sctrl to circuit 77.

[0074] The circuit element shown in Figure 14(c) consists of a tri-state circuit element 94 and a pull-up resistor 95. In one example, the circuit element consists only of the tri-state circuit element 94 and the pull-up resistor 95. The pull-up resistor 95 is connected between the output terminal of the circuit element 94 and the power supply voltage Vdd. This circuit element may also have a pull-down resistor connected between the output terminal of the circuit element 94 and the reference potential (ground potential) instead of the pull-up resistor 95, or together with the pull-up resistor 95. Any of the configurations shown in Figures 14(a) to (c) can suppress the level of the clock signal to the circuit 77 from becoming undefined, thereby preventing malfunction of the circuit 77.

[0075] In addition, in the above-described embodiment, an example in which the clock transmission circuit 80 is applied to an imaging device has been shown. However, the clock transmission circuit 80 can be applied not only to an imaging device but also to various semiconductor devices.

[0076] In addition, in the above-described embodiment, the clock tree is completed by a plurality of circuit regions 81 having a common circuit pattern. However, the clock tree does not necessarily have to be completed only by the plurality of circuit regions 81 having a common circuit pattern. For example, another circuit region that is arranged alongside the plurality of circuit regions 81 and has a different circuit pattern from the plurality of circuit regions 81 may constitute a part of the clock tree.

Explanation of Reference Numerals

[0077] 1... Exposure apparatus, 10... Light source, 20... Photomask, 21... Reticle pattern, 30... Lens, 40... Imaging device, 41 - 43... Circuit regions, 44... Circuit region group, 45... Pixel array, 46... Amplifier array, 47... A / D converter array, 48... Memory array, 49... Horizontal scanning circuit group, 50... Output circuit group, 62... Substrate, 70... Clock tree, 76... Wiring, 77... Circuit using a clock signal, 78... Repeater buffer, 80, 80A, 80B... Clock transmission circuits, 81, 81A - 81D... Circuit regions, 82... Clock supply portion, 83 - 85... Circuit portions, 86... Wiring, 87... Branch wiring, 88... Flip-flop, 91... AND element, 92... OR element, 93... NOT element, 94... Circuit element, 95... Pull-up resistor, 100... Clock transmission circuit, 101 - 104... Repeater buffers, 110... Circuit region, 211... First portion, 212... Second portion, 213... Third portion, 421... Timing control circuit, 431... Bias voltage generation circuit, 451, 461, 471, 481, 491, 501... Regions, C1... First stage, C2... Second stage, C3... Third stage (final stage), CLK... Clock, D1, D2... Directions, Dout... Output data, E0 - E8... Circuit elements, F1... Clock propagation path, L... Light, N1 - N3... Nodes, R... Resist, S E0 ,S E1 … Binary signal, Sclk... Clock signal, Sctrl... Control signal, W... Wafer, W1 - W6... Wiring.

Claims

1. A signal transmission circuit provided on a single substrate, It comprises multiple circuit regions that share a common circuit pattern and are arranged in one direction, Each of the aforementioned circuit patterns in the plurality of circuit regions is A first circuit element, a second circuit element, and a third circuit element that can switch between a high impedance state and a pass-through state, A first wiring portion connects the output terminal of the first circuit element to the input terminal of the second circuit element and the input terminal of the third circuit element, A second wiring portion for connecting the input terminal of the first circuit element to the output terminal of the second circuit element and to the first wiring portion of the circuit region adjacent to one side, A signal transmission circuit, including a signal transmission circuit.

2. Each of the aforementioned circuit patterns in the plurality of circuit regions is A fourth and fifth circuit element capable of switching between a high-impedance state and a pass-through state, A third wiring portion connects the input terminal of the fourth circuit element to the output terminal of the third circuit element, A fourth wiring portion connects the output terminal of the fourth circuit element to the output terminal of the fifth circuit element, A fifth wiring portion for connecting the input terminal of the fifth circuit element to the third wiring portion of the circuit region adjacent to the one side, The signal transmission circuit according to claim 1, further comprising:

3. Each of the aforementioned circuit patterns in the plurality of circuit regions is The system further includes a sixth and a seventh circuit element that can switch between a high-impedance state and a pass-through state. The signal transmission circuit according to claim 2, wherein the input terminals of the sixth circuit element and the seventh circuit element are connected to the fourth wiring portion.

4. Each of the aforementioned circuit patterns in the plurality of circuit regions is An eighth and a ninth circuit element capable of switching between a high-impedance state and a pass-through state, The seventh wiring portion connected to the input terminal of the eighth circuit element, The output terminal of the eighth circuit element is connected to the input terminal of the ninth circuit element and to the seventh wiring portion of the circuit region adjacent to the one side, It further includes, The signal transmission circuit according to any one of claims 1 to 3, wherein the output terminal of the ninth circuit element is connected to the second wiring portion.

5. A method for manufacturing a signal transmission circuit according to any one of claims 1 to 4, A method for manufacturing a signal transmission circuit, comprising the step of forming the plurality of circuit regions by performing sequential exposure using a common exposure pattern.

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