Method and apparatus for mitigating collisions of NAND dies in a solid-state drive

Abstract

The quality of service of the multi-stream solid-state drive is improved by storing data to be written to a NAND die in the solid-state drive in a byte-addressable, write-in-place non-volatile memory in the solid-state drive when a NAND die collision prevents a write to the NAND die. The data stored in the byte-addressable, write-in-place non-volatile memory is written to the NAND die when the NAND die is not busy.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Patent Application No. 17 / 222,048, filed on April 5, 2021, which is hereby incorporated by reference in its entirety.

Background Art

[0002] This disclosure relates to solid - state drives, and particularly to collisions of NAND dies within a solid - state drive.

[0003] Non - volatile memory refers to memory whose state is determined even when the power supply to the device is cut off. A solid - state drive is a storage device that stores data in non - volatile memory. Typically, a solid - state drive includes block - based memory such as NAND flash, and a controller that manages read / write requests directed to the NAND flash received from a host communicatively coupled to the solid - state drive.

[0004] A host system can communicate with a solid - state drive (SSD) via a high - speed serial computer expansion bus, such as a Peripheral Component Interconnect Express (PCIe) bus using the Non - Volatile Memory Express (NVMe) standard protocol. The Non - Volatile Memory Express (NVMe) standard protocol defines a register - level interface of host software for communicating with a solid - state drive via a Peripheral Component Interconnect Express (PCIe) bus.

Brief Description of the Drawings

[0005] Features of the claimed embodiments of the subject matter will become apparent as the following detailed description progresses and by reference to drawings in which similar figures indicate similar parts.

[0006] [Figure 1] This is a block diagram of a computer system including a host circuit that is communicatively coupled to a multi-stream solid-state drive.

[0007] [Figure 2] Figure 1 is a block diagram of one embodiment of a multi-stream solid-state drive.

[0008] [Figure 3] This diagram shows queues in byte-addressable write-in-place non-volatile memory used to manage data transfer streams between block-addressable non-volatile memory and host systems.

[0009] [Figure 4] This is a flow graph illustrating how firmware tasks within the firmware manage byte-addressable in-place write non-volatile memory.

[0010] [Figure 5] This is a flow graph of the actions performed by firmware tasks within the firmware of a multi-stream solid-state drive in response to write requests received from the host.

[0011] [Figure 6] This is a flow graph of the actions performed by firmware tasks within the firmware of a multi-stream solid-state drive in response to read requests received from the host.

[0012] [Figure 7]This is a flow graph of how to handle Power Loss Recovery (PLR) events in a solid-state drive.

[0013] [Figure 8] This is a block diagram of one embodiment of a computer system including a multi-stream solid-state drive.

[0014] The following detailed description will proceed with reference to exemplary embodiments of the claimed subject matter, many of which will be apparent to those skilled in the art.

[0015] Therefore, the subject matter claimed is intended to be taken broadly and defined as described in the attached claims. [Modes for carrying out the invention]

[0016] Typically, a solid-state drive (SSD) includes independent NAND dies (also called NAND flash dies) that are communicatively coupled to a controller, enabling parallelization of I / O operations to the NAND dies.

[0017] The time it takes to execute a program operation on a NAND die is far longer than the time it takes to execute a read operation on a NAND die. While the Program Suspend Resume (PSR) function in a solid-state drive allows for pausing an ongoing program operation to perform a read operation, this pause and resume increases the time required to complete the read operation. Read requests received from the host system, queued in the background while an ongoing program operation is running on the NAND die, can significantly impact the read delay or read quality of service (rQoS) of the solid-state drive.

[0018] When data stored in a block of NAND flash memory within a solid-state drive becomes unnecessary, the data must be erased in order to make the block available for storing new data. Before erasing, valid data from one or more blocks must be written to other blocks in the NAND flash memory. These additional NAND operations create a multiplicative effect that increases the number of writes required, resulting in an "amplification" effect called "write amplification." For example, if three pages out of 64 in a block are valid (in use) and all other pages are invalid (no longer in use), the three valid pages must be written to another block before erasing the block, resulting in three page write operations in addition to the erase operation and the writing of new data. The write amplification factor is a numerical value that represents the amount of data that the solid-state drive controller must write in relation to the amount of new data being written. The writing of valid data to other blocks and the erasing operation of the NAND flash memory are commonly referred to as "garbage" collection.

[0019] A host read operation request for the same NAND die can be received while a garbage collection read operation is in progress on the same NAND die. This can be called a "read-on-read collision." A "read-on-read collision" leads to an increased read delay for the host read operation. This read delay includes the time required to complete the garbage collection read operation and the time required to perform error handling (if necessary).

[0020] While the garbage collection program operation for the same NAND die is in progress, a request for a host read operation on the NAND die can be received. While the host program operation for the same NAND die is in progress, a request for a host read operation on the NAND die can be received. These can be referred to as "read collisions during write". "Read collisions during write" cause an increase in the write delay of the write operation. The write delay includes the time to temporarily pause the program operation, execute the read operation, and resume the program operation. "Read collisions during write" and "read collisions during read" are referred to as NAND die collisions.

[0021] Before erasing invalid data in a block within a NAND die, due to the data movement operation of writing valid data stored in one or more pages within the block from the block within the NAND die being erased to another block within the NAND die, the bandwidth that may be used for processing user requests for reading / writing data in the solid state drive is used.

[0022] To reduce the number of pages moved between blocks within a NAND die that store valid data in the NAND die, the Non-Volatile Memory Express (NVMe) standard protocol allows the host to associate write operations to the NAND die with a stream. All data associated with a stream is expected to become invalid simultaneously (i.e., the data has the same expected lifespan). Data with different expected lifespans is mapped to different streams.

[0023] The host system can explicitly open a "stream" within the solid-state drive and send write requests to different streams according to the expected lifespan of the data written to the solid-state drive. The solid-state drive can be called a multi-stream solid-state drive. A multi-stream solid-state drive ensures that the data within a stream is written together to a NAND block and separated from the data associated with other streams.

[0024] The use of multiple streams within a multi-stream solid-state drive reduces write amplification. However, as the number of streams increases, the probability of NAND die collisions increases, which may affect the read service quality. Multiple streams can independently send read and write requests to the same NAND die. For example, for a mixed workload of 70% reads and 30% writes, a command queue depth of 1 (Queue Depth: QD1) per stream, a data transfer of 4 kibibytes (KiB) for each read and write, and the read latency of a multi-stream solid-state drive by logical block address for reads and writes is random, and the 99th percentile level of triple-level cell (TLC) NAND increases from 124 microseconds for 4 streams to 2200 microseconds for 8 streams.

[0025] The service quality of a multi-stream solid-state drive is improved by storing the data to be written to the NAND die within the solid-state drive in a byte-addressable write-in-place non-volatile memory within the solid-state drive when the write to the NAND die is blocked due to die collisions.

[0026] Various embodiments and aspects of the present invention are described with reference to the details discussed below, and the accompanying drawings illustrate various embodiments. The following description and drawings are illustrative of the present invention and should not be construed as limiting the invention. Many specific details are described in order to provide a full understanding of the various embodiments of the present invention. However, in some cases, well-known or prior details are omitted in order to provide a concise discussion of embodiments of the present invention.

[0027] Any reference in this specification to “one embodiment” or “an embodiment” means that certain features, structures, or characteristics described in relation to an embodiment may be included in at least one embodiment of the present invention. Where the phrase “in one embodiment” appears in various parts of this specification, it does not necessarily refer to the same embodiment.

[0028] Figure 1 is a block diagram of a computer system 100, which includes a host circuit 112 that is communicatively coupled to a multistream solid-state drive 102. The host circuit 112 includes host memory 114 and a central processing unit (CPU) 122, which may also be called a processor. One or more applications 116 (programs that perform a specific task or set of tasks) and an operating system 142, which includes a storage stack 124 and a non-volatile memory express (NVMe) driver 110, may be stored in the host memory 114.

[0029] In one embodiment, the multistream solid-state drive 102 has an Enterprise and Data Center SSD Form Factor (EDSFF) and includes 124 or more NAND dies.

[0030] Operating System 142 is software that manages computer hardware and software, including memory allocation and access to input / output (I / O) devices.

[0031] Examples of operating systems include Microsoft® Windows®, Linux®, iOS®, and Android®. In embodiments of the Microsoft® Windows® operating system, the storage stack 124 may be a device stack including port / miniport drivers for the multi-stream solid-state drive 102.

[0032] In one embodiment, the host memory 114 is volatile memory. Volatile memory is memory whose state (and therefore the data stored therein) becomes undefined when the power supply to the device is cut off. Dynamic volatile memory requires refreshing the data stored in the device to maintain its state. Examples of dynamic volatile memory include DRAM (Dynamic Random Access Memory) or several variants such as Synchronous DRAM (SDRAM). As described herein, the memory subsystem may be compatible with several memory technologies, such as DDR3 (Double Data Rate Version 3, first released by JEDEC (Japan Advanced Data Center) on June 27, 2007). DDR4 (DDR version 4, first released by JEDEC in September 2012), DDR5 (DDR version 5, first released in July 2020), LPDDR3 (Low Power DDR version 3, JESD209-3B, released by JEDEC in August 2013), LPDDR4 (LPDDR version 4, JESD209-4, first released by JEDEC in August 2014), LPDDR5 (LPDDR version 5, JESD209-5A, first released by JEDEC in January 2020), WI02 ( It may be compatible with several memory technologies, including Wide Input / Output Version 2 (JESD229-2, first published by JEDEC in August 2014), HBM (High Bandwidth Memory, JESD235, first published by JEDEC in October 2013), HBM2 (HBM Version 2, JESD235C, first published by JEDEC in January 2020), or HBM3 (HBM Version 3, currently under discussion at JEDEC), or other combinations of memory technologies, and technologies based on derivatives or extensions of such specifications. JEDEC standards are available at www.jedec.org.

[0033] The host circuit 112 can communicate with the multi-stream solid-state drive 102 via a high-speed serial computer expansion bus 120, such as a Peripheral Component Interconnect Express (PCIe) bus. The host circuit 112 manages the communication via the Peripheral Component Interconnect Express (PCIe) bus. In one embodiment, the host system communicates via the Peripheral Component Interconnect Express (PCIe) bus using the Non-Volatile Memory Express (NVMe) standard protocol. The Non-Volatile Memory Express (NVMe) standard protocol defines a register-level interface for host software to communicate with the solid-state drive (SSD) 102 via the Peripheral Component Interconnect Express (PCIe) bus. The NVM Express standard is available at www.nvmexpress.org. The PCIe standard is available at pcisig.com.

[0034] The multi-stream solid-state drive 102 includes a solid-state drive controller circuit 104 and a block-addressable non-volatile memory 108. A request to read data stored in the block-addressable non-volatile memory 108 within the multi-stream solid-state drive 102 can be issued to the solid-state drive controller circuit 104 through a storage stack 124 in the operating system 142 by one or more applications 116 (programs that perform a specific task or set of tasks).

[0035] The solid-state drive controller circuit 104 within the multi-stream solid-state drive 102 queues and processes commands received from the host circuit 112 (e.g., read commands, write commands ("program"), erase commands), and performs operations within the block-addressable non-volatile memory 108. Commands received by the solid-state drive controller circuit 104 from the host interface circuit 202 may be called host input / output (IO) commands.

[0036] Figure 2 is a block diagram of one embodiment of the multi-stream solid-state drive 102 of Figure 1. The solid-state drive controller circuit 104 within the multi-stream solid-state drive 102 includes a host interface circuit 202, a non-volatile block-addressable memory controller circuit 212, a CPU 122, firmware 213, a Direct Memory Access Controller (DMAC) 224, static random access memory 230, dynamic random access memory (DRAM) 250, and byte-addressable in-place write non-volatile memory 226. Firmware 213 may be executed by the CPU 122. The solid-state drive controller circuit 104 may be contained in a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). Firmware 213 may be executed by the processor 122.

[0037] A logical block is the smallest addressable data unit for read and write commands to access block-addressable non-volatile memory 108 within the solid-state drive 102. The address of a logical block is generally called a Logical Block Address (LBA).

[0038] The logical-to-physical (L2P) address indirection table 252 (also called the L2P table 252) in the dynamic random access memory 250 stores the physical block addresses in the block-addressable non-volatile memory 108 in the multi-stream solid-state drive 102 corresponding to each LBA. Typically, the L2P address indirection table 252 stores the physical block addresses of the block-addressable non-volatile memory at a granularity of 4 kibibytes (KiB) indirection units (IU).

[0039] Static Random Access Memory (SRAM) is a type of volatile memory. Volatile memory is memory whose state (and therefore the data stored within it) becomes undefined when the power supply to the device is cut off. SRAM is a type of volatile memory that uses latch circuits to store each bit. In contrast to Dynamic Random Access Memory (DRAM), SRAM is typically used as buffer memory because the data stored in SRAM does not need to be refreshed periodically.

[0040] Examples of byte-addressable in-place write non-volatile memory 226 include, but are not limited to, single-level or multi-level phase-change memory (PCM) or phase-change memory with a switch (PCMS), non-volatile memory types including chalcogenide phase-change materials (e.g., chalcogenide glass), metal oxide-based, oxygen vacancy-based and conductive bridge random access memory (CB-RAM), nanowire memory, ferroelectric random access memory (FeRAM, FRAM®), magnetoresistive random access memory (MRAM) incorporating memristor technology, spin transfer torque (STT) MRAM, spintronic magnetic junction memory-based devices, magnetic tunneling junction (MTJ)-based devices, domain wall (DW) and spin orbit transfer devices. This may include Transfer (SOT)-based devices, resistive memory including thyristor-based memory devices, or any combination of the above, or other types of block or byte-addressable in-place write memory.

[0041] The byte-addressable in-place write non-volatile memory 226 may also be volatile memory with power loss protection energy (such as onboard capacitors), such as an Integrated Memory Buffer (IMB) or a Persistent Memory Region (PMB). Examples of volatile memory include DRAM (Dynamic Random Access Memory) and variants of DRAM such as Synchronous DRAM (SDRAM).

[0042] The block-addressable non-volatile memory 108 is a non-volatile memory. A non-volatile memory (NVM) device is a memory whose state is determined even when the power supply to the device is cut off. In one embodiment, the block-addressable non-volatile memory 108 is a NAND flash memory, more specifically, a multi-threshold level NAND flash memory (e.g., a single-level cell ("Single-Level Cell: SLC"), a multi-level cell ("Multi-Level Cell: MLC"), a tri-level cell ("Tri-Level Cell: TLC"), a quad-level cell ("Quad-Level Cell: QLC"), a penta-level cell ("Penta-Level Cell: PLC"), or other NAND flash memory).

[0043] The block-addressable non-volatile memory 108 includes multiple NAND dies 210-1, ..., 210-N (also called NAND flash dies). Typically, data is written (stripeed) across many NAND dies 210-1, ..., 210-N in the multi-stream solid-state drive 102 to optimize the write bandwidth to the block-addressable non-volatile memory 108.

[0044] The bandwidth 240, also known as a stripe, spans one or more blocks of all individual NAND dies 210-1, ..., 210-N, thereby maximizing I / O bandwidth through parallel I / O operation across block-addressable non-volatile memory dies 210-1, ..., 210-N.

[0045] Each of the non-volatile memories of the multiple NAND dies 210-1, ..., 210-N contains multiple blocks 220-1, ..., 220-N, each block containing multiple pages. Each page of the multiple pages stores data and associated metadata.

[0046] In one embodiment, each NAND die 210-1, ..., 210-N has 2048 blocks, each block has 64 pages, and each page can store 2048 bytes of data and 64 bytes of metadata. The bandwidth 240 may include multiple blocks 220-1, ..., 220-N, with one block per NAND die allocated to the bandwidth 240. In the multi-stream solid-state drive 102, a bandwidth 240 having multiple blocks in multiple NAND dies can be allocated to the stream, or one or more individual blocks in a NAND die can be allocated to the stream. In another embodiment, multiple blocks per NAND die can be allocated to the bandwidth 240. For example, n squared (2, 4, 8...) blocks per NAND die can be allocated to the bandwidth 240.

[0047] The non-volatile block-addressable memory controller circuit 212 within the solid-state drive controller circuit 104 queues and processes commands received from the host circuit 112 (e.g., read commands, write commands ("programs"), erase commands) for the block-addressable non-volatile memory 108. Data associated with host I / O commands, such as host read commands and host write commands received from the host circuit 112 via the PCIe bus 120, are stored in buffer 216 within the static random-access memory 230. Buffer 216 may also be called a transfer buffer (TBUF). The received host I / O commands are stored in the command queue 254 within the host interface circuit 202.

[0048] Figure 3 shows a queue in static random access memory 230 for byte-addressable in-place write non-volatile memory 226, which is used to manage the transfer of stream data between block-addressable non-volatile memory 108 and host circuit 112. The byte-addressable in-place write non-volatile memory 226 is managed at the same indirect unit granularity as block-addressable non-volatile memory 108.

[0049] The byte-addressable in-place write non-volatile memory 226 has a pool of indirect units that are allocated to one of three queues: a free queue 300, a processing queue 302, and an active queue 304.

[0050] In response to receiving a host write request to write to block-addressable non-volatile memory 108, the indirect unit is allocated to a stream for data transfer from the free queue 300. After the indirect unit is allocated to the data transfer stream, a pointer to the allocated indirect unit is moved to the processing queue 302.

[0051] After data is written to the allocated indirect unit, the pointer to the allocated indirect unit is moved to the active queue 304. After the data in the allocated indirect unit in the active queue 304 is written to the block-addressable non-volatile memory 108 or rewritten by the host circuit 112, the allocated indirect unit is moved to the free queue 300. If the indirect unit is rewritten by the host circuit 112 before it is written to the NAND dies 210-1, ..., 210-N, the updated host data becomes available in buffer 216 of the static random access memory 230. If there are no collisions, the updated data is written from buffer 216 to the NAND dies 210-1, ..., 210-N.

[0052] The byte-addressable in-place write non-volatile memory 226 improves the quality of service (QoS) of the multi-stream solid-state drive 102 without per-stream bandwidth limitations and scales as the number of streams increases.

[0053] Figure 4 is a flow graph showing how firmware tasks within firmware 213 manage the byte-addressable in-place write non-volatile memory 226.

[0054] In block 400, if the host is inactive or the free space in the byte-addressable in-place write non-volatile memory 226 falls below a threshold, the process proceeds to block 402, where the indirect units in the byte-addressable in-place write non-volatile memory 226 are released.

[0055] In block 402, if the valid queue 304 is empty, there are no indirect units to be written to the block-addressable non-volatile memory 108 in the byte-addressable in-place write non-volatile memory 226, and processing proceeds to block 400.

[0056] In block 404, the active queue 304 is not empty, and within the byte-addressable in-place write non-volatile memory 226, there are indirect units to be written to the block-addressable non-volatile memory 108. The indirect units from the active queue 304 to be written to the block-addressable non-volatile memory 108 may be selected based on LRU (Least Recently Used), FIFO (First In First Out), or the inactive state of the NAND die.

[0057] In one embodiment, the inactive state of the NAND die can be determined by the state of the ready / busy signal on the NAND die. The state of the ready / busy signal can be read by the solid-state drive controller circuit 104. The number of indirect units selected for writing depends on the size of the indirect units and the physical layout of the NAND die. For example, in an embodiment where the size of the indirect units is 4 KiB, the NAND die has a dual plane, and the number of pages in the NAND die is 16 KiB, eight indirect units are selected. The selected indirect units are read from the byte-addressable in-place write non-volatile memory 226 and written to the block-addressable non-volatile memory 108.

[0058] In block 406, the L2P table 252 is updated with the physical address in the block-addressable non-volatile memory 108 where the indirect unit is written.

[0059] In block 408, the selected indirect unit is moved from the active queue 304 to the free queue 300.

[0060] Figure 5 is a flow graph of the operations performed by a firmware task in firmware 213 within the solid-state drive 102 in response to a write request received from the host circuit 112.

[0061] In block 500, if the NAND die to which the write request is directed is busy, this can be determined based on the state of the ready / busy signal on the NAND die, and processing proceeds to block 502. If the NAND die is not busy, processing proceeds to block 504.

[0062] In block 502, the NAND die is busy. The data associated with the write request is written to byte-addressable in-place write non-volatile memory 226 (which may also be called a non-volatile memory cache or persistent memory cache). Processing proceeds to block 506, where the L2P table 252 is updated with the physical location of the data written to byte-addressable in-place write non-volatile memory 226.

[0063] In block 504, the NAND die is not busy. The data associated with the write request is written directly to the NAND die. Processing proceeds to block 506, where the L2P table 252 is updated with the physical location of the data written to the NAND die.

[0064] In block 506, in one embodiment, the most significant bit (MSB) of an L2P entry in the L2P table 252 is used as an identifier for the memory corresponding to the physical block address. The state of the MSB is used to indicate whether the data is stored on the NAND die or in the byte-addressable in-place write non-volatile memory 226. For example, if the state of the MSB is logical "1", the remaining bits represent an offset in the byte-addressable in-place write non-volatile memory 226, and if the state of the MSB is logical "0", the remaining bits represent an address in the NAND die.

[0065] Figure 6 is a flow graph of the operations performed by firmware tasks in firmware 213 within the solid-state drive 102 in response to a read request received from the host circuit 112.

[0066] In block 600, in response to a read request received from the host circuit 112 directed to the block-addressable non-volatile memory 108, the solid-state drive controller circuit 212 reads the entry in the L2P table 252 corresponding to the logical block address included in the read request and obtains the physical address in the block-addressable non-volatile memory 108.

[0067] In block 602, if the physical address is in byte-addressable in-place write non-volatile memory 226, processing proceeds to block 604. If the physical address is in block-addressable non-volatile memory 108, processing proceeds to block 606.

[0068] In block 604, data in the byte-addressable in-place write non-volatile memory 226 is read from the byte-addressable in-place write non-volatile memory 226 and moved to the host circuit 112 by the Direct Memory Access (DMA) controller 224 (also called a DMA engine or DMA circuit) in the solid-state drive controller circuit 212.

[0069] In block 606, the solid-state drive controller circuit 212 reads data from the block-addressable non-volatile memory 108 and writes that data to the buffer 216 in the static random-access memory 230.

[0070] In block 608, after the data is written to buffer 216 in static random access memory 230, the data is read from buffer 216 and moved to the host circuit by DMA controller 224 in solid-state drive controller circuit 212.

[0071] Figure 7 is a flow graph of how power loss recovery (PLR) events are handled in the multi-stream solid-state drive 102.

[0072] During host writing, both the data in the byte-addressable in-place write non-volatile memory 226 and the buffer 216 in the static random access memory 230 are power loss protection (PLI) safe. Therefore, no additional power loss processing is required before power loss. Upon subsequent power-up of the multi-stream solid-state drive 102 after power loss, the firmware 213 in the solid-state drive controller circuit 104 restores the L2P table 252 to its latest state before power loss. The accuracy of the power loss recovery task is maintained by ensuring that the byte-addressable in-place write non-volatile memory 226 has the latest copy of the logical block addresses before power loss by first recovering data from the byte-addressable in-place write non-volatile memory 226.

[0073] In block 700, the solid-state drive 102 re-executes data from NAND dies (also called NAND media) 210-1, ..., 201-N. During the re-execution, the solid-state drive controller circuit 104 reads a backup copy of the L2P table 252 from the block-addressable non-volatile memory 108. However, the backup copy of the L2P table 252 in the block-addressable non-volatile memory 108 may not be the most recent L2P table 252 before the PLI event. To recover the most recent L2P table 252 before the PLI event, the solid-state drive controller circuit 104 re-executes the host write after the backup copy of the L2P table 252 has been written to the block-addressable non-volatile memory 108 before the PLI event. The host write is re-executed by reading the bandwidth journal of the corresponding bandwidth 240 and verifying the logical block address sequence of the host write (write operation from the host circuit received by the host interface circuit 202).

[0074] In block 702, the byte-addressable in-place write non-volatile memory 226 stores the host write before detecting the PLI event. The solid-state drive 102 re-executes the data stored in the byte-addressable in-place write non-volatile memory 226, i.e., updates the L2P table 252 with the host write in the byte-addressable in-place write non-volatile memory 226.

[0075] Figure 8 is a block diagram of one embodiment of a computer system 800 including a multi-stream solid-state drive 102. The computer system 800 can be a computing device including, but is not limited to, a server, a workstation computer, a desktop computer, a laptop computer, and / or a tablet computer.

[0076] The computer system 800 includes a system-on-a-chip (SOC or System on Chip: SoC) 804 that combines a processor, graphics, memory, and input / output (I / O) control logic into a single SoC package. The SoC 804 includes at least one central processing unit (CPU) module 808, a memory controller 814 which may be coupled to volatile memory 826 and / or non-volatile memory 822, and a graphics processor unit (GPU) 810. In other embodiments, the memory controller 814 may be located outside the SoC 804. The CPU module 808 includes at least one processor core 802 and a level 2 (L2) cache 806.

[0077] Although not shown, each of the processor cores 802 may internally include one or more instruction / data caches, execution units, prefetch buffers, instruction queues, branch address calculation units, instruction decoders, floating-point units, retirement units, etc. In one embodiment, the CPU module 808 can support single-core or multi-core general-purpose processors, such as those provided by Intel®.

[0078] The graphics processor unit (GPU) 810 may include one or more GPU cores and a GPU cache capable of storing graphics-related data for the GPU cores. The GPU cores may internally include one or more execution units and one or more instruction and data caches. Furthermore, the graphics processor unit (GPU) 810 may include one or more vertex processing units, rasterization units, media processing units, and codecs, among other graphics logic units not shown in Figure 8.

[0079] Within the I / O subsystem 812, there are one or more I / O adapters 816 that convert the host communication protocols used within the processor core 802 to protocols compatible with specific I / O devices. Some of the protocols that the adapters can convert include Peripheral Component Interconnect (PCI)-Express (PCIe); Universal Serial Bus (USB); Serial Advanced Technology Attachment (SATA); and Institute of Electrical and Electronics Engineers (IEEE) 1594 "FireWire".

[0080] The I / O adapter 816 can communicate with an external I / O device 824, which may include, for example, a display and / or touchscreen display 840, a printer, a keypad, a keyboard, communication logic, user interface devices including wired and / or wireless, a storage device including a hard disk drive ("HDD"), a solid-state drive ("SSD"), removable storage media, a digital video disc (DVD) drive, a compact disc (CD) drive, a redundant array of independent disks (RAID), a tape drive, or other storage devices. Storage devices may communicate and / or be physically coupled through one or more buses using one or more of a variety of protocols, including, but not limited to, SAS (Serial Attached SCSI (Small Computer System Interface)), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express) over PCIe (Peripheral Component Interconnect Express), and SATA (Serial ATA (Advanced Technology Attachment)).

[0081] Furthermore, one or more wireless protocol I / O adapters may be present. Examples of wireless protocols include those used in personal area networks such as IEEE 802.15 and Bluetooth® 4.0; IEEE 802.11-based wireless protocols; and wireless local area networks such as cellular protocols.

[0082] The I / O adapter 816 can also communicate with a solid-state drive ("SSD") 102, which includes a solid-state drive controller circuit 104, a host interface circuit 202, and a block-addressable non-volatile memory 108 containing one or more NAND dies 210-1, ..., 210-N. The solid-state drive controller circuit 104 includes firmware 213 and a byte-addressable in-place write non-volatile memory 226.

[0083] The I / O adapter 816 may include a Peripheral Component Interconnect Express (PCIe) adapter that is communicably coupled to the host interface circuit 202 in the multi-stream solid-state drive 102 using the NVMe (NVM Express) over PCIe (Peripheral Component Interconnect Express) protocol via bus 120.

[0084] Volatile memory is memory whose state (and therefore the data stored within it) becomes undefined when the power supply to the device is cut off. Dynamically volatile memory requires refreshing the data stored in the device to maintain its state. Examples of dynamically volatile memory include DRAM (Dynamic Random Access Memory) and several variants such as Synchronous DRAM (SDRAM). As described herein, the memory subsystem may be compatible with several memory technologies, such as DDR3 (Double Data Rate Version 3, first released by JEDEC (Japan Advanced Data Center) on June 27, 2007). DDR4 (DDR version 4, JESD79-4, first published by JEDEC in September 2012), DDR5 (DDR version 5, JESD79-5, first published in July 2020), LPDDR3 (Low Power DDR version 3, JESD209-3B, published by JEDEC in August 2013), LPDDR4 (LPDDR version 4, JESD209-4, first published by JEDEC in August 2014), LPDDR5 (LPDDR version 5, JESD209-5A, first published by JEDEC in January 2020) It may be compatible with several memory technologies, including publicly available standards, WI02 (Wide Input / Output Version 2, JESD229-2, first published by JEDEC in August 2014), HBM (High Bandwidth Memory, JESD235, first published by JEDEC in October 2013), HBM2 (HBM Version 2, JESD235C, first published by JEDEC in January 2020), or HBM3 (HBM Version 3, currently under discussion at JEDEC), or combinations of other memory technologies, and technologies based on derivatives or extensions of such specifications. JEDEC standards are available at www.jedec.org.

[0085] Power supply 842 supplies power to the components of system 800. More specifically, power supply 842 typically interfaces with one or more power supplies 844 of system 800 to supply power to the components of system 800. In one example, power supply 844 includes an AC-DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power can be a renewable energy (e.g., solar power) power supply 842. In one example, power supply 842 includes a DC power source such as an external AC-DC converter. In one example, power supply 842 or power supply 844 includes wireless charging hardware for charging in proximity to a charging field. In one example, power supply 842 may include an internal battery or fuel cell power source.

[0086] Embodiments of a byte-addressable in-place write non-volatile memory 226 inside a solid-state drive 102 have been described. In another embodiment, the byte-addressable in-place write non-volatile memory 226 is outside the solid-state drive 102 and can be shared across multiple solid-state drives 102. For example, the byte-addressable in-place write non-volatile memory 226 may be within a volatile memory 826, for example, within a battery-backed volatile random-access memory, or within a non-volatile memory 822.

[0087] The flowcharts illustrated herein provide examples of sequences of various process actions. Flowcharts can illustrate actions performed by software or firmware routines, as well as physical actions. In one embodiment, a flowchart may illustrate the states of a finite state machine (FSM) that can be implemented in hardware and / or software form. While shown in a specific sequence or order, the order of actions can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, processes can be executed in different orders, and some actions can be executed in parallel. Furthermore, in various embodiments, one or more actions can be omitted, and therefore, not all actions are required in all embodiments. Other process flows are possible.

[0088] To the extent that various operations or functions are described herein, they may be described or defined as software code, instructions, configurations, and / or data. Content may be in direct executable form ("object" or "executable" form), source code, or differential code ("delta" or "patch" code). Software content of embodiments described herein may be provided via a product on which the content is stored, or via a method of operating a communication interface for transmitting data via a communication interface. Machine-readable storage media include any mechanism for storing information in a form accessible by machines (e.g., computing devices, electronic systems, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.), which can cause a machine to perform the described functions or operations. Communication interfaces include any mechanism for interfaced with any medium, such as hardwired, wireless, or optical, for communicating with another device, such as a memory bus interface, processor bus interface, internet connection, or disk controller. A communication interface can be configured by providing configuration parameters to provide data signals that describe software content, and / or by transmitting signals to prepare the communication interface. A communication interface can be accessed via one or more commands or signals transmitted to it.

[0089] The various components described herein may be means for performing the operations or functions described herein. Each component described herein may include software, hardware, or a combination thereof. Components may be implemented as software modules, hardware modules, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuits, etc.

[0090] In addition to what is described herein, various modifications can be made to the disclosed embodiments and implementations of the present invention without departing from their respective scopes.

[0091] Therefore, the examples and illustrations herein should be interpreted as illustrative, not restrictive. The scope of the present invention should be evaluated solely by reference to the following claims.

Claims

1. It is a solid-state drive, A controller for receiving commands from a host system communicatively coupled to the solid-state drive, the commands indicating writing data to the solid-state drive, the data being associated with a stream; Multiple NAND dies used to store data, one block of the multiple NAND dies being allocated to the stream; and In response to the determination that the NAND die is busy, a byte-addressable in-place write non-volatile memory for storing the data is created. Equipped with, The aforementioned controller further The host system receives the command for writing the data, Upon receiving the command to write the aforementioned data, an indirect unit from the queue of free indirect units is allocated to the stream, and a pointer to the indirect unit is placed in the queue of indirect units being processed. The data is written to the indirect unit in the byte-addressable in-place write non-volatile memory, In response to the data being written to the byte-addressable in-place non-volatile memory, the pointer to the indirect unit is placed in the queue of valid indirect units. It is determined that the free space in the byte-addressable in-place write non-volatile memory is below a threshold, Determine that the queue for a valid indirect unit is not empty. The system is configured to read the indirect unit from the byte-addressable in-place write non-volatile memory and write the indirect unit to at least some of the multiple NAND dies, depending on whether the free space in the byte-addressable in-place write non-volatile memory is below the threshold and the queue of valid indirect units is not empty. Solid-state drive.

2. The solid-state drive according to claim 1, wherein, in response to determining that the NAND die is not busy, the data of the stream is written directly to the block in the NAND die.

3. The solid-state drive according to claim 1, wherein the byte-addressable in-place write non-volatile memory comprises a chalcogenide phase change material.

4. The solid-state drive according to claim 1, wherein the byte-addressable in-place write non-volatile memory is a battery-backed volatile random-access memory.

5. A volatile memory for storing a logical-to-physical address indirection table, each entry in the logical-to-physical address indirection table storing the physical block address where the data is stored, and the identifier of the memory corresponding to the physical block address. The solid-state drive according to claim 1, further comprising:

6. The solid-state drive according to claim 5, wherein the memory is the byte-addressable in-place write non-volatile memory.

7. A solid-state drive, A controller circuit for receiving commands from a host system communicatively coupled to the solid-state drive, the commands for writing data to the solid-state drive, the data being associated with a stream; Multiple NAND dies for storing data, one block of the multiple NAND dies is allocated to the stream; When the NAND die is busy, a byte-addressable in-place write non-volatile memory for storing the data associated with the stream written to the block in the NAND die; and A volatile memory for storing a logical-to-physical address indirection table, each entry in the logical-to-physical address indirection table storing the physical block address where the data is stored, and the identifier of the memory corresponding to the physical block address. Equipped with, The memory is a solid-state drive which is a byte-addressable, in-place write, non-volatile memory.

8. The solid-state drive according to any one of claims 5 to 7, wherein the memory is the NAND die.

9. The controller receives a command from a host system communicatively coupled to the solid-state drive, the command indicating that data should be written to the solid-state drive, the data being associated with a stream; The step of assigning blocks within the NAND die to the stream; In response to the determination that the NAND die is busy, In response to the command for writing the aforementioned data, the step of allocating an indirect unit from a queue of free indirect units to the stream and placing a pointer to the indirect unit in the queue of indirect units being processed; The step of writing the aforementioned data to the indirect unit in a byte-addressable in-place write non-volatile memory; The step of placing the pointer to the indirect unit into the queue of valid indirect units in response to the data being written to the byte-addressable in-place write non-volatile memory; A step of determining whether the free space in the byte-addressable in-place write non-volatile memory is below a threshold; The step of determining that the queue of valid indirect units is not empty; and In response to determining that the free space in the byte-addressable in-place write non-volatile memory is below the threshold and that the queue of valid indirect units is not empty, the step of reading the indirect units from the byte-addressable in-place write non-volatile memory and writing the indirect units to at least a portion of the plurality of NAND dies; A method for providing this.

10. The method according to claim 9, wherein, in response to determining that the NAND die is not busy, the data of the stream is written directly to the block in the NAND die.

11. The method according to claim 9, wherein the byte-addressable in-place write non-volatile memory comprises a chalcogenide phase change material.

12. The method according to claim 9, wherein the byte-addressable in-place write non-volatile memory is a battery-backed volatile random-access memory.

13. In the step of storing the logical-to-physical address indirection table in volatile memory, each entry in the logical-to-physical address indirection table stores the physical block address in which the data is stored, and the identifier of the memory corresponding to the physical block address. The method according to claim 9, further comprising:

14. The method according to claim 13, wherein the memory is the byte-addressable in-place write non-volatile memory.

15. A controller circuit receives a command from a host system communicatively coupled to a solid-state drive, the command being for writing data to the solid-state drive, the data being associated with a stream; The step of assigning blocks within the NAND die to the stream; If the NAND die is busy, the step of storing the data associated with the stream written to the block in the NAND die in byte-addressable in-place write non-volatile memory; and In the step of storing a logical-to-physical address indirection table in volatile memory, each entry in the logical-to-physical address indirection table stores the physical block address where the data is stored, and the identifier of the memory corresponding to the physical block address. Equipped with, The method wherein the memory is the byte-addressable in-place write non-volatile memory.

16. The method according to any one of claims 13 to 15, wherein the memory is the NAND die.

17. A system, Processor; and A controller for receiving commands from the processor, which is communicatively coupled to the solid-state drive, for performing operations within the solid-state drive, the commands indicating writing data to the solid-state drive, the data being associated with a stream; Multiple NAND dies used to store data, one block of the multiple NAND dies being allocated to the stream; and In response to the determination that the NAND die is busy, a byte-addressable in-place write non-volatile memory for storing the data is created. The solid state drive having Equipped with, The aforementioned controller further The system receives the command to write the data, Upon receiving the command to write the aforementioned data, an indirect unit from the queue of free indirect units is allocated to the stream, and a pointer to the indirect unit is placed in the queue of indirect units being processed. The data is written to the indirect unit in the byte-addressable in-place write non-volatile memory, In response to the data being written to the byte-addressable in-place non-volatile memory, the pointer to the indirect unit is placed in the queue of valid indirect units. It is determined that the free space in the byte-addressable in-place write non-volatile memory is below a threshold, Determine that the queue for a valid indirect unit is not empty. The system is configured to read the indirect unit from the byte-addressable in-place write non-volatile memory and write the indirect unit to at least some of the multiple NAND dies, depending on whether the free space in the byte-addressable in-place write non-volatile memory is below the threshold and the queue of valid indirect units is not empty. system.

18. The system according to claim 17, wherein, in response to determining that the NAND die is not busy, the data of the stream is written directly to the block in the NAND die.

19. Processor; and A controller circuit for receiving commands to perform operations within the solid-state drive from the processor, which is communicatively coupled to the solid-state drive, the commands being associated with a stream for writing data to the solid-state drive; Multiple NAND dies for storing data, one block of the multiple NAND dies is allocated to the stream; When the NAND die is busy, a byte-addressable in-place write non-volatile memory for storing data to be written to the block in the NAND die; and A volatile memory for storing a logical-to-physical address indirection table, each entry in the logical-to-physical address indirection table storing the physical block address where the data is stored, and the identifier of the memory corresponding to the physical block address. The solid state drive having Equipped with, The memory is a byte-addressable, in-place write, non-volatile memory in the system.

20. The system according to any one of claims 17 to 19, wherein the byte-addressable in-place write non-volatile memory comprises a chalcogenide phase change material.

21. The system according to any one of claims 17 to 19, wherein the byte-addressable in-place write non-volatile memory is a battery-backed volatile random-access memory.

22. A volatile memory for storing a logical-to-physical address indirection table, each entry in the logical-to-physical address indirection table storing the physical block address where the data is stored, and the identifier of the memory corresponding to the physical block address. The system according to any one of claims 17 to 19, further comprising the above.

23. A display communicatively coupled to the aforementioned processor; or Battery coupled to the aforementioned processor The system according to any one of claims 17 to 19, further comprising one or more of the above.

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