Analog switch circuit

Abstract

To provide an analog switch circuit that can reduce sufficiently noise due to switching between an ON state and an OFF state of a main transistor even when a value (voltage) of a control signal has changed suddenly.SOLUTION: An analog switch circuit includes a switch main body circuit and a control circuit 3. The control circuit 3 includes a first logic gate 31, a second logic gate 32, a first feedback circuit 3a, and a second feedback circuit 3b. To the first logic gate 31 and the second logic gate 32, a control input signal is input. The first feedback circuit 3a inputs a signal obtained by branching output of the first logic gate 31, to the second logic gate 32. The second feedback circuit 3b inputs a signal obtained by branching output of the second logic gate 32, to the first logic gate 31. When Hi / Lo of the control input signal is inverted, inversion timing of Hi / Lo of a first timing signal and inversion timing of Hi / Lo of a second timing signal are different each other because of the first feedback circuit 3a and the second feedback circuit 3b.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an analog switch circuit including a switch body circuit and a control circuit.

Background Art

[0002] Patent Document 1 discloses an analog switch body circuit configured by arranging a PMOS transistor and an NMOS transistor in parallel, and a control circuit for operating the analog switch body circuit. A plurality of inverters are arranged in the control circuit, and by supplying control voltages with opposite phases to the gates of the PMOS transistor and the NMOS transistor, the states where the PMOS transistor and the NMOS transistor are ON and the states where the PMOS transistor and the NMOS transistor are OFF can be switched.

[0003] Furthermore, the analog switch body circuit of Patent Document 1 includes a plurality of sub-transistors in addition to the above-described main transistors (PMOS transistor and NMOS transistor). The sub-transistors switch between a state where the back gate of the main transistor is connected to the source and a state where the back gate of the main transistor is connected to a predetermined potential (high potential in the case of a PMOS transistor and low potential in the case of an NMOS transistor). In Patent Document 1, a plurality of inverters with different thresholds are arranged, and by inputting a control signal having a slope characteristic, a time difference is provided between the operation timing of the main transistor and the operation timing of the sub-transistor. Thereby, noise caused by the switching between the ON state and the OFF state of the main transistor is reduced.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the circuit configuration of Patent Document 1, if the value (voltage) of the control signal changes rapidly, the time difference between the operation timing of the main transistor and the operation timing of the sub-transistor becomes shorter. As a result, it may not be possible to sufficiently reduce the noise caused by the switching between the ON and OFF states of the main transistor.

[0006] This invention has been made in view of the above circumstances, and its main objective is to provide an analog switch circuit that can sufficiently reduce noise caused by the switching between the ON and OFF states of the main transistor, even when the value (voltage) of the control signal changes rapidly. Means and effects for solving the problem

[0007] The problems that this invention aims to solve are as described above, and next, the means for solving these problems and their effects will be explained.

[0008] According to a first aspect of the present invention, an analog switch circuit having the following configuration is provided. That is, the analog switch circuit comprises a switch body circuit and a control circuit. The switch body circuit receives as timing signals a first timing signal including a first inverting signal and a first non-inverting signal, and a second timing signal including a second inverting signal and a second non-inverting signal. The switch body circuit switches between an ON state and an OFF state based on the timing signals. The control circuit outputs the timing signals. The control circuit comprises a first logic gate, a second logic gate, a first feedback circuit, and a second feedback circuit. A control input signal is input to the first logic gate. The control input signal is input to the second logic gate. The first feedback circuit inputs a signal obtained by branching the output of the first logic gate to the second logic gate. The second feedback circuit inputs a signal obtained by branching the output of the second logic gate to the first logic gate. The signal obtained by branching and inverting the output of the first logic gate is the first inverting signal. The first non-inverted signal is obtained by branching the output of the first logic gate and obtaining a non-inverted signal. The second inverted signal is obtained by branching the output of the second logic gate and obtaining an inverted signal. The second non-inverted signal is obtained by branching the output of the second logic gate and obtaining a non-inverted signal. When the Hi / Lo of the control input signal is inverted, the inversion timing of the Hi / Lo of the first timing signal and the inversion timing of the Hi / Lo of the second timing signal are different due to the first feedback circuit and the second feedback circuit.

[0009] Even if the value (voltage) of the control input signal changes rapidly, the Hi / Lo inversion timings of the first timing signal and the second timing signal can be made different. Furthermore, the Hi / Lo inversion timings of both can be made different with a simple configuration using logic gates. As a result, even if the value of the control input signal changes rapidly, the noise caused by the switching between the ON and OFF states of the switch body circuit can be sufficiently reduced.

[0010] In the analog switch circuit described above, the following configuration is preferable. That is, the control circuit comprises a first delay circuit and a second delay circuit. The first delay circuit delays the output of the first logic gate. The second delay circuit delays the output of the second logic gate.

[0011] This allows for a greater difference in the Hi / Lo inversion timing between the first and second timing signals.

[0012] In the analog switch circuit described above, it is preferable that the first delay circuit and the second delay circuit each include an even number of inverters.

[0013] This allows for signal delay without inverting the signal.

[0014] In the analog switch circuit described above, it is preferable that the first delay circuit and the second delay circuit each include a low-pass filter circuit.

[0015] This allows for delaying the signal while cutting out the high-frequency components.

[0016] In the analog switch circuit described above, the following configuration is preferable: The first inverted signal is obtained by branching the output of the first logic gate and inverting it through one inverter. The first non-inverted signal is obtained by branching the output of the first logic gate and not passing through the inverter. The second inverted signal is obtained by branching the output of the second logic gate and inverting it through one inverter. The second non-inverted signal is obtained by branching the output of the second logic gate and not passing through the inverter.

[0017] This allows for the generation of inverted and non-inverted signals with a simple configuration.

[0018] In the analog switch circuit described above, the following configuration is preferable: The first inverted signal is obtained by branching the output of the first logic gate and inverting it through an odd number of inverters. The first non-inverted signal is obtained by branching the output of the first logic gate and inverting it through an even number of inverters. The second inverted signal is obtained by branching the output of the second logic gate and inverting it through an odd number of inverters. The second non-inverted signal is obtained by branching the output of the second logic gate and inverting it through an even number of inverters.

[0019] As a result, the waveform is shaped via the inverter, allowing the switch body circuit to be driven even if the output load of the control circuit increases.

[0020] In the analog switch circuit described above, the following configuration is preferable: The first logic gate is a first NAND gate. The second logic gate is a second NAND gate. The control input signal input to the first NAND gate is non-inverting. The control input signal input to the second NAND gate is inverted by an inverter.

[0021] In the analog switch circuit described above, the following configuration is preferable: The first logic gate is a first NOR gate. The second logic gate is a second NOR gate. The control input signal input to the first NOR gate is non-inverting. The control input signal input to the second NOR gate is inverted by an inverter.

[0022] In the analog switch circuit described above, the following configuration is preferable: The first logic gate is an AND gate. The second logic gate is an OR gate. The control input signal input to the AND gate is non-inverting. The control input signal input to the OR gate is non-inverting.

[0023] In the above analog switch circuit, the following configuration is preferable. That is, the switch body circuit includes a first main transistor, a second main transistor, a first dummy transistor, and a second dummy transistor. The first main transistor functions as a switch for switching between the ON state and the OFF state of the switch body circuit, and a non-inverting signal is input to the 2 first main transistor. The second main transistor functions as a switch for switching between the ON state and the OFF state of the switch body circuit, and an inverting signal is input to the 2 second main transistor. The first dummy transistor is connected to the output side of the first main transistor, and the back gates of the first main transistor and the first dummy transistor are connected to each other, and an inverting signal is input to the 2 first dummy transistor. The second dummy transistor is connected to the output side of the second main transistor, and the back gates of the second main transistor and the second dummy transistor are connected to each other, and a non-inverting signal is input to the 2 second dummy transistor.

[0024] As a result, since the first and second dummy transistors operate in the opposite manner to the main transistors, charge charging and discharging can be canceled.

Brief Description of Drawings

[0025] [Figure 1] Circuit diagram of the analog switch circuit of the embodiment. [Figure 2] Circuit diagram and timing chart of the control circuit of the embodiment. [Figure 3] Circuit diagram and timing chart of the control circuit of the first modification. [Figure 4] Circuit diagram of the control circuit of the second modification. [Figure 5] Circuit diagram of the control circuit of the third modification. [Figure 6] Circuit diagram of the control circuit of the fourth modification. [Figure 7] Circuit diagram and timing chart of the control circuit of the fifth modification. [Figure 8] Circuit diagram and timing chart of the control circuit of the sixth modification. [Figure 9] Circuit diagram of the switch body circuit for the seventh modified example. [Modes for carrying out the invention]

[0026] Next, embodiments of the present invention will be described with reference to the drawings. Figure 1 is a circuit diagram of an analog switch circuit 1 according to an embodiment.

[0027] The analog switch circuit 1 shown in Figure 1 comprises a switch body circuit 2 and a control circuit 3.

[0028] The switch body circuit 2 is connected to input terminal 4 and output terminal 5. When the switch body circuit 2 is ON, it outputs the signal input from input terminal 4 to output terminal 5. When the switch body circuit 2 is OFF, it does not output the signal input from input terminal 4 to output terminal 5.

[0029] The control circuit 3 receives a control input signal from the control terminal 6. In this embodiment, the control input signal is a voltage signal. Based on the control input signal, the control circuit 3 outputs four timing signals. The control input signal is a digital signal and takes either a Hi or Lo value. The four timing signals output by the control circuit 3 are input to the switch body circuit 2. This switches the switch body circuit 2 between the ON state and the OFF state.

[0030] In this specification, the four timing signals are referred to as the first timing signal B+, the first timing signal B-, the second timing signal A+, and the second timing signal A-. As will be described later, the first timing signal B+ and the first timing signal B- are in opposite phase, and the second timing signal A+ and the second timing signal A- are in opposite phase. Furthermore, the first timing signal B+ and the second timing signal A+ are in phase with the control input signal. The first timing signal B- and the second timing signal A- are in opposite phase with the control input signal. However, as will be described in detail later, due to the delay of the signals, they are not strictly in phase / out of phase instantaneously, but there is a time difference.

[0031] Next, the circuit configuration of the switch body circuit 2 will be described. The switch body circuit 2 is a switch circuit that uses MOS transistors as switching elements. The switch body circuit 2 includes a first PMOS transistor 11 and a first NMOS transistor 21 as elements for switching between the ON state and the OFF state. The first PMOS transistor 11 and the first NMOS transistor 21 correspond to the main transistors.

[0032] The source of the first PMOS transistor 11 is connected to input terminal 4, and the drain of the first PMOS transistor 11 is connected to output terminal 5. The gate of the first PMOS transistor 11 is input to the second timing signal A+ output by the control circuit 3. When the second timing signal A+ is low, input terminal 4 and output terminal 5 are connected via the first PMOS transistor 11 (ON state). On the other hand, when the second timing signal A+ is high, input terminal 4 and output terminal 5 are blocked by the first PMOS transistor 11 (OFF state).

[0033] The source of the first NMOS transistor 21 is connected to input terminal 4, and the drain of the first NMOS transistor 21 is connected to output terminal 5. The gate of the first NMOS transistor 21 is input to the second timing signal A- output by the control circuit 3. When the second timing signal A- is Hi, input terminal 4 and output terminal 5 are connected via the first NMOS transistor 21 (ON state). On the other hand, when the second timing signal A- is Lo, input terminal 4 and output terminal 5 are blocked by the first NMOS transistor 21 (OFF state).

[0034] The second timing signals A+ and A- are in opposite phase. Therefore, the first PMOS transistor 11 and the first NMOS transistor 21 will either both be ON or both OFF depending on the control input signal. In other words, the ON and OFF states of the switch body circuit 2 can be switched by inverting the Hi / Lo of the control input signal.

[0035] A second PMOS transistor 12 and a third PMOS transistor 13 are provided in the vicinity of the first PMOS transistor 11. The second PMOS transistor 12 and the third PMOS transistor 13 adjust the back gate voltage of the first PMOS transistor 11. The second PMOS transistor 12 is positioned between the back gate and source of the first PMOS transistor 11. The gate of the second PMOS transistor 12 is input to the first timing signal B+.

[0036] The third PMOS transistor 13 is positioned between the back gate of the first PMOS transistor 11 and a predetermined potential VDD. VDD is a high potential because it is the power supply potential. The gate of the third PMOS transistor 13 is input to the first timing signal B-.

[0037] Here, when the second timing signal A+ is low, the first PMOS transistor 11 is ON. During this time, since the first timing signal B+ is low, the second PMOS transistor 12 is ON. At this time, since the first timing signal B- is high, the third PMOS transistor 13 is OFF. As a result, the back gate voltage of the first PMOS transistor 11 is connected to the source. Therefore, fluctuations in the threshold voltage of the first PMOS transistor 11 can be suppressed.

[0038] On the other hand, when the second timing signal A+ is high, the first PMOS transistor 11 is in the OFF state. During this time, since the first timing signal B+ is high, the second PMOS transistor 12 is in the OFF state. At this time, since the first timing signal B- is low, the third PMOS transistor 13 is in the ON state. As a result, the back gate voltage of the first PMOS transistor 11 is connected to VDD. Therefore, no potential difference is generated that would cause the parasitic diode between the back gate and drain of the first PMOS transistor 11 to operate, and thus it can maintain the OFF state.

[0039] Similarly, on the side of the first NMOS transistor 21, a second NMOS transistor 22 and a third NMOS transistor 23 are also provided. The circuit configuration and function of the second NMOS transistor 22 and the third NMOS transistor 23 are the same as those of the second PMOS transistor 12 and the third PMOS transistor 13, so they will be briefly explained.

[0040] The second NMOS transistor 22 is positioned between the back gate and source of the first NMOS transistor 21. The first timing signal B- is input to the gate of the second NMOS transistor 22. The third NMOS transistor 23 is positioned between the back gate of the first NMOS transistor 21 and GND (ground). The first timing signal B+ is input to the gate of the third NMOS transistor 23.

[0041] When the first NMOS transistor 21 is ON, the second NMOS transistor 22 is also ON, and the back gate voltage of the first NMOS transistor 21 is connected to the source. Therefore, fluctuations in the threshold voltage of the first NMOS transistor 21 can be suppressed. When the first NMOS transistor 21 is OFF, the third NMOS transistor 23 is also ON, and the back gate voltage of the first NMOS transistor 21 is connected to GND. Therefore, no potential difference is generated that would cause the parasitic diode between the back gate and drain of the first NMOS transistor 21 to operate, and thus the OFF state can be maintained.

[0042] Next, the circuit configuration of control circuit 3 will be explained with reference to Figure 2.

[0043] As described above, the second timing signals A+ and A- control the operating timing of the main transistors (first PMOS transistor 11, first NMOS transistor 21) which function as switches. The first timing signals B+ and B- control the operating timing of the sub-transistors (second PMOS transistor 12, third PMOS transistor 13, second NMOS transistor 22, third NMOS transistor 23) for adjusting the back gate voltage.

[0044] Here, when the ON and OFF states of the first PMOS transistor 11 and the first NMOS transistor 21 are switched, a current is generated due to the charging and discharging of charge, so noise is included in the signal output to the output terminal 5. However, if the back gates and sources of the first PMOS transistor 11 and the first NMOS transistor 21 are connected at the Hi / Lo inversion timing of the first PMOS transistor 11 and the first NMOS transistor 21, the charging and discharging of charge can be suppressed. In other words, if the first timing signal B+ is Lo and the first timing signal B- is Hi at the Hi / Lo inversion timing of the second timing signals A+ and A-, the above noise problem can be avoided.

[0045] In this regard, the control circuit 3 of this embodiment can invert the first timing signals B+ and B- at this timing by adopting the circuit configuration shown in Figure 2(a). Specifically, the control circuit 3 comprises a first logic gate 31, a second logic gate 32, a first inverter 41, a second inverter 42, and a third inverter 43.

[0046] The first logic gate 31 and the second logic gate 32 are NAND gates. The circuit connected to the control terminal 6 is branched into two; one is connected to the input of the first logic gate 31, and the other is connected to the input of the second logic gate 32 via the first inverter 41. The Hi / Lo state of the control input signal is inverted via the first inverter 41.

[0047] The output of the first logic gate 31 is split into three parts. The first is output as the first timing signal B+ after being inverted Hi / Lo via the second inverter 42. The second is output as the first timing signal B- without going through the inverter (without Hi / Lo inversion). The third is fed back by the first feedback circuit 3a and input to the second logic gate 32.

[0048] The output of the second logic gate 32 is split into three parts. The first is output as the second timing signal A+ without going through the inverter (without Hi / Lo inversion). The second is output as the second timing signal A- after Hi / Lo inversion via the third inverter 43. The third is fed back by the second feedback circuit 3b and input to the first logic gate 31.

[0049] Next, the operation of the control circuit 3 will be explained with reference to Figure 2(b).

[0050] When the voltage Va at control terminal 6 is low, the first logic gate 31 receives the low signal from control terminal 6. Therefore, the output of the first logic gate 31 becomes high. Consequently, the first timing signal B+ becomes low, and the first timing signal B- becomes high.

[0051] When the voltage Va at control terminal 6 is low, the second logic gate 32 receives a high signal from control terminal 6 and a high signal from the first logic gate 31. Therefore, the output of the second logic gate 32 becomes low. Consequently, the second timing signal A+ becomes low, and the second timing signal A- becomes high.

[0052] Subsequently, the voltage Va at control terminal 6 inverts from Lo to Hi, causing the input from control terminal 6 to the first logic gate 31 to become Hi, and the input from control terminal 6 to the second logic gate 32 to become Lo. As a result, at time T1, the output of the second logic gate 32 inverts from Lo to Hi. Consequently, the second timing signal A+ becomes Hi, and the second timing signal A- becomes Lo.

[0053] Then, the input to the first logic gate 31 becomes the Hi input from control terminal 6 and the Hi input from the second logic gate 32. As a result, at a slightly later time T2, the output of the first logic gate 31 inverts from Hi to Lo. Consequently, the first timing signal B+ becomes Hi and the first timing signal B- becomes Lo.

[0054] Subsequently, the voltage Va at control terminal 6 inverts from Hi to Lo, causing the input from control terminal 6 to the first logic gate 31 to become Lo and the input from control terminal 6 to the second logic gate 32 to become Hi. As a result, at time T3, the output of the first logic gate 31 inverts from Lo to Hi. Consequently, the first timing signal B+ becomes Lo and the first timing signal B- becomes Hi.

[0055] Then, the input to the second logic gate 32 becomes the Hi input from control terminal 6 and the Hi input from the first logic gate 31. As a result, at a slightly later time T4, the output of the second logic gate 32 inverts from Hi to Lo. Consequently, the second timing signal A+ becomes Lo and the second timing signal A- becomes Hi.

[0056] As shown above, when the voltage Va at control terminal 6 is inverted, the output of one of the logic gates, the first logic gate 31 and the second logic gate 32, is inverted first. Then, after the inverted output of one logic gate is input to the other logic gate, the output of the other logic gate is inverted. This makes it possible to make the inversion timing of the Hi / Lo of the first timing signals B+, B- and the inversion timing of the second timing signals A+, A- different. Furthermore, at the inversion timing of the second timing signals A+, A-, the first timing signal B+ is always Lo and the first timing signal B- is always Hi. As a result, at the Hi / Lo inversion timing of the first PMOS transistor 11 and the first NMOS transistor 21, the back gates and sources of the first PMOS transistor 11 and the first NMOS transistor 21 are connected, thus avoiding the noise problem mentioned above. Moreover, the control circuit 3 can operate without problems even if the slope of the voltage Va at control terminal 6 is steep.

[0057] Next, a first modified example will be described with reference to Figure 3. Figure 3 is a circuit diagram and timing chart of the control circuit 3 of the first modified example. In the following description, components that are the same as or similar to those in the previously described embodiment will be denoted by the same reference numerals in the drawings, and their descriptions may be omitted.

[0058] The first modified example differs from the above embodiment in that a first delay circuit 7 and a second delay circuit 8 are provided. The first delay circuit 7 and the second delay circuit 8 are circuits that delay a signal.

[0059] The first delay circuit 7 delays the output of the first logic gate 31. Specifically, the first delay circuit 7 is positioned between the output of the first logic gate 31 and a branching point that splits the output of the first logic gate 31. The first delay circuit 7 includes a fourth inverter 44 and a fifth inverter 45. By passing through the fourth inverter 44 and the fifth inverter 45, the transmission of the signal is delayed. Also, because an even number of inverters are connected, the Hi / Lo of the signal is not inverted.

[0060] The second delay circuit 8 delays the output of the second logic gate 32. Specifically, the second delay circuit 8 is positioned between the output of the second logic gate 32 and the branching point that splits the output of the second logic gate 32. The second delay circuit 8 includes a sixth inverter 46 and a seventh inverter 47. By passing through the sixth inverter 46 and the seventh inverter 47, the transmission of the signal is delayed. Also, because the number of inverters is even, the Hi / Lo of the signal is not inverted.

[0061] By delaying the output of the first logic gate 31, the time between the inversion of the output of the first logic gate 31 and the inversion of the first timing signals B+ and B- is increased (the time from time T1 to time T2 is increased). By delaying the output of the second logic gate 32, the time between the inversion of the output of the second logic gate 32 and the inversion of the second timing signals A+ and A- is increased (the time from time T3 to time T4 is increased). This makes it possible to more reliably avoid noise problems.

[0062] In the first modified example, an inverter is used to delay the signal, but other methods may be used to delay the signal. For example, as shown in the second modified example in Figure 4, a low-pass filter circuit may be used to delay the signal. As shown in Figure 4, the first delay circuit 7 in the second modified example is a low-pass filter circuit including a first resistor 61 and a first capacitor 62. The second delay circuit 8 in the second modified example is a low-pass filter circuit including a second resistor 63 and a second capacitor 64. This allows the signal to be delayed while cutting out the high-frequency components of the signal.

[0063] Furthermore, as shown in the third modified example in Figure 5, the first modified example and the second modified example may be combined. The first delay circuit 7 of the third modified example includes a fourth inverter 44, a fifth inverter 45, a first resistor 61, and a first capacitor 62. The second delay circuit 8 of the third modified example includes a sixth inverter 46, a seventh inverter 47, a second resistor 63, and a second capacitor 64.

[0064] In the first and third modified examples, two inverters are arranged in each example. Alternatively, an even number of inverters greater than 2 (4, 6, ...) may be arranged in each example.

[0065] Next, the fourth modified example will be described with reference to Figure 6. Figure 6 is a circuit diagram of the control circuit 3 of the fourth modified example.

[0066] The fourth modified example differs from the above embodiment in that it includes an eighth inverter 48, a ninth inverter 49, a tenth inverter 50, and an eleventh inverter 51.

[0067] The eighth inverter 48 and the ninth inverter 49 are positioned between the branching point of the output of the first logic gate 31 and the terminal of the first timing signal B-. In other words, the output of the first logic gate 31 is output as the first timing signal B- via the eighth inverter 48 and the ninth inverter 49. Note that the Hi / Lo state of the output does not change even when passing through the two inverters.

[0068] The 10th inverter 50 and the 11th inverter 51 are positioned between the branching point of the output of the second logic gate 32 and the terminal of the second timing signal A+. In other words, the output of the second logic gate 32 is output as the second timing signal A+ via the 10th inverter 50 and the 11th inverter 51. Note that the Hi / Lo state of the output does not change even when passing through the two inverters.

[0069] As a result, all four timing signals pass through the inverter, thus shaping the signal waveforms. Consequently, the switch body circuit 2 can be driven even if the output load of the control circuit 3 increases.

[0070] Furthermore, an even number of inverters greater than 2 (4, 6, ...) may be placed between the branching point of the output of the first logic gate 31 and the terminal of the first timing signal B-. An odd number of inverters greater than 1 (3, 5, ...) may be placed between the branching point of the output of the first logic gate 31 and the terminal of the first timing signal B+. Also, an even number of inverters greater than 2 (4, 6, ...) may be placed between the branching point of the output of the second logic gate 32 and the terminal of the second timing signal A+. An odd number of inverters greater than 1 (3, 5, ...) may be placed between the branching point of the output of the second logic gate 32 and the terminal of the second timing signal A-.

[0071] In the above embodiment, the first logic gate 31 and the second logic gate 32 of the control circuit 3 are NAND gates. However, other logic gates may be used, as in the fifth and sixth modified examples, as long as they can achieve the same functionality.

[0072] In the fifth modified example shown in Figure 7, NOR gates are used as the first logic gate 33 and the second logic gate 34, respectively. The control terminal 6 is connected to the input of the first logic gate 33 without going through an inverter, and is also connected to the input of the second logic gate 34 via the first inverter 41. The output of the first logic gate 33 is inverted via the second inverter 42 and output as the second timing signal A+. The output of the first logic gate 33 is output without inversion as the second timing signal A-. The output of the first logic gate 33 is fed back by the first feedback circuit 3a and input to the second logic gate 34. The output of the second logic gate 34 is output without inversion as the first timing signal B+. The output of the second logic gate 34 is inverted by the third inverter 43 and output as the first timing signal B-. The output of the second logic gate 34 is fed back by the second feedback circuit 3b and input to the first logic gate 33.

[0073] Thus, in the fifth modification, the functions of the first logic gate 33 and the second logic gate 34 are different, and as a result, the first timing signals B+, B- and the second timing signals A+, A- are swapped compared to the above embodiment. In the fifth modification, the principle of time differences occurring between time T1 and time T2, and between time T3 and time T4 is the same as in the above embodiment. That is, of the first logic gate 33 and the second logic gate 34, the output of one logic gate is immediately inverted due to a change in the voltage Va at the control terminal 6, and the output of the other logic gate is inverted due to a change in the output of the other logic gate.

[0074] In the sixth modified example shown in Figure 8, an AND gate is used as the first logic gate 35, and an OR gate is used as the second logic gate 36. The control terminal 6 is connected to the inputs of the first logic gate 35 and the second logic gate 36, respectively, without going through an inverter. The output of the first logic gate 35 is output as the first timing signal B+ without inversion. The output of the first logic gate 35 is inverted via the second inverter 42 and output as the first timing signal B-. The output of the first logic gate 35 is fed back by the first feedback circuit 3a and input to the second logic gate 36. The output of the second logic gate 36 is output as the second timing signal A+ without inversion. The output of the second logic gate 36 is inverted by the third inverter 43 and output as the second timing signal A-. The output of the second logic gate 36 is fed back by the second feedback circuit 3b and input to the first logic gate 35.

[0075] Thus, in the sixth modification, the first inverter 41 is omitted due to the different functions of the first logic gate 35 and the second logic gate 36, and furthermore, the signal output as the first timing signal B- passes through the second inverter 42. Also, in the sixth modification, the principle that a time difference occurs between time T1 and time T2, and between time T3 and time T4, is the same as in the above embodiment.

[0076] Next, the seventh modified example will be described with reference to Figure 9. Figure 9 is a circuit diagram of the switch body circuit 2 of the seventh modified example.

[0077] The seventh modification differs from the above embodiment in that a dummy MOS transistor is further provided adjacent to each of the MOS transistors described above.

[0078] A first dummy PMOS transistor 11a is provided between the first PMOS transistor 11 and the output terminal 5 (i.e., on the drain side of the first PMOS transistor 11). The back gate of the first dummy PMOS transistor 11a is connected to the back gate of the first PMOS transistor 11. In addition, the second timing signal A- is input to the gate of the first dummy PMOS transistor 11a. Similar to the above embodiment, the second timing signal A+ output by the control circuit 3 is input to the gate of the first PMOS transistor 11. In other words, signals with opposite phases are input to the gate of the first PMOS transistor 11 and the gate of the first dummy PMOS transistor 11a. As a result, the first PMOS transistor 11 and the first dummy PMOS transistor 11a operate in opposite directions, so that the charge generated in one can be canceled out by the charge generated in the other. Furthermore, the capacitance (size) of the first dummy PMOS transistor 11a is preferably smaller than the capacitance of the first PMOS transistor 11, and more preferably half (the same applies to other dummy MOS transistors).

[0079] The placement and function of the first dummy NMOS transistor 21a are the same as those of the first dummy PMOS transistor 11a, so they will be briefly explained. The first dummy NMOS transistor 21a is located between the first NMOS transistor 21 and the output terminal 5. The back gate of the first dummy NMOS transistor 21a is connected to the back gate of the first NMOS transistor 21. Opposite-phase signals are input to the gates of the first NMOS transistor 21 and the gate of the first dummy NMOS transistor 21a. This allows the charge generated in one to be canceled out by the charge generated in the other.

[0080] Furthermore, a second dummy PMOS transistor 12a is provided on the VDD side of the second PMOS transistor 12. A third dummy PMOS transistor 13a is provided on the input terminal 4 side of the third PMOS transistor 13. A second dummy NMOS transistor 22a is provided on the GND side of the second NMOS transistor 22. A third dummy NMOS transistor 23a is provided on the input terminal 4 side of the third NMOS transistor 23. The gates of the dummy transistors are input to signals that are in opposite phase to the gates of the main transistors. This allows the charge generated in one to be canceled out by the charge generated in the other.

[0081] The embodiments and modifications described above can be combined as appropriate, as long as no inconsistencies arise. For example, the switch body circuit 2 of the seventh modification can be applied to any of the embodiments and modifications 1 through 6 described above.

[0082] As described above, the analog switch circuit 1 of the above embodiment and modified example comprises a switch body circuit 2 and a control circuit 3. The switch body circuit 2 receives a first timing signal including a first inverting signal and a first non-inverting signal, and a second timing signal including a second inverting signal and a second non-inverting signal as timing signals. The switch body circuit 2 switches between an ON state and an OFF state based on the timing signals. The control circuit 3 outputs timing signals. The control circuit 3 comprises first logic gates 31, 33, 35, second logic gates 32, 34, 36, a first feedback circuit 3a, and a second feedback circuit 3b. The first logic gates 31, 33, 35 receive control input signals (including signals obtained by inverting the control input signals). The second logic gates 32, 34, 36 receive control input signals (including signals obtained by inverting the control input signals). The first feedback circuit 3a inputs the signals obtained by branching the outputs of the first logic gates 31, 33, and 35 to the second logic gates 32, 34, and 36. The second feedback circuit 3b inputs the signals obtained by branching the outputs of the second logic gates 32, 34, and 36 to the first logic gates 31, 33, and 35. The first inverted signal is obtained by branching and inverting the outputs of the first logic gates 31, 33, and 35. The first non-inverted signal is obtained by branching and not inverting the outputs of the first logic gates 31, 33, and 35. The second inverted signal is obtained by branching and inverting the outputs of the second logic gates 32, 34, and 36. The second non-inverted signal is obtained by branching and not inverting the outputs of the second logic gates 32, 34, and 36. When the Hi / Lo of the control input signal is inverted, the inversion timing of the Hi / Lo of the first timing signal and the inversion timing of the Hi / Lo of the second timing signal differ due to the first feedback circuit 3a and the second feedback circuit 3b.

[0083] Even if the value (voltage) of the control input signal changes rapidly, the Hi / Lo inversion timings of the first timing signal and the second timing signal can be made different. Furthermore, the Hi / Lo inversion timings of both can be made different with a simple configuration using logic gates. As a result, even if the value of the control input signal changes rapidly, the noise caused by the switching between the ON and OFF states of the switch body circuit 2 can be sufficiently reduced.

[0084] Furthermore, in the first to third modified analog switch circuits 1, the control circuit 3 includes a first delay circuit 7 and a second delay circuit 8. The first delay circuit 7 delays the output of the first logic gate 31. The second delay circuit 8 delays the output of the second logic gate 32.

[0085] This allows for a greater difference in the Hi / Lo inversion timing between the first and second timing signals.

[0086] Furthermore, in the first and third modified analog switch circuits 1, the first delay circuit 7 and the second delay circuit 8 each include an even number of inverters 44, 45, 46, and 47.

[0087] This allows for signal delay without inverting the signal.

[0088] Furthermore, in the second and third modified analog switch circuits 1, the first delay circuit 7 and the second delay circuit 8 each include a low-pass filter circuit.

[0089] This allows for delaying the signal while cutting out the high-frequency components.

[0090] In the analog switch circuit 1 of the above embodiment, the first to third modifications, and the fifth and sixth modifications, the first inverted signal is obtained by branching the outputs of the first logic gates 31, 33, and 35 and inverting them through a single second inverter 42. The first non-inverted signal is obtained by branching the outputs of the first logic gates 31, 33, and 35 and passing them without an inverter. The second inverted signal is obtained by branching the outputs of the second logic gates 32, 34, and 36 and inverting them through a single third inverter 43. The second non-inverted signal is obtained by branching the outputs of the second logic gates 32, 34, and 36 and passing them without an inverter.

[0091] This allows for the generation of inverted and non-inverted signals with a simple configuration.

[0092] In the fourth modified analog switch circuit 1, the first inverted signal is obtained by branching the output of the first logic gate 31 and inverting it through an odd number of inverters (one second inverter 42). The first non-inverted signal is obtained by branching the output of the first logic gate 31 and inverting it through an even number of inverters (eighth inverter 48 and ninth inverter 49). The second inverted signal is obtained by branching the output of the second logic gate 32 and inverting it through an odd number of inverters (third inverter 43). The second non-inverted signal is obtained by branching the output of the second logic gate and inverting it through an even number of inverters (tenth inverter 50 and eleventh inverter 51).

[0093] As a result, the waveform is shaped via the inverter, allowing the switch body circuit 2 to be driven even if the output load of the control circuit 3 increases.

[0094] In the analog switch circuit 1 of the above embodiment and the first to fourth modified examples, the first logic gate 31 is a first NAND gate. The second logic gate 32 is a second NAND gate. The control input signal input to the first NAND gate is non-inverting. The control input signal input to the second NAND gate is inverted by an inverter.

[0095] In the fifth modified analog switch circuit 1, the first logic gate 33 is a first NOR gate. The second logic gate 34 is a second NOR gate. The control input signal input to the first NOR gate is non-inverting. The control input signal input to the second NOR gate is inverted by an inverter.

[0096] In the sixth modified analog switch circuit 1, the first logic gate 35 is an AND gate. The second logic gate 36 is an OR gate. The control input signal input to the AND gate is non-inverting. The control input signal input to the OR gate is non-inverting.

[0097] The switch body circuit 2 of the seventh modified analog switch circuit 1 comprises a first PMOS transistor 11, a first NMOS transistor 21, a first dummy PMOS transistor 11a, and a first dummy NMOS transistor 21a. The first PMOS transistor 11 functions as a switch to switch the ON state and OFF state of the switch body circuit 2, and a second non-inverting signal is input to it. The first NMOS transistor 21 functions as a switch to switch the ON state and OFF state of the switch body circuit 2, and a second inverting signal is input to it. The first dummy PMOS transistor 11a is connected to the output side of the first PMOS transistor 11, and its back gate is connected to the first PMOS transistor 11, and a second inverting signal is input to it. The first dummy NMOS transistor 21a is connected to the output side of the first NMOS transistor 21, and its back gate is connected to the first NMOS transistor 21, and a second non-inverting signal is input to it.

[0098] As a result, the first and second dummy transistors operate in the opposite direction to the main transistor, thus canceling out the charging and discharging of the charge. [Explanation of Symbols]

[0099] 1. Analog switch circuit 2. Switch main circuit 3. Control circuits 31, 33, 35 First logic gate 32, 34, 36 Second logic gate 3a First feedback circuit 3b Second feedback circuit

Claims

1. A switch body circuit receives a first timing signal including a first inverted signal and a first non-inverted signal, and a second timing signal including a second inverted signal and a second non-inverted signal as timing signals, and switches between an ON state and an OFF state based on these timing signals. A control circuit that outputs the aforementioned timing signal, Equipped with, The aforementioned switch body circuit is The gate of the first main transistor is a PMOS transistor to which the second non-inverting signal is input and which is connected between the input terminal and the output terminal. The gate of the second inverting signal is input to a second main transistor, which is an NMOS transistor connected between the input terminal and the output terminal, The gate of the first inverting signal is input to a second PMOS transistor, which is a PMOS transistor connected between the back gate of the first main transistor and the input terminal, The gate of the first non-inverting signal is input to a third PMOS transistor, which is a PMOS transistor connected between the back gate of the first main transistor and a high potential, The gate of the second NMOS transistor is input to the first non-inverting signal and is connected between the back gate of the second main transistor and the input terminal. The gate of the first inverting signal is input to a third NMOS transistor, which is an NMOS transistor connected between the back gate of the second main transistor and a low potential, Equipped with, The aforementioned control circuit is A first logic gate to which a control input signal is input, The control input signal is input to a second logic gate, A first feedback circuit inputs a signal obtained by branching the output of the first logic gate to the second logic gate, A second feedback circuit inputs the signal obtained by branching the output of the second logic gate to the first logic gate, Equipped with, The first inverted signal is obtained by branching and inverting the output of the first logic gate. The first non-inverted signal is obtained by branching the output of the first logic gate and obtaining a non-inverted signal. The second inverted signal is obtained by branching and inverting the output of the second logic gate. The second non-inverted signal is obtained by branching the output of the second logic gate and obtaining a non-inverted signal. When the Hi / Lo of the control input signal is inverted, the inversion timing of the Hi / Lo of the first timing signal and the inversion timing of the Hi / Lo of the second timing signal differ due to the first feedback circuit and the second feedback circuit. The first main transistor functions as a switch that switches between the ON state and the OFF state of the switch body circuit. The second main transistor functions as a switch that toggles the ON state and the OFF state of the switch body circuit. The aforementioned switch body circuit further, A first dummy transistor, which is a PMOS transistor connected to the output side of the first main transistor with its drain and source short-circuited, has its back gate connected to the first main transistor, and receives the second inverting signal. A second dummy transistor, which is an NMOS transistor connected to the output side of the second main transistor with its drain and source short-circuited, has its back gate connected to the second main transistor, and receives the second non-inverting signal. An analog switch circuit characterized by having the following features.

2. The analog switch circuit according to claim 1, The aforementioned control circuit is A first delay circuit that delays the output of the first logic gate, A second delay circuit that delays the output of the second logic gate, An analog switch circuit characterized by having the following features.

3. The analog switch circuit according to claim 2, The first delay circuit and the second delay circuit are analog switch circuits characterized in that they each include an even number of inverters.

4. The analog switch circuit according to claim 2, The analog switch circuit is characterized in that the first delay circuit and the second delay circuit each include a low-pass filter circuit.

5. The analog switch circuit according to claim 1, The first inverted signal is obtained by branching the output of the first logic gate and inverting it through one inverter. The first non-inverting signal is obtained by branching the output of the first logic gate and bypassing the inverter. The second inverted signal is obtained by branching the output of the second logic gate and inverting it through one of the inverters. An analog switch circuit characterized in that the output of the second logic gate is branched, and the signal that does not go through the inverter is the second non-inverting signal.

6. The analog switch circuit according to claim 1, The first inverted signal is obtained by branching the output of the first logic gate and inverting it through an odd number of inverters. The output of the first logic gate is branched, and the signal obtained by passing through an even number of inverters is the first non-inverting signal. The second inverted signal is obtained by branching the output of the second logic gate and inverting it through an odd number of inverters. An analog switch circuit characterized in that the output of the second logic gate is branched, and the signal transmitted through an even number of inverters is the second non-inverting signal.

7. The analog switch circuit according to claim 1, The first logic gate is a first NAND gate, The second logic gate is a second NAND gate, The control input signal input to the first NAND gate is non-inverting, An analog switch circuit characterized in that the control input signal input to the second NAND gate is inverted by an inverter.

8. The analog switch circuit according to claim 1, The first logic gate is a first NOR gate, The second logic gate is a second NOR gate, The control input signal input to the first NOR gate is non-inverting, An analog switch circuit characterized in that the control input signal input to the second NOR gate is inverted by an inverter.

9. The analog switch circuit according to claim 1, The first logic gate is an AND gate, The second logic gate is an OR gate, The control input signal input to the AND gate is non-inverting. An analog switch circuit characterized in that the control input signal input to the OR gate is non-inverting.

10. The analog switch circuit according to Claim 1, The capacitance of the first dummy transistor is smaller than the capacitance of the first main transistor. An analog switch circuit characterized in that the capacitance of the second dummy transistor is smaller than the capacitance of the second main transistor.

11. The analog switch circuit according to claim 1, The capacitance of the first dummy transistor is half the capacitance of the first main transistor. An analog switch circuit characterized in that the capacitance of the second dummy transistor is half the capacitance of the second main transistor.

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