Semiconductor device and method for manufacturing the same

Abstract

To improve a performance of a semiconductor device.SOLUTION: A semiconductor substrate includes: a plurality of emitter formation regions ER that is separated in a Y direction between a pair of trenches TR; and a separation region SR that is positioned between the emitter formation regions ER. A p-type base region PB is formed in each emitter formation region ER and each semiconductor substrate of the separation region SR. An n-type impurity region CSL is formed in a base region PB of each emitter formation region ER. The n-type impurity region CSL is also formed in the base region PB at a portion contacted to the pair of trenches TR of the separation region SR.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a gate electrode formed inside a trench and a method for manufacturing the same. [Background technology]

[0002] In recent years, semiconductor devices equipped with power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) have been widely used. Furthermore, IGBTs with low on-resistance, specifically those with a structure in which the gate electrode is embedded inside a trench, are known.

[0003] For example, Patent Document 1 discloses an IGBT with a GGEE structure that utilizes the IE (Injection Enhancement) effect. The IE effect is a technique that increases the concentration of charge accumulated in the drift region by making it difficult for holes to be discharged to the emitter electrode EE side when the IGBT is in the ON state.

[0004] In the GGEE structure, the "G" refers to a structure in which a gate electrode connected to the gate potential is embedded inside a trench, and this is called a gate trench. Similarly, the "E" refers to a structure in which a gate electrode connected to the emitter potential is embedded inside a trench, and this is called an emitter trench. Therefore, a GGEE structure is a structure in which a pair of emitter trenches are formed at a certain distance from a pair of gate trenches.

[0005] Patent Document 1 discloses an IGBT with a GGEE structure that utilizes the IE effect. In this IGBT, the n-type emitter region formed between a pair of gate trenches is divided into multiple parts along the direction of extension of the trenches. [Prior art documents] [Patent Documents]

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] FIG. 39 is a plan view showing a semiconductor device of an examination example studied by the inventors of the present application, and shows an IGBT of a GGEE structure. A gate trench is constituted by a trench TR formed in an active cell AC and a gate electrode GE1 formed inside the trench TR. Further, an emitter trench is constituted by a trench TR formed in an inactive cell IAC and a gate electrode GE2 formed inside the trench TR. An n-type impurity region NE is formed in a plurality of emitter formation regions ER. No impurity region NE is formed in a separation region SR between the plurality of emitter formation regions ER.

[0008] For products that require a high breakdown voltage such as 750V to 2,300V, since the power supply voltage is high, it is necessary to strengthen the load short-circuit withstand capacity. For this purpose, in the Y direction, it is effective to reduce the channel density by using methods such as reducing the width of the emitter formation region ER and increasing the width of the separation region SR. Since this method can be dealt with only by changing the layout of the mask, there is also an advantage that an increase in manufacturing cost can be suppressed.

[0009] However, when the inventors of the present application verified high-breakdown-voltage products, a voltage tail was observed in the waveform of the forward voltage Vce at turn-on, and there were cases where a significant increase in switching loss was observed. In order to identify the cause, the inventors of the present application performed analysis using TCAD and the like. As a result, it was found that in the process of switching, an inversion layer spreads in the p-type base region PB of the separation region SR due to the voltage of the gate electrode GE1. And it was found that sufficient electrons are not supplied near the center of the separation region SR due to the influence of the resistance of this inversion layer. The inventors of the present application found that this shortage of electrons is one of the causes of the above voltage tail.

[0010] The main objective of this invention is to improve the performance of a semiconductor device by suppressing the effect of the resistance of the inversion layer and improving switching losses. Other issues and novel features will become apparent from the description herein and the accompanying drawings. [Means for solving the problem]

[0011] A brief overview of some of the representative embodiments disclosed in this application is as follows:

[0012] A semiconductor device according to one embodiment comprises: a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a pair of first trenches formed within the semiconductor substrate on the upper surface side of the semiconductor substrate and extending in a first direction in a plan view; a pair of first gate insulating films formed inside the pair of first trenches; a pair of first gate electrodes embedded inside the pair of first trenches via the pair of first gate insulating films; a base region of a second conductivity type opposite to the first conductivity type formed within the semiconductor substrate on the upper surface side of the semiconductor substrate; and a first impurity region of the first conductivity type and a second impurity region of the first conductivity type formed within the semiconductor substrate on the upper surface side of the semiconductor substrate. The semiconductor substrate has a first emitter formation region and a second emitter formation region spaced apart from each other in a first direction between the pair of first trenches, and a spaced-out region located between the first emitter formation region and the second emitter formation region. The base region is formed within each of the semiconductor substrates of the first emitter formation region, the second emitter formation region, and the spaced-out region. The first impurity region is formed within the base region of each of the first emitter formation region and the second emitter formation region. The second impurity region is formed within the base region at a first location in the spaced-out region that is in contact with the pair of first trenches, and the second impurity region is connected to the first impurity region of each of the first emitter formation region and the second emitter formation region.

[0013] A semiconductor device according to one embodiment comprises: a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a pair of first trenches formed within the semiconductor substrate on the upper surface side of the semiconductor substrate and extending in a first direction in a plan view; a pair of first gate insulating films formed inside the pair of first trenches; a pair of first gate electrodes embedded inside the pair of first trenches via the pair of first gate insulating films; a base region of a second conductivity type opposite to the first conductivity type formed within the semiconductor substrate on the upper surface side of the semiconductor substrate; and a first impurity region of the first conductivity type and a second impurity region of the first conductivity type formed within the semiconductor substrate on the upper surface side of the semiconductor substrate. The semiconductor substrate has a first emitter formation region and a second emitter formation region spaced apart from each other in a first direction between the pair of first trenches, and a spaced-out region located between the first emitter formation region and the second emitter formation region. The base region is formed within each of the semiconductor substrates of the first emitter formation region, the second emitter formation region, and the spaced-out region. The first impurity region is formed within each of the base regions of the first emitter formation region and the second emitter formation region. The impurity concentration of the base region at a first location in the spaced-out region that is in contact with the pair of first trenches is lower than the impurity concentration of the base region in each of the first emitter formation region and the second emitter formation region.

[0014] A method for manufacturing a semiconductor device according to one embodiment comprises: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) forming a pair of first trenches in the semiconductor substrate on the upper surface side so as to extend in a first direction in a plan view; (c) forming a pair of first gate insulating films inside the pair of first trenches; (d) embedding a pair of first gate electrodes inside the pair of first trenches via the pair of first gate insulating films; (e) forming a base region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate on the upper surface side; and (f) forming a first impurity region of the first conductivity type and a second impurity region of the first conductivity type in the semiconductor substrate on the upper surface side. The semiconductor substrate has a first emitter formation region and a second emitter formation region spaced apart from each other in a first direction between the pair of first trenches, and a spaced-out region located between the first emitter formation region and the second emitter formation region. The base region is formed within each of the semiconductor substrates of the first emitter formation region, the second emitter formation region, and the spaced-out region. The first impurity region is formed within the base region of each of the first emitter formation region and the second emitter formation region. The second impurity region is formed within the base region at a first location in the spaced-out region that is in contact with the pair of first trenches, and the second impurity region is connected to the first impurity region of each of the first emitter formation region and the second emitter formation region. [Effects of the Invention]

[0015] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawing]

[0016] [Figure 1] This is a plan view showing the semiconductor device in Embodiment 1. [Figure 2] This is a plan view of the main components of the semiconductor device in Embodiment 1. [Figure 3]This is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 4] This is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 5] This graph shows the results of a simulation conducted by the inventors of the present invention. [Figure 6] This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 7] This is a cross-sectional view showing the manufacturing process following Figure 6. [Figure 8] This is a cross-sectional view showing the manufacturing process following Figure 7. [Figure 9] This is a cross-sectional view showing the manufacturing process following Figure 8. [Figure 10] This is a cross-sectional view showing the manufacturing process following Figure 9. [Figure 11] This is a cross-sectional view showing the manufacturing process following Figure 10. [Figure 12] This is a plan view of the main parts showing the manufacturing process, following Figure 11. [Figure 13] This is a cross-sectional view showing the manufacturing process following Figure 11. [Figure 14] This is a cross-sectional view showing the manufacturing process following Figure 11. [Figure 15] This is a cross-sectional view showing the manufacturing process, following Figures 12 to 14. [Figure 16] This is a cross-sectional view showing the manufacturing process following Figure 15. [Figure 17] This is a cross-sectional view showing the manufacturing process following Figure 16. [Figure 18] This is a plan view of the main components of a semiconductor device in modified example 1. [Figure 19] This is a cross-sectional view showing a semiconductor device in a modified example (1). [Figure 20] This is a cross-sectional view showing the manufacturing process of a semiconductor device in modified example 1. [Figure 21] This is a plan view of the main components of the semiconductor device in modified example 2. [Figure 22] This is a cross-sectional view showing a semiconductor device in modified example 2. [Figure 23]This is a plan view of the main components of the semiconductor device in Embodiment 2. [Figure 24] This is a cross-sectional view showing a semiconductor device in Embodiment 2. [Figure 25] This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 2. [Figure 26] This is a cross-sectional view showing the manufacturing process following Figure 25. [Figure 27] This is a plan view of the main components of the semiconductor device in Embodiment 3. [Figure 28] This is a cross-sectional view showing a semiconductor device in Embodiment 3. [Figure 29] This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 3. [Figure 30] This is a plan view of the main components of the semiconductor device in Embodiment 4. [Figure 31] This is a cross-sectional view showing the semiconductor device in Embodiment 4. [Figure 32] This is a plan view of the main parts showing the manufacturing process of the semiconductor device in Embodiment 4. [Figure 33] This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 4. [Figure 34] This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 4. [Figure 35] This is a plan view of the main components of the semiconductor device in modified example 3. [Figure 36] This is a cross-sectional view showing the manufacturing process of a semiconductor device in modified example 3. [Figure 37] This is a cross-sectional view showing the manufacturing process following Figure 36. [Figure 38] This is a cross-sectional view showing the manufacturing process following Figure 36. [Figure 39] This is a plan view of the main components of the semiconductor device used in the study example. [Modes for carrying out the invention]

[0017] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0018] Furthermore, the X, Y, and Z directions described in this application intersect and are orthogonal to each other. In this application, the Z direction is described as the vertical direction, height direction, or thickness direction of a structure. Also, expressions such as "plan view" or "planar view" used in this application mean that the surface formed by the X and Y directions is called a "plane," and this "plane" is viewed from the Z direction.

[0019] (Embodiment 1) <Structure of a semiconductor device> The structure of the semiconductor device 100 in Embodiment 1 will be described below with reference to Figures 1 to 4.

[0020] Figure 1 is a plan view showing a semiconductor chip, which is a semiconductor device 100. As shown in Figure 1, most of the semiconductor device 100 is covered by an emitter electrode EE. The gate wiring GW is formed to surround the emitter electrode EE in a plan view.

[0021] Although not shown in the diagram, the emitter electrode EE and gate wiring GW are covered with a protective film such as a polyimide film. Openings are provided in a portion of the protective film on the emitter electrode EE and gate wiring GW, and the areas exposed by these openings become the emitter pad EP and gate pad GP. By connecting external connection members such as bonding wires or clips to the emitter pad EP and gate pad GP, the semiconductor device 100 is electrically connected to other semiconductor chips or wiring boards.

[0022] Figure 2 is a plan view of the main part corresponding to region 1A shown in Figure 1. Region 1A is a cell region where power semiconductor elements such as IGBTs are formed. The IGBT shown in Figure 2 is a GGEE structure IGBT that utilizes the IE effect. The semiconductor device 100 has an active cell AC for performing the main operation of the IGBT and inactive cells IAC other than the active cell AC.

[0023] As shown in Figure 2, the multiple trenches TR extend in the Y direction and are adjacent to each other in the X direction. A gate electrode GE1 is formed inside the trench TR of the active cell AC. A gate electrode GE2 is formed inside the trench TR of the inactive cell IAC.

[0024] The gate electrode GE1 of the active cell AC is electrically connected to the gate wiring GW, supplying the gate potential during IGBT operation. The gate electrode GE2 of the inactive cell IAC is electrically connected to the emitter electrode EE, supplying the emitter potential during IGBT operation. In addition, the base region PB and impurity region CSL of the active cell AC, and the base region PB between the pair of gate electrodes GE2, are electrically connected to the emitter electrode EE via plug PG, supplying the emitter potential during IGBT operation.

[0025] In the inactive cell IAC, a floating region PF is provided between the gate electrode GE1 and the gate electrode GE2. The floating region PF and the base region PB formed within the floating region PF are electrically floating.

[0026] Furthermore, the semiconductor substrate SUB has a plurality of emitter formation regions ER spaced apart in the Y direction between a pair of trenches TR of the active cell AC, and spaced-apart regions SR located between each emitter formation region ER. The n-type impurity regions formed in the emitter formation regions ER become the emitter regions of the IGBT. In Embodiment 1, n-type impurity regions CSL are formed in the emitter formation regions ER.

[0027] The impurity region CSL is also formed in the area of ​​the separated region SR that is in contact with a pair of trenches TR. The impurity region CSL in the separated region SR is connected to the impurity region CSL in the emitter formation region ER. In Embodiment 1, these impurity regions CSL have the same impurity concentration.

[0028] The main feature of Embodiment 1 is that an impurity region CSL is formed in the area of ​​the separated region SR that is in contact with a pair of trenches TR. This feature and its effects will be explained in detail later.

[0029] The width of the emitter formation region ER in the Y direction is, for example, 0.25 μm or more and 2.0 μm or less, and the width of the separation region SR in the Y direction is, for example, 0.25 μm or more and 50 μm or less. Furthermore, it is preferable that the ratio of the widths of these regions in the Y direction is set to "separation region SR / emitter formation region ER = 0.125 to 200".

[0030] Figure 3 is a cross-sectional view along line AA shown in Figure 2, showing the cross-sectional structure of the emitter formation region ER. Figure 4 is a cross-sectional view along line BB shown in Figure 2, showing the cross-sectional structure of the separated region SR.

[0031] As shown in Figures 3 and 4, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface and a lower surface. The semiconductor substrate SUB is made of n-type silicon and has an n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The semiconductor substrate SUB may also be a laminate of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate by epitaxial growth while introducing phosphorus (P). In that case, the n-type silicon layer having a lower impurity concentration than the n-type silicon substrate constitutes the drift region NV.

[0032] On the lower surface of the semiconductor substrate SUB, an n-type field stop region (impurity region) NS is formed within the semiconductor substrate SUB. The field stop region NS is provided to prevent the depletion layer extending from the pn junction on the upper surface of the semiconductor substrate SUB from reaching the p-type collector region PC during IGBT turn-off.

[0033] On the underside of the semiconductor substrate SUB, a p-type collector region (impurity region) PC is formed within the semiconductor substrate SUB. The collector region PC is located below the field stop region NS.

[0034] A collector electrode CE is formed beneath the lower surface of the semiconductor substrate SUB. The collector electrode CE is electrically connected to the collector region PC and supplies the collector potential to the collector region PC. The collector electrode CE is either a single-layer metal film such as an Au film, Ni film, Ti film, or AlSi film, or a multilayer metal film formed by appropriately stacking these.

[0035] On the upper surface of the semiconductor substrate SUB, multiple trenches TR are formed within the substrate SUB. The depth of the trenches TR is, for example, 2 μm or more and 5 μm or less. A gate insulating film GI is formed inside the trenches TR. The gate electrodes GE1 and GE2 are embedded inside the trenches TR via the gate insulating film GI. The gate insulating film GI is an insulating film, for example, a silicon oxide film. The gate electrodes GE1 and GE2 are conductive films, for example, polycrystalline silicon films into which n-type impurities have been introduced. The thickness of the gate insulating film GI is, for example, 70 nm or more and 150 nm or less.

[0036] On the upper surface of the semiconductor substrate SUB of the active cell AC, a hole barrier region (impurity region) NHB, a p-type base region (impurity region) PB, and an n-type impurity region CSL are formed within the semiconductor substrate SUB between a pair of trenches TR (a pair of gate electrodes GE1).

[0037] The base region PB is formed within the hole barrier region NHB of the emitter formation region ER and the separation region SR. The impurity region CSL is formed within the base region PB of the emitter formation region ER. In addition, the impurity region CSL is also formed within the base region PB at the location in contact with a pair of trenches TR in the separation region SR. The base region PB is formed to be shallower than the depth of each of the trenches TR and the hole barrier region NHB. The impurity region NE is formed to be shallower than the depth of the base region PB.

[0038] On the upper surface of the inactive cell IAC, a hole barrier region NHB and a base region PB are formed in the semiconductor substrate SUB between a pair of trenches TR (a pair of gate electrodes GE2). The p-type base region PB is formed within the hole barrier region NHB.

[0039] Furthermore, a p-type floating region (impurity region) PF and a base region PB are formed in the semiconductor substrate SUB between the gate electrode GE1 and the gate electrode GE2. The p-type base region PB is formed within the floating region PF.

[0040] The floating region PF and the base region PB formed within the floating region PF are not electrically connected to the gate wiring GW and the emitter electrode EE, and are electrically floating. To improve the junction withstand voltage, the floating region PF is formed to a depth greater than the bottom of the trench TR and is formed to cover the bottom of the trench TR.

[0041] An interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB, covering the trench TR. The interlayer insulating film IL is, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 600 nm or more and 1500 nm or less.

[0042] In the active cell AC, the pores CH penetrate the interlayer insulating film IL and the impurity region CSL, and reach the interior of the base region PB. Furthermore, the pores CH are in contact with the base region PB in the emitter formation region ER and the separation region SR, and are in contact with the impurity region CSL in the emitter formation region ER. In the inactive cell IAC, the pores CH reach the interior of the base region PB and are in contact with the base region PB.

[0043] Above the pore CH, the interlayer insulating film IL recedes. That is, the size of the opening of a pore CH located above the upper surface of the semiconductor substrate SUB is larger than the size of the opening of a pore CH located within the semiconductor substrate SUB. As a result, a portion of the upper surface of the impurity region CSL is exposed from the interlayer insulating film IL. Consequently, the emitter electrode EE not only contacts the side surface of the impurity region CSL within the pore CH, but also contacts a portion of the upper surface of the impurity region CSL. This reduces the contact resistance between the emitter electrode EE and the impurity region CSL.

[0044] In the active cell AC and inactive cell IAC, a p-type high-concentration diffusion region (impurity region) PR is formed in the base region PB surrounding the bottom of the pore CH. The high-concentration diffusion region PR is provided to reduce the contact resistance with the emitter electrode EE and to prevent latch-up.

[0045] A plug PG is embedded inside the pore CH. The plug PG includes a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film is, for example, a tungsten film.

[0046] Although not shown in the diagram, holes CH are also formed on parts of gate electrodes GE1 and GE2, and plugs PG are formed inside these holes CH.

[0047] An emitter electrode EE is formed on the interlayer insulating film IL. The emitter electrode EE is electrically connected to the impurity region CSL, the base region PB, the high-concentration diffusion region PR, and the gate electrode GE2 via a hole CH (plug PG), supplying them with emitter potential. Although not shown in the diagram, a gate wiring GW is also formed on the interlayer insulating film IL using the same manufacturing process as the emitter electrode EE. The gate wiring GW is electrically connected to the gate electrode GE1 via a hole CH (plug PG), supplying the gate potential to the gate electrode GE1.

[0048] Such emitter electrode EE and gate wiring GW include a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a TiW film. The conductive film is, for example, an aluminum alloy film doped with copper or silicon. The aluminum alloy film is the main film of the emitter electrode EE and gate wiring GW and is sufficiently thicker than the TiW film.

[0049] Furthermore, as shown in Figure 3, the impurity region CSL of the emitter formation region ER is in contact with the pore CH, while as shown in Figure 4, the impurity region CSL of the separation region SR is physically separated from the pore CH. The impurity region CSL of the separation region SR is indirectly supplied with emitter potential from the emitter electrode EE via the impurity region CSL and pore CH of the emitter formation region ER.

[0050] The following are examples of impurity concentrations in each impurity region.

[0051] The impurity concentration in the drift region NV is, for example, 1 × 10⁻⁶. 13 cm -3 The above and 2 × 10 14 cm -3 The following applies: The impurity concentration in the field stop region (NS) is higher than the impurity concentration in the drift region (NV), for example, 5 × 10⁻⁶. 16 cm -3 The above and 5 x 10 17 cm -3The following holds. The impurity concentration of the hole barrier region NHB is higher than the impurity concentration of the drift region NV, for example, 2×10 16 cm -3 or more and 1×10 17 cm -3 or less.

[0052] The impurity concentration of the collector region PC is 1×10 17 cm -3 or more and 1×10 21 cm -3 or less. The impurity concentration of the floating region PF is 1×10 15 cm -3 or more and 1×10 16 cm -3 or less. The impurity concentration of the base region PB is higher than the impurity concentration of the floating region PF, 1×10 16 cm -3 or more and 1×10 18 cm -3 or less. The impurity concentration of the high-concentration diffusion region PR is higher than the impurity concentration of the base region PB, 1×10 18 cm -3 or more and 1×10 21 cm -3 or less.

[0053] In Embodiment 1, the impurity concentration of the impurity region CSL is higher than the impurity concentration of the drift region NV and lower than the impurity concentration of the hole barrier region NHB, for example, 1×10 15 cm -3 or more and 1×10 16 cm -3 or less. The impurity concentration of the impurity region CSL is set to a concentration at which an ohmic contact with the plug PG is established.

[0054] <Main features of Embodiment 1> As explained in the above problem, in the example shown in Figure 39, during the switching process, the inversion layer expands in the base region PB of the separated region SR due to the voltage of the gate electrode GE1. However, due to the resistance of this inversion layer, sufficient electrons are not supplied to the central part of the separated region SR, and this electron deficiency is a factor in the increase of switching losses.

[0055] In Embodiment 1, an impurity region CSL is formed in the area of ​​the separated region SR that is in contact with a pair of trenches TR. Therefore, a diffusion layer resistance corresponding to the width of the separated region SR exists between each emitter formation region ER. As a result, electrons are more easily supplied from this diffusion layer resistance to the area near the center of the separated region SR, and the resistance of the inversion layer can be reduced. Consequently, switching losses can be improved, and the performance of the semiconductor device 100 can be enhanced.

[0056] Figure 5 is a graph showing the results of a simulation performed by the inventors of the present invention, comparing the example under consideration with Embodiment 1. The horizontal axis shows the forward saturation current Ic(sat) when the forward voltage Vce is 5V, and the vertical axis shows the switching loss at turn-on.

[0057] As shown in Figure 5, the switching loss is improved in Embodiment 1 compared to the study example. For example, when comparing with a forward saturation current Ic(sat) of 300A, the switching loss in Embodiment 1 is improved by about 21% compared to the study example.

[0058] Furthermore, while the impurity region CSL makes ohmic contact with the plug PG, the impurity region CSL in the separation region SR is separated from the pore CH. Therefore, the discharge of holes due to parasitic PMOS operation in the separation region SR is not hindered. By appropriately adjusting the width and impurity concentration of the impurity region CSL in the separation region SR, it is possible to adjust the appropriate forward saturation current Ic(sat).

[0059] <Manufacturing method for semiconductor devices> The following describes each manufacturing step included in the manufacturing method of the semiconductor device 100 in Embodiment 1, using Figures 6 to 17.

[0060] As shown in Figure 6, first, an n-type semiconductor substrate SUB having an upper surface and a lower surface is prepared. As described above, in this case, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The drift region NV may also be a low-concentration n-type semiconductor layer grown on a high-concentration n-type silicon substrate while introducing phosphorus (P) by epitaxial growth. In this application, a laminate consisting of such an n-type silicon substrate and an n-type semiconductor layer will also be described as a semiconductor substrate SUB.

[0061] Next, a floating region PF and a hole barrier region NHB are formed within the semiconductor substrate SUB using photolithography and ion implantation techniques. For ion implantation of the floating region PF, for example, boron (B) is used as an impurity. For ion implantation of the hole barrier region NHB, for example, phosphorus (P) is used as an impurity. Multiple ion implantations with different energy and dose conditions are performed for the formation of each of the floating region PF and the hole barrier region NHB. Next, the semiconductor substrate SUB is heat-treated to activate the impurities contained in the floating region PF and the hole barrier region NHB. This heat treatment is performed, for example, in an atmosphere filled with an inert gas such as nitrogen gas, at a temperature of 900°C or higher and 1000°C or lower, for 25 minutes or more and 40 minutes or less.

[0062] As shown in Figure 7, trenches TR are formed in the semiconductor substrate SUB on the upper surface side. To form the trenches TR, first, a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB, for example, by CVD. Next, a resist pattern having openings is formed on the silicon oxide film. Then, the silicon oxide film is patterned by anisotropic etching using the resist pattern as a mask, forming a hard mask HM. Finally, the resist pattern is removed by ashing.

[0063] Next, trenches TR are formed in the semiconductor substrate SUB by performing anisotropic etching using the hard mask HM as a mask. Subsequently, the hard mask HM is removed by wet etching using, for example, a solution containing hydrofluoric acid.

[0064] As shown in Figure 8, a sacrificial oxide film IF1 is formed inside the trench TR and on the upper surface of the semiconductor substrate SUB. This removes the damaged layer formed on the semiconductor substrate SUB. Subsequently, the sacrificial oxide film IF1 is removed by wet etching using, for example, a solution containing hydrofluoric acid. The sacrificial oxide film IF1 is formed by thermal oxidation treatment of the semiconductor substrate SUB. This thermal oxidation treatment is carried out, for example, in an atmosphere filled with oxygen gas, at a temperature of 1000°C or higher and 1200°C or lower, for 50 minutes or more and 70 minutes or less. This causes impurities contained in the floating region PF and the hole barrier region NHB to diffuse.

[0065] As shown in Figure 9, the semiconductor substrate SUB is subjected to heat treatment. This heat treatment is carried out in an atmosphere filled with an inert gas, such as nitrogen gas, at a temperature of 1000°C or higher and 1200°C or lower, for a period of 80 minutes or higher and 120 minutes or lower. This heat treatment further diffuses impurities contained in the floating region PF and the hole barrier region NHB, so that the floating region PF covers the bottom of the trench TR.

[0066] Next, a gate insulating film GI is formed inside the trench TR and on the upper surface of the semiconductor substrate SUB by thermal oxidation. Then, a conductive film CF1 is formed inside the trench TR and on the upper surface of the semiconductor substrate SUB, for example by CVD, so as to fill the inside of the trench TR through the gate insulating film GI. The conductive film CF1 is, for example, a polycrystalline silicon film into which n-type impurities have been introduced. Note that the gate insulating film GI may be a laminated film of a relatively thin silicon oxide film formed by thermal oxidation and a relatively thick silicon oxide film formed by CVD.

[0067] As shown in Figure 10, first, the conductive film CF1 formed on the outside of the trench TR is removed by anisotropic etching. The conductive film CF1 that was embedded inside the trench TR remains as gate electrodes GE1 and GE2. Next, the gate insulating film GI formed on the outside of the trench TR is removed by isotropic etching.

[0068] As shown in Figure 11, a p-type base region PB is formed on the upper surface of the semiconductor substrate SUB (floating region PF and hole barrier region NHB) using photolithography and ion implantation techniques. For ion implantation of the base region PB, boron (B), for example, is used as a p-type impurity.

[0069] Figures 12 to 14 show the manufacturing process for forming the n-type impurity region CSL. First, as shown in Figures 13 and 14, a resist pattern RP1 is formed on the upper surface of the semiconductor substrate SUB. The resist pattern RP1 has a pattern that opens up the entire emitter formation region ER and the portion of the separated region SR that is in contact with the trench TR.

[0070] Next, by performing ion implantation using the resist pattern RP1 as a mask, n-type impurities, such as arsenic (As) ions, are implanted into the semiconductor substrate SUB in the emitter formation region ER and in the semiconductor substrate SUB at the location of the separation region SR that is in contact with the trench TR. This forms a planar impurity region CSL as shown in Figure 12.

[0071] Next, the resist pattern RP1 is removed by ashing. Then, the semiconductor substrate SUB is subjected to heat treatment to activate the impurities contained in the base region PB and the impurity region CSL, respectively. The heat treatment for activating the impurities is carried out in an atmosphere filled with an inert gas such as nitrogen gas, at a temperature of 900°C or higher and 1000°C or lower, for a period of 30 seconds or higher and 50 seconds or lower.

[0072] Furthermore, the order in which the base region PB is formed and the impurity region CSL is formed does not matter.

[0073] As shown in Figure 15, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB, for example by CVD, so as to cover the trench TR. The interlayer insulating film IL is, for example, a silicon oxide film.

[0074] As shown in Figure 16, pores CH are formed in the interlayer insulating film IL and semiconductor substrate SUB in the active cell AC by photolithography and anisotropic etching, penetrating the impurity region CSL and reaching the interior of the base region PB. Simultaneously, pores CH are also formed in the interlayer insulating film IL and semiconductor substrate SUB in the inactive cell IAC. Although not shown in the figure, pores CH are also formed on parts of the gate electrodes GE1 and GE2.

[0075] Next, a p-type high-concentration diffusion region PR is formed within the base region PB at the bottom of the pore CH using photolithography and ion implantation techniques. For ion implantation of the high-concentration diffusion region PR, for example, boron difluoride (BF2) is used as a p-type impurity. Next, the interlayer insulating film IL is recessed by isotropic etching. As a result, the opening width of the pore CH located on the upper surface of the semiconductor substrate SUB becomes larger than the opening width of the pore CH located inside the semiconductor substrate SUB.

[0076] As shown in Figure 17, a plug PG is formed inside the pore CH, and an emitter electrode EE is formed on the interlayer insulating film IL. First, a barrier metal film is formed inside the pore CH and on the interlayer insulating film IL. For example, the barrier metal film can be formed by forming a titanium film inside the pore CH and on the interlayer insulating film IL by sputtering, and then forming a titanium nitride film on the titanium film by sputtering. Next, a conductive film, for example, made of tungsten, is formed on the barrier metal film, for example, by CVD, so as to fill the inside of the pore CH. Next, the conductive film and the barrier metal film formed outside the pore CH are removed by anisotropic etching. This forms a plug PG so as to fill the inside of the pore CH.

[0077] Next, a TiW film is formed on the interlayer insulating film IL, for example by sputtering, and an aluminum alloy film is formed on the TiW film, for example by sputtering. Then, the emitter electrode EE is formed by patterning the TiW film and the aluminum alloy film using photolithography and anisotropic etching. The gate wiring GW is also formed on the interlayer insulating film IL in the same process as the formation of the emitter electrode EE.

[0078] Subsequently, the structure shown in Figures 3 and 4 is obtained through the following manufacturing process. First, the underside of the semiconductor substrate SUB is polished as needed. Next, an n-type field stop region NS and a p-type collector region PC are formed by ion implantation from the underside of the semiconductor substrate SUB. After these ion implantations, laser annealing is performed to activate the impurities contained in the field stop region NS and the collector region PC. Next, a metal film, such as an Au film, Ni film, Ti film, or AlSi film, is formed beneath the underside of the semiconductor substrate SUB, for example, by sputtering. This metal film becomes the collector electrode CE. The collector electrode CE may be a laminated film formed by appropriately stacking the above-mentioned metal films.

[0079] In Embodiment 1, the impurity region CSL of the emitter formation region ER functions as the emitter region of the IGBT. Since the impurity region CSL of the emitter formation region ER and the impurity region CSL of the separation region SR are formed in the same manufacturing process, there is no need to add a new manufacturing process, and the increase in manufacturing costs can be suppressed.

[0080] For example, in the example study (Figure 39), the impurity region NE functions as the emitter region of the IGBT. However, by simply changing the mask used to form the impurity region NE in the example study, the impurity region CSL of Embodiment 1 can be formed. Therefore, an increase in manufacturing costs can be suppressed.

[0081] (Variation 1) Figures 18 and 19 show the semiconductor device 100 in Modification 1 of Embodiment 1. As shown in Figures 18 and 19, in Modification 1, an n-type impurity region NE is formed in the emitter formation region ER. The impurity concentration in the impurity region NE is higher than the impurity concentration in the impurity region CSL, for example, 1 × 10⁻⁶ 18 cm -3 The above and 1 × 10 21 cm -3 The following applies: The impurity concentration in the impurity region NE is set to a concentration that allows ohmic contact with plug PG to occur.

[0082] In the emitter formation region ER, if the contact resistance between the impurity region CSL and the plug PG is high, the contact resistance can be reduced by providing such a high-concentration impurity region NE.

[0083] Figure 20 shows the manufacturing process for forming the impurity region NE. After the manufacturing processes shown in Figures 12 to 14, a resist pattern RP2 is formed on the upper surface of the semiconductor substrate SUB, as shown in Figure 20. The resist pattern RP2 has a pattern that opens up the entire emitter formation region ER.

[0084] Next, ion implantation is performed using the resist pattern RP2 as a mask to implant n-type impurities, such as arsenic (As) ions, into the semiconductor substrate SUB of the emitter formation region ER. This forms a planar impurity region NE as shown in Figure 20. Subsequently, the resist pattern RP2 is removed by ashing.

[0085] The impurity region CSL includes impurities ion-implanted in the manufacturing processes shown in Figures 12 to 14. The impurity region NE includes impurities ion-implanted in the manufacturing processes shown in Figures 12 to 14 and impurities ion-implanted in the manufacturing process shown in Figure 20. Finally, the amount of impurities ion-implanted in Figure 20 is adjusted so that the impurity concentration in the impurity region NE falls within the above values.

[0086] The order in which the base region PB, the impurity region CSL, and the impurity region NE are formed does not matter. Furthermore, the heat treatment for activating the impurities is performed after these regions have been formed.

[0087] (Modification 2) Figure 21 shows a semiconductor device 100 in a modified example 2 of Embodiment 1. As shown in Figure 21, in Modified Example 2, an n-type impurity region CSL is formed within the base region PB at the location of the pore CH in the separated region SR. This impurity region CSL is connected to the impurity region CSL of the emitter formation region ER, similar to the impurity region CSL at the location of the trench TR.

[0088] Furthermore, the impurity region CSL in contact with the pore CH and the impurity region CSL in contact with the trench TR are separated from each other. Therefore, the ejection of holes by parasitic PMOS operation in the separated region SR is not hindered.

[0089] To form an impurity region CSL in contact with such a pore CH, this can be achieved by changing the mask used in Figures 12 to 14. An opening pattern is provided in the resist pattern RP3 that passes near the center of the separated region SR and extends in the Y direction. If the opening width of this opening pattern encompasses the opening width of the pore CH, an impurity region CSL as shown in Figure 21 can be formed.

[0090] In addition, in Modification 2, as in Modification 1, a high-concentration impurity region NE may be formed in the emitter formation region ER.

[0091] (Embodiment 2) The semiconductor device 100 and its manufacturing method in Embodiment 2 will be described below with reference to Figures 23 to 26. In the following description, the differences from Embodiment 1 will be mainly explained, and points that overlap with Embodiment 1 will not be explained.

[0092] In Embodiment 1, an impurity region CSL was formed using a resist pattern RP1. Therefore, if a misalignment occurs in the formation position of the resist pattern RP1, the width of the impurity region CSL in the X direction changes, resulting in a problem of changes in the resistance value as a diffusion layer resistance. Embodiment 2 provides a technique that can suppress such changes in resistance value.

[0093] As shown in Figure 25, in Figure 7, a step of forming an impurity region CSL by oblique ion implantation is added between the step of forming the hard mask HM and the step of forming the trench TR. That is, arsenic (As) ions, for example, are implanted as n-type impurities from an angle inclined with respect to the normal to the upper surface of the semiconductor substrate SUB. Here, the thickness of the hard mask HM and the implantation energy are adjusted so that the ions do not pass through the hard mask HM and reach the semiconductor substrate SUB. Subsequently, as shown in Figure 26, a trench TR is formed in the semiconductor substrate SUB.

[0094] By performing oblique ion implantation using a hard mask HM as a mask, impurity regions CSL can be self-aligned in the areas in contact with the trenches TR. Therefore, problems caused by misalignment of the resist pattern RP1 are avoided, and variations in the width of the impurity regions CSL can be suppressed. Furthermore, since the trenches TR are also formed self-aligned using the same hard mask HM as a mask, the positional relationship between the trenches TR and the impurity regions CSL is less likely to change.

[0095] Furthermore, as shown in Figure 26, in Embodiment 2, it is difficult to form an impurity region CSL across the entire emitter formation region ER. Therefore, in order to form the emitter region of the IGBT, it is necessary to perform ion implantation as described in Figure 20 of Modification 1. This allows for the formation of an impurity region NE in the emitter formation region ER, as shown in Figures 23 and 24.

[0096] In Embodiment 2, the resist pattern is not used when forming the impurity region CSL, and the resist pattern RP2 is used when forming the impurity region NE. Therefore, the number of masks is the same in Embodiment 1 and Embodiment 2, which helps to suppress increases in manufacturing costs. Furthermore, Embodiment 2 can reduce the number of masks compared to Modification 1 because there is no mask for the impurity region CSL.

[0097] As shown in Figures 23 and 24, in Embodiment 2, impurity regions CSL are formed without using a resist pattern, so impurity regions CSL are also formed in a part of the base region PB within the floating region PF. However, since the floating region PF is electrically floating, these impurity regions CSL are also electrically floating. Therefore, the characteristics of the IGBT are not particularly affected by these impurity regions CSL.

[0098] Furthermore, impurity regions CSLs are formed within the base region PB between the pair of gate electrodes GE2. However, since these impurity regions CSLs are physically separated from the pore CH, they are electrically floating. These impurity regions CSLs do not particularly affect the properties of the IGBT.

[0099] (Embodiment 3) The semiconductor device 100 and its manufacturing method in Embodiment 3 will be described below with reference to Figures 27 to 29. In the following description, the differences from Embodiment 1 will be mainly explained, and points that overlap with Embodiment 1 will not be explained.

[0100] In Embodiment 3, the impurity region CSL is formed not only in the area of ​​the separated region SR that is in contact with the pair of trenches TR, but also throughout the semiconductor substrate SUB (within the base region PB) of the active cell AC and inactive cell IAC. However, in Embodiment 3, the impurity concentration of the impurity region CSL is set to a concentration such that ohmic contact with the plug PG does not occur. The impurity concentration of the impurity region CSL is, for example, 1 × 10⁻⁶ 12 / cm 3 The above and 1 × 10 14 / cm 3 The following applies:

[0101] Even low-concentration impurity regions (CSL) like those in Embodiment 3 can function as diffusion layer resistors, making it easier for electrons to be supplied to the central area of ​​the intercalated regions (SR). As a result, switching losses can be improved, and the performance of the semiconductor device 100 can be enhanced.

[0102] In Embodiment 3, the formation of the impurity region CSL can be achieved by performing ion implantation into the semiconductor substrate SUB of the active cell AC and inactive cell IAC without forming the resist pattern RP1 in the manufacturing process shown in Figures 12 to 14. Therefore, the number of masks can be reduced, and manufacturing costs can be suppressed compared to Embodiment 1. However, since the impurity region CSL is of a lower concentration than in Embodiment 1, Embodiment 1 is superior to Embodiment 3 in terms of improving electron supply and switching loss.

[0103] In Embodiment 3, an impurity region CSL is formed in a part of the base region PB within the floating region PF, but for the same reasons as in Embodiment 2, the characteristics of the IGBT are not particularly affected. Furthermore, an impurity region CSL is also formed in the base region PB between the pair of gate electrodes GE2, but since the impurity region CSL does not make ohmic contact with the plug PG, the characteristics of the IGBT are not particularly affected by these impurity regions CSL either.

[0104] Furthermore, since the impurity region CSL does not make ohmic contact with the plug PG, in Embodiment 3, ion implantation as described in Figure 20 of Modification 1 is necessary to form the emitter region of the IGBT. This allows the impurity region NE to be formed in the emitter formation region ER, as shown in Figures 27 and 28.

[0105] (Embodiment 4) The semiconductor device 100 and its manufacturing method in Embodiment 4 will be described below with reference to Figures 30 to 34. Note that the following description will mainly focus on the differences from Embodiment 1, and will omit explanations of points that overlap with Embodiment 1.

[0106] In Embodiment 1, an n-type impurity region CSL was formed as the diffusion layer resistor for electron supply, but in Embodiment 4, a strong inversion layer resistor with a similar function is formed by changing the configuration of the p-type base region PB.

[0107] As shown in Figures 30 and 31, in Embodiment 4 as well, the p-type base region PB is formed within the semiconductor substrate SUB of each emitter formation region ER and separation region SR. However, the impurity concentration of the base region PB in the area of ​​the separation region SR that is in contact with the trench TR is lower than the impurity concentration of the base region PB in each emitter formation region ER. The base region PB in such areas is shown as the low-concentration region PBa. The impurity concentration of the low-concentration region PBa is, for example, 1 × 10⁻⁶ 12 / cm 3 The above and 1 × 10 14 / cm 3 The following applies:

[0108] In Embodiment 4, the high-concentration n-type impurity region NE described in Modification 1 is used as the emitter region of the IGBT. Also, in the separated region SR, the low-concentration region PBa is physically separated from the pore CH.

[0109] As described above, the configuration of the base region PB results in a threshold voltage in the separation region SR being lower than the threshold voltage in the emitter formation region ER. During turn-on, when a channel is formed in the base region PB of the emitter formation region ER, a strong inversion layer is formed in the separation region SR by the low-concentration region PBa. As a result, the resistance value at the point of contact with the trench TR is reduced, making it easier for electrons to be supplied to the vicinity of the center of the separation region SR, and improving switching losses.

[0110] As shown in the graph in Figure 5, it can be seen that the switching loss is improved in Embodiment 4 compared to the study example. For example, when comparing with a forward saturation current Ic(sat) of 300A, the switching loss in Embodiment 4 is improved by about 37% compared to the study example. Thus, in Embodiment 4 as well, the switching loss can be improved and the performance of the semiconductor device 100 can be enhanced.

[0111] Using Figures 32 to 34, the manufacturing process for forming the base region PB and the low-concentration region PBa in Embodiment 4 will be explained. The manufacturing process in Figures 32 to 34 is performed instead of the manufacturing process in Figure 11.

[0112] As shown in Figures 32 to 34, in Embodiment 4, first, a resist pattern RP3 is formed on the upper surface of the semiconductor substrate SUB so as to cover the portion of the separated region SR that is in contact with the trench TR. Next, using the resist pattern RP3 as a mask, p-type impurities are ion-implanted into the semiconductor substrate SUB of each emitter formation region ER and into the semiconductor substrate SUB of the separated region SR excluding the above-mentioned portion. The p-type impurities are, for example, boron (B). This forms the base region PB. After that, the resist pattern RP3 is removed by ashing.

[0113] In this state, an n-type hole barrier region NHB exists between the base region PB and the trench TR in the separated region SR. Subsequently, when heat treatment is performed to activate impurities, the p-type impurities in the separated region SR diffuse to the area in contact with the trench TR, forming a low-concentration region PBa.

[0114] Furthermore, the portion in contact with the trench TR does not necessarily have to be p-type after the above heat treatment, and may be a very thin n-type. For example, the portion in contact with the trench TR may be an impurity region with a concentration such that ohmic contact with the plug PG does not occur, such as the impurity region CSL in Embodiment 3.

[0115] (Variation 3) Figure 35 shows the configuration of the base region in Modification 3 of Embodiment 4. As shown in Figure 35, in Modification 3, the base region PB of each emitter formation region ER is the same as in Embodiment 4, but a low-concentration region PBb with a lower impurity concentration than the base region PB is formed throughout the entire separation region SR. The impurity concentration of the low-concentration region PBb is, for example, 1 × 10⁻⁶ 12 / cm 3 The above and 1 × 10 14 / cm 3 The following applies:

[0116] In other words, the overall impurity concentration in the base region of the separated region SR, not just in the area in contact with the trench TR, is lower than the impurity concentration in the base region of each emitter formation region ER. In the modified example 3, the switching loss can be improved to the same extent as in the embodiment 4.

[0117] Using Figures 36 to 38, the manufacturing process for forming the base region PB and the low-concentration region PBb in Modification Example 3 will be explained. The manufacturing process in Figures 36 to 38 is performed instead of the manufacturing process in Figure 11.

[0118] As shown in Figure 36, in Modification 3, first, p-type impurities are ion-implanted into the semiconductor substrate SUB of the active cell AC and inactive cell IAC to form a low-concentration region PBb. The p-type impurities are, for example, boron (B).

[0119] As shown in Figures 37 and 38, first, a resist pattern RP4 is formed on the upper surface of the semiconductor substrate SUB so as to cover the separated region SR. Next, using the resist pattern RP4 as a mask, p-type impurities are ion-implanted into the semiconductor substrate SUB of each emitter formation region ER. The p-type impurities are, for example, boron (B). This forms the base region PB. Subsequently, the resist pattern RP4 is removed by ashing. Note that the base region PB is also formed in the semiconductor substrate SUB of the inactive cell IAC.

[0120] The base region (low-concentration region PBb) of the separated region SR contains impurities ion-implanted in the manufacturing process shown in Figure 38. The base region PB of each emitter formation region ER contains impurities ion-implanted in the manufacturing process shown in Figure 38 and impurities ion-implanted in the manufacturing process shown in Figure 39. Finally, the amount of impurities implanted by ion implantation in Figure 39 is adjusted so that the impurity concentration of the base region PB of each emitter formation region ER is approximately the same as the impurity concentration of the base region PB in Embodiment 1.

[0121] In Embodiment 4, a low-concentration region PBb is formed using the resist pattern RP3. However, if a misalignment occurs in the formation position of the resist pattern RP3, the width of the hole barrier NHB covered by the resist pattern RP3 in the separated region SR will fluctuate. This results in a change in the width of the low-concentration region PBb in the X direction, which in turn causes a change in the resistance value as a strong inversion layer.

[0122] In Modification 3, a resist pattern RP4 is used. The edges of the resist pattern RP4 only need to be located on the gate insulating film GI or the gate electrode GE1 in the X direction, and can be positioned with a relatively large margin. Therefore, misalignment in the X direction can be addressed within the margin.

[0123] In the Y direction, if one end of the resist pattern RP4 is shifted, the other end of the resist pattern RP4 will also be shifted in the same direction. In other words, even if a shift occurs in the Y direction to match the formation position of the resist pattern RP4, the width of the low-concentration region PBb in the separated region SR does not change. Therefore, according to Modification 3, fluctuations in the width of the low-concentration region PBb can be suppressed in both the X and Y directions.

[0124] Although the present invention has been specifically described above based on embodiments, the present invention is not limited to these embodiments and can be modified in various ways without departing from its essence.

[0125] For example, in the above embodiment, the case in which the IGBT has a GGEE structure was illustrated, but the IGBT may also have a GGEEs structure in which the GGEE structure is shrunk. In the GGEE structure, the width between the pair of gate electrodes GE1 is approximately the same as the width between the pair of gate electrodes GE2. In the GGEEs structure, the width between the pair of gate electrodes GE2 is smaller than the width between the pair of gate electrodes GE1.

[0126] Some of the details described in the above embodiment are described below.

[0127] [Note 1] (a) A step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, (b) A step of forming a pair of first trenches within the semiconductor substrate on the upper surface side of the semiconductor substrate so as to extend in a first direction in a plan view, (c) A step of forming a pair of first gate insulating films inside the pair of first trenches, (d) A step of embedding a pair of first gate electrodes inside the pair of first trenches via the pair of first gate insulating films, (e) A step of forming a base region of a second conductivity type opposite to the first conductivity type within the semiconductor substrate on the upper surface side of the semiconductor substrate. (f) A step of forming a first impurity region of the first conductivity type within the semiconductor substrate on the upper surface side of the semiconductor substrate. Equipped with, The semiconductor substrate has a first emitter formation region and a second emitter formation region that are spaced apart from each other in the first direction between the pair of first trenches, and a spaced-apart region located between the first emitter formation region and the second emitter formation region. The base region is formed within the semiconductor substrate of the first emitter formation region, the second emitter formation region, and the separation region, The first impurity region is formed within the base region of the first emitter formation region and the second emitter formation region, A method for manufacturing a semiconductor device, wherein the impurity concentration of the base region at a first location in the separated region that is in contact with the pair of first trenches is lower than the impurity concentration of the base region in each of the first emitter formation region and the second emitter formation region.

[0128] [Note 2] In the method for manufacturing a semiconductor device described in Appendix 1 above, (g) A step of forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the pair of first trenches, (h) A step of forming holes in the interlayer insulating film and the semiconductor substrate so as to penetrate the first impurity region and reach the interior of the base region. (i) A step of forming an emitter electrode on the interlayer insulating film, Furthermore, The base region and the first impurity region are electrically connected to the emitter electrode via the holes. A method for manufacturing a semiconductor device, wherein the base region at the first location is physically separated from the hole.

[0129] [Note 3] In the method for manufacturing a semiconductor device described in Appendix 2 above, The impurity concentration in the base region of each of the first emitter formation region and the second emitter formation region is 1 × 10⁻⁶ 17 / cm 3 The above and 1 × 10 18 / cm 3 The following: The impurity concentration in the base region at the first location is 1 × 10⁻⁶ 12 / cm 3 The above and 1 × 10 14 / cm 3 The following is a method for manufacturing a semiconductor device.

[0130] [Note 4] In the method for manufacturing a semiconductor device described in Appendix 1 above, The aforementioned step (e) is, (e1) A step of ion implanting an impurity of the second conductivity type into the semiconductor substrate in each of the first emitter formation region and the second emitter formation region, and into the semiconductor substrate in the separated region excluding the first location. (e2) A step of performing heat treatment on the semiconductor substrate, It has, A method for manufacturing a semiconductor device, wherein, by the heat treatment, a portion of the impurities in the separated region ion-implanted in step (f1) diffuse to the first location.

[0131] [Note 5] In the method for manufacturing a semiconductor device described in Appendix 1 above, The aforementioned step (e) is, (e3) A step of ion implanting an impurity of the second conductivity type into the semiconductor substrate of each of the first emitter formation region, the second emitter formation region, and the separation region. (e4) A step of ion implanting the second conductivity type impurity into the semiconductor substrate of the first emitter formation region and the second emitter formation region, The base region of the separated region contains impurities ion-implanted in step (e3), The base region of each of the first emitter formation region and the second emitter formation region includes the impurity ion-implanted in step (e3) and the impurity ion-implanted in step (e4), A method for manufacturing a semiconductor device, wherein the total impurity concentration of the base region in the separated region is lower than the impurity concentration of the base region in each of the first emitter formation region and the second emitter formation region. [Explanation of Symbols]

[0132] 100 Semiconductor Equipment 1A area (cell area) AC Active Cell CE collector electrode CF1 conductive film CH hole CSL impurity region EE emitter electrode EP Emitter Pad ER emitter formation region GE1, GE2 gate GI gate insulating film GP Gate Pad GW gate wiring HM Hard Mask IAC Inactive Cell IF1 Sacrificial Oxide Film IL interlayer film NE impurity region NHB Hole Barrier Region NS Field Stop Area NV drift region PB Base Area PBa, PBb low concentration area PC collector area PF Floating Area PG Plug PR High-concentration diffusion area RP1~RP4 Resist Pattern SR separation area SUB Semiconductor Substrate TR Trench

Claims

1. A first-type conductive semiconductor substrate having an upper surface and a lower surface, On the upper surface side of the semiconductor substrate, a pair of first trenches are formed within the semiconductor substrate and extend in a first direction in a plan view, A pair of first gate insulating films formed inside the pair of first trenches, A pair of first gate electrodes embedded inside the pair of first trenches via the pair of first gate insulating films, On the upper surface side of the semiconductor substrate, a base region of a second conductivity type opposite to the first conductivity type is formed within the semiconductor substrate, On the upper surface side of the semiconductor substrate, a first impurity region of the first conductivity type and a second impurity region of the first conductivity type formed within the semiconductor substrate, Equipped with, The semiconductor substrate has a first emitter formation region and a second emitter formation region that are spaced apart from each other in the first direction between the pair of first trenches, and a spaced-apart region located between the first emitter formation region and the second emitter formation region. The base region is formed within the semiconductor substrate of the first emitter formation region, the second emitter formation region, and the separation region, The first impurity region is formed within the base region of the first emitter formation region and the second emitter formation region, The second impurity region is formed within the base region at a first location in the separated region that is in contact with the pair of first trenches. The second impurity region is connected to the first impurity region of each of the first emitter formation region and the second emitter formation region, A semiconductor device wherein the first impurity region has a higher impurity concentration than the second impurity region.

2. In the semiconductor device described in claim 1, The second impurity region is formed throughout the base region of the separated region, The impurity concentration in the second impurity region is 1 × 10⁻⁶ １２ / cm ３ The above and 1 x 10 １４ / cm ３ The following is a semiconductor device.

3. In the semiconductor device described in claim 1, An interlayer insulating film formed on the upper surface of the semiconductor substrate so as to cover the pair of first trenches, A hole formed in the interlayer insulating film and the semiconductor substrate so as to penetrate the first impurity region and reach the interior of the base region, An emitter electrode formed on the interlayer insulating film, Furthermore, The base region, the first impurity region, and the second impurity region are electrically connected to the emitter electrode via the holes. A semiconductor device in which, in the separated region, the second impurity region is physically separated from the hole.

4. In the semiconductor device described in claim 3, In the second location of the separated region that is in contact with the hole, the third impurity region of the first conductivity type is formed within the base region. The third impurity region is connected to the first impurity region of each of the first emitter formation region and the second emitter formation region, A semiconductor device in which the second impurity region and the third impurity region are separated from each other in the aforementioned separated region.

5. A first-type conductive semiconductor substrate having an upper surface and a lower surface, On the upper surface side of the semiconductor substrate, a pair of first trenches are formed within the semiconductor substrate and extend in a first direction in a plan view, A pair of first gate insulating films formed inside the pair of first trenches, A pair of first gate electrodes embedded inside the pair of first trenches via the pair of first gate insulating films, On the upper surface side of the semiconductor substrate, a base region of a second conductivity type opposite to the first conductivity type is formed within the semiconductor substrate, On the upper surface side of the semiconductor substrate, a first impurity region of the first conductivity type and a second impurity region of the first conductivity type formed within the semiconductor substrate, An interlayer insulating film formed on the upper surface of the semiconductor substrate so as to cover the pair of first trenches, A hole formed in the interlayer insulating film and the semiconductor substrate so as to penetrate the first impurity region and reach the interior of the base region, An emitter electrode formed on the interlayer insulating film, Equipped with, The semiconductor substrate has a first emitter formation region and a second emitter formation region that are spaced apart from each other in the first direction between the pair of first trenches, and a spaced-apart region located between the first emitter formation region and the second emitter formation region. The base region is formed within the semiconductor substrate of the first emitter formation region, the second emitter formation region, and the separation region, The first impurity region is formed within the base region of the first emitter formation region and the second emitter formation region, The impurity concentration of the base region at the first location in the separated region that is in contact with the pair of first trenches is lower than the impurity concentration of the base region in each of the first emitter formation region and the second emitter formation region. The base region and the first impurity region are electrically connected to the emitter electrode via the holes. The base region at the first location is physically separated from the hole. The impurity concentration in the base region of each of the first emitter formation region and the second emitter formation region is 1 × 10¹⁷ / cm³ or more and 1 × 10¹⁸ / cm³ or less. A semiconductor device wherein the impurity concentration of the base region at the first location is 1 × 10¹² / cm³ or more and 1 × 10¹⁴ / cm³ or less.

6. In the semiconductor device described in claim 5, A semiconductor device wherein the total impurity concentration of the base region of the separated region is lower than the impurity concentration of the base region of each of the first emitter formation region and the second emitter formation region.

7. (a) A step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, (b) A step of forming a pair of first trenches within the semiconductor substrate on the upper surface side of the semiconductor substrate so as to extend in a first direction in a plan view, (c) A step of forming a pair of first gate insulating films inside the pair of first trenches, (d) A step of embedding a pair of first gate electrodes inside the pair of first trenches via the pair of first gate insulating films, (e) A step of forming a base region of a second conductivity type opposite to the first conductivity type within the semiconductor substrate on the upper surface side of the semiconductor substrate. (f) A step of forming a first impurity region of the first conductivity type and a second impurity region of the first conductivity type within the semiconductor substrate on the upper surface side of the semiconductor substrate. Equipped with, The semiconductor substrate has a first emitter formation region and a second emitter formation region that are spaced apart from each other in the first direction between the pair of first trenches, and a spaced-apart region located between the first emitter formation region and the second emitter formation region. The base region is formed within the semiconductor substrate of the first emitter formation region, the second emitter formation region, and the separation region, The first impurity region is formed within the base region of the first emitter formation region and the second emitter formation region, The second impurity region is formed within the base region at a first location in the separated region that is in contact with the pair of first trenches. The second impurity region is connected to the first impurity region of each of the first emitter formation region and the second emitter formation region, The aforementioned step (f) is, (f1) A step of ion implanting an impurity of the first conductivity type into the semiconductor substrate in each of the first emitter formation region and the second emitter formation region, and into the semiconductor substrate at the first location of the separation region. (f2) A step of ion implanting the first conductivity type impurity into the semiconductor substrate of the first emitter formation region and the second emitter formation region, It has, The second impurity region includes the impurities ion-implanted in step (f1), A method for manufacturing a semiconductor device, wherein the first impurity region includes impurities ion-implanted in step (f1) and impurities ion-implanted in step (f2), and has a higher impurity concentration than the second impurity region.

8. In the method for manufacturing a semiconductor device according to claim 7, In step (f1) above, the first conductivity type impurity is ion-implanted throughout the semiconductor substrate in the separated region. The second impurity region is formed throughout the base region of the separated region, The impurity concentration in the second impurity region is 1 × 10⁻⁶ １２ / cm ３ The above and 1 x 10 １４ / cm ３ The following is a method for manufacturing a semiconductor device.

9. In the method for manufacturing a semiconductor device according to claim 7, The above step (b) is, (b1) A step of forming a hard mask on the upper surface of the semiconductor substrate so as to selectively cover the upper surface of the semiconductor substrate. (b2) After step (b1), a step of forming the pair of first trenches in the semiconductor substrate exposed from the hard mask, (b3) After step (b2), a step of removing the hard mask, It has, The aforementioned step (f) is, (f3) Between step (b1) and step (b2), a step of ion implanting the first conductivity type impurity into the semiconductor substrate exposed from the hard mask at an angle inclined with respect to the normal to the upper surface of the semiconductor substrate, (f4) After step (d), a step of ion implanting the first conductivity type impurity into the semiconductor substrate of the first emitter formation region and the second emitter formation region, It has, The aforementioned second impurity region includes the impurities ion-implanted in step (f3), A method for manufacturing a semiconductor device, wherein the first impurity region includes impurities ion-implanted in step (f3) and impurities ion-implanted in step (f4), and has a higher impurity concentration than the second impurity region.

10. In the method for manufacturing a semiconductor device according to claim 7, (g) A step of forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the pair of first trenches. (h) A step of forming holes in the interlayer insulating film and the semiconductor substrate so as to penetrate the first impurity region and reach the interior of the base region. (i) A step of forming an emitter electrode on the interlayer insulating film, Furthermore, The base region, the first impurity region, and the second impurity region are electrically connected to the emitter electrode via the holes. A method for manufacturing a semiconductor device, wherein in the separated region, the second impurity region is physically separated from the hole.

11. In the method for manufacturing a semiconductor device according to claim 10, In the step of forming the second impurity region, the third impurity region of the first conductivity type is formed within the semiconductor substrate. The third impurity region is formed within the base region at a second location in contact with the pore within the separated region. The third impurity region is connected to the first impurity region of each of the first emitter formation region and the second emitter formation region, A method for manufacturing a semiconductor device, wherein in the separated region, the second impurity region and the third impurity region are separated from each other.

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