Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device and a method for manufacturing the same, which can prevent damage to elements formed on the main surface of a semiconductor substrate in the manufacturing process of the semiconductor device.SOLUTION: A method for manufacturing a semiconductor device comprises: a step for forming an annular convex portion surrounding an element region on the outer periphery of a semiconductor substrate; a step for forming a groove in the element region, a step for forming a capacitor structure inside the groove; a step for forming an interlayer insulating film by embedding the inside of the convex portion.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In the manufacture of a semiconductor device, a series of processes are performed while placing a semiconductor substrate to be processed on a substrate stage of a semiconductor manufacturing apparatus. At this time, the main surface of the semiconductor substrate is attracted by a vacuum chuck or the like, so that the semiconductor substrate adheres to the substrate stage of the semiconductor manufacturing apparatus. In order to prevent damage to the elements formed on the main surface of the semiconductor substrate due to contact between the semiconductor substrate and the substrate stage, a step is formed around the region where the elements are formed on the main surface of the semiconductor substrate (hereinafter referred to as the "element region"), and a structure for providing a space above the element region is being studied.

Prior Art Documents

Patent Documents

[0003] [

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, by providing a space above the main surface of the semiconductor substrate, there arises a problem that when the main surface of the semiconductor substrate is attracted, the semiconductor substrate is curved or the like, and the elements formed in the element region are damaged.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device and a method for manufacturing the same that can prevent damage to elements formed on the main surface of a semiconductor substrate in a manufacturing process of the semiconductor device.

Means for Solving the Problems

[0006] A method for manufacturing a semiconductor device according to one aspect of the present invention comprises the steps of forming an annular protrusion surrounding an element region in the outer peripheral region of a semiconductor substrate, forming a groove in the element region, forming a capacitor structure inside the groove, and filling the inside of the protrusion to form an interlayer insulating film. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the same that can prevent damage to elements formed on the main surface of a semiconductor substrate during the manufacturing process of the semiconductor device. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing the configuration of a semiconductor device according to the first embodiment. [Figure 3A] Figure 3A is a schematic plan view illustrating the manufacturing method of a semiconductor device according to the first embodiment (Part 1). [Figure 3B] Figure 3B is a schematic cross-sectional view along the BB direction in Figure 3A. [Figure 4A] Figure 4A is a schematic plan view illustrating the manufacturing method of a semiconductor device according to the first embodiment (part 2). [Figure 4B] Figure 4B is a schematic cross-sectional view along the BB direction in Figure 4A. [Figure 5A] Figure 5A is a schematic plan view illustrating the manufacturing method of a semiconductor device according to the first embodiment (part 3). [Figure 5B] Figure 5B is a schematic cross-sectional view along the BB direction in Figure 5A. [Figure 6A] Figure 6A is a schematic plan view illustrating the manufacturing method of a semiconductor device according to the first embodiment (part 4). [Figure 6B] Figure 6B is a schematic cross-sectional view along the BB direction in Figure 6A. [Figure 7A]FIG. 7A is a schematic plan view (part 5) for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 7B] FIG. 7B is a schematic cross-sectional view taken along the B-B direction of FIG. 7A. [Figure 8A] FIG. 8A is a schematic plan view (part 6) for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 8B] FIG. 8B is a schematic cross-sectional view taken along the B-B direction of FIG. 8A. [Figure 9A] FIG. 9A is a schematic plan view (part 7) for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 9B] FIG. 9B is a schematic cross-sectional view taken along the B-B direction of FIG. 9A. [Figure 10A] FIG. 10A is a schematic plan view (part 8) for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 10B] FIG. 10B is a schematic cross-sectional view taken along the B-B direction of FIG. 10A. [Figure 11A] FIG. 11A is a schematic plan view (part 9) for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 11B] FIG. 11B is a schematic cross-sectional view taken along the B-B direction of FIG. 11A. [Figure 12A] FIG. 12A is a schematic plan view (part 10) for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 12B] FIG. 12B is a schematic cross-sectional view taken along the B-B direction of FIG. 12A. [[ID=�5]] [Figure 13A] FIG. 13A is a schematic plan view (part 11) for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 13B] FIG. 13B is a schematic cross-sectional view taken along the B-B direction of FIG. 13A. [Figure 14A] FIG. 14A is a schematic plan view (part 12) for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 14B]FIG. 14B is a schematic cross-sectional view taken along the B-B direction of FIG. 14A. [Figure 15A] FIG. 15A is a schematic plan view (part 13) for explaining a method of manufacturing a semiconductor device according to the first embodiment. [Figure 15B] FIG. 15B is a schematic cross-sectional view taken along the B-B direction of FIG. 15A. [Figure 16] FIG. 16 is a schematic cross-sectional view showing the configuration of a first comparative example substrate. [Figure 17] FIG. 17 is a schematic cross-sectional view showing the configuration of a second comparative example substrate. [Figure 18A] FIG. 18A is a schematic plan view for explaining a method of manufacturing a semiconductor device according to the second embodiment. [Figure 18B] FIG. 18B is a schematic cross-sectional view taken along the B-B direction of FIG. 18A. [Figure 19] FIG. 19 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the third embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view showing the configuration of a semiconductor device according to the fourth embodiment. [Figure 21] FIG. 21 is a schematic plan view showing the convex portions of a semiconductor device according to other embodiments.

MODE FOR CARRYING OUT THE INVENTION

[0009] Embodiments will be described below with reference to the drawings. In the description of the drawings, the same reference numerals are given to the same parts and the description thereof is omitted. However, the drawings are schematic, and include parts where the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. are different from the actual ones. Also, parts where the dimensional relationships and ratios are different are included among the drawings.

[0010] (First Embodiment) As shown in Figures 1 and 2, the semiconductor device according to the first embodiment of the present invention comprises a semiconductor substrate 1 including an element region in which grooves 10 extending from a first main surface 110 to a second main surface 120 are formed, and a region surrounding the element region (hereinafter referred to as the "outer peripheral region"). Figure 1 is a cross-sectional view along direction II in Figure 2. In the following, unless otherwise specified, the first main surface 110 and the second main surface 120 will be referred to as the main surface.

[0011] The semiconductor device according to the first embodiment includes a capacitor structure in which dielectric layers and conductive layers are stacked inside a groove 10. The capacitor structure shown in Figure 1 is a structure in which a first dielectric layer 31, a first conductive layer 41, a second dielectric layer 32, a second conductive layer 42, a third dielectric layer 33, a third conductive layer 43, a fourth dielectric layer 34, a fourth conductive layer 44, a fifth dielectric layer 35, and a fifth conductive layer 45 are stacked in this order.Hereafter, unless the first dielectric layer 31 to the fifth dielectric layer 35 is specifically defined, it will be referred to as dielectric layer 30. Unless the first conductive layer 41 to the fifth conductive layer 45 is specifically defined, it will be referred to as conductive layer 40.

[0012] As shown in Figure 2, when viewed from the direction normal to the first main surface 110 (hereinafter also referred to as "plan view"), a plurality of grooves 10 are arranged in the element region of the semiconductor substrate 1. An annular first protrusion 11 is arranged in the outer peripheral region of the first main surface 110 so as to surround the element region in which the grooves 10 are formed. An annular second protrusion 12 is arranged in the outer peripheral region of the second main surface 120 so as to surround the element region. In the following, unless otherwise specified, the first protrusion 11 and the second protrusion 12 will be referred to as protrusions. The protrusions are formed in a ridge shape in the outer peripheral region of the semiconductor substrate 1 so as to surround the element region.

[0013] A first interlayer insulating film 51, a second interlayer insulating film 52, and a third interlayer insulating film 53 are laminated on the main surface of the semiconductor substrate 1. The first interlayer insulating film 51 is positioned to cover the element region by embedding the inside of the protrusions. As shown in Figure 1, the surface of the first interlayer insulating film 51 and the surface of the protrusions are at the same plane level. The second interlayer insulating film 52 is positioned to cover the surface of the first interlayer insulating film 51 and the surface of the protrusions. The third interlayer insulating film 53 is positioned to cover the surface of the second interlayer insulating film 52. Hereinafter, the first interlayer insulating film 51, the second interlayer insulating film 52, and the third interlayer insulating film 53 will be collectively referred to as the interlayer insulating film 50.

[0014] The first electrode 21 is positioned on the surface of the third interlayer insulating film 53 on the first main surface 110 side. The second electrode 22 is positioned on the surface of the third interlayer insulating film 53 on the second main surface 120 side. For the semiconductor device to function as a semiconductor capacitor, the first electrode 21 and the second electrode are electrically connected to the conductive layer 40 of the capacitor structure formed inside the groove 10.

[0015] Specifically, the first electrode 21 is electrically connected to the first conductive layer 41 via the first contact hole 211, to the third conductive layer 43 via the second contact hole 212, and to the fifth conductive layer 45 via the third contact hole 213. In addition, the second electrode 22 is electrically connected to the conductive semiconductor substrate 1 via the fourth contact hole 221, to the second conductive layer 42 via the fifth contact hole 222, and to the fourth conductive layer 44 via the sixth contact hole 223.

[0016] The first contact hole 211 penetrates the interlayer insulating film 50 and the second dielectric layer 32 to the fifth dielectric layer 35 and the second conductive layer 42 to the fifth conductive layer 45. The second contact hole 212 penetrates the interlayer insulating film 50 and the fourth dielectric layer 34 to the fifth dielectric layer 35 and the fourth conductive layer 44 to the fifth conductive layer 45. The third contact hole 213 penetrates the interlayer insulating film 50. The fourth contact hole 221 penetrates the interlayer insulating film 50 and the first dielectric layer 31 to the fifth dielectric layer 35 and the first conductive layer 41 to the fifth conductive layer 45. The fifth contact hole 222 penetrates the interlayer insulating film 50 and the third dielectric layer 33 to the fifth dielectric layer 35 and the third conductive layer 43 to the fifth conductive layer 45. The sixth contact hole 223 penetrates the interlayer insulating film 50 and the fifth dielectric layer 35 and the fifth conductive layer 45.

[0017] In the following, unless otherwise specified, the first electrode 21 and the second electrode 22 will simply be referred to as electrodes. Furthermore, the first contact holes 211 to the sixth contact holes 223 will be collectively referred to as contact holes. Electrodes are embedded within the contact holes that penetrate the dielectric layer 30, the conductive layer 40, and the interlayer insulating film 50. The sides of the contact holes are covered by the third interlayer insulating film 53, and the electrodes are electrically connected only to the semiconductor substrate 1 or the conductive layer 40 exposed at the bottom of the contact holes.

[0018] The operation of the semiconductor device is described below. When a negative voltage is applied to the first electrode 21 and a positive voltage to the second electrode 22, the first conductive layer 41, the third conductive layer 43, and the fifth conductive layer 45 are charged with positive charge, and the second conductive layer 42 and the fourth conductive layer 44 are charged with negative charge. At this time, polarization occurs inside the dielectric layer 30 placed between the conductive layers 40, and capacitance is generated. Alternatively, if the semiconductor substrate 1 is a conductive substrate, the semiconductor substrate 1 may function as an electrode in a capacitor structure. That is, polarization occurs inside the first dielectric layer 31 placed between the semiconductor substrate 1 and the first conductive layer 41, and the semiconductor substrate 1 is charged with negative charge. In this way, by making the semiconductor substrate 1 an electrode in a capacitor structure, the capacitance value of the capacitor structure can be increased. Note that the positive and negative signs of the voltages applied to the first electrode 21 and the second electrode 22 may be reversed from the above.

[0019] As shown in Figure 2, contact holes are arranged between adjacent grooves 10 in a plan view. By arranging contact holes between grooves 10, the number of contact holes can be increased compared to when contact holes are arranged in the outer peripheral region of the semiconductor substrate 1. Furthermore, since contact holes can be arranged near grooves 10 formed near the center of the semiconductor substrate 1, the equivalent series resistance (ESR) between the electrode and the conductive layer 40 can be reduced.

[0020] In the semiconductor device according to the first embodiment, multiple dielectric layers 30 are alternately stacked with conductive layers 40 inside grooves 10 formed in the semiconductor substrate 1, and capacitance can be generated in each dielectric layer 30. Therefore, the capacitance density per unit area of ​​the semiconductor substrate 1 can be improved.

[0021] The method for manufacturing a semiconductor device according to the first embodiment will be described below with reference to Figures 3A, 3B to 15A, and 15B. Figures 3B to 12B are cross-sectional views along the BB direction in Figures 3A to 12A. The method for manufacturing a semiconductor device described below is just one example, and can be realized by various other manufacturing methods, including this modified version.

[0022] First, a semiconductor substrate 1 is prepared having a first main surface 110 and a second main surface 120 that are opposite to each other. The first main surface 110 and the second main surface 120 are defined to include an element region and an outer peripheral region surrounding the element region. Then, as shown in Figures 3A and 3B, an annular first protrusion 11 is formed in the outer peripheral region of the first main surface 110 of the semiconductor substrate 1 so as to surround the element region. The first protrusion 11 is formed by selectively etching the first main surface 110 using an etching mask formed by patterning a first mask material 71 deposited on the first main surface 110.

[0023] For example, a silicon oxide film can be used as the mask material. For the deposition method of the mask material, thermochemical vapor deposition (thermal CVD) or plasma chemical vapor deposition (plasma CVD) can be used. Patterning of the mask material is performed, for example, by patterning a photoresist film formed on the surface of the mask material using photolithography, and then etching the mask material using the photoresist film as an etching mask (the same applies to the mask material patterning described below). After patterning the mask material, the photoresist film is removed using oxygen plasma or sulfuric acid.

[0024] Next, as shown in Figures 4A and 4B, an annular second protrusion 12 is formed on the outer periphery of the second main surface 120 of the semiconductor substrate 1 so as to surround the element region. The second protrusion 12 is formed by selectively etching the second main surface 120 using an etching mask formed by patterning a second mask material 72 deposited on the second main surface 120.

[0025] The length along the normal direction of the main surface from the surface of the element region to the surface of the protrusion (hereinafter referred to as the "height of the protrusion") is, for example, about 2 μm. The surface of the semiconductor substrate 1 that has been recessed in the normal direction of the main surface by etching in order to form the protrusion is also referred to as the first main surface 110 and the second main surface 120.

[0026] Subsequently, as shown in Figures 5A and 5B, a plurality of grooves 10 are formed on the semiconductor substrate 1 from the first main surface 110 toward the second main surface 120. The grooves 10 are formed, for example, by etching using an etching mask formed by patterning a mask material deposited on the first main surface 110.

[0027] For etching the groove 10, a wet etching method using potassium hydroxide (KOH) as the etching solution or a dry etching method such as reactive ion etching can be used.

[0028] After forming the groove 10, a capacitor structure is formed by stacking a dielectric layer 30 and a conductive layer 40 inside the groove 10. First, as shown in Figures 6A and 6B, a first dielectric layer 31 is deposited on the surface of the semiconductor substrate 1. For example, a silicon oxide film may be used as the dielectric layer 30. For the deposition method of the dielectric layer 30, a thermal oxidation method or a thermal CVD method may be used. When using the thermal CVD method, by depositing the dielectric layer 30 under reduced pressure conditions, the silicon oxide film can be deposited inside the groove 10 with good coverage even when the groove 10 is deep.

[0029] Next, as shown in Figures 7A and 7B, a first conductive layer 41 is deposited so as to cover the first dielectric layer 31. For example, a polysilicon film may be used as the conductive layer 40. A vacuum CVD method may be used for depositing the polysilicon film. Alternatively, after depositing the polysilicon film, an n-type polysilicon film may be formed by annealing at 950°C in phosphorus oxychloride (POCl3) to give conductivity to the conductive layer 40. Alternatively, a metal film and a silicide film may be used for the conductive layer 40.

[0030] Subsequently, the second dielectric layer 32, the second conductive layer 42, the third dielectric layer 33, the third conductive layer 43, the fourth dielectric layer 34, the fourth conductive layer 44, the fifth dielectric layer 35, and the fifth conductive layer 45 are sequentially laminated in the same manner as the formation of the first dielectric layer 31 and the first conductive layer 41. The groove 10 is filled by the fifth conductive layer 45. As a result, a structure is formed in which five dielectric layers 30 and five conductive layers 40 are deposited inside the groove 10, as shown in Figures 8A and 8B.

[0031] Next, an interlayer insulating film is formed to fill the inside of the protrusions and cover the element region. That is, as shown in Figures 9A and 9B, the first interlayer insulating film 51 is deposited covering the fifth conductive layer 45. For the first interlayer insulating film 51, for example, a silicon oxide film may be used.

[0032] Subsequently, as shown in Figures 10A and 10B, the surface of the first interlayer insulating film 51 is etched and planarized until the surface of the protrusion is exposed. By planarizing the surface of the first interlayer insulating film 51, the surface of the first interlayer insulating film 51 and the surface of the protrusion become on the same plane. For example, the surface of the first interlayer insulating film 51 may be planarized using a chemical mechanical polishing (CMP) method.

[0033] After planarizing the surface of the first interlayer insulating film 51, a second interlayer insulating film 52 is formed on the surface of the first interlayer insulating film 51, as shown in Figures 11A and 11B. For the second interlayer insulating film 52, for example, a silicon oxide film may be used.

[0034] After forming the second interlayer insulating film 52, contact holes are formed by etching all or some of the layers of the first interlayer insulating film 51, the second interlayer insulating film 52, and the conductive layer 40 using an etching mask (not shown), as shown in Figures 12A and 12B. For example, a photoresist film may be used as the etching mask, or the contact holes may be formed by a dry etching method. The surface of the first conductive layer 41 is exposed at the bottom of the first contact hole 211. The surface of the third conductive layer 43 is exposed at the bottom of the second contact hole 212. The surface of the fifth conductive layer 45 is exposed at the bottom of the third contact hole 213. The main surface of the semiconductor substrate 1 is exposed at the bottom of the fourth contact hole 221. The surface of the second conductive layer 42 is exposed at the bottom of the fifth contact hole 222. The surface of the fourth conductive layer 44 is exposed at the bottom of the sixth contact hole 223.

[0035] As described above, the layer to be removed by etching differs depending on each of the first to sixth contact holes 211 to 223. For this reason, the pattern of the mask material for forming the contact holes may be changed for each step that penetrates each layer.

[0036] After forming the contact hole, a third interlayer insulating film 53 is formed. The third interlayer insulating film 53 covers the surface of the second interlayer insulating film 52 and the sides and bottom of the contact hole. Then, as shown in Figures 13A and 13B, the third interlayer insulating film 53 on the bottom of the contact hole is removed. For example, the third interlayer insulating film 53 on the bottom of the contact hole may be removed by a dry etching method.

[0037] Next, as shown in Figures 14A and 14B, a first electrode 21 and a second electrode 22 are formed on the surface of the third interlayer insulating film 53. The contact holes are filled by the first electrode 21 and the second electrode 22. This electrically connects the electrodes to the conductive layer 40 and the semiconductor substrate 1. For example, a titanium (Ti) / aluminum (Al) film may be used as the electrode material. For electrode formation methods, sputtering, electron beam (EB) deposition, atomic layer deposition (ALD), etc., can be used.

[0038] Subsequently, as shown in Figures 15A and 15B, a chip dicing process is performed to divide the semiconductor substrate 1 into multiple chips. In the chip dicing process, for example, a dicing blade BL is used to cut the semiconductor substrate 1 in the outer peripheral region along a dicing line DL that overlaps the protrusion. Because the width of the protrusion is wider than the blade width of the dicing blade BL, a portion of the protrusion remains in the cross-section of the chipped semiconductor device. The width of the protrusion is the length of the protrusion parallel to the main surface in the cross-sectional view of the semiconductor substrate 1. For example, the blade width of the dicing blade BL is 100 μm, and the width of the protrusion is approximately 120 μm to 150 μm.

[0039] The chip dicing process exposes the edges of the semiconductor substrate 1, dielectric layer 30, conductive layer 40, and interlayer insulating film 50 on the side surface of the chip. This completes the semiconductor device shown in Figure 1.

[0040] The above describes a method of polishing the surface of the first interlayer insulating film 51 using the CMP method to make the surface of the first interlayer insulating film 51 at the same plane level as the surface of the protrusion. By matching the height of the first interlayer insulating film 51 and the protrusion using a polishing method such as the CMP method, the flatness of the surfaces of the first interlayer insulating film 51 and the protrusion can be increased. By making the surfaces of the first interlayer insulating film 51 and the protrusion at the same plane level with high flatness, subsequent film deposition processes are facilitated. For example, a decrease in step coverage of the first electrode 21 and the second electrode 22 formed above the first interlayer insulating film 51 and the protrusion can be suppressed.

[0041] Alternatively, the surface of the first interlayer insulating film 51 may be etched using a dry etching method such as inductively coupled plasma-reactive ion etching (ICP-RIE) to bring the surface of the first interlayer insulating film 51 to the same plane as the surface of the protrusion. By matching the height of the first interlayer insulating film 51 and the protrusion using a dry etching method, the etching range can be defined with high precision.

[0042] Alternatively, the surface of the first interlayer insulating film 51 may be etched using a wet etching method to make the surface of the first interlayer insulating film 51 at the same plane level as the surface of the protrusion. By matching the height of the first interlayer insulating film 51 and the protrusion using a wet etching method, the surface of the first interlayer insulating film 51 and the surface of the protrusion can be made at the same plane level at a lower cost than the dry etching method.

[0043] In the above description, a method was explained in which the second interlayer insulating film 52 is formed after the first interlayer insulating film 51 has been planarized. However, the first interlayer insulating film 51 may be formed thickly and its surface may be planarized. This would allow the formation of the second interlayer insulating film 52 to be omitted, thereby shortening the manufacturing process. However, the method of planarizing the first interlayer insulating film 51 before forming the second interlayer insulating film 52 makes it easier to planarize the surface of the interlayer insulating film.

[0044] For etching to form grooves 10 in the semiconductor substrate 1, either a dry etching method or a wet etching method may be used. Using the dry etching method allows for easy formation of deep grooves 10. Using the wet etching method allows for the formation of grooves 10 at a lower cost than the dry etching method.

[0045] In the above series of semiconductor device manufacturing methods, when the first main surface 110 of the semiconductor substrate 1 is processed by a semiconductor manufacturing apparatus, the second main surface 120 is adsorbed onto the substrate stage of the semiconductor manufacturing apparatus. In the semiconductor device shown in Figure 1, in the process of forming elements on the first main surface 110, a second protrusion 12 is formed on the second main surface 120 that is adsorbed onto the substrate stage, thereby preventing the element region of the second main surface 120 from adhering closely to the substrate stage. This suppresses damage to the elements formed on the second main surface 120. Furthermore, in the process of forming elements on the second main surface 120, a first protrusion 11 is formed on the first main surface 110 that is adsorbed onto the substrate stage, thereby preventing the element region of the first main surface 110 from adhering closely to the substrate stage. This suppresses damage to the elements formed on the first main surface 110.

[0046] In contrast, in the first comparative example substrate 1A, which does not have the protrusions shown in Figure 16, the element region of the second main surface 120 comes into close contact with the substrate stage 300 during the process of forming elements on the first main surface 110. As a result, there is a risk that the elements formed on the second main surface 120 may be damaged. Also, in the process of forming elements on the second main surface 120 of the first comparative example substrate 1A, the element region of the first main surface 110 comes into close contact with the substrate stage 300. As a result, there is a risk that the elements formed on the first main surface 110 may be damaged.

[0047] As described above, according to the semiconductor device of the first embodiment, by arranging protrusions on the first main surface 110 and the second main surface 120 of the semiconductor substrate 1 to create a step, the element region is prevented from adhering closely to the substrate stage. Therefore, damage to the elements formed in the element regions of the first main surface 110 and the second main surface 120 can be suppressed.

[0048] Furthermore, if protrusions are formed on the main surface as in the second comparative example substrate 1B shown in Figure 17, and the inside of the first protrusion 11 and the inside of the second protrusion 12 are voids, the second comparative example substrate 1B will bend when its main surface is adsorbed. As a result, elements such as capacitor structures formed on the second comparative example substrate 1B may be damaged. However, with the semiconductor device shown in Figure 1, by filling the inside of the protrusions with the first interlayer insulating film 51, it is possible to suppress the bending of the semiconductor substrate 1 when its main surface is adsorbed.

[0049] Furthermore, when elements with similar structures are symmetrically formed on the first main surface 110 and the second main surface 120, warping of the semiconductor substrate 1 is unlikely to occur. However, warping of the semiconductor substrate 1 is common due to differences in the structures of the elements formed on the first main surface 110 and the elements formed on the second main surface 120. To suppress the amount of warping that occurs in the semiconductor substrate 1, the film thickness of the first interlayer insulating film 51 formed on the first main surface 110 and the film thickness formed on the second main surface 120 may be adjusted. That is, the amount of warping of the semiconductor substrate 1 may be suppressed by adjusting the height of the first protrusion 11 formed on the first main surface 110 and the height of the second protrusion 12 formed on the second main surface 120. For example, if the semiconductor substrate 1 is prone to warping such that the first main surface 110 becomes concave, the film thickness of the first interlayer insulating film 51 on the first main surface 110 may be made thicker than the film thickness of the first interlayer insulating film 51 on the second main surface 120.

[0050] As described above, in the semiconductor device according to the first embodiment of the present invention, by providing annular protrusions on the outer peripheral region of the main surface, damage to the elements caused by the main surface being pressed against the substrate stage during the manufacturing process can be suppressed. Furthermore, since the inside of the protrusions is embedded and covers the element region to form an interlayer insulating film, the occurrence of warping of the semiconductor substrate 1 can be suppressed. For this reason, according to the semiconductor device according to the first embodiment, damage to the elements formed on the main surface can be prevented.

[0051] As described above, in the semiconductor device according to the first embodiment, a protrusion is formed by etching the element region of the main surface back in the thickness direction of the semiconductor substrate 1. In other words, the protrusion is part of the semiconductor substrate 1, and the protrusion is made of the same material as the semiconductor substrate 1. By processing the semiconductor substrate 1 in this way to form the protrusion, and by integrating the semiconductor substrate 1 and the protrusion, the rigidity of the semiconductor substrate 1 after the protrusion is formed can be improved. That is, the semiconductor substrate 1 becomes thicker in the part where the protrusion is formed, and the rigidity of the semiconductor substrate 1 increases.

[0052] As shown in Figure 1, the groove 10 may penetrate the semiconductor substrate 1 from the first main surface 110 to the second main surface 120. By having the groove 10 penetrate the semiconductor substrate 1, the area of ​​the conductive layer 40 inside the groove 10 is increased, and the capacitance density per unit area of ​​the semiconductor substrate 1 can be increased.

[0053] A silicon substrate may be used for the semiconductor substrate 1. By using an inexpensive silicon substrate for the semiconductor substrate 1, the manufacturing cost of the semiconductor device can be reduced.

[0054] When a silicon substrate is used for the semiconductor substrate 1, the surface orientation of the first main surface 110 of the semiconductor substrate 1 may be (110), and the surface orientation of the side walls of the groove 10 may be (111). When the semiconductor substrate 1 is a silicon substrate, the semiconductor substrate 1 is prone to cleavage along the (111) plane. Therefore, by making the longitudinal side walls of the groove 10 the (111) plane, it is possible to prevent the (111) plane of the semiconductor substrate 1 from crossing the longitudinal side walls of the groove 10. As a result, the occurrence of cleavage that divides the groove 10 can be suppressed. Also, when the first main surface 110 is the (110) plane and the side walls of the groove 10 are the (111) plane, the side walls of the groove 10 are perpendicular to the first main surface 110. In other words, the groove 10 extends perpendicularly in the depth direction from the first main surface 110.

[0055] The above describes the case where the semiconductor substrate 1 is a conductive substrate, but the semiconductor substrate 1 may also be an insulating substrate. Because the semiconductor substrate 1 is insulating, when multiple elements are formed on the semiconductor substrate 1, there is no need to form isolation regions to isolate the elements. In other words, element isolation is easy. Furthermore, when the semiconductor substrate 1 is an insulating substrate, contact holes for electrically connecting the semiconductor substrate 1 and the electrodes are unnecessary.

[0056] (Second embodiment) In the semiconductor device according to the second embodiment of the present invention, the width of the protrusion is set to be narrower than the blade width of the dicing blade BL used in the chip dicing process. In this case, as shown in Figure 18A, the first protrusion 11 and the second protrusion 12 are removed by cutting the semiconductor substrate 1 in the outer peripheral region along the dicing line DL that overlaps the protrusion with the dicing blade BL. As a result, as shown in Figure 18B, the main surface of the semiconductor device after chipping is at the same plane level from one end to the other. For example, the blade width of the dicing blade BL is 100 μm, and the width of the protrusion is about 50 μm to 80 μm. The other configurations of the semiconductor device according to the second embodiment are the same as those of the first embodiment.

[0057] In the semiconductor device according to the second embodiment, by providing annular protrusions on the outer peripheral region of the main surface, damage to the element caused by the element region being pressed against the substrate stage during the manufacturing process can be suppressed. Furthermore, since the inside of the protrusions is embedded and covers the element region to form an interlayer insulating film, the occurrence of warping of the semiconductor substrate 1 can be suppressed.

[0058] Furthermore, according to the semiconductor device of the second embodiment, by narrowing the widths of the first protrusion 11 and the second protrusion 12, the proportion of the element area on the main surface of the semiconductor substrate 1 can be increased. As a result, the manufacturing cost of the semiconductor device can be reduced. Otherwise, the semiconductor device of the second embodiment is substantially the same as that of the first embodiment, so redundant explanations will be omitted.

[0059] (Third embodiment) The semiconductor device according to the third embodiment shown in Figure 19 differs from the first embodiment, in that the protrusions are made of a different material from the semiconductor substrate 1, while the protrusions are made of the same material as the semiconductor substrate 1. The other configurations of the semiconductor device according to the third embodiment are the same as those of the first embodiment.

[0060] The protrusions of the semiconductor device shown in Figure 19 may be made of an insulating material such as an oxide film. By patterning an oxide film formed on the main surface of the semiconductor substrate 1 to form the first protrusion 11 and the second protrusion 12, the step of etching the main surface of the semiconductor substrate 1 to form the protrusions can be eliminated. Therefore, by using a different material for the protrusions than the semiconductor substrate 1, damage to the semiconductor substrate 1 caused by etching the main surface using, for example, a dry etching method can be suppressed.

[0061] In the semiconductor device shown in Figure 19, by providing annular protrusions on the outer peripheral region of the main surface, damage to the element caused by the element region being pressed against the substrate stage during the manufacturing process can be suppressed. Furthermore, since the inside of the protrusions is embedded and covers the element region to form an interlayer insulating film, the occurrence of warping of the semiconductor substrate 1 can be suppressed. Otherwise, the semiconductor device according to the third embodiment is substantially the same as that of the first or second embodiment, so redundant explanations will be omitted. For example, in the semiconductor device according to the third embodiment, the protrusions may also be removed during the chip dicing process.

[0062] (Fourth embodiment) In the semiconductor device according to the fourth embodiment shown in Figure 20, the groove 10, which contains a capacitor structure, is formed only on the first main surface 110, and no groove 10 is formed on the second main surface 120. In other words, the semiconductor device shown in Figure 20 differs from the semiconductor device according to the first embodiment, in that the groove 10 extends from the first main surface 110 and does not reach the second main surface 120. The other configurations of the semiconductor device according to the fourth embodiment are the same as those of the first embodiment.

[0063] In the semiconductor device shown in Figure 20, both the first electrode 21 and the second electrode 22 are located on the surface of the interlayer insulating film 50 on the first main surface 110 side of the semiconductor substrate 1. The first electrode 21 and the second electrode 22 are electrically connected to either the conductive layer 40 or the semiconductor substrate 1 via contact holes. Dielectric layers 30 and conductive layers 40 are alternately stacked on the second main surface 120 of the semiconductor substrate 1. A second protrusion 12 is formed on the second main surface 120 of the semiconductor substrate 1 and is planarized by the interlayer insulating film 50.

[0064] In the semiconductor device shown in Figure 20, the second main surface 120 is adsorbed to the substrate stage during the process of forming elements on the first main surface 110. At this time, the element region of the second main surface 120 is protected by the second protrusion 12. In other words, damage to elements not shown in Figure 20 that are formed in the element region of the second main surface 120 is suppressed. Furthermore, even in a semiconductor device comprising a semiconductor substrate 1 in which element regions are set only on either the first main surface 110 or the second main surface 120, damage to elements formed in the element region can be suppressed by forming protrusions so as to surround the periphery of the element region. In addition, by filling the inside of the protrusions with an interlayer insulating film, the occurrence of warping of the semiconductor substrate 1 can be suppressed.

[0065] As described above, in the semiconductor device according to the fourth embodiment, by providing annular protrusions on the outer peripheral region of the main surface, damage to the element caused by the element region being pressed against the substrate stage during the manufacturing process can be suppressed. Furthermore, since the inside of the protrusions is embedded and covers the element region to form an interlayer insulating film, the occurrence of warping of the semiconductor substrate 1 can be suppressed.

[0066] Otherwise, the semiconductor device according to the fourth embodiment is substantially the same as that of the first to third embodiments, so redundant explanations will be omitted. For example, in the semiconductor device according to the fourth embodiment, the protrusions may be removed in the chip dicing process, or the protrusions may be made of a different material from the semiconductor substrate 1.

[0067] (Other embodiments) As described above, embodiments of the present invention have been presented, but the statements and drawings that constitute part of this disclosure should not be understood as limiting the invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0068] For example, at the same time as forming the protrusions, an alignment pattern for aligning the mask pattern used in the manufacturing process with the semiconductor substrate 1 may be formed in the outer peripheral region. Using the alignment pattern, the mask patterns used in each manufacturing process of the semiconductor device are aligned with the semiconductor substrate 1 as the reference. For example, as shown in Figure 21, an alignment pattern 80 may be formed on the surface of the protrusions. By forming the alignment pattern at the same time as the protrusions, it is not necessary to perform a separate step for forming the alignment pattern, thus reducing the number of manufacturing steps for the semiconductor device.

[0069] The above describes the case where the conductive layer 40 is an n-type polysilicon film, but the conductive layer 40 may also be a p-type polysilicon film. Alternatively, the conductive layer 40 may be another semiconductor material, or a conductive material such as a metal. For example, the material of the conductive layer 40 may be conductive polysilicon carbide, silicon germanium (SiGe), or aluminum (Al). Furthermore, the electrode material may be a metal other than Ti / Al, such as silver (Ag) or nickel (Ni). [Explanation of Symbols]

[0070] 1. Semiconductor substrate 10 grooves 11. First protrusion 12 Second protrusion 21 1st electrode 22 2nd electrode 30 Dielectric layer 40 Conductive layer 50 Interlayer insulating film 110 First Main Surface 120 Second Main Surface

Claims

1. A semiconductor substrate having an element region and an outer peripheral region surrounding the element region on at least one of a first main surface and a second main surface facing each other, comprising the steps of forming an annular protrusion on the outer peripheral region so as to surround the element region, The process of forming grooves in the element region from the first main surface toward the second main surface, A step of forming a capacitor structure in which a dielectric layer and a conductive layer are stacked inside the groove, A step of filling the inside of the protrusion and forming an interlayer insulating film that covers the element region. A method for manufacturing a semiconductor device comprising the same equipment.

2. A method for manufacturing a semiconductor device according to claim 1, wherein, at the same time as forming the protrusions, an alignment pattern is formed for aligning a mask pattern used in the manufacturing process with the semiconductor substrate.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of polishing the surface of the interlayer insulating film using a polishing method to make the surface of the interlayer insulating film and the surface of the protrusions on the same plane level.

4. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of etching the surface of the interlayer insulating film using a dry etching method to make the surface of the interlayer insulating film coplanar with the surface of the protrusion.

5. A method for manufacturing a semiconductor device according to claim 1, further comprising the step of etching the surface of the interlayer insulating film using a wet etching method to make the surface of the interlayer insulating film coplanar with the surface of the protrusion.

6. The process further includes a chip dicing step of cutting the semiconductor substrate in the outer peripheral region to divide the semiconductor substrate into a plurality of chips, In the chip dicing process, the protrusions are removed. A method for manufacturing a semiconductor device according to claim 1.

7. A method for manufacturing a semiconductor device according to claim 1, wherein the groove is formed using a dry etching method.

8. A method for manufacturing a semiconductor device according to claim 1, wherein the grooves are formed using a wet etching method.

9. A semiconductor substrate having an element region and an outer peripheral region surrounding the element region on at least one of a first main surface and a second main surface facing each other, wherein a groove is formed in the element region extending from the first main surface to the second main surface, A capacitor structure in which a dielectric layer and a conductive layer are stacked inside the groove, An annular protrusion is arranged in the outer peripheral region so as to surround the periphery of the element region, An interlayer insulating film is arranged to embed the inside of the protrusion and cover the element region. A semiconductor device equipped with the following features.

10. The semiconductor device according to claim 9, wherein the protrusion is part of the semiconductor substrate.

11. The semiconductor device according to claim 9, wherein the protrusion is made of a material different from the semiconductor substrate.

12. The semiconductor device according to claim 9, wherein the convex portions are arranged on the first main surface and the second main surface, respectively.

13. The semiconductor device according to claim 9, wherein the groove penetrates the semiconductor substrate from the first main surface to the second main surface.

14. The semiconductor substrate is a silicon substrate, The surface orientation of the first main surface of the semiconductor substrate is (110), The surface orientation of the side wall of the groove is (111). The semiconductor device according to claim 9.

15. The semiconductor device according to claim 9, wherein the semiconductor substrate is a conductive substrate.

16. The semiconductor device according to claim 9, wherein the semiconductor substrate is an insulating substrate.

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