System and Method for DRAM Contact Formation

Abstract

The present disclosure generally relates to dynamic random access memory (DRAM) devices and semiconductor fabrication of DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and method for forming CMOS contacts, DRAM array bit line contacts (BLC), and storage node structures. The integrated processing system and method enable deposition of contact and storage node layers with reduced contamination and improved quality, thereby reducing leakage current and resistance of the final contact and storage node structures.

Description

[Technical Field]

[0001] Embodiments of this disclosure generally relate to methods and apparatus for forming semiconductor device contacts and storage nodes, and more specifically to methods and apparatus for forming dynamic random access memory (DRAM) array bit-line contacts (BLCs) and storage nodes. [Background technology]

[0002] Technological advancements in semiconductor processing have brought integrated circuits to the physical limits of Moore's Law. These advancements have introduced new paradigms in integrated circuit devices and structures. For example, various three-dimensional (3D) devices, such as 3D dynamic random-access memory (DRAM), are being developed for integrated circuits. However, such 3D devices can present a range of new challenges in processing and manufacturing.

[0003] A critical challenge in the design, production, and operation of 3D DRAM is contact resistance (Rc). DRAM cells operate in arrays of columns (bit lines) and rows (word lines). Bit lines propagate charge to and from sense amplifiers to program (write) a given cell or retrieve (read) data from a given cell. The speed of writing data to and reading data from DRAM cells depends on the resistance of the bit lines (R in Rc), with lower resistance resulting in faster data transfer. The resistance of a conductor depends on the scattering sites that electrons encounter as they move along the line. Impurities, grain boundaries, and surface roughness within the film are some of the obstacles that slow down electrons. The formation of these obstacles, and therefore their relative contributions, depends on the film deposition method and / or layer thickness.

[0004] Another significant challenge for 3D DRAM devices is contact stability. Generally, bit line contacts involve a very thin silicide layer that undergoes high-temperature processing after deposition. Downstream thermal processes can utilize temperatures above approximately 1050°C, which can cause degradation of the bit line contact silicide layer, such as its aggregation and nucleation, which affects the overall performance of the bit line.

[0005] Therefore, in this field, there is a need for improved contact and storage node structures that have reduced contact resistance and improved thermal stability. [Overview of the project]

[0006] Embodiments of this disclosure generally relate to processing systems and methods for forming contacts.

[0007] In one embodiment, a method is provided for forming bit line contacts within a dynamic random access memory (DRAM) device. This method involves depositing a doped semiconductor layer on an exposed surface of a doped region of a substrate in a first chamber, wherein the doped region is exposed through trenches formed in a dielectric material above the doped region. A metal silicide layer is then deposited on top of the doped semiconductor layer and subjected to a nitriding process to form a nitride layer on top of the metal silicide layer. The formation of the semiconductor layer, the metal silicide layer, and the nitride layer is performed without breaking the vacuum.

[0008] In another embodiment, a method is provided for forming bit line contacts within a dynamic random access memory (DRAM) device. This method includes pre-cleaning a substrate in a first chamber and depositing a doped semiconductor layer on the exposed surface of a doped region of the substrate in a second chamber, wherein the doped region is exposed through trenches formed in a dielectric material formed on the doped region. A metal silicide layer is deposited on the doped semiconductor layer in a third chamber and subjected to a nitriding process to form a nitride layer on the metal silicide layer. This method further includes depositing a conductive layer on the nitride layer in a fourth chamber, wherein the pre-cleaning and the formation of the doped semiconductor layer, metal silicide layer, nitride layer, and conductive layer are performed without breaking the vacuum.

[0009] In yet another embodiment, a processing system is provided. The processing system includes a system controller and a first process chamber, the system controller configured to perform a pre-cleaning process on doped regions formed at the bottom of trenches formed in a dielectric layer formed on a substrate placed in the first process chamber, the pre-cleaning process being performed on doped regions formed at the bottom of trenches formed in the dielectric layer. The processing system further includes a second process chamber, the system controller configured to form a doped epitaxial layer and a metal silicide layer on the exposed surface of the doped region of a substrate placed in the second process chamber, and to perform a nitriding process on the metal silicide layer to form a nitride layer. The processing system further includes a third process chamber, the system controller configured to form a conductive layer on top of the nitride layer, and the processing system configured to transfer the substrate between the first process, the second process chamber and the third process chamber without breaking the vacuum.

[0010] To better understand the features listed above of the present disclosure, a more detailed description of the present disclosure, briefly summarized above, can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings merely illustrate exemplary embodiments and should not be regarded as limiting the scope thereof, and other equally effective embodiments can be recognized.

Brief Description of the Drawings

[0011] [Figure 1] FIG. 8 is a cross-sectional view of a device contact according to an embodiment of the present disclosure. [Figure 2A] FIG. 11 is a cross-sectional view of device contacts in various devices according to an embodiment of the present disclosure. [Figure 2B] FIG. 14 is a cross-sectional view of device contacts in various devices according to an embodiment of the present disclosure. [Figure 2C] FIG. 17 is a cross-sectional view of device contacts in various devices according to an embodiment of the present disclosure. [Figure 3] FIG. 20 is a flowchart of a method for forming a device contact according to an embodiment of the present disclosure. [Figure 4A-4C] FIG. XX is a diagram showing the device contact of FIG. 1 in various steps of the method of FIG. 3 according to an embodiment of the present disclosure. [Figure 4D-4E] FIG. XX is a diagram showing the device contact of FIG. 1 in various steps of the method of FIG. 3 according to an embodiment of the present disclosure. [Figure 5] FIG. 29 is a schematic top view of a multi-chamber processing system for performing the method of FIG. 3 according to an embodiment of the present disclosure.

Modes for Carrying Out the Invention

[0012] For ease of understanding, the same reference numerals are used, if possible, to designate the same elements common to the figures. It is intended that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further elaboration.

[0013] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of embodiments of the present disclosure. However, one or more embodiments of the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order not to obscure one or more embodiments of the present disclosure.

[0014] Embodiments disclosed herein generally relate to dynamic random access memory (DRAM) devices and semiconductor manufacturing methods for such devices. For example, certain embodiments disclosed herein provide a processing system and method for forming DRAM array bit line contacts (BLCs) and storage node structures. Although generally described with reference to DRAM devices, the structures and methods disclosed herein may also be used to form other types of devices such as complementary metal oxide semiconductor (CMOS) devices.

[0015] In various embodiments, the method includes performing various processes of the processing system without breaking vacuum. Such processes can include performing a pre-cleaning process on an exposed surface of a source / drain region of a transistor of a substrate, where the source / drain region is exposed through a trench formed in a dielectric material formed over the source / drain region. Such processes can further include forming an epitaxial layer over the exposed source / drain region by an epitaxial deposition process, where the epitaxial layer is either doped or undoped. In certain embodiments, a metal silicide layer is formed over the epitaxial layer by a plasma enhanced deposition process, followed by in-situ nitridation to form a barrier or cap layer. In further embodiments, a metal layer is formed over the cap layer, for example, by a deposition process, and the substrate may then be subjected to further processing.

[0016] Integration processes can form contact structures that reduce leakage current and resistance, as well as improve thermal stability. Embodiments disclosed herein, without limitation, may be useful in creating DRAM bit line contacts and / or DRAM storage nodes with reduced contact resistance, thereby facilitating improvements to DRAM systems. Embodiments disclosed herein, without limitation, may also be useful in creating CMOS source / drain contacts.

[0017] As used herein, the term "approximately" refers to a variation of ±10% from the nominal value. It should be understood that such variation may be present in any value provided herein.

[0018] Figure 1 is a partial cross-sectional view of a device contact 100 along the length of a metal layer 116 formed on the device contact 100 according to an embodiment described herein. In a particular embodiment, the device contact 100 is a contact formed in a DRAM bit line structure. In a particular embodiment, the device contact 100 is formed in a contact region of a DRAM bit line array, and the contact region may include the contact and any adjacent structure, such as the source / drain region of a substrate. For example, the device contact 100 may be a bit line contact in a three-dimensional (3D) capacitor over bit-like structure. In a particular embodiment, the device contact 100 is a contact for the source-drain region of a CMOS logic device, such as an NMOS or PMOS transistor.

[0019] The device contact 100 includes a spacer layer 104 formed on the substrate 102. Generally, the substrate 102 includes any suitable type of semiconductor substrate and material. For example, the substrate 102 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), or III / V compound semiconductors, such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or similar materials. In certain embodiments, the substrate 102 is a silicon-on-insulator (SOI) substrate.

[0020] The substrate 102 can be doped with a p-type or n-type dopant to form a doped region 106. In one embodiment, the substrate 102 is doped with an n-type dopant such as phosphorus (P) or arsenic (As). In another embodiment, the substrate 102 is doped with a p-type dopant such as boron (B). The doped region 106 can form the source / drain region 107 of the transistor. In one example, the source / drain region 107 is either the source region or the drain region. In another example, the source / drain region 107 includes a merged source / drain region. In a particular embodiment, the source / drain region 107 is epitaxially grown on the substrate 102.

[0021] The spacer layer 104 is formed on the substrate 102 and can be fabricated from any suitable insulating material. For example, the spacer layer 104 may include oxides such as silicon dioxide (SiO2), or nitrides such as silicon nitride (Si3N4) and silicon carbonitride (SiCN), combinations thereof, or other dielectric materials. In certain examples, the spacer layer 104 includes tetraethyl orthosilicate (TEOS), phosphate glass (PSG), borosilicate glass (BSG), or spin-on dielectric (SOD). In certain embodiments, the spacer layer 104 is monolayer or multilayer. The spacer layer 104 can be formed by deposition processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), (e.g., high-density plasma CVD (HDPCVD)), and fluid CVD (FCVD), or by other suitable methods.

[0022] One or more trenches 108 are formed through the spacer layer 104 such that the trenches 108 penetrate the spacer layer 104 and partially expose the substrate 102 and / or source / drain region 107. The trenches 108 can be formed by any suitable patterning and material removal process, such as lithography, followed by dry etching, wet etching, or a combination of etching processes. Furthermore, the trenches 108 can have any suitable size and shape. In certain examples, the trenches 108 have a substantially circular or substantially rectangular shape when viewed from above (not shown).

[0023] The epitaxial layer 110 is formed on the substrate 102 within the trench 108. The epitaxial layer 110 is generally formed by a bottom-up growth process such as selective epitaxial growth (SEG) or deposition process. The epitaxial layer 110 of the device contact 100 is formed on a single substrate 102, but may be formed at separate times by separate epitaxial growth processes.

[0024] The epitaxial layer 110 may include any suitable silicon-containing semiconductor layer, such as a polysilicon epitaxial layer. In certain examples, the epitaxial layer 110 may contain Si, SiC, SiGe, or similar materials. The epitaxial layer 110 may be further doped with a p-type or n-type dopant, thereby forming a doped epitaxial layer. In certain examples, the epitaxial layer 110 is doped with an n-type dopant such as phosphorus, arsenic, antimony, or similar materials. In certain examples, the epitaxial layer 110 is doped with carbon. Thus, in certain embodiments, the epitaxial layer 110 is a high-strain insiturin-doped silicon (HS-Si:P) epitaxial layer, or a phosphorus and carbon-doped silicon (SiP:C) epitaxial layer. In certain embodiments, the epitaxial layer 110 is approximately 5 × 10⁻¹⁶ 21 atoms / cm 3 Or approximately 5 x 10 21 atoms / cm3 a phosphorus concentration less than, for example, about 1×10 21 or about 1×10 21 has a phosphorus concentration less than. In certain embodiments, the epitaxial layer 110 has a carbon concentration less than, for example, about 5×10 21 or about 5×10 21 For example, about 2.5×10 21 or about 2.5×10 21 such as a carbon concentration less than, for example, about 2.5×10 20 or about 2.5×10 20 has a carbon concentration less than, etc. In certain embodiments, the epitaxial layer 110 includes a gradient dopant concentration of phosphorus and / or carbon along its height.

[0025] As shown in Figures 1 and 2, the metal silicide layer 112 is formed on the epitaxial layer 110. The metal silicide layer 112 can be formed by selectively depositing a metal layer on the surface of the epitaxial layer 110 and / or on the exposed surface of the source / drain region 107, and in certain embodiments, by subsequent annealing. In certain embodiments, the metal silicide layer 112 is deposited directly on the epitaxial layer 110 and / or the source / drain region 107, but not on the spacer layer 104 (e.g., by selective epitaxial deposition). The metal silicide layer 112 can be a high-melting-point metal layer formed using a CVD process, PECVD process, HDPCVD process, PVD process, plating process, sputtering process, vapor deposition process, epitaxial deposition process, selective epitaxial deposition process, or any suitable process. In certain embodiments, the metal silicide layer 112 includes titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, ruthenium (Ru) silicide, tantalum (Ta) silicide, tungsten (W) silicide, molybdenum (Mo) silicide, their alloys, other suitable metal silicides, or any combination thereof. Further examples of metals for the metal silicide layer 112 include, but are not limited to, TiSi, RuSi, nickel-platinum (NiPt) alloys, nickel-palladium (NiPd), nickel-rhenium (NiRe), titanium-tantalum (TiTa), or titanium-niobium (TiNb).

[0026] In certain embodiments, the metal silicide layer 112 is formed in the same process chamber as the epitaxial layer 110. In certain embodiments, the metal silicide layer 112 is formed in a different process chamber than the epitaxial layer 110, but in the same processing system. In certain examples, the metal silicide layer 112 is formed in the epitaxial deposition chamber of the processing system. Since the epitaxial layer 110 and the metal silicide layer 112 are formed in the same processing system, there is no vacuum break between processes.

[0027] A cap layer 114 is formed on the device contact 100, for example, on the metal silicide layer 112 and the spacer layer 104. In certain embodiments, the cap layer 114 is formed by using a conformal deposition process that allows the cap layer 114 to be formed along the sidewall of the spacer layer 104, thereby forming a trench lined within it. The cap layer 114 acts as a barrier layer to prevent metal from a subsequently formed metal layer, for example, metal layer 116, from diffusing and reacting with the underlying metal silicide layer 112 and / or source / drain region 107. The cap layer 114 can also act as an adhesive layer to improve adhesion between the subsequent metal layer and the metal silicide layer 112. In certain embodiments, the cap layer 114 is a nitride layer. For example, the cap layer 114 may include, but is not limited to, TiN, Si3N4, or metallic silicon nitride. The cap layer 114 may include a metallic material containing a transition metal such as iridium (Ir) or molybdenum (Mo). In certain embodiments, the cap layer 114 is a nitride layer, such as a TiN layer, formed by a physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD) process, or a nitriding process. The nitriding process may include exposing the metal silicide layer 112 to a nitrogen-containing plasma or nitrogen-containing ambient environment so that nitrogen (N) atoms chemically react with atoms present on the exposed surface of the metal silicide layer 112 to form a surface nitride layer (e.g., the cap layer 114).

[0028] The metal layer 116 is formed on the surface of the cap layer 114 and can function as a bit line and / or storage node conductor metal. Examples of suitable materials for the metal layer 116 include, but are not limited to, W, Co, Cu, Al, Ru, Ti, Ag, platinum (Pt), palladium (Pa), their alloys, their derivatives, or any combination thereof. The metal layer 116 can be deposited on the cap layer 114 using one or more deposition processes such as CVD process, PECVD process, atomic layer deposition (ALD) process, plasma ALD (PEALD) process, physical vapor deposition (PVD) process, electroless plating process, electroplating (ECP) process, or other suitable deposition methods.

[0029] Figure 2A is a partial cross-sectional view of a DRAM system 200, including at least a portion of the device contacts 100 in Figure 1, as viewed in a plane perpendicular to the plane shown in Figure 1 (for example, across the metal layer 116a, which is the bit line in Figure 2A), according to an embodiment described herein. In certain embodiments, the DRAM system 200 is a 3D DRAM structure including a plurality of device contacts 100 and a plurality of storage nodes 201 arranged in an alternating array. For example, the DRAM system 200 can be a 3D capacitor-over-bit type structure.

[0030] As shown in Figure 2A, each of the contact devices 100 or "contact plugs" has a metal layer 116 formed on the source / drain region 107 and acting as a bit line formed thereon. The storage node 201 can have a structure substantially similar to the device contact 100 except for its size, and therefore can be formed in substantially the same manner. For reference, bit line contact structures such as the device contact 100 in Figure 2A can have cross-sectional dimensions of approximately 10 nm × 4 nm or approximately 8 nm × 4 nm.

[0031] Figure 2B is a partial cross-sectional view of the DRAM system 200 of Figure 2A, viewed in the same plane as shown in Figure 1 (for example, a plane perpendicular to the plane shown in Figure 2A and along the metal layer 116, which is the bit line). As shown in Figure 2B, the DRAM system 200 includes a plurality of contact devices 100 on which the bit line is formed, as well as embedded word lines 224 positioned between the contact devices 100. Each embedded word line 224 is positioned in a channel 208 formed in the substrate 102 between two source / drain regions 107 formed beneath the contact devices 100. The embedded word lines 224 partially fill the channel 208, which is backed by an insulating layer 226 conformally formed on its inner surface. A sealing layer 222 may be further formed on the remaining exposed surfaces of the embedded word lines 224 and the insulating layer 226, such that the sealing layer 206 has an upper surface that is flat with the upper surface of the substrate 102.

[0032] Similar to the metal layer 116, the embedded world line 224 can be formed from any suitable low-resistance metallic material. In certain embodiments, the embedded world line 224 is formed from W, Co, Cu, Al, Ru, Ti, Ag, platinum (Pt), palladium (Pa), their alloys, their derivatives, or any combination thereof. The seal layer 222 and / or insulating layer 226 can be formed from any suitable insulating material. For example, the seal layer 222 and / or insulating layer 226 may include oxides such as silicon dioxide (SiO2), or nitrides such as silicon nitride (Si3N4) and silicon carbonitride (SiCN), combinations thereof, or other dielectric materials. In certain examples, the seal layer 222 and / or insulating layer 226 include tetraethyl orthosilicate (TEOS), phosphate glass (PSG), borosilicate glass (BSG), or spin-on dielectric (SOD). In certain embodiments, the insulating layer 226 is monolayer or multilayer.

[0033] Figure 2C is a partial cross-sectional view of a portion of a CMOS device 250, including at least a portion of the device contacts 100 of Figure 1, according to embodiments described herein. The CMOS device 250 will include appropriate MOSFET device elements such as PMOS transistors and NMOS transistors. The portion of the CMOS device 250 shown in Figure 2C is formed on a substrate 102 and includes a gate 232 formed on the substrate 102, an insulating layer 230, and at least two source / drain regions 107. In Figure 2C, the device contacts 100 function as contacts for the source / drain regions 107 of the MOSFET device. Thus, each device contact 100 (two are shown in Figure 2C) is formed on at least a portion of the source / drain region 107 and on both sides of the transistor gate 232.

[0034] In some embodiments, at least one device contact 100 of the MOSFET devices in the CMOS device 250 is formed simultaneously with the device contact 100 of the DRAM system 200 and / or the device contacts and / or storage nodes of other devices or systems, including the storage node 201. For example, the source / drain region 107, device contact 100, and contact region of the CMOS device 250 can be formed simultaneously with and around the DRAM system 200, for example, on the same substrate 102. In certain examples, the device contact 100 of the CMOS device 250 and the DRAM system 200 are formed within or through a spacer layer 104 on the same substrate 102. In such embodiments, the device contacts 100 of the CMOS device 250 may include a carbon-doped, in certain examples, carbon-doped epitaxial layer 110 to improve the thermal stability of its metal silicide layer 112. In certain other examples, the device contacts 100 of the CMOS device 250 may be formed in or through a separate spacer layer on the same substrate 102 (e.g., a spacer layer other than spacer layer 104 on the substrate 102).

[0035] Figure 3 is a flowchart of a method 300 for forming a contact structure, such as a device contact 100, and / or a storage node, such as a DRAM storage node 201, according to embodiments described herein. Figures 4A to 4E show various diagrams of the device contact 100 during different steps of method 300, according to a particular embodiment. Therefore, Figures 3 and 4A to 4E are described together herein for clarity.

[0036] The steps of Method 300 are described in relation to Figures 3 and 4A-4E, but those skilled in the art will understand that any system configured to perform the steps of this Method in any order falls within the scope of the embodiments described herein. Furthermore, although Figures 4A-4E show Method 300 applied to the formation of device contacts 100, those skilled in the art will understand that Method 300 can also be used to form DRAM storage nodes 201. It should be further noted that Method 300 can be used to form any other semiconductor structures not presented herein. Those skilled in the art should understand that all processes and associated structures for forming semiconductor devices are not shown in the drawings or described herein. Contacts may be part of a DRAM bitline structure, a storage node, a transistor (e.g., an nMOS transistor), a CMOS device, or other semiconductor device.

[0037] Method 300 begins in step 302 and Figure 4A, where a substrate 102 on which a patterned spacer layer 104 is formed is optionally subjected to one or more pre-cleaning processes in one or more process chambers of a processing system. As described above, the substrate 102 may include any suitable type of semiconductor substrate and material, e.g., Si, Ge, SiGe, III / V compound semiconductors, or similar materials. In certain embodiments, the substrate 102 includes doped regions 106 on which source / drain regions 107 of a transistor can be formed. The spacer layer 104 is formed on the substrate 102 and includes any suitable type of insulating material. The spacer layer 104 may be formed in the same or different process chamber and / or processing system as one or more pre-cleaning processes in step 302 by a deposition process (not shown), such as a CVD process.

[0038] As shown in Figure 4A, a trench 108 is formed in the spacer layer 104 such that a portion of the surface of the doped region 106 of the substrate 102 is exposed. The trench 108 can be formed in the same or different process chamber and / or processing system as one or more pre-cleaning processes of step 302 by any suitable removal process (not shown), such as an etching process using a mask pattern (not shown). In certain embodiments, the removal process is a chemical dry etching process, a wet etching process, or a combination thereof. In certain embodiments, a dry etching process is used in the process chamber to form the trench 108 in the spacer layer 104.

[0039] One or more pre-cleaning processes in step 302 may include wet or dry cleaning processes. In certain embodiments, one or more pre-cleaning processes are performed in one or more vacuum process chambers using a remote plasma source. For example, one or more pre-cleaning processes may include exposing the substrate 102 to a nitrogen-based plasma such as a hydrogen (H2) and / or chlorine (Cl2) based plasma, and / or nitrogen trifluoride (NF3) and / or ammonia (NH3) plasma. In other examples, one or more pre-cleaning processes may include exposing the substrate 102 to an inert gas-containing plasma in a first process chamber of the processing system. One or more pre-cleaning processes can remove native oxides and / or carbon, as well as damaged layers on the substrate 102, from the substrate 102.

[0040] A suitable example of a first process chamber for performing a pre-cleaning process includes the AKTIV Pre-Clean® SiCoNi® cleaning chamber, available from Applied Materials, Inc. (Santa Clara, California). In certain other examples, pre-cleaning may be performed in an etching chamber, such as an etching chamber using an inductively coupled plasma (ICP) source. One example of an etching chamber is the improved Decoupled Plasma Source (DPS) etching chamber, available from Applied Materials, Inc. (Santa Clara, California). However, it is further intended that other well-configured chambers from other manufacturers may also be implemented to perform the pre-cleaning process described herein.

[0041] In step 304 and Figure 4B, the epitaxial layer 110 is formed within the trench 108, filling a portion of it. The epitaxial layer 110 may contain any suitable silicon-containing material and may be formed by a bottom-up growth process such as a selective epitaxial deposition process. For example, the epitaxial layer 110 may be formed via CVD, PECVD, low-pressure CVD (LPCVD), very low-pressure CVD (VLPCVD), very high-vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD), atomic pressure CVD (APCVD), molecular beam epitaxy (MBE), or similar processes.

[0042] The epitaxial layer 110 can be further doped by an in-situ doping process. For example, the in-situ doping process can be carried out by supplying a dopant gas while the silicon-containing epitaxial layer 110 is being grown using a silicon source gas. In certain embodiments, the epitaxial layer 110 is a highly strained Si layer in-situ doped with phosphorus and / or carbon. In such embodiments, the epitaxial deposition and dopant immersion processes can be carried out in a temperature range between about 450°C and about 550°C, for example, about 500°C, and in a pressure range between about 10 Torr and about 80 Torr, for example, between about 30 Torr and about 60 Torr, for example, about 50 Torr.

[0043] In certain embodiments, the doping process includes flowing a phosphorus-based gas, such as phosphine (PH3), into the process chamber at a flow rate between approximately 500 sccm and approximately 1500 sccm, for example between approximately 750 sccm and approximately 1250 sccm, for example between approximately 900 sccm and approximately 1100 sccm, for example, approximately 1000 sccm. In certain embodiments, the doping process includes flowing a carbon-based gas into the process chamber at a flow rate between approximately 30 sccm and approximately 200 sccm, for example between approximately 50 sccm and approximately 150 sccm, for example between approximately 75 sccm and approximately 125 sccm, for example, approximately 100 sccm. In certain embodiments, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 A silicon source gas, such as tetrasilane (SiH2Cl2), or a combination thereof, is flowed into the process chamber at a flow rate between approximately 50 sccm and approximately 200 sccm, for example between approximately 75 sccm and approximately 175 sccm, for example between approximately 100 sccm and approximately 150 sccm, for example, approximately 125 sccm. In certain embodiments, hydrogen chloride (HCl) gas is flowed into the process chamber at a flow rate between approximately 50 sccm and approximately 500 sccm, for example between approximately 100 sccm and approximately 400 sccm, for example between approximately 200 sccm and approximately 300 sccm, for example, approximately 250 sccm. In one example, the epitaxial silicon layer deposition process uses tetrasilane (SiH2Cl2). 10 The mixture is flowed at 11 sccm and executed on the substrate at a deposition pressure of 40 Torr while a hydrogen-containing carrier gas is flowed at 5 SLM for approximately 712 seconds at a temperature of 450°C.

[0044] In further embodiments, the epitaxial layer 110 may include a SiGe layer doped with an N-type dopant, or a SiC layer doped with an N-type dopant.

[0045] The epitaxial deposition and doping processes may be carried out in a second process chamber of the processing system described herein. One example of a suitable chamber is the reduced-pressure (RP) Epi chamber available from Applied Materials, Inc. (Santa Clara, California). However, it is further intended that other well-configured chambers from other manufacturers may also be implemented to carry out the deposition processes described herein.

[0046] In step 306 and Figure 4C, the metal silicide layer 112 is formed on the epitaxial layer 110 and / or on the exposed surface of the source / drain region 107. In certain embodiments, the metal silicide layer 112 is conformally formed on the epitaxial layer 110 and / or on the exposed surface of the source / drain region 107 to partially fill the trench 108. The metal silicide layer 112 can be a silicitable, high-melting-point metal layer formed using an ALD process, CVD process, PECVD process, HDPCVD process, PVD process, plating process, sputtering process, vapor deposition process, or any suitable process followed by annealing to induce a silicide reaction. In certain embodiments, the metal silicide layer 112 is a Ti layer deposited by PECVD and then annealed.

[0047] In certain embodiments, the metal silicide layer 112 is formed by a CVD or epitaxial deposition process without annealing. For example, the metal silicide layer 112 may be formed on the source / drain region 107 of the epitaxial layer 110 and / or the substrate 102 as a result of a selective epitaxial deposition process, but not on the spacer layer 104. The metal silicide layer 112 may include titanium silicide, cobalt silicide, ruthenium silicide, tungsten silicide, molybdenum silicide, combinations thereof, or other suitable metal silicides.

[0048] In certain embodiments, the deposition of the metal silicide layer 112 is carried out in the same chamber in which the epitaxial layer 110 is formed, such as a second chamber of the processing system described herein. In certain other embodiments, the metal silicide layer 112 is deposited in a third process chamber. Thus, the metal silicide layer 112 can be formed in-situ on top of the epitaxial layer 110. By performing steps 302-306 in-situ, interfacial contamination between the substrate 102, the epitaxial layer 110, and the metal silicide layer 112 can be significantly reduced, thereby reducing the overall resistance of the final device contact 100 and improving thermal stability.

[0049] In certain embodiments, the annealing process is performed on the deposited metal silicide layer 112 in a second, third, or fourth process chamber of the processing system described herein. In certain embodiments, the third or fourth process chamber is a rapid thermal annealing (RTA) chamber. One example of a suitable RTA chamber is the Vantage® RADOX® RTP chamber, available from Applied Materials, Inc. (Santa Clara, California). However, it is further intended that other appropriately configured chambers from other manufacturers may also be implemented to perform the deposition process described herein.

[0050] In step 308 and Figure 4D, a capping layer 114 is formed on the device contact 100, for example, on the metal silicide layer 112 and the spacer layer 104. At this point, the device contact 100 may be referred to as a "contact plug". In certain embodiments, the capping layer 114 is a nitride layer formed by a nitriding process. The nitriding process can be carried out in the same or a different chamber as the formation of the metal silicide layer 112 and / or the epitaxial layer 110. For example, the nitriding process can be carried out in a second or third process chamber together with the deposition of the epitaxial layer 110 and the metal silicide layer 112, thereby further reducing interfacial contamination within the device contact 100. The nitriding process in step 308 provides improved thermal stability to the metal silicide layer 112, thereby reducing the possibility of degradation and / or oxidation of the metal silicide layer 112 during subsequent processing with a high heat balance. Generally, the cap layer 114 can have a thickness of about 5 nm or less than about 5 nm, for example, about 2 nm or less than about 2 nm.

[0051] In certain embodiments, the nitriding process is a plasma nitriding process utilizing a mixture of nitrogen (N2) gas, hydrogen (H2) gas, and / or argon (Ar) gas. In certain embodiments, the plasma nitriding process is performed at a pressure between approximately 5 Torr and approximately 50 Torr using RF power between approximately 100 W and approximately 1000 W.

[0052] In step 310 and in Figure 4E, the metal layer 116 is formed on the cap layer 114. The metal layer 116 is formed on the surface of the cap layer 114 and can function as a bit-line conductor metal, sometimes simply called a bit line. In certain embodiments, a seed layer (not shown) and / or a barrier layer (not shown) are formed between the cap layer 114 and the metal layer 116 and may contain materials similar to or different from the metal layer 116.

[0053] Examples of suitable materials for the metal layer 116 include, but are not limited to, W, Co, Cu, Al, Ru, Ti, Ag, Pt, Pa, their alloys, their derivatives, or any combination thereof. The metal layer 116 can be deposited on the cap layer 114 using one or more deposition processes, such as a CVD process, PECVD process, ALD process, PEALD process, PVD process, plating process, ECP process, or other suitable deposition method. The formation of the metal layer 116 can be carried out in a third, fourth, or fifth process chamber of the processing system. In certain embodiments, the metal layer 116 is formed in a CVD chamber. One example of a suitable CVD chamber is the Volta® CVD chamber, available from Applied Materials, Inc. (Santa Clara, California). However, it is further intended that other appropriately configured chambers from other manufacturers may also be implemented to carry out the deposition processes described herein.

[0054] After the formation of the metal layer 116, the device contact 100 can undergo further processes used to complete a CMOS device and / or a DRAM device, such as a DRAM bit line array.

[0055] Examples of processing systems that can be appropriately modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems, or other suitable processing systems, commercially available from Applied Materials, Inc. (Santa Clara, California). It is intended that other processing systems (including those from other manufacturers) may be configured to benefit from the embodiments described herein.

[0056] Figure 5 shows a schematic top view of a multi-chamber processing system 500 according to one embodiment. The multi-chamber processing system 500 is configured to perform various semiconductor processing methods, such as method 300 described above, on one or more substrates. As shown in the figure, the multi-chamber processing system 500 includes a plurality of process chambers 502, 514, and 516, a first transfer chamber 504, a pass-through chamber 506, a second transfer chamber 510, a load-lock chamber 512, a factory interface 520, one or more pods 530, and a system controller 580.

[0057] Each of the process chambers 502 is coupled to a first transfer chamber 504. The first transfer chamber 504 is further coupled to a first pair of pass-through chambers 506. The first transfer chamber 504 has a centrally located transfer robot (not shown) for transferring substrates between the pass-through chambers 506 and the process chambers 502. The pass-through chambers 506 are coupled to a second transfer chamber 510, which is coupled to process chambers 514 and 516 configured to perform a pre-cleaning process (step 302) and / or an annealing process as an option. The second transfer chamber 510 has a load-lock chamber 512 and a centrally located transfer robot (not shown) for transferring substrates between the pass-through chambers 506 and the process chambers 514 and / or the process chambers 516. The factory interface 520 is connected to the second transfer chamber 510 by the load-lock chamber 512. The factory interface 520 is coupled to one or more pods 530 on the opposite side of the load lock chamber 512. The pods 530 are typically forward-opening unified pods (FOUPs) accessible from the cleanroom.

[0058] In certain embodiments, the substrate is transferred from pod 530 to process chambers 514 and / or 516, where a pre-cleaning process (e.g., step 302) is performed to remove contaminants such as carbon or oxide contaminants from the exposed surfaces of the source / drain regions of the transistors on the substrate. The substrate is then transferred to one or more process chambers 502, where an epitaxial layer is deposited (e.g., step 304, such as SEG of SiCP or SiP), a silicide layer is deposited (e.g., step 306, such as PECVD of Ti or Mo), an optional cap layer is formed (e.g., step 308, such as nitriding of a Ti layer to form TiN), and a metal layer is deposited (e.g., step 310, such as CVD of W). Since all these steps 302-310 are performed within the same processing system, the vacuum is not broken when the substrate is transferred to different chambers, which reduces the opportunity for contamination, improves the quality of the deposited epitaxial film, and thereby reduces the contact resistance of the formed contact structure.

[0059] The system controller 580 is coupled to the processing system 500. The system controller 580 controls the processing system 500 or its components. For example, the system controller 580 controls the process of the processing system 500 by using the chambers 502, 504, 506, 510, 512, 514, 516, and / or the factory interface 520, and / or the pod 530 of the processing system 500, or by controlling the controllers associated with the chambers 502, 504, 506, 510, 512, 514, 515, and / or the factory interface 520, and / or the pod 530. During the process, the system controller 580 enables data collection and feedback from each chamber to adjust the performance of the processing system 500.

[0060] As shown in the figure, the system controller 580 includes a central processing unit (CPU) 582, memory 584, and support circuitry 586. The CPU 582 can be one of any form of general-purpose processor used in an industrial environment. The memory 584 can include non-temporary computer-readable media and / or machine-readable storage devices. The memory 584 is accessible by the CPU 582 and can be one or more of the following: random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage. The support circuitry 586 is coupled to the CPU 582 and can include a cache, clock circuitry, input / output subsystems, power supply, etc. The system controller 580 is configured to execute the steps of method 300 stored in the memory 584. Various embodiments disclosed in this disclosure can generally be implemented by executing computer instruction code stored in the memory 584 (or in the memory of a particular process chamber) as, for example, a computer program product or software routine, under the control of the CPU 582. In other words, the computer program product is tangibly embodied on memory 584 (or a non-temporary computer-readable medium or machine-readable storage device). When computer instruction code is executed by CPU 582, CPU 582 controls the chamber to perform processes according to various embodiments.

[0061] As described above, methods and processing systems for forming semiconductor device contacts are provided herein. In certain embodiments, the methods and systems provided herein can be used to form dynamic random access memory (DRAM) array bit-line contacts (BLCs), storage nodes, and reduced-thickness CMOS device contacts.

[0062] The processing system includes multiple process chambers configured to clean, deposit, etch, and / or anneal a substrate on which a semiconductor device contact structure is formed. The chambers are integrated into a single integrated system, which has previously been found difficult due to the high sensitivity of epitaxy chambers to contamination. By integrating at least the epitaxy chamber with the metal deposition chamber, the various steps of the contact formation method described herein can be performed within the same processing system. Thus, the vacuum is not broken while the substrate is transferred between the various process chambers, thereby reducing the opportunity for interfacial contamination and improving the quality of the deposited layer. Furthermore, this processing system and method provides a highly nitrided metal silicide layer, thereby improving its thermal stability and reducing degradation during subsequent heat treatment. As a result, the integration process described herein can form a contact structure with reduced resistance. Exemplary Embodiments

[0063] Embodiment 1 A method for forming a device contact, comprising: depositing a doped semiconductor layer on an exposed surface of a first doped region of a substrate in a first chamber, wherein the first doped region is exposed through a trench formed in a dielectric material formed on the first doped region; depositing a metal silicide layer on the doped semiconductor layer; and exposing the metal silicide layer to a nitriding process to form a nitride layer on the metal silicide layer, wherein the semiconductor layer, the metal silicide layer, and the nitride layer are formed without breaking the vacuum; the doped semiconductor layer and the metal silicide layer form a bit line contact plug for a dynamic random access memory (DRAM) device; and the DRAM device includes a word line formed between a first doped region and a second doped region of the substrate and a bit line formed on the bit line contact plug, comprising forming a nitride layer.

[0064] Embodiment 2 The method according to Embodiment 1 described above, wherein the doped semiconductor layer is a high-distortion inciturin-doped silicon (HS-Si:P) layer or a phosphorus and carbon-doped silicon (SiP:C) layer.

[0065] Embodiment 3 The semiconductor layer is approximately 1 × 10 21 atoms / cm 3 Or approximately 1 × 10 21 atoms / cm 3 The method according to Embodiment 2 described above, having a phosphorus concentration of less than [amount missing].

[0066] Embodiment 4 The method according to Embodiment 1 described above, wherein a metal silicide layer is deposited in a first chamber by a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, a high-density plasma CVD (HDPCVD) process, a physical vapor deposition (PVD) process, a plating process, a sputtering process, or a vapor deposition process.

[0067] Embodiment 5 The method according to Embodiment 4 described above, wherein the metal silicide layer comprises titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), molybdenum (Mo), or an alloy thereof.

[0068] Embodiment 6 The method according to Embodiment 1, wherein the nitride layer is a titanium nitride (TiN) layer.

[0069] Embodiment 7 The method according to Embodiment 1, further comprising pre-cleaning the substrate in a second chamber before depositing the doped semiconductor layer, wherein the pre-cleaning and the formation of the doped semiconductor layer, the metal silicide layer, and the nitride layer are performed without breaking the vacuum.

[0070] Embodiment 8 The method according to Embodiment 1, further comprising depositing a conductive layer on a nitride layer in a second chamber, wherein the formation of the doped semiconductor layer, the metal silicide layer, the nitride layer, and the conductive layer is carried out without breaking the vacuum, and the conductive layer forms a bit line on the bit line contact plug.

[0071] Embodiment 9 The method according to Embodiment 8, wherein the conductive layer is deposited by a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a plasma ALD (PEALD) process.

[0072] Embodiment 10 The method according to Embodiment 9, wherein the conductive layer comprises tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), silver (Ag), platinum (Pt), palladium (Pa), or an alloy thereof.

[0073] Embodiment 11 A method for forming device contacts, comprising: pre-cleaning a substrate in a first chamber; depositing a doped semiconductor layer on the exposed surface of a plurality of doped regions of the substrate in a second chamber, wherein the doped regions are exposed through trenches formed in a dielectric material formed on the plurality of doped regions; and depositing a metal silicide layer on the doped semiconductor layer in a third chamber, wherein the doped semiconductor layer and the metal silicide layer form a bit line contact plug for a dynamic random access memory (DRAM) device. A method comprising depositing layers, exposing a metal silicide layer to a nitriding process to form a nitride layer on the metal silicide layer, and depositing a conductive layer on the nitride layer in a fourth chamber, wherein the conductive layer forms a bit line on a bit line contact plug, and the cleaning and formation of the doped semiconductor layer, metal silicide layer, nitride layer, and conductive layer are performed without breaking the vacuum, and the DRAM device further includes a word line, the word line is located within a portion of the substrate and the conductive layer is formed between a first doped region and a second doped region of a plurality of doped regions.

[0074] Embodiment 12 The method according to Embodiment 11, wherein the doped semiconductor layer is a high-distortion inciturin-doped silicon (HS-Si:P) layer or a phosphorus and carbon-doped silicon (SiP:C) layer.

[0075] Embodiment 13 The semiconductor layer is approximately 1 × 10 21 atoms / cm 3 Or approximately 1 × 10 21 atoms / cm 3 The method according to Embodiment 12, having a phosphorus concentration of less than [amount missing].

[0076] Embodiment 14 The method according to Embodiment 11, wherein the metal silicide layer is deposited by a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, a high-density plasma CVD (HDPCVD) process, a physical vapor deposition (PVD) process, a plating process, a sputtering process, or a vapor deposition process.

[0077] Embodiment 15 The method according to Embodiment 14, wherein the metal silicide layer comprises titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), molybdenum (Mo), or an alloy thereof.

[0078] Embodiment 16 The method according to Embodiment 11, wherein the nitride layer is a titanium nitride (TiN) layer.

[0079] Embodiment 17 A processing system comprising: a system controller; a first process chamber configured such that the system controller causes a pre-cleaning process to be performed on a doped region at the bottom of a trench formed in a dielectric layer on a substrate; a second process chamber configured such that the system controller causes a doped epitaxial layer and a metal silicide layer to be formed on the exposed surface of the doped region of the substrate, the doped epitaxial layer and the metal silicide layer to form a bit line contact plug for a dynamic random access memory (DRAM) device, and a nitriding process to be performed on the metal silicide layer to form a nitride layer; and a third process chamber configured such that the system controller causes a conductive layer to be formed on the nitride layer, the conductive layer to form a bit line on the bit line contact plug, and the processing system is configured to transfer the substrate between the first process, the second process chamber and the third process chamber without breaking the vacuum.

[0080] Embodiment 18 The processing system according to Embodiment 17, wherein the doped epitaxial layer is a high-strain inciturin-doped silicon (HS-Si:P) layer or a phosphorus and carbon-doped silicon (SiP:C) layer.

[0081] Embodiment 19 The doped epitaxial layer is approximately 1 × 10⁻⁶ 21 atoms / cm 3 Or approximately 1 × 10 21 atoms / cm 3 The processing system according to Embodiment 17, having a phosphorus concentration of less than [amount missing].

[0082] Embodiment 20 The processing system according to Embodiment 17, wherein the metal silicide layer comprises titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), molybdenum (Mo), or an alloy thereof.

[0083] Embodiment 21 A processing system comprising a transfer chamber, a plurality of process chambers coupled to the transfer chamber, and a system controller configured to cause the process system to execute a process including: performing a pre-cleaning process on a substrate; forming a doped epitaxial semiconductor layer on a doped region of the substrate; forming a metal silicide layer on the doped epitaxial semiconductor layer; exposing the metal silicide layer to a nitriding process to form a nitride layer on the metal silicide layer; and depositing a conductive layer on the nitride layer, wherein the pre-cleaning and the formation of the doped epitaxial semiconductor layer, the metal silicide layer, and the nitride layer are performed without breaking the vacuum, and the deposition of the conductive layer is performed.

[0084] Embodiment 22 The processing system according to Embodiment 21, wherein the doped epitaxial semiconductor layer is a high-strain inciturin-doped silicon (HS-Si:P) layer or a phosphorus- and carbon-doped silicon (SiP:C) layer, and the metal silicide layer comprises titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), molybdenum (Mo), or an alloy thereof.

[0085] Embodiment 23 The doped epitaxial semiconductor layer is approximately 1 × 10⁻⁶ 21 atoms / cm 3 Or approximately 1 × 10 21 atoms / cm 3 The processing system according to embodiment 22, having a phosphorus concentration of less than [amount missing].

[0086] While the foregoing relates to embodiments of the present disclosure, other and further embodiments of the present disclosure can be conceived without departing from its basic scope, the scope of which is determined by the following claims.

Claims

1. A method for forming a dynamic random access memory (DRAM) device, Forming a plurality of bit line contact regions in an array on the DRAM device, wherein each of the bit line contact regions is formed Forming multiple source / drain contact regions, When depositing a doped semiconductor layer on a first doped region, the doped semiconductor layer is deposited on each of the source / drain contact regions, and the doped semiconductor layer is deposited such that the first doped region is exposed through trenches in the dielectric material formed on the first doped region of the substrate. Depositing a metal silicide layer on the doped semiconductor layer, The process involves forming a nitride layer on the metal silicide layer, wherein the doped semiconductor layer, the metal silicide layer, and the nitride layer are formed in a single processing system without breaking the vacuum, and the single processing system comprises a plurality of process chambers for forming the nitride layer. Forming multiple bit line contact regions in an array, including A method comprising, wherein the doped semiconductor layer comprises a silicon layer doped solely with carbon, and the carbon concentration is less than about 5 × 10²¹ atoms / cm³ or less than about 5 × 10²¹ atoms / cm³.

2. The doped semiconductor layer comprises a silicon layer doped with phosphorus and carbon, wherein the phosphorus is approximately 5 × 10 ２１ atoms / cm ３ Or approximately 5 x 10 ２１ atoms / cm ３ Having a concentration of less than 5 × 10, the carbon is approximately 5 × 10 ２１ atoms / cm ３ Or approximately 5 x 10 ２１ atoms / cm ３ The method according to claim 1, having a concentration less than [amount missing].

3. The method according to claim 1, wherein the doped semiconductor layer is deposited by an epitaxial deposition process.

4. The method according to claim 1, wherein the metal silicide layer is deposited by a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, a high-density plasma CVD (HDPCCVD) process, a physical vapor deposition (PVD) process, a plating process, a sputtering process, or a vapor deposition process.

5. The method according to claim 4, wherein the metal silicide layer comprises at least one of titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), molybdenum (Mo), and tungsten (W).

6. Exposing the first doped region to a pre-cleaning process before depositing the doped semiconductor layer, wherein the pre-cleaning process, and the formation of the doped semiconductor layer, the metal silicide layer, and the nitride layer, are performed in a single processing system without breaking the vacuum. The method according to claim 1, further comprising:

7. A conductive layer is deposited on the nitride layer, wherein the conductive layer forms a bit line on the bit line contact region. The method according to claim 6, further comprising:

8. The method according to claim 7, wherein the formation of the doped semiconductor layer, the metal silicide layer, the nitride layer, and the conductive layer is carried out in the single processing system without breaking the vacuum.

9. The method according to claim 1, wherein the nitride layer is formed by exposing the metal silicide layer to a nitriding process.

10. A method for forming a dynamic random access memory (DRAM) device, Forming a plurality of bit line contact regions in an array on the DRAM device, wherein each of the bit line contact regions is formed Exposing a first doped region in a first chamber to a pre-cleaning process, wherein the first doped region is exposed through a trench formed in the dielectric material formed on the first doped region of the substrate. In the second chamber, a doped semiconductor layer is deposited on the first doped region, In the third chamber, a metal silicide layer is deposited on the doped semiconductor layer, The process involves subjecting the metal silicide layer to a nitriding process to form a nitride layer on the metal silicide layer, A method for depositing a conductive layer on the nitride layer in a fourth chamber, wherein the pre-cleaning process and the formation of the doped semiconductor layer, the metal silicide layer, and the nitride layer are carried out without breaking the vacuum. Forming multiple bit line contact regions in an array, including Includes, A method wherein the doped semiconductor layer is a high-distortion inciturin-doped silicon (HS-Si:P) layer.

11. The method according to claim 10, wherein the pre-cleaning process and the formation of the doped semiconductor layer, the metal silicide layer, the nitride layer, and the conductive layer are carried out without breaking the vacuum.

12. The method according to claim 10, wherein the metal silicide layer is deposited by a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, a high-density plasma CVD (HDPCCVD) process, a physical vapor deposition (PVD) process, a plating process, a sputtering process, or a vapor deposition process.

13. The method according to claim 12, wherein the metal silicide layer comprises titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), molybdenum (Mo), or an alloy thereof.

14. The method according to claim 10, wherein the doped semiconductor layer is deposited by an epitaxial deposition process.

15. A processing system, Transfer chamber and A plurality of process chambers coupled to the transfer chamber, A system controller configured to cause the processing system to execute a process including the method described in any one of claims 10 to 14. A processing system equipped with the following features.

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