Nitride semiconductor devices

Abstract

This nitride semiconductor device comprises: a substrate; a drift layer of a first conductivity type; a first underlayer of a second conductivity type; an intermediate high-resistance layer which has a higher resistance than the first underlayer; a second underlayer of the second conductivity type; a gate opening which passes through the second underlayer, the intermediate high-resistance layer, and the first underlayer to the drift layer; a semiconductor lamination film which has a channel region of the first conductivity type, a part of which is disposed along an inner surface of the gate opening, another part of which is disposed above the second underlayer; a threshold value adjustment layer of the second conductivity type; a gate electrode; a source electrode which is disposed apart from the gate electrode; and a drain electrode which is disposed on the lower surface side of the substrate.

Description

Technical Field

[0001] The present disclosure relates to nitride semiconductor devices.

Background Art

[0002] Nitride semiconductors such as GaN (gallium nitride) are wide-gap semiconductors with a large bandgap, have a high breakdown electric field strength, and have the feature that the saturation drift velocity of electrons is large compared to GaAs (gallium arsenide) semiconductors or Si (silicon) semiconductors. Therefore, research and development of power transistors using nitride semiconductors, which are advantageous for increasing output power and withstand voltage, have been carried out.

[0003] For example, Patent Documents 1 and 2 disclose a vertical field-effect transistor (FET: Field Effect Transistor) including a regrowth layer positioned to cover an opening provided in a GaN-based laminate and a gate electrode positioned on the regrowth layer along the regrowth layer. A channel is formed by a two-dimensional electron gas (2DEG: 2-Dimensional Electron Gas) generated in the regrowth layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

[0005] There is room for improvement in the electrical characteristics of the above conventional semiconductor devices.

[0006] The present disclosure provides a nitride semiconductor device with improved electrical characteristics. <00000​A nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first semiconductor layer of a first conductivity type disposed above the substrate, a second semiconductor layer of a second conductivity type disposed above the first semiconductor layer, a third semiconductor layer disposed above the second semiconductor layer and having a higher resistance than the second semiconductor layer, a fourth semiconductor layer of the second conductivity type disposed above the third semiconductor layer, and a fifth semiconductor layer having a channel region of the first conductivity type. A part of the fifth semiconductor layer is disposed along an inner surface of a first opening that penetrates the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer to reach the first semiconductor layer, and another part of the fifth semiconductor layer is disposed above the fourth semiconductor layer. ,of It comprises.

[0008] According to the present disclosure, a nitride semiconductor device with improved electrical characteristics can be provided.

Brief Description of Drawings

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a nitride semiconductor device according to Embodiment 1. [Figure 2] FIG. 2 is a plan view of a nitride semiconductor device according to Embodiment 1. [Figure 3] FIG. 3 is a cross-sectional view of a nitride semiconductor device according to a modification of Embodiment 1. [Figure 4] FIG. 4 is a cross-sectional view of a nitride semiconductor device according to Embodiment 2. [Figure 5] FIG. 5 is a cross-sectional view of a nitride semiconductor device according to Modification 1 of Embodiment 2. [Figure 6] FIG. 6 is a cross-sectional view of a nitride semiconductor device according to Modification 2 of Embodiment 2.

Modes for Carrying Out the Invention

[0010] (Findings on which the present disclosure is based) The inventors of the present invention have found that the following problems arise with the conventional nitride semiconductor devices described in the "Background Art" section.

[0011] In the nitride semiconductor devices disclosed in Patent Documents 1 and 2, a high-resistance GaN layer is placed between the p-type underlayer and the channel (two-dimensional electron gas) to prevent the formation of a parasitic npn bipolar structure between the n-type drift layer, the p-type underlayer, and the n-type channel. This improves the off-characteristics of the transistor.

[0012] However, during switching operation, there is a risk that electrons in the channel may be trapped in this high-resistance GaN layer. This is because carbon (C) or iron (Fe) doped into the high-resistance GaN layer generates trap levels. Electron trapping can degrade the dynamic characteristics of the transistor.

[0013] Therefore, this disclosure provides a nitride semiconductor device including a transistor in which the off-pass characteristics are improved while suppressing the degradation of the dynamic characteristics.

[0014] A nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first semiconductor layer of a first conductivity type disposed above the substrate, a second semiconductor layer of a second conductivity type disposed above the first semiconductor layer, a third semiconductor layer having a higher resistance than the second semiconductor layer and disposed above the second semiconductor layer, a fourth semiconductor layer of the second conductivity type disposed above the third semiconductor layer, and a fifth semiconductor layer having a channel region of the first conductivity type, wherein a portion of the fifth semiconductor layer is disposed along the inner surface of a first opening that penetrates the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer and reaches the first semiconductor layer, and another portion of the fifth semiconductor layer is disposed above the fourth semiconductor layer. ,of Prepare.

[0015] As a result, the fourth semiconductor layer is positioned above the high-resistance third semiconductor layer, making it less likely for electrons to be trapped in the trap levels generated in the third semiconductor layer. Therefore, the degradation of the transistor's dynamic characteristics can be suppressed.

[0016] Furthermore, if the sole purpose is to suppress electron trapping, it is conceivable to place a high-resistance third semiconductor layer at the bottommost pn junction (specifically, in contact with the upper surface of the first semiconductor layer). However, high-resistance third semiconductor layers tend to have reduced crystal quality due to doping with carbon, etc. Therefore, if a high-resistance third semiconductor layer is provided at the pn junction where a high electric field is applied during the off state, the off characteristics may deteriorate. In contrast, according to the nitride semiconductor device of this embodiment, a second semiconductor layer is placed below the third semiconductor layer, and a pn junction is formed between the second semiconductor layer and the first semiconductor layer, thus improving the off characteristics.

[0017] Also, for example, A nitride semiconductor device according to one aspect of the present disclosure comprises a drain electrode disposed on the lower side of the substrate, The fifth semiconductor layer includes an electron transport layer and an electron supply layer disposed above the electron transport layer, and the distance between the bottom of the electron supply layer and the drain electrode may be shorter than the distance between the bottom of the third semiconductor layer and the drain electrode.

[0018] The electron transport layer and the electron supply layer can be formed continuously by crystal growth. Therefore, the pn junction at the interface between the electron transport layer and the electron supply layer (i.e., the pn junction at the gate) has fewer energy levels caused by impurities or damage, making it the part of the nitride semiconductor device that can withstand the highest electric field strength. By bringing the pn junction at the gate closer to the drain electrode, the electric field generated between the gate electrode or source electrode and the drain electrode during the off state can be concentrated at the pn junction at the gate. This suppresses the concentration of the electric field in weaker areas, improving the off-state characteristics.

[0019] Furthermore, for example, nitride semiconductor devices according to one aspect of this disclosure S , The device comprises a sixth semiconductor layer of the second conductivity type disposed above the fifth semiconductor layer, a gate electrode disposed above the sixth semiconductor layer, and a source electrode disposed spaced apart from the gate electrode.The source electrode may be a second opening spaced apart from the gate electrode, and may be provided along the inner surface of the second opening that penetrates the fifth semiconductor layer and reaches the fourth semiconductor layer.

[0020] As a result, the channel is exposed to the inner surface of the second opening, allowing the source electrode to contact the channel at this exposed portion. This reduces the ohmic contact resistance between the source electrode and the channel. Furthermore, since a high-resistance third semiconductor layer is positioned below the fourth semiconductor layer that the source electrode contacts at the bottom of the second opening, it is possible to suppress the flow of current through the parasitic pn diode formed between the source and drain. This improves the reliability of the nitride semiconductor device.

[0021] Furthermore, for example, a nitride semiconductor device according to one aspect of this disclosure in teeth, The source electrode is It is provided spaced apart from the gate electrode. The third opening , a third aperture that penetrates the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer and reaches the second semiconductor layer. department It does not need to be positioned along the inner surface.

[0022] As a result, the channel is exposed to the inner surface of the third opening, allowing the source electrode to contact the channel at this exposed portion. This reduces the ohmic contact resistance between the source electrode and the channel. Furthermore, since the source electrode contacts both the fourth and second semiconductor layers, the potential of each semiconductor layer can be firmly fixed. This further improves the off-characteristics of the nitride semiconductor device.

[0023] Furthermore, for example, the third semiconductor layer may contain C, Fe, B, or Mg.

[0024] This makes it possible to easily form a third semiconductor layer with high resistance through methods such as doping during crystal growth or ion implantation after growth.

[0025] Furthermore, for example, the first semiconductor layer may be composed of multiple layers with different impurity concentrations, and the impurity concentration of the uppermost layer among the multiple layers may be the lowest among the multiple layers.

[0026] As a result, the impurity concentration near the pn junction between the first and second semiconductor layers is reduced, thereby mitigating electric field concentration during the off state. Therefore, the off characteristics of the nitride semiconductor device can be improved.

[0027] Furthermore, for example, the bottom of the first opening may be located in the nth layer from the top (where n is a natural number greater than or equal to 2) among the plurality of layers.

[0028] This allows for improved off-resistance while suppressing an increase in on-resistance. Specifically, the layer with a low impurity concentration located at the top of the first semiconductor layer contributes to the improvement of off-resistance. On the other hand, since the layer with a low impurity concentration has high resistance, the on-resistance increases when it is included in the current path during the on state. In contrast, by having the bottom of the first opening penetrate the layer with a low impurity concentration located at the top of the first semiconductor layer, the layer with a low impurity concentration can be excluded from the current path during the on state. Therefore, the on-resistance can be reduced.

[0029] Furthermore, in the gate region, layers with low impurity concentrations do not contribute to improving the off-pass characteristics. However, in the gate region, the pn junction at the interface between the electron transport layer and the electron supply layer can receive an electric field, thus suppressing the degradation of the off-pass characteristics. This is because the pn junction in the gate region is the part of the nitride semiconductor device that can withstand the highest electric field strength.

[0030] Furthermore, for example, at the terminal portion of the nitride semiconductor device teeth , groove portion reaching the first semiconductor layer A This may also be the case. For example, the distance between the bottom of the first opening and the drain electrode may be shorter than the distance between the bottom of the groove and the drain electrode.

[0031] This helps to suppress the degradation of the off-state characteristics. The grooves at the end of the device are prone to etching damage during formation, and may not be able to withstand sufficient electric field strength. By bringing the pn junction of the gate closer to the drain electrode, the electric field during the off state can be received at the pn junction of the gate, thus suppressing the degradation of the off-state characteristics.

[0032] The embodiments will be described in detail below with reference to the drawings.

[0033] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0034] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, in each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0035] Furthermore, in this specification, terms indicating relationships between elements such as parallel or orthogonal, terms indicating the shape of elements such as rectangles or trapezoids, and numerical ranges are not expressions that represent only strict meanings, but also expressions that include substantially equivalent ranges, such as differences of a few percent.

[0036] In this specification and in the drawings, the x, y, and z axes represent the three axes of a three-dimensional Cartesian coordinate system. The x and y axes are parallel to the first side and the second side perpendicular to the first side of the rectangle, respectively, when the plan view shape of the substrate is rectangular. The z axis is the thickness direction of the substrate. In this specification, the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layer and is also referred to as the "vertical direction". In addition, the direction parallel to the main surface of the substrate may be referred to as the "horizontal direction".

[0037] Furthermore, the side of the substrate on which the gate electrode and source electrode are provided (the positive side of the z-axis) is considered "up" or "upper," and the side of the substrate on which the drain electrode is provided (the negative side of the z-axis) is considered "down" or "lower."

[0038] In this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather to terms defined by the relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other.

[0039] Furthermore, in this specification, "plan view" means a view taken from a direction perpendicular to the main surface of the nitride semiconductor device substrate, that is, a view of the main surface of the substrate from the front.

[0040] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., do not mean the number or order of components unless otherwise specified, but are used to avoid confusion and to distinguish similar components.

[0041] Furthermore, in this specification, AlGaN refers to ternary mixed crystal Al x Ga 1-xIt represents N (0 < x < 1). Hereinafter, a ternary mixed crystal is abbreviated with an array of symbols of respective constituent elements, for example, AlInN, GaInN, etc. For example, Al of an example of a nitride semiconductor x Ga 1-x-y In y N (0 < x < 1, 0 < y < 1, and 0 < x + y < 1) is abbreviated as AlGaInN.

[0042] (Embodiment 1) [Overview] First, the overview of the nitride semiconductor device according to Embodiment 1 will be described with reference to FIGS. 1 and 2.

[0043] [[ID=IS]]FIG. 1 is a cross-sectional view of a nitride semiconductor device 1 according to the present embodiment. FIG. 2 is a plan view of the nitride semiconductor device 1 according to the present embodiment. FIG. 1 shows a cross-section taken along line I-I of FIG. 2. In FIG. 1, the space between the transistor portion 2 and the termination portion 3 is schematically separated and illustrated.

[0044] As shown in FIG. 1, the nitride semiconductor device 1 includes a transistor portion 2 and a termination portion 3. Specifically, the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a first underlayer 14, an intermediate high-resistance layer 16, a second underlayer 18, a third underlayer 20, a gate opening 22, a semiconductor laminate film 24, a threshold adjustment layer 32, a source opening 34, a source electrode 36, a gate electrode 38, and a drain electrode 40. The semiconductor laminate film 24 is a laminate of an electron traveling layer 26 and an electron supply layer 28, and includes a two-dimensional electron gas (2DEG) 30 as a channel region. Further, the nitride semiconductor device 1 includes a groove portion 42 provided in the termination portion 3.

[0045] The transistor portion 2 is a region including a FET, and as shown in FIG. 2, is a region including the center of the nitride semiconductor device 1. Specifically, in a plan view, the transistor portion 2 is a region where the third underlayer 20, the gate opening 22, the semiconductor laminate film 24, the threshold adjustment layer 32, the source electrode 36 or the gate electrode 38 are arranged.

[0046] Note that in Figure 2, the individual components arranged in the transistor section 2 are not shown. As an example, multiple source electrodes 36, each elongated in one direction in plan view, are arranged in a stripe pattern, with the gate electrode 38, threshold adjustment layer 32, and gate opening 22 positioned between adjacent source electrodes 36. Alternatively, multiple source electrodes 36, each hexagonal in plan view, may be arranged to fill the plane with gaps between them.

[0047] The termination section 3 is the region other than the transistor section 2 and is provided in a ring shape surrounding the transistor section 2. The termination section 3 does not contain the third underlayer 20, gate opening 22, semiconductor multilayer film 24, threshold adjustment layer 32, source electrode 36, or gate electrode 38.

[0048] In this embodiment, the nitride semiconductor device 1 is a device having a stacked structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN. Specifically, the nitride semiconductor device 1 has a heterostructure of an AlGaN film and a GaN film.

[0049] In the heterostructure of an AlGaN film and a GaN film, spontaneous polarization or piezoelectric polarization on the (0001) plane generates a high concentration of two-dimensional electron gas 30 at the heterointerface. Therefore, even in an undoped state, 1 × 10⁻¹⁰ electrons are present at the interface. 13 cm -2 It has the characteristic of being able to obtain the above sheet carrier concentrations.

[0050] The nitride semiconductor device 1 according to this embodiment is a field-effect transistor (FET) that utilizes a two-dimensional electron gas 30 generated at the AlGaN / GaN heterointerface as a channel. Specifically, the nitride semiconductor device 1 is a so-called vertical FET.

[0051] The nitride semiconductor device 1 according to this embodiment is a normally-off type FET. In the nitride semiconductor device 1, for example, the source electrode 36 is grounded (i.e., the potential is 0 V), and a positive potential is applied to the drain electrode 40. The potential applied to the drain electrode 40 is, for example, 100 V or more and 1200 V or less, but is not limited thereto. When the nitride semiconductor device 1 is in the off state, a potential of 0 V or a negative potential (e.g., -5 V) is applied to the gate electrode 38. When the nitride semiconductor device 1 is in the on state, a positive potential (e.g., +5 V) is applied to the gate electrode 38. Note that the nitride semiconductor device 1 may be a normally-on type FET.

[0052] [Configuration of Transistor Section] Hereinafter, the configuration of the transistor section 2 of the nitride semiconductor device 1 will be described.

[0053] The substrate 10 is a substrate made of a nitride semiconductor, and as shown in FIG. 1, has a first main surface 10a and a second main surface 10b facing each other. The first main surface 10a is the main surface (upper surface) on the side where the drift layer 12 is formed. Specifically, the first main surface 10a substantially coincides with the c plane. The second main surface 10b is the main surface (lower surface) on the side where the drain electrode 40 is formed. The planar shape of the substrate 10 is, for example, rectangular, but is not limited thereto.

[0054] The substrate 10 has, for example, a thickness of 300 μm and a carrier concentration of 1×10 18 cm -3 and is a substrate made of n + -type GaN. Note that n-type and p-type indicate the conductivity type of the semiconductor. n + -type represents a state in which an n-type dopant is added to the semiconductor at a high concentration, so-called heavy doping. Also, n - -type represents a state in which an n-type dopant is added to the semiconductor at a low concentration, so-called light doping. The same applies to p + -type and p - -type. n-type, n + -type and n -The type is an example of the first conductivity type. p-type, p + type and p - The type shown is an example of a second conductivity type. The second conductivity type is a conductivity type with the opposite polarity to the first conductivity type.

[0055] Note that the substrate 10 does not have to be a nitride semiconductor substrate. For example, the substrate 10 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.

[0056] The drift layer 12 is an example of a first semiconductor layer of a first conductivity type disposed on top of the substrate 10. The drift layer 12 is, for example, n with a thickness of 8 μm. - The film is made of type GaN. The donor concentration of the drift layer 12 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 17 cm -3 The range is as follows, for example 1 × 10 16 cm -3 Furthermore, the carbon concentration (C concentration) of the drift layer 12 is 1 × 10⁻⁶. 15 cm -3 The above 2 x 10 17 cm -3 The range is as follows:

[0057] The drift layer 12 is provided, for example, in contact with the first main surface 10a of the substrate 10. The drift layer 12 is formed on the first main surface 10a of the substrate 10 by crystal growth, for example, by a metal-organic vapor phase epitaxial growth (MOVPE) method.

[0058] The first underlayer 14 is an example of a second semiconductor layer of a second conductivity type positioned above the drift layer 12. The first underlayer 14 has, for example, a thickness of 400 nm and a carrier concentration of 1 × 10⁻¹⁶ 17 cm -3The film is made of p-type GaN. The first underlayer 14 is provided in contact with the upper surface of the drift layer 12. The first underlayer 14 is formed on the drift layer 12 by crystal growth such as the MOVPE method. The first underlayer 14 may also be formed by ion implanting magnesium (Mg) into the deposited undoped GaN film. Here, "undoped" means that the GaN is not doped with a dopant such as Si or Mg that changes the polarity of the GaN to n-type or p-type.

[0059] The intermediate high-resistance layer 16 is an example of a third semiconductor layer positioned above the first substrate layer 14. The intermediate high-resistance layer 16 is a high-resistance layer with higher resistance than the first substrate layer 14. The intermediate high-resistance layer 16 is formed from an insulating or semi-insulating nitride semiconductor. For example, the intermediate high-resistance layer 16 is a film made of GaN with a thickness of 200 nm. The intermediate high-resistance layer 16 is provided in contact with the first substrate layer 14.

[0060] The intermediate high-resistance layer 16 contains carbon (C). The carbon concentration of the intermediate high-resistance layer 16 is higher than the carbon concentrations of the first underlayer 14 and the second underlayer 18, respectively. For example, the carbon concentration of the intermediate high-resistance layer 16 is, for example, 3 × 10⁻¹⁶. 17 cm -3 That's all, but 1 × 10 18 cm -3 That's fine too.

[0061] Furthermore, the intermediate high-resistance layer 16 may contain silicon (Si) or oxygen (O) that is mixed in during film formation. In this case, the carbon concentration of the intermediate high-resistance layer 16 is higher than the silicon concentration (Si concentration) or oxygen concentration (O concentration). The silicon concentration or oxygen concentration of the intermediate high-resistance layer 16 is, for example, 5 × 10⁻¹⁰ 16 cm -3 The following is 2 × 10 16 cm -3 The following is also acceptable.

[0062] The intermediate high-resistance layer 16 may contain magnesium (Mg), iron (Fe), or boron (B) in addition to or instead of carbon. The intermediate high-resistance layer 16 may also contain other impurities as long as they enable the GaN to have high resistance.

[0063] The intermediate high-resistivity layer 16 is formed on the first substrate layer 14 by crystal growth, for example, by the MOVPE method. Alternatively, the intermediate high-resistivity layer 16 may be formed by ion implantation of impurities into the deposited undoped GaN film.

[0064] The second underlayer 18 is an example of a fourth semiconductor layer of second conductivity type located above the intermediate high-resistance layer 16. The second underlayer 18 has, for example, a thickness of 200 nm and a carrier concentration of 1 × 10⁻¹⁶ 17 cm -3 The film is made of p-type GaN. The second underlayer 18 is provided in contact with the upper surface of the intermediate high-resistance layer 16. The second underlayer 18 is formed on the intermediate high-resistance layer 16 by crystal growth, for example, by the MOVPE method. The second underlayer 18 may also be formed by ion implanting magnesium (Mg) into the deposited undoped GaN film.

[0065] The third underlayer 20 is an undoped semiconductor layer positioned above the second underlayer 18. The third underlayer 20 is, for example, a film made of undoped AlGaN with a thickness of 150 nm. The third underlayer 20 may also be a film made of GaN, InAlN, or InAlGaN. The third underlayer 20 is provided in contact with the upper surface of the second underlayer 18. The third underlayer 20 is formed on the second underlayer 18 by crystal growth, for example, by the MOVPE method. The provision of the third underlayer 20 makes it possible to suppress the diffusion of p-type impurities such as Mg from the second underlayer 18 to the electron transport layer 26.

[0066] Furthermore, the drift layer 12, the first sub-layer 14, the intermediate high-resistance layer 16, the second sub-layer 18, and the third sub-layer 20 can be formed continuously within the same chamber.

[0067] The gate opening 22 is an example of a first opening that penetrates the third sublayer 20, the second sublayer 18, the intermediate high-resistance layer 16, and the first sublayer 14 to reach the drift layer 12. The bottom 22a of the gate opening 22 is part of the upper surface of the drift layer 12. As shown in Figure 1, the bottom 22a is located below the lower surface of the first sublayer 14. The lower surface of the first sublayer 14 corresponds to the interface between the first sublayer 14 and the drift layer 12. The bottom 22a is, for example, parallel to the first main surface 10a of the substrate 10.

[0068] In this embodiment, the gate opening 22 is formed such that its opening area increases as it moves away from the substrate 10. Specifically, the side wall 22b of the gate opening 22 is inclined at an angle. As shown in Figure 1, the cross-sectional shape of the gate opening 22 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0069] The inclination angle of the side wall 22b relative to the bottom portion 22a is, for example, in the range of 30° to 45°. The smaller the inclination angle, the closer the side wall 22b is to the c-plane, which allows for an improvement in the film quality of the electron transport layer 26 and other layers formed along the side wall 22b by crystal regrowth. On the other hand, the larger the inclination angle, the more the gate opening 22 is prevented from becoming too large, enabling miniaturization of the nitride semiconductor device 1.

[0070] The gate opening 22 is formed by continuously depositing a drift layer 12, a first underlayer 14, an intermediate high-resistance layer 16, a second underlayer 18, and a third underlayer 20 in that order on the first main surface 10a of the substrate 10, and then removing a portion of each of the third underlayer 20, the second underlayer 18, the intermediate high-resistance layer 16, and the first underlayer 14 so as to partially expose the drift layer 12. At this time, by removing the surface portion of the drift layer 12 by a predetermined thickness, the bottom 22a of the gate opening 22 is formed below the lower surface of the first underlayer 14.

[0071] The removal of the third underlayer 20, the second underlayer 18, the intermediate high-resistance layer 16, and the first underlayer 14 is performed by coating and patterning the resist, as well as by dry etching. Specifically, after patterning the resist, the edges of the resist are angled by baking. Subsequently, dry etching is performed to form a gate opening 22 with angled side walls 22b, so as to transfer the shape of the resist.

[0072] The semiconductor multilayer film 24 is an example of a fifth semiconductor layer in which a portion is arranged along the inner surface of the gate opening 22 and another portion is arranged above the second underlying layer 18. That is, a portion of the semiconductor multilayer film 24 is arranged along the inner surface of the gate opening 22, and another portion of the semiconductor multilayer film 24 is arranged above the second underlying layer 18. The semiconductor multilayer film 24 is a laminate of an electron transport layer 26 and an electron supply layer 28.

[0073] The electron traveling layer 26 is an example of a first regrowth layer provided along the inner surface of the gate opening 22. Specifically, a portion of the electron traveling layer 26 is provided along the bottom 22a and side wall 22b of the gate opening 22, while the other portion of the electron traveling layer 26 is provided on the upper surface of the third underlayment layer 20. The electron traveling layer 26 is, for example, a film made of undoped GaN with a thickness of 150 nm. Note that the electron traveling layer 26 may be made n-type by Si doping or the like, instead of being undoped.

[0074] The electron traveling layer 26 is in contact with the drift layer 12 at the bottom 22a and side wall 22b of the gate opening 22. The electron traveling layer 26 is in contact with the end faces of the first substrate layer 14, the intermediate high-resistance layer 16, the second substrate layer 18, and the third substrate layer 20 at the side wall 22b of the gate opening 22. Furthermore, the electron traveling layer 26 is in contact with the upper surface of the third substrate layer 20. The electron traveling layer 26 is formed by crystal regrowth after the gate opening 22 has been formed.

[0075] The electron transport layer 26 has a channel region of a first conductivity type. Specifically, a two-dimensional electron gas 30 is generated near the interface between the electron transport layer 26 and the electron supply layer 28. The two-dimensional electron gas 30 functions as a channel in the electron transport layer 26. In Figure 1, the two-dimensional electron gas 30 is schematically shown by a dashed line. The two-dimensional electron gas 30 is bent along the interface between the electron transport layer 26 and the electron supply layer 28, that is, along the inner surface of the gate opening 22.

[0076] Furthermore, although not shown in Figure 1, an AlN film with a thickness of approximately 1 nm may be provided as a second regrowth layer between the electron transport layer 26 and the electron supply layer 28. The AlN film can suppress alloy scattering and improve channel mobility.

[0077] The electron supply layer 28 is an example of a third regrowth layer provided along the inner surface of the gate opening 22. The electron supply layer 28 is located above the electron transport layer 26. The electron supply layer 28 is formed with a substantially uniform thickness and a shape along the upper surface of the electron transport layer 26. The electron supply layer 28 is, for example, a film made of undoped AlGaN with a thickness of 50 nm. The electron supply layer 28 is formed by crystal regrowth following the formation process of the electron transport layer 26.

[0078] The electron supply layer 28 forms an AlGaN / GaN heterointerface with the electron transport layer 26. This generates a two-dimensional electron gas 30 within the electron transport layer 26. The electron supply layer 28 supplies electrons to the channel region (i.e., the two-dimensional electron gas 30) formed in the electron transport layer 26.

[0079] The threshold adjustment layer 32 is an example of a sixth semiconductor layer of a second conductivity type, positioned above the semiconductor multilayer film 24. Specifically, the threshold adjustment layer 32 is provided between the gate electrode 38 and the electron supply layer 28. The threshold adjustment layer 32 is formed with a substantially uniform thickness and a shape that follows the upper surface of the electron supply layer 28.

[0080] The threshold adjustment layer 32 has, for example, a thickness of 100 nm and a carrier concentration of 1 × 10⁻⁶ 17 cm-3 This is a nitride semiconductor layer made of p-type GaN or AlGaN. The threshold adjustment layer 32 is formed by regrowth using the MOVPE method immediately following the formation of the electron supply layer 28, and then patterned. The electron transport layer 26, electron supply layer 28, and threshold adjustment layer 32 can be formed in this order continuously within the same chamber.

[0081] The presence of the threshold adjustment layer 32 raises the potential at the conduction band edge of the channel portion. This allows the threshold voltage of the nitride semiconductor device 1 to be increased. Consequently, the nitride semiconductor device 1 can be realized as a normally-off type FET. In other words, the nitride semiconductor device 1 can be turned off when a potential of 0V is applied to the gate electrode 38.

[0082] The source opening 34 is an example of a second opening that penetrates the semiconductor multilayer film 24 and the third underlying layer 20 to reach the second underlying layer 18, at a position away from the gate opening 22. In a plan view, the source opening 34 is located at a position away from the gate electrode 38.

[0083] The bottom 34a of the source opening 34 is part of the upper surface of the second substrate 18. As shown in Figure 1, the bottom 34a is located below the lower surface of the third substrate 20. The lower surface of the third substrate 20 corresponds to the interface between the third substrate 20 and the second substrate 18. The bottom 34a is parallel to, for example, the first main surface 10a of the substrate 10.

[0084] As shown in Figure 1, the source opening 34 is formed such that its opening area is constant regardless of its distance from the substrate 10. Specifically, the side wall 34b of the source opening 34 is perpendicular to the bottom 34a. In other words, the cross-sectional shape of the source opening 34 is rectangular.

[0085] Furthermore, the source opening 34 may be formed such that its opening area increases as it moves away from the substrate 10, similar to the gate opening 22. Specifically, the side wall 34b of the source opening 34 may be inclined at an angle. For example, the cross-sectional shape of the source opening 34 may be an inverted trapezoid, or more specifically, an inverted isosceles trapezoid. In this case, the inclination angle of the side wall 34b with respect to the bottom 34a may be in the range of 30° to 60°. For example, the inclination angle of the side wall 34b of the source opening 34 may be greater than the inclination angle of the side wall 22b of the gate opening 22. The inclination of the side wall 34b increases the contact area between the source electrode 36 and the electron transport layer 26 (two-dimensional electron gas 30), making ohmic connection easier. The two-dimensional electron gas 30 is exposed on the side wall 34b of the source opening 34 and connected to the source electrode 36 at the exposed portion.

[0086] The source opening 34 is formed, for example, by etching the threshold adjustment layer 32, the electron supply layer 28, the electron transport layer 26, and the third underlayment 20 so as to expose the second underlayment 18 in a region different from the gate opening 22, following the threshold adjustment layer 32 formation process (i.e., the crystal regrowth process). At this time, by also removing the surface portion of the second underlayment 18, the bottom 34a of the source opening 34 is formed below the lower surface of the third underlayment 20. The source opening 34 is formed into a predetermined shape by, for example, photolithography patterning and dry etching.

[0087] The source electrode 36 is positioned spaced apart from the gate electrode 38. In this embodiment, the source electrode 36 is provided along the inner surface of the source opening 34. Specifically, the source electrode 36 is connected to the electron supply layer 28, the electron transport layer 26, and the second base layer 18. The source electrode 36 is ohmic connected to the electron transport layer 26 and the electron supply layer 28. The source electrode 36 is in direct contact with the two-dimensional electron gas 30 at the side wall 34b. This reduces the contact resistance between the source electrode 36 and the two-dimensional electron gas 30 (channel).

[0088] The source electrode 36 is formed using a conductive material such as a metal. As the material for the source electrode 36, for example, a material such as Ti / Al that becomes ohmic connected to the n-type GaN layer through heat treatment can be used. The source electrode 36 is formed, for example, by patterning a conductive film deposited by sputtering or vapor deposition.

[0089] The gate electrode 38 is positioned above the threshold adjustment layer 32. Specifically, the gate electrode 38 is provided in contact with the upper surface of the threshold adjustment layer 32 so as to cover the gate opening 22. The gate electrode 38 is formed, for example, with a substantially uniform film thickness in a shape that follows the upper surface of the threshold adjustment layer 32. Alternatively, the gate electrode 38 may be formed to fill a recess in the upper surface of the threshold adjustment layer 32.

[0090] The gate electrode 38 is formed using a conductive material such as a metal. For example, the gate electrode 38 is formed using palladium (Pd). The material for the gate electrode 38 can be a material that is Schottky connected to the p-type GaN layer, such as nickel (Ni)-based materials, tungsten silicide (WSi), or gold (Au). The gate electrode 38 is formed after the deposition of the threshold adjustment layer 32, after the formation of the source opening 34, or after the formation of the source electrode 36, by patterning a conductive film deposited by sputtering or vapor deposition, for example.

[0091] The drain electrode 40 is provided on the lower side of the substrate 10, that is, on the side opposite to the drift layer 12. Specifically, the drain electrode 40 is provided in contact with the second main surface 10b of the substrate 10. The drain electrode 40 is formed using a conductive material such as metal. As for the material of the drain electrode 40, similar to the material of the source electrode 36, a material that is ohmic connected to the n-type GaN layer, such as Ti / Al, can be used. The drain electrode 40 is formed, for example, by patterning a conductive film deposited by sputtering or vapor deposition.

[0092] [Configuration of the terminal section] Next, the configuration of the termination portion 3 of the nitride semiconductor device 1 according to this embodiment will be described.

[0093] As shown in Figure 1, the third underlayer 20, semiconductor multilayer film 24, and threshold adjustment layer 32 are not provided at the termination section 3. For example, simultaneously with the formation of the source opening 34, the third underlayer 20, semiconductor multilayer film 24, and threshold adjustment layer 32 at the termination section 3 are removed. At the termination section 3, the upper surface of the second underlayer 18 is at the same height as the bottom 34a of the source opening 34. "Same height" means that the distance from the first main surface 10a of the substrate 10 is the same.

[0094] A groove 42 is provided at the terminal section 3. The groove 42 is an isolation trench for partitioning and separating the transistor section 2. The groove 42 penetrates the second base layer 18, the intermediate high-resistance layer 16, and the first base layer 14 to reach the drift layer 12.

[0095] The groove 42 has a bottom portion 42a and a side wall 42b. In this embodiment, the groove 42 is a stepped portion having a side wall 42b only on the transistor portion 2 side. That is, the bottom portion 42a of the groove 42 is connected to the end face of the nitride semiconductor device 1. As shown in Figure 2, the groove 42 is provided in a ring shape surrounding the transistor portion 2.

[0096] The bottom 42a of the groove 42 is part of the upper surface of the drift layer 12. As shown in Figure 1, the bottom 42a is located below the lower surface of the first sublayer 14. The bottom 42a is parallel to, for example, the first main surface 10a of the substrate 10.

[0097] As shown in Figure 1, the groove 42 is formed such that its opening area is constant regardless of its distance from the substrate 10. Specifically, the side wall 42b of the groove 42 is perpendicular to the bottom 42a. In other words, the cross-sectional shape of the groove 42 is rectangular.

[0098] The groove 42 is formed, for example, by changing the etching mask and performing dry etching following the dry etching step for forming the source opening 34. Alternatively, the groove 42 may be formed by dry etching after forming the source electrode 36 or after forming the gate electrode 38.

[0099] [Main characteristic configuration] Next, the main characteristic configuration of the nitride semiconductor device 1 according to this embodiment will be described.

[0100] As shown in Figure 1, in the nitride semiconductor device 1, a laminated structure is provided between the source electrode 36 and the drain electrode 40, consisting of a first p-type underlayer 14, an intermediate high-resistance layer 16, and a second p-type underlayer 18. In other words, the intermediate high-resistance layer 16, which has high resistance, is sandwiched between two p-type semiconductor layers.

[0101] As described above, the intermediate high-resistance layer 16 is a nitride semiconductor layer such as GaN that has been made highly resistive by doping it with impurities such as carbon. The doped impurities can generate trap levels within the intermediate high-resistance layer 16.

[0102] In this embodiment, since the second underlayer 18 is placed above the intermediate high-resistance layer 16, electrons in the channel are less likely to be trapped in the trap level of the intermediate high-resistance layer 16. This makes it possible to suppress the degradation of the dynamic characteristics of the transistor section 2.

[0103] Furthermore, a first underlayer 14 is positioned below the intermediate high-resistance layer 16. The presence of the first underlayer 14 suppresses leakage current between the source electrode 36 and the drain electrode 40. For example, when a reverse voltage is applied to the pn junction formed by the first underlayer 14 and the drift layer 12, specifically when the drain electrode 40 becomes at a higher potential than the source electrode 36, a depletion layer extends in the drift layer 12. This enables the nitride semiconductor device 1 to have a high breakdown voltage. As described above, in this embodiment, the drain electrode 40 is at a higher potential than the source electrode 36 in both the off and on states. Therefore, the nitride semiconductor device 1 has a high breakdown voltage.

[0104] Furthermore, if the sole purpose is to suppress electron trapping by the aforementioned intermediate high-resistance layer 16, it is conceivable to place the intermediate high-resistance layer 16 between the first base layer 14 and the drift layer 12. However, the intermediate high-resistance layer 16 tends to have reduced crystal quality due to doping with carbon, etc. Therefore, if it is placed in the pn junction where a high electric field is applied during the off state, the off-state characteristics may deteriorate. In this embodiment, the deterioration of the off-state characteristics can be suppressed by placing the intermediate high-resistance layer 16 above the first base layer 14.

[0105] Furthermore, if the nitride semiconductor device 1 does not have an intermediate high-resistance layer 16, a parasitic NPN structure, i.e., a parasitic bipolar transistor, will exist between the source electrode 36 and the drain electrode 40, consisting of the electron transport layer 26, a p-type first underlayer 14 and a second underlayer 18, and an n-type drift layer 12. Therefore, when the nitride semiconductor device 1 is in the off state, if current flows through the p-type first underlayer 14 or the second underlayer 18, the parasitic bipolar transistor will turn on, potentially reducing the breakdown voltage of the nitride semiconductor device 1. In this case, malfunction of the nitride semiconductor device 1 is likely to occur. In this embodiment, the provision of the intermediate high-resistance layer 16 suppresses the formation of a parasitic NPN structure and thus suppresses malfunction of the nitride semiconductor device 1.

[0106] Furthermore, in this embodiment, a source opening 34 that reaches the second underlying layer 18 is provided. Since the channel (two-dimensional electron gas 30) is exposed on the side wall 34b of the source opening 34, the source electrode 36 can contact the channel at this exposed portion. This reduces the ohmic contact resistance between the source electrode 36 and the channel.

[0107] Furthermore, since the intermediate high-resistance layer 16 is positioned below the second underlayer 18, which the source electrode 36 contacts at the bottom 34a of the source opening 34, it is possible to suppress the flow of current through the parasitic pn diode formed between the source and drain. This improves the reliability of the nitride semiconductor device 1.

[0108] Furthermore, the distance D1 shown in Figure 1 is shorter than the distance D2. Distance D1 is the distance between the bottom 28a of the electron supply layer 28 and the drain electrode 40. Distance D2 is the distance between the bottom 16a of the intermediate high-resistance layer 16 and the drain electrode 40.

[0109] The bottom 28a of the electron supply layer 28 is the portion of the lower surface of the electron supply layer 28 that is closest to the drain electrode 40. Specifically, it is the portion of the lower surface of the electron supply layer 28 that is located within the gate opening 22 and is parallel to the bottom 22a of the gate opening 22. The bottom 16a of the intermediate high-resistance layer 16 is the portion of the lower surface of the intermediate high-resistance layer 16 that is closest to the drain electrode 40. In this embodiment, since the lower surface of the intermediate high-resistance layer 16 is parallel to the upper surface of the drain electrode 40 (the second main surface 10b of the substrate 10), the bottom 16a is any portion of the lower surface of the intermediate high-resistance layer 16.

[0110] The electron transport layer 26 and the electron supply layer 28 can be formed continuously by crystal growth. Therefore, the pn junction portion at the interface between the electron transport layer 26 and the electron supply layer 28, i.e., the bottom portion 28a of the electron supply layer 28, has fewer energy levels caused by impurities or damage, and becomes the portion that can withstand the highest electric field strength within the nitride semiconductor device 1. By bringing the bottom portion 28a of the electron supply layer 28 closer to the drain electrode 40, the electric field generated between the gate electrode 38 or source electrode 36 and the drain electrode 40 during the off state can be concentrated at the bottom portion 28a of the electron supply layer 28. This suppresses the concentration of the electric field in weaker areas and improves the off characteristics.

[0111] [Differentiation] Next, a modified example of Embodiment 1 will be described using Figure 3. Figure 3 is a cross-sectional view of a nitride semiconductor device 101 according to a modified example of this embodiment.

[0112] As shown in Figure 3, the nitride semiconductor device 101 differs from the nitride semiconductor device 1 shown in Figure 1 in that it has a source opening 134 and a source electrode 136 instead of a source opening 34 and a source electrode 36. In the following, the differences from the embodiment will be described in detail, and the explanation of common points may be omitted or simplified.

[0113] The source opening 134 is an example of a third opening that penetrates the semiconductor multilayer film 24, the third underlayer 20, the second underlayer 18, and the intermediate high-resistance layer 16 to reach the first underlayer 14, at a position away from the gate opening 22. In a plan view, the source opening 134 is located at a position away from the gate electrode 38.

[0114] The bottom 134a of the source opening 134 is part of the upper surface of the first sublayer 14. As shown in Figure 3, the bottom 134a is located below the lower surface (bottom 16a) of the intermediate high-resistance layer 16. The lower surface of the intermediate high-resistance layer 16 corresponds to the interface between the intermediate high-resistance layer 16 and the first sublayer 14.

[0115] Thus, in this modified example, the source opening 134 reaches the first substrate layer 14. The source electrode 136 is provided along the inner surface of the source opening 134 and is therefore in contact with the first substrate layer 14. Specifically, the source electrode 136 is connected to the electron supply layer 28, the electron transport layer 26, the second substrate layer 18, and the first substrate layer 14, respectively.

[0116] Therefore, similar to the embodiment, the channel (two-dimensional electron gas 30) is exposed on the side wall 34b of the source opening 134, allowing the source electrode 136 to contact the channel at this exposed portion. This reduces the ohmic contact resistance between the source electrode 136 and the channel.

[0117] Furthermore, since the source electrode 136 is in contact with both the second underlayer 18 and the first underlayer 14, the potential of each layer can be firmly fixed. This further improves the off-mode characteristics of the nitride semiconductor device 1.

[0118] Furthermore, a second base layer 18 and an intermediate high-resistance layer 16 may be provided at the terminal section 3. That is, at the terminal section 3, the second base layer 18 and the intermediate high-resistance layer 16 may be removed simultaneously with the formation of the source opening 134, exposing the upper surface of the first base layer 14.

[0119] (Embodiment 2) Next, Embodiment 2 will be described.

[0120] The nitride semiconductor device according to Embodiment 2 differs from Embodiment 1 in that the drift layer includes multiple layers with different impurity concentrations. In the following, the differences between Embodiment 1 and its modified examples will be described in detail, and the explanation of common points may be omitted or simplified.

[0121] [composition] First, the configuration of the nitride semiconductor device according to this embodiment will be explained using Figure 4. Figure 4 is a cross-sectional view of the nitride semiconductor device 201 according to this embodiment.

[0122] As shown in Figure 4, the nitride semiconductor device 201 differs from the nitride semiconductor device 1 according to Embodiment 1 in that it includes a drift layer 212 instead of a drift layer 12.

[0123] The drift layer 212 is composed of multiple layers with different impurity concentrations. In this embodiment, the multiple layers consist of two layers. Specifically, as shown in Figure 3, the drift layer 212 has a high-concentration layer 212a and a low-concentration layer 212b. The high-concentration layer 212a and the low-concentration layer 212b are formed continuously on the substrate 10 by crystal growth, for example, by the MOVPE method.

[0124] The high-density layer 212a is an example of the nth layer from the top among multiple layers. n is a natural number greater than or equal to 2. In this embodiment, n is 2. The high-density layer 212a is provided in contact with the first main surface 10a of the substrate 10.

[0125] The high-concentration layer 212a is, for example, n with a thickness of 7 μm. + This is a film made of GaN of type 10. The impurity concentration (donor concentration) of the high-concentration layer 212a is, for example, 3 × 10⁻⁶. 15 cm -3 The above 5 x 10 16 cm -3 The range is as follows, for example 1.5 × 10 16 cm -3 That is the case.

[0126] The low-concentration layer 212b is an example of a layer located above the nth layer. In this embodiment, the low-concentration layer 212b is the uppermost layer within the drift layer 212 and is provided in contact with the high-concentration layer 212a and the first base layer 14. The impurity concentration of the low-concentration layer 212b is the lowest among the multiple layers that make up the drift layer 212. In other words, the impurity concentration of the low-concentration layer 212b is lower than the impurity concentration of the high-concentration layer 212a.

[0127] The low-concentration layer 212b is, for example, n with a thickness of 1 μm. -This is a film made of type GaN. The impurity concentration (donor concentration) of the low-concentration layer 212b is, for example, 1 × 10⁻⁶ 15 cm -3 The above is 3 x 10 16 cm -3 The range is as follows, for example 9×10 15 cm -3 That is the case.

[0128] In this way, by making the impurity concentration of the low-concentration layer 212b on the first underlayer 14 side (upper side) lower than the donor concentration of the high-concentration layer 212a on the side closer to the substrate 10 (lower side), the extension of the depletion layer into the drift layer 212 is promoted when a high voltage is applied to the drain electrode 40 in the off state. This makes it possible to increase the breakdown voltage of the nitride semiconductor device 201.

[0129] [Example 1] Next, a modified example 1 of Embodiment 2 will be described using Figure 5. Figure 5 is a cross-sectional view of the nitride semiconductor device 202 according to this modified example.

[0130] As shown in Figure 5, the nitride semiconductor device 202 differs from the nitride semiconductor device 201 shown in Figure 4 in that it has a source opening 134 and a source electrode 136 instead of a source opening 34 and a source electrode 36. The source opening 134 and source electrode 136 are the same as the source opening 134 and source electrode 136 in the modified example of Embodiment 1.

[0131] Therefore, the nitride semiconductor device 202 according to this modified example can obtain the effects of both nitride semiconductor devices 101 and 201. Specifically, the nitride semiconductor device 202 can further improve the off-state characteristics and increase the breakdown voltage.

[0132] [Differentiation 2] Next, a modified example 2 of Embodiment 2 will be described using Figure 6. Figure 6 is a cross-sectional view of the nitride semiconductor device 203 according to this modified example.

[0133] As shown in Figure 6, the nitride semiconductor device 203 differs from the nitride semiconductor device 202 shown in Figure 5 in that it has a gate opening 222 instead of a gate opening 22.

[0134] The gate opening 222 penetrates the third sublayer 20, the second sublayer 18, the intermediate high-resistance layer 16, the first sublayer 14, and the low-concentration layer 212b to reach the high-concentration layer 212a. The bottom 222a of the gate opening 222 is part of the upper surface of the high-concentration layer 212a. As shown in Figure 1, the bottom 222a is located below the lower surface of the low-concentration layer 212b. The lower surface of the low-concentration layer 212b corresponds to the interface between the low-concentration layer 212b and the high-concentration layer 212a.

[0135] As a result, in the ON state, the drain current flows from the drain electrode 40 through the substrate 10, the high-concentration layer 212a, and the two-dimensional electron gas 30 to the source electrode 36. Since the low-concentration layer 212b, which has high resistance, is not present in the drain current path, the ON resistance can be reduced.

[0136] Furthermore, in this modified example, the distance D3 shown in Figure 6 is shorter than the distance D4. Distance D3 is the distance between the bottom 222a of the gate opening 222 and the drain electrode 40. Distance D4 is the distance between the bottom 42a of the groove 42 and the drain electrode 40. This improves the off-characteristics of the nitride semiconductor device 203. Specifically, it is as follows.

[0137] When transistor unit 2 is in the off state, a high voltage is applied between the drain electrode 40 and the source electrode 136, such that the potential on the drain electrode 40 side is higher than that on the source electrode 136 side. Therefore, in the off state, a high electric field is generated in the longitudinal direction of the nitride semiconductor device 203.

[0138] Since distance D3 is shorter than distance D4, the electric field is more likely to concentrate at the gate opening 222 of the transistor section 2 than at the termination section 3. The concentrated electric field can be received by the pn junction between the electron supply layer 28 and the electron transport layer 26. This pn junction is of higher quality and has a higher electric field strength compared to the pn junction between the first underlayment layer 14 and the drift layer 212 near the groove section 42 where etching damage occurs. Because the electric field concentration can be received by a pn junction with a high electric field strength, the electric field concentration at the pn junction near the groove section 42 can be mitigated.

[0139] In this way, the off-state characteristics of the nitride semiconductor device 203 can be improved. Specifically, the leakage current near the groove 42 can be reduced, and the decrease in breakdown voltage can be suppressed. The larger the difference between distance D3 and distance D4, the more the electric field concentration near the groove 42 can be mitigated.

[0140] In this embodiment, the distance D1 may be shorter than the distance D4. This makes it possible to mitigate the concentration of the electric field near the groove 42.

[0141] Although the explanation used two layers as an example for the number of layers in the drift layer 212, the number of layers may be three or more. When the drift layer 212 contains three or more semiconductor layers, the bottom 222a of the gate opening 222 is located in a layer other than the top layer, which has the lowest impurity concentration. In other words, the bottom 222a is located in the nth layer from the top (where n is a natural number greater than or equal to 2) among the multiple layers that make up the drift layer 212.

[0142] (Other embodiments) Although nitride semiconductor devices according to one or more embodiments have been described above based on these embodiments, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to these embodiments that a person skilled in the art could conceive of, as well as forms constructed by combining components from different embodiments, are also included within the scope of this disclosure.

[0143] For example, the source opening 34 or 134 may not be provided. In this case, the source electrode 36 or 136 is provided on the upper surface of the semiconductor multilayer film 24 at a position away from the threshold adjustment layer 32.

[0144] Furthermore, for example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) is gradually reduced from the substrate 10 side to the first underlayer 14 side. The donor concentration may be controlled by the donor Si, or by the acceptor carbon that compensates for the Si.

[0145] Furthermore, for example, the termination portion 3 does not necessarily include the end face of the nitride semiconductor device. The termination portion 3 is a part for isolating the transistor portion 2 from other devices. Other elements may be arranged in the adjacent region of the transistor portion 2, flanking the termination portion 3. For example, the other element is a pn diode utilizing the pn junction between the drift layer 12 and the first underlayer 14. In this case, the nitride semiconductor device comprises the transistor portion 2, the termination portion 3, and the pn diode.

[0146] Furthermore, the first conductivity type may be p-type, p+-type, or p-type, and the second conductivity type may be n-type, n+-type, or n-type.

[0147] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or their equivalents. [Industrial applicability]

[0148] This disclosure can be used as a nitride semiconductor device with improved electrical properties, and can be used, for example, as a power device such as a power transistor used in the power supply circuit of consumer electronics such as televisions. [Explanation of Symbols]

[0149] 1, 101, 201, 202, 203 Nitride Semiconductor Devices 2 Transistor section 3. Termination section 10 circuit boards 10a First main surface 10b Second main surface 12,212 drift layers 14. The first sublayer 16 Intermediate high-resistance layer 16a, 22a, 28a, 34a, 42a, 134a, 222a bottom 18. Second sublayer 20 Third sublayer 22,222 Gate opening 22b, 34b, 42b side wall 24 Semiconductor multilayer film 26 Electronic transport layer 28 Electron supply layer 30 Two-dimensional electron gas 32 Threshold adjustment layer 34, 134 Source openings 36, 136 source electrodes 38 Gate 40 Drain electrode 42 Groove 212a High concentration layer 212b Low concentration layer

Claims

1. circuit board and A first semiconductor layer of a first conductivity type is disposed above the substrate, A second semiconductor layer of a second conductivity type is disposed above the first semiconductor layer, A third semiconductor layer, which has a higher resistance than the second semiconductor layer, is disposed above the second semiconductor layer. A fourth semiconductor layer of the second conductivity type, disposed above the third semiconductor layer, A fifth semiconductor layer having a channel region of the first conductivity type, wherein a portion of the fifth semiconductor layer is arranged along the inner surface of a first opening that penetrates the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer and reaches the first semiconductor layer, and another portion of the fifth semiconductor layer is arranged above the fourth semiconductor layer. Nitride semiconductor devices.

2. The substrate comprises a drain electrode located on the lower side, The fifth semiconductor layer includes an electron transport layer and an electron supply layer disposed above the electron transport layer. The distance between the bottom of the electron supply layer and the drain electrode is shorter than the distance between the bottom of the third semiconductor layer and the drain electrode. The nitride semiconductor device according to claim 1.

3. A sixth semiconductor layer of the second conductivity type disposed above the fifth semiconductor layer, A gate electrode disposed above the sixth semiconductor layer, The system comprises a source electrode positioned spaced apart from the gate electrode, The source electrode is a second opening provided spaced apart from the gate electrode, and is provided along the inner surface of the second opening, penetrating the fifth semiconductor layer and reaching the fourth semiconductor layer. A nitride semiconductor device according to claim 1 or 2.

4. The source electrode is a third opening spaced apart from the gate electrode, and is provided along the inner surface of the third opening that penetrates the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor layer and reaches the second semiconductor layer. The nitride semiconductor device according to claim 3.

5. The third semiconductor layer comprises C, Fe, B, or Mg. A nitride semiconductor device according to claim 1 or 2.

6. The first semiconductor layer is composed of multiple layers with different impurity concentrations. The impurity concentration of the uppermost layer among the aforementioned multiple layers is the lowest among the aforementioned multiple layers. A nitride semiconductor device according to claim 1 or 2.

7. The bottom of the first opening is located in the nth layer from the top (where n is a natural number of 2 or more) among the plurality of layers. The nitride semiconductor device according to claim 6.

8. The terminal portion of the nitride semiconductor device is provided with a groove that reaches the first semiconductor layer. A nitride semiconductor device according to claim 1 or 2.

9. The substrate is provided with a drain electrode on the lower surface side, The terminal portion of the nitride semiconductor device is provided with a groove that reaches the first semiconductor layer. The distance between the bottom of the first opening and the drain electrode is shorter than the distance between the bottom of the groove and the drain electrode. The nitride semiconductor device according to claim 1.

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