Vertical capacitively coupled gate-controlled junction field-effect transistor and method for manufacturing the same

Abstract

To provide a vertical capacitive coupling gate control junction type field effect transistor, and a manufacturing method for the same.SOLUTION: A field effect transistor includes a departure substrate 1 of a first doping type, two bottom gates 3 of a second doping type formed in the departure substrate 1 and provided apart from each other in a lateral direction, a top gate 8 of the second doping type formed in the departure substrate 1, existing over the space between the two bottom gates 3, and having a space from the bottom gates 3, a dielectric layer 9 formed on the departure substrate 1 and existing at a position on the top gate 8 of the second doping type, and a coupling capacitance upper electrode 10 formed on the dielectric layer 9. The top gate 8 of the second doping type is controlled indirectly by the coupling capacitance upper electrode 10 through the dielectric layer 9.SELECTED DRAWING: Figure 3-4

Description

[Technical Field]

[0001] This application relates to the semiconductor technology field, and more specifically to a vertical capacitively coupled gate-controlled junction field-effect transistor and a method for manufacturing the same. [Background technology]

[0002] Silicon carbide (SiC) is a third-generation wide-bandgap semiconductor with a bandgap width of 3.2 eV, which is significantly larger than the 1.1 eV of conventional silicon materials. It also has advantages such as a critical breakdown field strength an order of magnitude higher than silicon materials, excellent resistance to high temperatures and pressures, and a fast saturation drift rate, making it suitable for manufacturing high-temperature, high-voltage power semiconductor devices that support fast response, such as VDMOS (Vertical Double-diffused MOSFET) and JFET (Junction Field-Effect Transistor). A junction field-effect transistor (JFET) is also a type of triode semiconductor device. Its operating principle involves controlling the reverse bias of the pn junction between the gate electrode and the channel by applying a voltage to the gate electrode, thereby turning off the drain and source electrodes. When no voltage is applied to the gate electrode, it is normally an on device, and its conductive channel is located within the device body. Junction field-effect transistors (JEMTs) offer advantages such as low noise, small size, and high-frequency response, making them commonly used in switching devices, power amplifiers, and digital electronic circuits to meet the requirements of various electronic devices.

[0003] Vertical double-diffused MOSFET (VDMOS) devices are vertical semiconductor devices that combine the advantages of bipolar transistors and conventional MOS devices. In VDMOS, the gate electrode and source electrode are located on the device surface, while the drain electrode is located on the back surface. The operating principle involves controlling the on / off state of the channel with the gate, thereby enabling current to flow from the drain electrode through the inverted channel inside the device and on the device surface to the source electrode, with the conductive channel located on the surface of the element. VDMOS is an ideal power device for both switching and linear applications and is mainly used in electronic switches, adapters, drive band energy, and industrial control. [Overview of the project] [Problems that the invention aims to solve]

[0004] The CN1238904C is a JFET device, and as shown in Figure 1, it comprises a single-crystal silicon SiC substrate 1, a p-type epitaxial layer 2, an n-type epitaxial layer 3, a p+-type semiconductor layer 4, an n+-type source region layer 5, a p+-type gate region layer 7, an n+-type drain region layer 9, a source electrode 10, a gate electrode 11, and a drain electrode 12. The conduction channel of the JFET device is located inside the device, within the n-type epitaxial layer 3, and the conduction channel is located inside the semiconductor material, thus avoiding the problem of low surface mobility of the SiC material. The JFET device is a normally-on device, meaning that when no voltage is applied to the p+-type gate region layer 7 (i.e., the gate electrode), the device is in a conduction state (shown as a dashed line representing current in Figure 1). Therefore, in order to turn off the device, a negative voltage must be applied to the p+-type gate region layer 7 (i.e., the gate electrode), which limits its application as a power switch. Furthermore, since the p+ type gate region layer 7 (i.e., the gate electrode) and the channel have a pn junction structure, it is not possible to apply a voltage exceeding 3V to the p+ type gate region layer 7 (i.e., the gate electrode). In the case of SiC material, if a voltage of 3V or more is applied to the gate electrode, the gate electrode and the channel or source electrode conduct, resulting in a large on-current that affects the current characteristics from drain to source, and because high voltage cannot be applied to the gate electrode, its application as a power switch is limited.

[0005] Therefore, the inability to apply high voltage to the gate of conventional silicon carbide junction field-effect transistors, and the resulting low reliability of the gate electrode, limit their application as power switches. This is a technical issue that those skilled in the art should urgently address.

[0006] The information disclosed in the background art is intended solely to enhance understanding of the background of the present application and therefore may contain information that does not constitute prior art known to those skilled in the art. [Means for solving the problem]

[0007] Embodiments of the present application provide a vertical capacitive-coupled gate-controlled junction field-effect transistor and a manufacturing method thereof to solve the technical problem that the conventional silicon carbide junction field-effect transistor has limited application as a power switch because a relatively high voltage cannot be applied to the gate and the gate reliability is low.

[0008] According to a first aspect of an embodiment of the present application, a vertical capacitive-coupled gate-controlled junction field-effect transistor is provided. A substrate of a first doping type, Two bottom gates of a second doping type formed in the substrate and spaced apart in the lateral direction, A top gate of a second doping type formed in the substrate, the top gate being located above the interval between the two bottom gates and having an interval between the top gate and the bottom gates, A dielectric layer formed on the substrate and located above the top gate, A coupling capacitor upper electrode formed on the dielectric layer, The top gate is indirectly controlled by the coupling capacitor upper electrode through the dielectric layer.

[0009] In implementation, the top gate is in a floating state, and the coupling capacitor upper electrode, the dielectric layer, and the top gate together constitute the gate structure of the field-effect transistor as a whole. The top gate of the second doping type, the portion located between the top gate and the bottom gates, and the bottom gates form JFET region one, and the two bottom gates and the portion located between the bottom gates form JFET region two. The top gate of JFET region one is indirectly controlled by the coupling capacitor upper electrode through the dielectric layer, so that JFET region one and JFET region two are indirectly controlled by the coupling capacitor upper electrode through the dielectric layer.

[0010] According to a second embodiment of the present invention, a method for manufacturing a vertical capacitively coupled gate-controlled junction field-effect transistor is provided. The steps include forming a first-doped substrate, The steps include forming two second doping-type bottom gates that are formed within the substrate and spaced apart in the lateral direction, The steps of forming a second doping-type top gate formed in the substrate, wherein the top gate is located above the gap between the two bottom gates and there is a gap between the top gate and the bottom gates, The steps include forming a dielectric layer on the substrate and located above the top gate, The steps include forming a coupling capacitance upper electrode on the dielectric layer, The steps of forming two first doping source regions, each located on one of the two bottom gates, wherein the two source regions are connected to a portion of the substrate located between the top gate and the bottom gate; The process includes the step of forming two source electrodes connected to the same side source region. [Effects of the Invention]

[0011] The embodiments of this application, by employing the above technical solutions, have the following technical effects.

[0012] In the vertical capacitive-coupled gate-controlled junction field-effect transistor according to the embodiment of the present application, the top gate 8 is indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9. The gate voltage applied to the coupling capacitance upper electrode 10 is coupled to the top gate 8 by coupling. Furthermore, since the top gate 8 is in a floating state and not directly connected to the gate electrode, even if the potential of the coupling capacitance upper electrode 10 rises to 3V or higher, the top gate 8, the portion of the substrate between the top gate 8 and the bottom gate 3, and the portion of the substrate between the bottom gate 3 do not conduct. Compared to the JFET device described in CN1238904C, in the embodiment of the present application, even if a high voltage (above 3V, e.g., 4V, 5V) is applied to the top gate 8, it does not conduct and does not affect the current characteristics from the drain electrode to the source electrode of the device. Because the top gate 8 is indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9, no current flows through the top gate 8, resulting in higher reliability. [Brief explanation of the drawing]

[0013] The accompanying drawings shown herein are for further understanding of this application and constitute part of this application, and the exemplary embodiments and descriptions thereof are for illustrative purposes of this application and do not constitute an unreasonable limitation of this application. Here, [Figure 1] This is a schematic diagram showing a conventional JFET device. [Figure 2] This is a schematic diagram showing a conventional SIC VDMOS device. [Figure 3-1] A schematic diagram showing a first embodiment of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-2] A schematic diagram showing a second embodiment of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-3] A schematic diagram showing a third embodiment of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-4] A schematic diagram showing a fourth embodiment of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-5] A schematic diagram showing a fifth embodiment of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 4] This is a schematic diagram illustrating the formation of an epitaxial layer on a starting substrate in a manufacturing method according to the fourth embodiment of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 5] This is a schematic diagram based on Figure 4 illustrating the formation of the top gate and the second doping type ohmic contact region. [Figure 6] This is a schematic diagram showing the formation of channel 1, channel 2, and the source region based on Figure 5. [Figure 7] This is a schematic diagram showing the formation of the top gate based on Figure 6. [Figure 8] This is a schematic diagram showing the formation of the dielectric layer and the coupling capacitance upper electrode based on Figure 7. [Figure 9] This is a schematic diagram showing the formation of the gate electrode and source electrode based on Figure 8. [Figure 10] This is a schematic diagram showing the formation of the drain electrode based on Figure 9. [Figure 11] This is an equivalent circuit diagram of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 12] This is a schematic diagram showing the current path when the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention is conducting. [Figure 13] This is a schematic diagram comparing the characteristics of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention with those of a conventional VDMOS device. [Figure 14-1] This is a schematic diagram showing the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 14-2] This figure shows the internal electric field distribution during breakdown of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 15-1] This is a schematic diagram showing the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 15-2] This is the potential distribution of the gate structure of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 16-1] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 16-2] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 16-3] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 16-4] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 16-5] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 16-6] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. [Figure 17-1] This figure shows the carrier concentration distribution in each region during device operation, as the hole concentrations in the top gate 8, channel 5, and bottom gate 3 of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention are affected by the voltage applied to the gate electrode 11. [Figure 17-2] This figure shows the carrier concentration distribution in each region during device operation, as the hole concentrations in the top gate 8, channel 5, and bottom gate 3 of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention are affected by the voltage applied to the gate electrode 11. [Figure 18-1] This figure shows the transfer characteristic curve of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 18-2] This figure shows the transfer characteristic curves of existing SiC MOSFET devices. [Modes for carrying out the invention]

[0014] To further clarify the technical solutions and advantages of the embodiments of this application, exemplary embodiments of this application will be described in more detail below with reference to the drawings. However, it is clear that the embodiments described are only a selection of embodiments of this application and do not exhaustively represent all embodiments. Furthermore, the embodiments and features of the embodiments of this application may be combined with each other without contradiction.

[0015] Conventional semiconductor devices are often manufactured using silicon, a first-generation semiconductor material. However, in recent years, silicon carbide, a third-generation wide-bandgap semiconductor material, has shown significant performance advantages over silicon-based semiconductor devices due to its material advantages such as wide bandgap, high breakdown voltage, and high thermal conductivity. However, because the growth of current silicon carbide materials is still immature, silicon carbide-based semiconductor devices have performance and reliability issues. For example, silicon carbide materials have many defects near the surface, resulting in low surface mobility and seriously impacting device performance. Furthermore, silicon carbide devices have high quality requirements for gate oxides, but the quality of existing gate oxides cannot meet these reliability requirements. In conventional power devices of the same type, the conductive channels are located on the surface of the silicon carbide material and oxide. Due to the material properties of silicon carbide, there are many charges and defects on the surface of the silicon carbide and oxide, which affects the mobility of carriers in the channels. As a result, the carrier mobility in the channels is much lower than the bulk mobility of silicon carbide. The channel mobility, i.e., surface mobility, of silicon carbide MOSFETs is approximately 20-40 cm⁻¹. 2 While the value is / V·s, the bulk mobility of silicon carbide material is approximately 1000 cm². 2is in / V·s. When the channel mobility is low, it affects the current transmission characteristics and on-resistance of the device. Also, since the part of the current flowing on the surface of the device is located under the gate oxide, unstable traps and defect centers affect the reliability of the operation of the device's gate electrode.

[0016] In the same type of power devices in the prior art, under the high voltage (breakdown condition) of the drain electrode when the device is off, the vertical epitaxial layer - JFET region - dielectric layer becomes the main breakdown voltage region. From the relationship between the electric displacement vector, electric field strength, and permittivity D = ε·E, the electric displacement vector in the semiconductor is D 半導体 = ε 半導体 ·E 半導体 It can be seen that the electric displacement vector in the dielectric layer immediately adjacent to the semiconductor is D 誘電体 = ε 誘電体 ·E 誘電体 At the interface between the semiconductor and the dielectric, the electric displacement vector D is continuous, that is, D 半導体 = D 誘電体 Therefore, ε 半導体 ·E 半導体 = ε 誘電体 ·E 誘電体 When the same type of dielectric material is adjacent to different semiconductor materials, if the substrate is silicon and silicon carbide, the permittivities ε of these two semiconductor materials are approximately the same (ε シリコン = 11.8, ε 炭化ケイ素 = 9.8), but the critical breakdown electric field strength of silicon carbide, which is a third-generation wide-bandgap semiconductor material, is much larger than that of the silicon material (E シリコン = 0.23 MV / cm, E 炭化ケイ素 = 2.2 MV / cm), ε 半導体 ·E 半導体 = ε 誘電体 ·E 誘電体 From this, it can be seen that the electric field strength in the dielectric layer corresponding to the silicon carbide material is much larger than that in the dielectric layer corresponding to the silicon material. Therefore, the dielectric layer (oxide layer or high-K dielectric) under the gate of a silicon carbide-based device in the breakdown state has a typical value of about 2×10 6With high electric field strengths of V / cm, and electric field strengths on the order of megavolts per centimeter, the high electric field strength within the dielectric layer affects the reliability of the gate electrode operation of silicon carbide-based devices.

[0017] As described above, conventional technology has several technical challenges, including the inability to apply high voltage to the gate electrode in conventional silicon carbide-based junction field-effect transistors, resulting in low gate reliability and thus limiting their application as power switches. These challenges also include performance degradation due to the conduction channel being close to the surface of a low-mobility material, and reduced device reliability due to the poor quality of the gate derivative layer.

[0018] CN116598356A discloses a SiC VDMOS device, as shown in Figure 2, where 0 is the gate oxide layer, 1 is the N-type region, 2 is the N+ doping region, 3 is the channel region, 4 is the N-type ohmic contact region, 5 is the SiC epitaxial layer, 6 is the SiC starting substrate, 7 is polysilicon, 9 is the source electrode, and 10 is the drain electrode. When no voltage is applied to the polysilicon 7, the device is off and does not conduct. When a voltage is applied to the polysilicon 7, the capacitance effect of the metal oxide semiconductor is utilized to attract positive charges near the surface of the channel region 3, forming an inverted channel on the surface and enabling conduction from the drain electrode to the source. The current (shown as a dotted line in Figure 2) first travels vertically from the drain electrode to the interface between the SiC surface and the oxide above the SiC, and then flows into the source electrode through the inverted channel on the SiC surface. That is, part of the conducting channel is vertical and located within the device, while the other part is along the transverse direction of the device surface. Due to the presence of charges, defects, and surface scattering at the interface between the semiconductor material and the oxide, the effective mobility of the SiC VDMOS surface is low. This results in a low device saturation current (Idsat), a high on-resistance (Rsp), and consequently affects device performance, limiting the device's output power and switching speed.

[0019] This application provides a vertical capacitively coupled gate-controlled junction field-effect transistor. The vertical capacitively coupled gate-controlled junction field-effect transistor of this application has a vertical device structure.

[0020] <Example 1> The first embodiment of the vertical capacitively coupled gate-controlled junction field-effect transistor according to the present invention is shown in Figure 3-1, First doping type substrate, Two second doping-type bottom gates 3 are formed within the substrate and spaced apart in the lateral direction, A second doping type top gate 8 formed in the substrate, wherein the top gate 8 is located above the gap between the two bottom gates and there is a gap between the top gate 8 and the bottom gate 3, A dielectric layer 9 formed on the substrate and located above the top gate 8, The dielectric layer 9 comprises a coupling capacitance upper electrode 10 formed on the dielectric layer 9, The top gate 8 is indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9.

[0021] Here, the top gate 8 is in a floating state, and the coupled capacitance upper electrode 10, the dielectric layer 9, and the top gate 8 together constitute the gate structure of a field-effect transistor. The second doped top gate 8, the portion of the substrate located between the top gate 8 and the bottom gate 3, and the bottom gate 3 form a JFET region. The two bottom gates 3 and the portion located between the bottom gates 3 form a JFET region 2. The top gate 8 of JFET region 1 is indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9, and thus JFET region 1 and JFET region 2 are indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9.

[0022] The portion of the substrate located between the top gate 8 and the bottom gate 3, and the portion of the substrate located between the bottom gates 3, together form a channel region.

[0023] In the vertical capacitive-coupled gate-controlled junction field-effect transistor according to the embodiment of the present application, the top gate 8 of JFET region 1 is indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9. The gate voltage applied to the coupling capacitance upper electrode 10 is coupled to the top gate 8 by coupling. Furthermore, since the top gate 8 is in a floating state and not directly connected to the gate electrode, even if the potential of the coupling capacitance upper electrode 10 rises to 3V or higher, the portion of the substrate located between the top gate 8 and the bottom gate 3 does not conduct. At this time, both JFET region 1 and JFET region 2 do not conduct. Compared with the JFET device described in CN1238904C, in the embodiment of the present application, even if a high voltage (above 3V, e.g., 4V, 5V) is applied to the top gate 8, it does not conduct and does not affect the current characteristics from the drain electrode to the source electrode of the device. Since the top gate 8 is indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9, no current flows through the top gate 8, resulting in higher reliability.

[0024] The portion located between the top gate 8 and the bottom gate 3 is maintained as a substrate, and is the portion of the substrate located between the top gate 8 and the bottom gate 3. The portion located between the bottom gates 3 is maintained as a substrate, and is the portion of the substrate located between the bottom gates 3.

[0025] The vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention is a vertical capacitively coupled gate-controlled junction field-effect transistor with a novel structure, and is neither a conventional JFET device nor a conventional SiC VDMOS device.

[0026] The vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of this application differs from conventional JFET devices in the following essential differences.

[0027] The vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention utilizes the principle of capacitive coupling to indirectly control the top gate, thereby avoiding current injection from the top gate to the channel and enabling channel control by applying a higher voltage to the upper electrode of the coupling capacitance, making it applicable to a wider range of applications.

[0028] The vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of this application differs in essential ways from a JFET device as follows:

[0029] The vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention utilizes the principle of capacitive coupling to indirectly control the on / off state of the portion located between the top gate 8 and the bottom gate 3 of the substrate, and the portion located between the bottom gate 3 of the substrate, by controlling the potential of the floating top gate 8 across the dielectric layer 9 using the coupled capacitance upper electrode 10.

[0030] In a typical JFET device, the top gate is directly connected to the electrodes, and when a high voltage is applied, the pn junction between the top gate and the channel turns on, causing current to flow from the top gate to the channel, resulting in a negative effect. In the vertical capacitively coupled gate-controlled junction field-effect transistor structure according to the embodiment of the present invention, this problem can be avoided because of the insulating dielectric layer.

[0031] Specifically, the upper surface of the top gate 8 and the upper surface of the substrate are flush.

[0032] In practice, the vertical capacitively coupled gate-controlled junction field-effect transistor is, A drain electrode 13 provided on the lower surface of the substrate, Two first doping-type source regions 7, each located above the two bottom gates, wherein the two source regions 7 are connected to the portion of the substrate located between the top gate 8 and the bottom gate 3, The system further comprises two source electrodes 12 connected to the same source region 7.

[0033] Thus, the first doping-type substrate, the portion located below the gate structure and between the bottom gate 3 of the substrate, and the portion located below the gate structure and between the top gate 8 and the bottom gate 3 of the substrate form an internal conductive path within the substrate from the drain electrode to the two source electrodes.

[0034] The main structure of the semiconductor device (including the bottom gate 3, the ohmic contact region 4 of the second doping type, the top gate 8, and the source region 7, which are part of the semiconductor device) is fabricated on the upper part of the first doping type substrate. Within the substrate, above the gap between the two bottom gates, the top gate 8 is located first, followed by the portion of the substrate located between the top gate 8 and the bottom gate 3, in that order from top to bottom. Therefore, it is guaranteed that the portion of the substrate located between the top gate 8 and the bottom gate 3, and the portion of the substrate located between the bottom gates 3, are all located within the substrate. This ensures that the lower part of the first doping type substrate, the portion of the substrate located between the bottom gates 3, the portion of the substrate located between the top gate 8 and the bottom gate 3, and the two source regions 7 are all of the first doping type. Therefore, the lower part of the first doped substrate, the portion located below the gate structure between the bottom gate 3 of the substrate, and the portion located below the gate structure between the top gate 8 and the bottom gate 3 of the substrate form an internal conduction path located within the substrate, from the drain electrode 13 to the two sources 12, and all of this internal conduction path is away from the region of low mobility on the device surface. The entire internal conduction path of the vertical capacitive-coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention is located inside the field-effect transistor, and all of this internal conduction path is away from the region of low mobility on the device surface. In other words, all of the internal conduction path is away from the semiconductor material surface, conduction occurs internally, and the problem of low surface mobility is avoided. As a result, the carriers maintain a state of high mobility and fast drift rate, and the vertical capacitive-coupled gate-controlled junction field-effect transistor has a large saturation current Idsat, a small on-resistance Rsp, and good performance.

[0035] In the SiC VDMOS device described in patent application CN116598356A, the conduction channel is partially vertical and located inside the device, while the other portion is aligned transversely to the device surface. In other words, part of the conduction channel is on the device surface. Due to charges, defects, and surface scattering at the interface between the SiC material surface and the oxide layer, the effective mobility of carriers is low, resulting in a low saturation current Idsat and a high on-resistance Rsp, which affects device performance and limits the device's output power and switching speed. That is, the vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of this application can solve the technical problem of the prior art in which device performance is degraded because the conduction channel is close to the low-mobility material surface.

[0036] The essential differences between the vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of this application and conventional SiC VDMOS devices are as follows.

[0037] In the vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of this application, the conduction path is an internal conduction path, and all of the internal conduction paths are away from the semiconductor material surface, resulting in conduction within the body. This avoids the problem of low surface mobility and provides superior performance. At the same time, the requirements for the quality of the gate dielectric layer of the device are lower, resulting in superior device reliability.

[0038] In practice, the vertical capacitively coupled gate-controlled junction field-effect transistor is, The device further comprises two second doping-type ohmic contact regions 4 provided on both sides of the two bottom gates 3, and the second doping-type ohmic contact regions 4 on the same side are connected to the bottom gates 3. The source electrode is located on the boundary between the source region 7 on the same side and the second doping type ohmic contact region 4; that is, the source electrode connects the source region 7 on the same side and the second doping type ohmic contact region 4.

[0039] The bottom gate 3 is connected to the second doping-type ohmic contact region 4, and the second doping-type ohmic contact region 4 is connected to the source electrode 12, thereby enabling the bottom gate 3 to be pulled out.

[0040] In practice, as shown in Figure 3-5, the vertical capacitively coupled gate-controlled junction field-effect transistor is used. The system further comprises a metal silicide layer 14 formed between the top gate 8 and the dielectric layer 9.

[0041] By adding a metal silicide layer (abbreviated as Silicide layer) beneath the dielectric layer of the gate, that is, by positioning the metal silicide layer between the dielectric layer 9 and the top gate 8, the metal silicide layer beneath the dielectric layer 9 is a metal layer, the electric field distribution within the metal layer is uniform, the electric field on the surface of the top gate 8 can be optimized, and device reliability can be improved.

[0042] As shown in Figure 3-1, in the implementation, the substrate is A first doping type starting substrate 1 having the drain electrode 13 provided on its lower surface, The device comprises a first doping-type epitaxial layer 2, the bottom gate 3, the top gate 8, the source region 7, and the second doping-type ohmic contact region 4, all of which are formed within the epitaxial layer 2.

[0043] Specifically, the first doped starting substrate 1 is highly doped, with a very high doping concentration, and functions as the drain region of a vertical capacitively coupled gate-controlled junction field-effect transistor.

[0044] In the implementation, the starting substrate is a silicon carbide substrate.

[0045] In practice, the starting substrate is a semiconductor device substrate such as a silicon substrate, a diamond substrate, or a potassium oxide substrate.

[0046] Conventional diamond substrate MOSFETs have a problem with their dielectric layer; the dielectric layer formed on the diamond substrate by deposition methods, such as the oxide layer, is of poor quality and therefore performs poorly. This device structure, a diamond vertical capacitively coupled gate-controlled junction field-effect transistor, solves this problem by having the conduction channel located within the device. MOSFETs (metal oxide semiconductor field-effect transistors) are common semiconductor devices.

[0047] Potassium oxide is a fourth-generation semiconductor material that can be used in the manufacture of electronic elements and electronic devices, particularly new types of controllable semiconductor devices.

[0048] In the implementation, the doping concentration of the top gate (8) is 1 × 10⁻⁶ 16 cm -3 That's all.

[0049] The doping concentration at Topgate is 1 × 10⁻¹⁶ 16 cm -3 Therefore, it is guaranteed that when a voltage is applied to the gate, the top gate will not become depleted and a strong electric field will not be generated inside the top gate.

[0050] In the implementation, the doping concentration of channel 5 is greater than the doping concentration of the substrate. The doping concentration of channel 6 is greater than the doping concentration of the substrate.

[0051] The doping concentrations in channels 1 and 2 are higher than those in the substrate, which helps reduce the device's on-resistance and improve device performance.

[0052] Specifically, silica or a high-K dielectric material may be used for the dielectric layer 9. Using a high-K dielectric helps control the coupling capacitance of the upper electrode to the P+ type top gate, thereby improving the performance of the device.

[0053] Specifically, the coupling capacitance upper electrode 10 can employ P+ and N+ type highly doped polysilicon, which reduces contact resistance with the gate metal and gate parasitic resistance, thereby improving the performance of the device.

[0054] High-K dielectrics refer to materials with a high dielectric constant (high relative permittivity).

[0055] <Example 2> As shown in Figure 3-2, a second embodiment of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention is shown. The vertical capacitively coupled gate-controlled junction field-effect transistor of the second embodiment has some structural similarities to the vertical capacitively coupled gate-controlled junction field-effect transistor of the first embodiment. The main difference between the vertical capacitively coupled gate-controlled junction field-effect transistor of the second embodiment and the vertical capacitively coupled gate-controlled junction field-effect transistor of the first embodiment is that, as shown in Figure 3-2, a first doping channel 5 is formed at a position located between the top gate 8 and the bottom gate 3 on the substrate. In this case, The top gate 8 is located above the channel 5.

[0056] As shown in Figure 3-2, the JFET region is specifically formed by a second-doped top gate 8, a first-doped channel 5, and a bottom gate 3. The JFET region 2 is still formed by two bottom gates 3 and a portion located between the bottom gates 3.

[0057] The top gate 8 of the JFET region is indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9. The channel region is formed by the portion located between the first doped channel 5 and the bottom gate 3 of the substrate.

[0058] The portion located between the top gate 8 and the bottom gate 3 forms the first doping-type channel 5, and the portion located between the bottom gates 3 is maintained as a substrate, which is the portion of the substrate located between the bottom gates 3.

[0059] As shown in Figure 3-2, the first doped substrate, the portion located below the gate structure and between the bottom gates 3 of the substrate, and the first doped channel 5 below the gate structure form an internal conduction path located within the substrate, from the drain electrode to the two source electrodes. Furthermore, all of this internal conduction path is located away from the low mobility region of the device surface.

[0060] The lower part of the first doping substrate, the portion located below the gate structure and between the bottom gate 3 of the substrate, and the first doping channel 5 located below the gate structure form an internal conduction path within the substrate, extending from the drain electrode to the source electrode. Control of this internal conduction path enables on / off control of the entire vertical capacitive-coupled gate-controlled junction field-effect transistor. On the other hand, control of the internal conduction path is achieved by controlling channel 5.

[0061] In the embodiment of the present invention, the entire internal conduction path of the vertical capacitive-coupled gate-controlled junction field-effect transistor is located inside the transistor, and all of this internal conduction path is away from the low-mobility region of the device surface. That is, all of the internal conduction path is away from the semiconductor material surface and conducts internally, thus avoiding the problem of low surface mobility. As a result, the carriers are kept in a state of high mobility and fast drift rate, and the vertical capacitive-coupled gate-controlled junction field-effect transistor has a large saturation current Idsat, a small on-resistance Rsp, and good performance.

[0062] As shown in Figure 3-2, the substrate is A first doping type starting substrate 1 has a drain electrode 13 provided on its lower surface, The device comprises a first doping-type epitaxial layer 2, the bottom gate 3, the channel 5, the top gate 8, the source region 7, and the second doping-type ohmic contact region 4, all of which are formed within the epitaxial layer 2.

[0063] Specifically, the first doped starting substrate 1 is highly doped, with a high doping concentration. It functions as the drain region of a vertical capacitively coupled gate-controlled junction field-effect transistor.

[0064] Specifically, channel 5 may be formed by ion implantation or by other means using the original substrate. The doping concentration of channel 5 will be higher than the doping concentration of epitaxial layer 2.

[0065] Specifically, since the doping concentration of channel 5 in the first doping type is higher than that of epitaxial layer 2, the resistance of channel 5 in the first doping type becomes smaller, which in turn reduces the on-resistance Rsp of the vertical capacitively coupled gate-controlled junction field-effect transistor, improving the performance of the vertical capacitively coupled gate-controlled junction field-effect transistor.

[0066] <Example 3> As shown in Figure 3-3, a third embodiment of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention is shown. The vertical capacitively coupled gate-controlled junction field-effect transistor of the third embodiment has some structural similarities to the vertical capacitively coupled gate-controlled junction field-effect transistor of the first embodiment. The main difference between the vertical capacitively coupled gate-controlled junction field-effect transistor of the third embodiment and the vertical capacitively coupled gate-controlled junction field-effect transistor of the first embodiment is that, as shown in Figure 3-3, a first-doped channel 6 is formed by ion implantation at a position located between the two bottom gates 3 of the substrate. In this case, As shown in Figure 3-3, the JFET region is specifically formed by a second-doped top gate 8, a portion of the substrate located between the top gate 8 and the bottom gate 3, and a second-doped bottom gate 3. Specifically, the JFET region 2 is formed by two bottom gates 3 and a channel 2 6. The top gate 8 of the JFET region is indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9. The entire portion of the substrate located between the top gate 8 and the bottom gate 3, along with the first doped channel 6, functions as a channel region.

[0067] The portion located between the top gate 8 and the bottom gate 3 is maintained as a substrate, and the portion of the substrate located between the top gate 8 and the bottom gate 3 forms a first doping type channel 6.

[0068] As shown in Figure 3-3, the first doped substrate, the first doped channel 6 below the gate structure, and the portion below the gate structure and located between the top gate 8 and the bottom gate 3 of the substrate form an internal conduction path located within the substrate, from the drain electrode to the two source electrodes. Furthermore, all of this internal conduction path is located away from the low mobility region of the device surface. The entire internal conduction path of the vertical capacitive-coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention is located inside the vertical capacitive-coupled gate-controlled junction field-effect transistor, and all of this internal conduction path is located away from the low mobility region of the device surface. In other words, all of the internal conduction path is located away from the semiconductor material surface, conducting within the body and avoiding the problem of low surface mobility. As a result, the carriers are kept in a state of high mobility and fast drift velocity, and the vertical capacitive-coupled gate-controlled junction field-effect transistor has a large saturation current Idsat, a small on-resistance Rsp, and good performance.

[0069] As shown in Figure 3-3, the substrate is A first doping type starting substrate 1 having the drain electrode 13 provided on its lower surface, The device comprises a first doping type epitaxial layer 2, the bottom gate 3, the channel 6, the top gate 8, the source region 7, and the second doping type ohmic contact region 4, all of which are formed within the epitaxial layer 2.

[0070] Specifically, the first doped starting substrate 1 is highly doped, with a high doping concentration. It functions as the drain region of a vertical capacitively coupled gate-controlled junction field-effect transistor.

[0071] Specifically, channel 6 is formed by ion implantation. The doping concentration in channel 6 is higher than the doping concentration in epitaxial layer 2.

[0072] Specifically, since the doping concentration of channel 6 in the first doping type is higher than that of epitaxial layer 2, the resistance of channel 6 in the first doping type becomes smaller, which in turn reduces the on-resistance RSP of the vertical capacitively coupled gate-controlled junction field-effect transistor, improving the performance of the vertical capacitively coupled gate-controlled junction field-effect transistor.

[0073] <Example 4> As shown in Figure 3-4, a fourth embodiment of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention is shown. The vertical capacitively coupled gate-controlled junction field-effect transistor of the fourth embodiment is structurally identical in some respects to the vertical capacitively coupled gate-controlled junction field-effect transistor of the second embodiment. The main difference between the vertical capacitively coupled gate-controlled junction field-effect transistor of the fourth embodiment and the vertical capacitively coupled gate-controlled junction field-effect transistor of the second embodiment is that, as shown in Figure 3-4, a first-doped channel 6 is formed by ion implantation at a position located between the two bottom gates 3 of the substrate. In this case,

[0074] As shown in Figure 3-4, the JFET region is specifically formed by a second-doped top gate 8, a first-doped channel 5, and a second-doped bottom gate 3.

[0075] Specifically, the JFET region 2 is formed by two bottom gates 3 and a channel 2 6.

[0076] The top gate 8 of the JFET region is indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9.

[0077] The first doping-type channel 5 and the first doping-type channel 6 function together as a channel region.

[0078] The portion located between the top gate 8 and the bottom gate 3 forms a first doping-type channel 5, and the portion located between the bottom gates 3 forms a first doping-type channel 6.

[0079] As shown in Figure 3-4, the first doped substrate, the first doped channel 6, and the first doped channel 5 form an internal conductive path located within the substrate, extending from the drain electrode to the two source electrodes. Furthermore, all of this internal conductive path is located away from the low mobility region of the device surface.

[0080] Specifically, the first doping type substrate, the first doping type channel 6, and the first doping type channel 5 are connected in sequence. Current is transmitted from the drain electrode 13, flows through the first doping type substrate and the first doping type channel 6, flows to the two source regions 7 on the left and right in the first doping type channel 5, and is finally collected by the two source electrodes 12 on the left and right.

[0081] The lower part of the first doped substrate, the first doped channel 6, and the first doped channel 5 form an internal conduction path located within the substrate, extending from the drain electrode to the source electrode. Control of this internal conduction path enables on / off control of the entire vertical capacitive-coupled gate-controlled junction field-effect transistor. On the other hand, control of the internal conduction path is achieved through control of channel 5.

[0082] In the embodiment of the present invention, the entire internal conduction path of the vertical capacitive-coupled gate-controlled junction field-effect transistor is located inside the transistor, and all of these internal conduction paths are away from the low-mobility region of the device surface. In other words, all of the internal conduction paths are away from the semiconductor material surface, conducting within the transistor and avoiding the problem of low surface mobility. As a result, the carriers are kept in a state of high mobility and fast drift rate, resulting in a large saturation current Idsat and a small on-resistance Rsp of the vertical capacitive-coupled gate-controlled junction field-effect transistor, and thus good performance.

[0083] As shown in Figure 3-4, the substrate is A first doping type starting substrate 1 having the drain electrode 13 provided on its lower surface, The device comprises a first doping type epitaxial layer 2, the bottom gate 3, channel 2 6, channel 1 5, top gate 8, source region 7, and a second doping type ohmic contact region 4 formed within the epitaxial layer 2.

[0084] Specifically, the first doped starting substrate 1 is highly doped, with a high doping concentration. It functions as the drain region of a vertical capacitively coupled gate-controlled junction field-effect transistor.

[0085] Specifically, since the doping concentrations of the first-doped channel 5 and the first-doped channel 6 are higher than the doping concentration of the epitaxial layer 2, the resistance between the first-doped channel 5 and the first-doped channel 6 decreases, which in turn reduces the on-resistance Rsp of the vertical capacitive-coupled gate-controlled junction field-effect transistor, improving the performance of the vertical capacitive-coupled gate-controlled junction field-effect transistor.

[0086] Furthermore, the vertical capacitively coupled gate-controlled junction field-effect transistors according to Examples 1 to 4 can all be implemented as both normally-off and normally-on devices.

[0087] To implement the vertical capacitively coupled gate-controlled junction field-effect transistors according to Examples 1-4 as normally-off devices, By controlling the doping of the second-doped bottom gate 3, the first-doped channel 5, the first-doped channel 6, and the second-doped top gate 8, when the voltage of the coupling capacitance upper electrode 10 is zero, the region between the bottom gate 3 and the top gate 8 becomes depleted, and the field-effect transistor becomes a normally-off device. Here, the doping position and doping concentration of the bottom gate 3 and top gate 8 are mainly adjusted to play a supplementary role to the doping position and doping concentration of the first-doped channel 5 and the first-doped channel 6.

[0088] Furthermore, if either or both of the first doped channel 5 and the first doped channel 6 are absent, the vertical capacitively coupled gate-controlled junction field-effect transistor can be implemented as a normally-off device by adjusting the doping position and doping concentration of the bottom gate 3 and the top gate 8.

[0089] If a vertical capacitively coupled gate-controlled junction field-effect transistor is a normally-off device, If the first type of doping is N-type doping and the second type of doping is P-type doping, When no voltage is applied to a vertical capacitively coupled gate-controlled junction field-effect transistor, the vertical capacitively coupled gate-controlled junction field-effect transistor turns off.

[0090] When a positive voltage is applied to a vertical capacitively coupled gate-controlled junction field-effect transistor, the vertical capacitively coupled gate-controlled junction field-effect transistor turns on.

[0091] If the first type of doping is P-type doping and the second type of doping is N-type doping, When no voltage is applied to a vertical capacitively coupled gate-controlled junction field-effect transistor, the vertical capacitively coupled gate-controlled junction field-effect transistor turns off.

[0092] When a negative voltage is applied to a vertical capacitively coupled gate-controlled junction field-effect transistor, the vertical capacitively coupled gate-controlled junction field-effect transistor turns on.

[0093] In order to implement the vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of this application as a normally-on device, By controlling the doping of the second-doped bottom gate 3, the first-doped channel 5, the first-doped channel 6, and the second-doped top gate 8, when the voltage of the coupled capacitance upper electrode 10 is zero, channel 5, sandwiched between the bottom gate 3 and the top gate 8, becomes conductive, and the vertical capacitive coupled gate-controlled junction field-effect transistor is a normally-on device. Here, the doping position and doping concentration of the bottom gate 3 and top gate 8 are mainly adjusted to play a supplementary role to the doping position and doping concentration of the first-doped channel 5 and the first-doped channel 6.

[0094] Furthermore, if either or both of the first doped channel 5 and the first doped channel 6 are absent, the vertical capacitively coupled gate-controlled junction field-effect transistor can be implemented as a normally-on device by adjusting the doping position and doping concentration of the bottom gate 3 and the top gate 8.

[0095] When a vertical capacitively coupled gate-controlled junction field-effect transistor is a normally-on device, If the first type of doping is N-type doping and the second type of doping is P-type doping, When no voltage is applied to a vertical capacitively coupled gate-controlled junction field-effect transistor, the vertical capacitively coupled gate-controlled junction field-effect transistor turns on.

[0096] When a negative voltage is applied to a vertical capacitively coupled gate-controlled junction field-effect transistor, the vertical capacitively coupled gate-controlled junction field-effect transistor turns off.

[0097] If the first type of doping is P-type doping and the second type of doping is N-type doping, When no voltage is applied to a vertical capacitively coupled gate-controlled junction field-effect transistor, the vertical capacitively coupled gate-controlled junction field-effect transistor turns on.

[0098] When a positive voltage is applied to a vertical capacitively coupled gate-controlled junction field-effect transistor, the vertical capacitively coupled gate-controlled junction field-effect transistor turns off.

[0099] The vertical capacitively coupled gate-controlled junction field-effect transistors according to Examples 1-4 of this application have a threshold voltage of 3.03V, a breakdown voltage of 1507V, and an on-resistance of 0.192Ω·mm. 2 That is the case.

[0100] In the vertical capacitively coupled gate-controlled junction field-effect transistors of Examples 1-4, all conduction channels are located inside the device and are less susceptible to influences from the device's interface charge and low interface mobility.

[0101] Compared to conventional silicon carbide-based VDMOS, the on-resistance is improved by 20%. Due to the capacitive coupling effect of the channel, the current of this invention saturates under high gate voltages, improving the short-circuit resistance of the device. The gate electrode of the vertical capacitively coupled gate-controlled junction field-effect transistor of this invention is a capacitively coupled gate, which operates using the principle of capacitive coupling to control the operation of the device. The requirements for the work function of the capacitance electrodes are low, and coupled capacitive dielectrics can be used flexibly. The typical electric field strength in the dielectric layer at the breakdown of the device is approximately 2 × 10⁻⁶. 5 With a voltage of V / cm, it is approximately an order of magnitude lower than conventional silicon carbide devices, has lower quality requirements for capacitively coupled dielectrics, and clearly offers higher reliability, robustness, and manufacturing advantages.

[0102] The following explanation will use the case where the first doping type is N-type and the second doping type is P-type as an example.

[0103] The P+ type top gate 8, the N type channel 5, and the P type bottom gate 3 form a JFET region, the P+ type top gate 8 and the N type channel 5 form a single PN junction, and the P type bottom gate 3 and the N type channel 5 form a single PN junction. By controlling the voltage of the coupling capacitance upper electrode 10, depletion and pinch-off of channel 5 are achieved, which in turn enables control of the internal conduction path, and ultimately enables on / off control of the vertical capacitance-coupled gate-controlled junction field-effect transistor.

[0104] In the CN1238904C JFET element, the gate electrode and channel have a pn junction structure, making it impossible to apply a voltage of 3V or higher to the gate electrode. When using SiC as the starting substrate material, applying a voltage of 3V or higher to the gate electrode causes conduction between the gate electrode and the channel or source electrode. The resulting large conduction current affects the current characteristics between the drain electrode and the source electrode, preventing the application of high voltages to the gate electrode and limiting its use as a power switch.

[0105] Next, we will explain using the example that the first doping type is N-type and the second doping type is P-type.

[0106] In the vertical capacitive-coupled gate-controlled junction field-effect transistor (JFET) region according to this embodiment, the depletion region formed by the self-formed electric field of two PN junctions—the depletion region formed by the P+-type top gate 8 and the self-formed electric field of the N-type channel 5, and the depletion region formed by the P-type bottom gate 3 and the self-formed electric field of the N-type channel 5—is connected, thereby realizing self-depletion and pinch-off of the N-type channel 5 and realizing the normally-off function of the device. That is, when no voltage is applied to the coupling capacitance upper electrode 10, the drain electrode-source electrode is off, and when a voltage is applied to the coupling capacitance upper electrode 10, the channel between the drain electrode and source electrode is opened.

[0107] The CN1238904C JFET element is a normally-on device, meaning that the device is on when no voltage is applied to the gate electrode, and it cannot be turned off unless a negative voltage is applied to the gate electrode, thus limiting its application as a power switch.

[0108] <Example 5> The method for manufacturing a vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention is as follows: The steps include forming a first-doped substrate, The steps include forming two second doping-type bottom gates 3 that are formed within the substrate and spaced apart in the lateral direction, A step of forming a second doping-type top gate 8 formed in the substrate, wherein the top gate 8 is located above the gap between the two bottom gates and there is a gap between the top gate 8 and the bottom gate 3, The steps include forming a dielectric layer 9 on the substrate and located above the top gate 8, The step of forming a coupling capacitance upper electrode 10 formed on the dielectric layer 9, The steps of forming two first doping-type source regions 7, each located above the two bottom gates, wherein the two source regions 7 are connected to a portion of the substrate located between the top gate 8 and the bottom gate 3; The process includes the step of forming two source electrodes 12 connected to the same side source region 7.

[0109] In implementation, the manufacturing method is: The method further includes forming a first doping-type channel 5 in the portion between the top gate 8 and the bottom gate 3, wherein the top gate 8 is located above the channel 1.

[0110] In implementation, the manufacturing method is: The process further includes the step of forming a first doping-type channel 6 between the two bottom gates by ion implantation.

[0111] In the implementation, the dielectric layer is a dielectric layer made of a high dielectric constant material, and the coupling capacitance upper electrode 10 is a polysilicon electrode or a metal electrode.

[0112] In practice, the method for manufacturing a vertical capacitively coupled gate-controlled junction field-effect transistor is as follows: The steps include providing a drain electrode 13 on the lower surface of the substrate, The steps of forming two first doping-type source regions 7, each located above the two bottom gates, wherein the two source regions 7 are connected to a portion of the substrate located between the top gate 8 and the bottom gate 3; The method further includes the step of forming two second doping type ohmic contact regions 4, each provided on either side of the two bottom gates 3, wherein the second doping type ohmic contact regions 4 on the same side are connected to the bottom gates 3, The source electrode is located on the boundary between the source region 7 and the second doping type ohmic contact region 4 on the same side, and the source electrode connects the source region 7 and the second doping type ohmic contact region 4 on the same side.

[0113] Next, a method for manufacturing a vertical capacitively coupled gate-controlled junction field-effect transistor according to an embodiment of the present application will be described, taking as an example the case where the first doping type is N-type and the second doping type is P-type, and including the following steps.

[0114] Referring to Figure 4, in the embodiment of the present invention, a SiC N+ type starting substrate 1 is used as the starting substrate structure for the vertical capacitively coupled gate-controlled junction field-effect transistor. This low-resistance starting substrate structure is used as a support structure, and an N-type epitaxial layer 2 is formed on it by epitaxial growth. The epitaxial layer 2 serves as the drift region for the device breakdown voltage and as the main region for forming the device.

[0115] Referring to Figure 5, based on the structure formed in Figure 4, a P-type bottom gate 3 and a P+-type ohmic contact region 4 are formed by ion implantation. Two parts of the P-type bottom gate 3 are implanted while maintaining an appropriate distance from each other and are then used to form an N-type channel 6 by implantation. This device has an intermediate symmetric structure and is a single complete cell; the actual device is composed of multiple similar cells arranged in a row.

[0116] Referring to Figure 6, based on the structure formed in Figure 5, N-type channel 5, N-type channel 2, and N+-type ohmic contact region 7 are formed by ion implantation, creating a conductive path from the drain electrode to the source electrode, namely the N+-type starting substrate 1, the N-type epitaxial layer 2, the N-type channel 2, the N-type channel 5, and the N+-type ohmic contact region 7. Current is then passed from the drain electrode 13 and collected by the two source electrodes 12 on the left and right.

[0117] Referring to Figure 7, a P+-type top gate 8 is formed by ion implantation based on the structure formed in Figure 6. The P+-type top gate, N-type channel 5, and P-type bottom gate 3 form the JFET region.

[0118] Referring to Figure 8, a dielectric layer 9 is formed by chemical vapor deposition based on the structure formed in Figure 7, and a coupling capacitance upper electrode 10 is deposited above the dielectric layer 9.

[0119] Referring to Figure 9, based on the structure formed in Figure 8, a metal silicide for the device surface source electrode 12 is formed by deposition, thermal reaction, and etching, creating a deposition with good ohmic contact with the device. Subsequently, a passivation layer is deposited through a later process, through holes are etched, surface metals are formed, and the device coupling capacitance upper electrode and source electrode are brought to the surface, completing the device surface process and structure.

[0120] Referring to Figure 10, based on the structure formed in Figure 9, after the surface process of the device is completed, the entire back surface of the wafer is ground to thin it, and the back surface is metallized to fabricate the back surface drain electrode 13 of the device, thereby forming the overall vertical device structure.

[0121] The operating principle of the vertical capacitively coupled gate-controlled junction field-effect transistor of this invention will be described in detail below.

[0122] The equivalent circuit diagram of the vertical capacitive-coupled gate-controlled junction field-effect transistor in Example 4 (corresponding to Figures 3 and 4) is shown in Figure 11. The capacitor and the gate electrode of the junction field-effect transistor are connected in series. In this circuit diagram, the capacitor couples with the semiconductor junction capacitance of the JFET to divide the voltage and control the on / off state of the junction field-effect transistor.

[0123] When the vertical capacitive-coupled gate-controlled junction field-effect transistor of this invention operates, a voltage is applied to the coupling capacitance upper electrode 10 and the drain electrode 13. The voltage applied to the coupling capacitance upper electrode 10 is coupled to the top gate 8 via the coupling capacitance upper electrode 10 and the dielectric layer 9. The potential coupled to the top gate 8 and the bottom gate 3 connected to the source electrode form a control channel region of the JFET device, which controls the on / off state of the intermediate channel.

[0124] When the applied voltage turns off the channels, the JFET region (including JFET region 1 and JFET region 2) is in an off state, and channels 1-5 and 2-6 are depleted. In the depleted state, the number of carriers in the channels is relatively small. At this time, if a voltage is applied to the drain electrode 13, the device channels are depleted and in an off state, so no current flows between the drain electrode 13 and the source electrode 12, or only a very small current flows.

[0125] When the applied voltage turns on the channels, the JFET region (including JFET region 1 and JFET region 2) becomes conductive, channels 1 5 and 2 6 become conductive, and the drain electrode and source electrode are connected. At this time, if a further voltage is applied to the drain electrode 13, the device channels are conductive and in the ON state, so current flows from the drain electrode 13 to the source electrode 12, and the device operates.

[0126] The vertical capacitively coupled gate-controlled junction field-effect transistor of this invention is a device that modulates the FET channel current by utilizing the characteristics of a SiC wide-bandgap semiconductor.

[0127] Conventional technologies employ three common methods for channel modulation. The first method is the inversion layer used in conventional Si MOSFETs, which, when combined with high-quality silicon dioxide grown using thermal-oxygen growth more suitable for silicon materials, enables large-scale production and application.

[0128] The second approach involves GaAs / AlGaAs or GaN / AlGaN heterojunction FETs, abbreviated as HFETs. This device structure is difficult to fabricate in an enhanced form factor, a challenge currently addressed by methods such as embedded gate structures and fluoride ion implantation.

[0129] The third approach is the JFET principle. Because silicon has a bandgap width of only 1.1 eV, silicon-based JFET devices can only be fabricated as normally-on devices. The present invention combines the wide bandgap characteristics of SiC material with the high built-in voltage created by the SiC wide bandgap to control the channel current and realize the normally-off function of the device (threshold voltage does not exceed 1V, and operating voltage does not exceed 3V). Combined with a capacitively coupled gate structure, the threshold voltage can reach 3V or higher and the operating voltage can reach 15V or higher, perfectly matching the performance of existing SiC MOSFETs.

[0130] The threshold voltage of the vertical capacitive-coupled gate-controlled junction field-effect transistor of this invention can be modulated by doping. When the JFET region forms self-pinch-off by doping control, when no voltage is applied to the device gate, the carriers in channel 5 and channel 6 are depleted by the built-in electric field due to the doping itself, forming a depleted region. At this time, the device is a normally-off device, and the depleted region can be eliminated by applying a positive voltage to the JFET region (including JFET region 1 and JFET region 2), thereby forming an effective channel and enabling conduction. Due to the wide bandgap characteristics of silicon carbide, the built-in potential of the pn junction formed from silicon carbide material is large, enabling the realization of a normally-off device structure.

[0131] When the JFET region (including JFET region 1 and JFET region 2) is not forming a self-pinch-off state, the device itself is a normally-on device with a channel present. According to the operating principle of the JFET, the corresponding voltage must be applied to the control region of the JFET, causing the channel to form a depletion region and turn off the device.

[0132] The on-resistance Rsp of the vertical capacitively coupled gate-controlled junction field-effect transistor apparatus of the present invention is mainly determined by the resistance R1 of JFET region 1, the resistance R2 of JFET region 2, and the resistance R3 of epitaxial layer 2. The voltage applied to the drain electrode 13 of the device is divided by the three resistors connected in series, reducing the resistance of each region and optimizing the on-resistance Rsp of the entire device.

[0133] The advantages of the vertical capacitively coupled gate-controlled junction field-effect transistor device of this application will be described below.

[0134] The gate of the vertical capacitively coupled gate-controlled junction field-effect transistor of this invention employs a capacitance coupling method, which offers the following advantages compared to conventional wide-bandgap metal-oxide-semiconductor field-effect transistors.

[0135] Figure 12 is a schematic diagram showing the current path when the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention is conducting. Figure 13 is a schematic diagram comparing the characteristics of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention with those of a conventional VDMOS device.

[0136] As shown in Figure 12, the solid line with the arrow represents the current path when the field-effect transistor is conducting. As shown in Figure 12, the current path when the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention conducts is located within the device and away from the surface of the semiconductor material, and is therefore not affected by the low interface mobility of the material. The performance of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention is mainly influenced by the thickness of the capacitive dielectric, and the work function requirements of the electrodes are low. For example, if the coupled capacitive upper electrode 10 is made of polysilicon material, either N-type polysilicon or P-type polysilicon can play the role of capacitive coupling, and capacitive dielectrics such as ordinary oxide materials or HighK dielectrics can be flexibly used, and both can play the role of capacitance coupling.

[0137] Figure 13 is a schematic diagram comparing the characteristics of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention with those of a conventional VDMOS technology device. As shown in Figure 13, when the area of ​​the active region is the same, the on-resistance of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention is smaller, clearly demonstrating the superiority of its on-resistance Rsp.

[0138] Figure 14-1 is a schematic diagram showing a vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention.

[0139] Figure 14-2 shows the vertical internal electric field distribution during breakdown of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention. In Figure 14-2, the vertical axis represents the electric field strength, and the horizontal axis represents the vertical position.

[0140] In Figure 14-1, the vertical dashed lines represent the vertical direction. The portion of the vertical dashed lines below the horizontal dashed lines corresponds to the area to the right of coordinate 0 on the horizontal axis in Figure 14-2, while the portion of the vertical dashed lines above the horizontal dashed lines corresponds to the area to the left of coordinate 0 on the horizontal axis in Figure 14-2.

[0141] As shown in Figure 14-1, the vertical capacitively coupled gate-controlled junction field-effect transistor of this invention operates using the principle of capacitive coupling. Therefore, the dielectric layer functions as an insulating layer, and when a voltage is applied to the gate of the device, the potential is coupled to the top gate 8. However, due to the physical floating of the top gate 8, current does not flow through the dielectric layer 9 to the top gate 8, which is the main control region of the JFET region of the device. As shown in Figure 12, since the current conduction path of the device does not pass through the top gate 8, a large current is not generated in the top gate 8, resulting in relatively high reliability. As shown in Figure 14-2, under the high drain voltage (breakdown condition) when the device is turned off, the vertical epitaxial layer-JFET region (JFET region 1 and JFET region 2)-top gate-dielectric layer becomes the main breakdown voltage region. Due to the presence of the semiconductor pn junction structure between the JFET region (JFET region 1 and JFET region 2) and the top gate, a fixed negative charge exists in the depletion region within the top gate, and the electric field line starts from the positive charge in the epitaxial layer and ends at the negative charge in the top gate. Therefore, the high electric field is shielded at the junction interface of the semiconductor junction. The electric field strength within the dielectric layer is reduced by the shielding effect of the top gate, and the typical electric field strength within the dielectric layer is approximately 2 × 10⁻⁶. 5 The electric field strength is V / cm (the field strength within the dielectric layer at the location indicated by the circle in Figure 14-2), which is an order of magnitude lower than the field strength of the dielectric layer in conventional silicon carbide VDMOS devices. Low dielectric layer field strength plays an important role in protecting the dielectric layer and improving its reliability.

[0142] Figure 15-1 is a schematic diagram showing the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention.

[0143] Figure 15-2 shows the potential distribution of the gate structure of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention. As shown in Figure 15-2, the vertical axis represents the potential distribution, and the horizontal axis represents the vertical position.

[0144] Here, in Figure 15-1, the vertical dashed line represents the vertical direction. In Figure 15-2, the portion of the vertical dashed line below the horizontal dashed line corresponds to the portion to the right of coordinate 0 on the horizontal axis of Figure 15-2. In Figure 15-2, the portion of the vertical dashed line above the horizontal dashed line corresponds to the portion to the left of coordinate 0 on the horizontal axis of Figure 15-2.

[0145] In the operating device of this invention, the current saturates at a high gate voltage due to the capacitive coupling effect of the channel.

[0146] The gate voltage division principle of the device of this invention is as shown in Figure 15-2, and is based on the dielectric layer capacitance C, which is composed of the coupling capacitance upper electrode 10, dielectric layer 9, and top gate 8. ゲート The junction capacitance C is formed by the semiconductor depletion region formed by the top gate 8 and the channel 5. 半導体 The two capacitances, and , are connected in series to divide the voltage and control the on / off state of the channel. When the external gate voltage is Vgs, the dielectric capacitance C ゲート The voltage distributed is Vgs·C 半導体 / (C ゲート +C 半導体 ) and the junction capacitance C in the semiconductor depletion region 半導体 The voltage distributed is Vgs·C ゲート / (C ゲート +C 半導体 ) is the dielectric layer capacitance C. ゲート This is determined as a fixed value by the material and thickness of the dielectric layer 9, and when Vgs increases from 0, C ゲート And the junction capacitance C in the depletion region formed by the self-formed electric field of the semiconductor. 半導体 The voltages are divided, and a portion of the voltage Vgs applied to the upper electrode 10 is coupled to the semiconductor junction, and at this time the junction capacitance C in the semiconductor depletion region 半導体 The percentage C of the voltage coupled to it ゲート / (Cゲート +C 半導体 ) becomes maximum. The gate voltage Vgs rises and the junction capacitance C in the semiconductor depletion region increases. 半導体 As the voltage coupled to it increases, the semiconductor junction capacitance C 半導体 The depletion region becomes narrower, and the junction capacitance C 半導体 The junction capacitance C in the semiconductor depletion region becomes larger. 半導体 The percentage C of the voltage coupled to it ゲート / (C ゲート +C 半導体 The junction capacitance C in the semiconductor depletion region gradually decreases. When the semiconductor depletion region narrows to a certain extent, the area in close contact with the semiconductor junction interface cannot be narrowed further, and the junction capacitance C in the semiconductor depletion region decreases. 半導体 The voltage rises to a relatively large value and remains thereafter, and there is no further increase. At this point, the voltage Vgs applied to the coupling capacitance upper electrode 10 and the potential coupled to the top gate 8 become maximum, and the device saturates.

[0147] Figures 16-1, 16-2, 16-3, 16-4, 16-5, and 16-6 show the energy band distribution when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical capacitive coupled gate-controlled junction field-effect transistor of the present invention, with the vertical axis representing the potential distribution and the horizontal axis representing the vertical position.

[0148] Here, in Figure 15-1, the vertical dashed lines represent the vertical direction. In Figure 15-1, the portion of the vertical dashed lines below the horizontal dashed lines corresponds to the portion to the right of coordinate 0 on the horizontal axis in Figures 16-1, 16-2, 16-3, 16-4, 16-5, and 16-6. In Figure 15-1, the portion of the vertical dashed lines above the horizontal dashed lines corresponds to the portion to the left of coordinate 0 on the horizontal axis in Figures 16-1, 16-2, 16-3, 16-4, 16-5, and 16-6.

[0149] As shown in Figures 16-1, 16-2, 16-3, 16-4, 16-5, and 16-6, the energy band distributions in the top gate 8, channel 5, and bottom gate 3 of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention show the relative changes in the conduction band, valence band, and Fermi levels of electrons and holes in each region when the gate of the device is operating. As shown in Figure 16-1, when the voltage Vgs applied to the coupling capacitance upper electrode 10 is 0V, taking channel 5 in a self-depleted state as an example, the Fermi level of channel 5 is located at the center of the band gap, the device is in a self-depleted state, and the concentrations of both electrons and holes in channel 5 are very low. The Fermi levels in the top gate 8 and bottom gate 3 are located near the valence band, with an extremely high concentration of holes and an extremely low concentration of electrons. As the voltage Vgs applied to gate 11 increases, the distance between the conduction band and the Fermi level of electrons in the top gate 8 and channel 5 gradually decreases, causing a low concentration of electrons to appear in the top gate 8, the conduction band in channel 5 to be close to the Fermi level of electrons, and the electron concentration in channel 5 to be very high, contributing to conductivity and forming a conductive channel. Additionally, the distance between the valence band and the Fermi level of holes in channel 5 gradually decreases, causing a low concentration of holes to appear in channel 5.

[0150] Figure 17-1 shows the carrier concentration distribution in each region when the device is operating, with the hole concentrations in the top gate 8, channel 5, and bottom gate 3 of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention being affected by the voltage applied to gate 11, where the vertical axis represents the hole concentration and the horizontal axis represents the vertical position. Figure 17-2 shows the carrier concentration distribution in each region when the device is operating, with the hole concentrations in the top gate 8, channel 5, and bottom gate 3 of the vertical capacitive-coupled gate-controlled junction field-effect transistor of the present invention being affected by the voltage applied to gate 11, where the vertical axis represents the hole concentration and the horizontal axis represents the vertical position. As shown in Figures 17-1 and 17-2, when the voltage Vgs applied to gate 11 is 0V, the hole concentration in the top gate 8 is extremely high and the electron concentration is extremely low, and when channel 5 is modulated into a self-depleted state by doping, both the electron and hole concentrations are extremely low. As the voltage Vgs applied to gate 11 increases, both the capacitor coupled to the dielectric layer 9 and the voltage drop on the semiconductor junction capacitor formed by top gate 8 and channel 5 increase due to the capacitive coupling principle. As the voltage on the semiconductor junction formed by top gate 8 and channel 5 increases, the depletion region within channel 5 narrows, and the depleted state becomes non-depleted, causing the electron concentration within channel 5 to rise sharply and forming a conductive channel. Additionally, the built-in potential at the semiconductor junction formed by top gate 8 and channel 5 decreases, allowing some electrons from channel 5 to enter top gate 8. As a result, the electron concentration in top gate 8 changes from extremely low to extremely low, and some holes from top gate 8 enter channel 5, increasing the hole concentration at the semiconductor junction of top gate 8 and channel 5.

[0151] Figure 18-1 shows the transfer characteristic curve of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention. As shown in Figure 18-1, the transfer characteristic of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention is as follows: According to the principle of transfer characteristics, a voltage is applied to both the gate electrode and the drain electrode, where the horizontal axis of the coordinate system is the gate voltage and the vertical axis is the drain current. When the gate voltage is low, the off-current of the device is small, and as the gate voltage increases, the drain current increases, and when the gate voltage increases significantly, the magnitude of the semiconductor junction capacitance is stably maintained and the device saturates. Figure 18-2 shows the transfer characteristic curve of an existing SiC MOSFET device, where the vertical axis is the drain current and the horizontal axis is the gate voltage. Current SiC MOSFET devices still do not show current saturation characteristics even at Vgs 20V, and in the device of the present invention, the bus through which the current flows is away from the surface of the dielectric, thereby improving the short-circuit resistance capability of the device. In Figure 18-1, when the gate voltage reaches 6V, the gate voltage is almost stable. In Figure 18-2, the gate voltage rises rapidly even after 15V. Therefore, the vertical capacitively coupled gate-controlled junction field-effect transistor of this invention has high stability.

[0152] The vertical capacitively coupled gate-controlled junction field-effect transistor of this invention clearly offers high reliability, high robustness, and manufacturing advantages.

[0153] In the description of this application and its embodiments, the orientations or positional relationships indicated by terms such as "peak," "base," and "height" are based on the orientations or positional relationships shown in the drawings and are merely for the purpose of facilitating and simplifying the description of this application. It should be understood that these terms do not indicate or imply that the referred devices or elements have a specific orientation, or must be constructed and operate in a specific orientation. Therefore, they should not be understood as limiting this application.

[0154] In this application and its embodiments, unless otherwise explicitly stated and limited, terms such as “to provide,” “to attach,” “to connect,” “to link,” and “to fix” should be understood broadly, and may, for example, be a fixed connection, a removable connection, or an integral connection; they may be a mechanical connection, an electrical connection, or a communication; they may be a direct connection, an indirect connection via an intermediate medium, an internal communication between two elements, or an interaction relationship between two elements. A person skilled in the art will be able to understand the specific meaning of the terms described herein depending on the specific circumstances.

[0155] In the present application and its embodiments, unless otherwise explicitly stated and limited, the presence of a first feature "above" or "below" a second feature may mean that the first and second features are in direct contact or indirectly in contact via an intermediate medium. Furthermore, the presence of a first feature "above," "above," and "on the top surface" of a second feature may mean that the first feature is directly above or diagonally above the second feature, or simply that the horizontal height of the first feature is greater than that of the second feature. The presence of a first feature "below," "below," and "on the bottom surface" of a second feature may mean that the first feature is directly below or diagonally below the second feature, or simply that the horizontal height of the first feature is lower than that of the second feature.

[0156] The above disclosure provides many different embodiments or examples for implementing different structures of the present application. For the sake of brevity of the disclosure, the components and settings of specific examples are described above. Of course, these are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numbers and / or reference letters in different examples for the purposes of simplification and clarity and are not in themselves to indicate relationships between the various embodiments and / or arrangements discussed. Furthermore, while the present application describes examples of various specific processes and materials, those skilled in the art may anticipate the application of other processes and / or the use of other materials.

[0157] While preferred embodiments of the present application have been described, those skilled in the art, knowing the basic inventive concept, may make additional changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as encompassing the preferred embodiments and all changes and modifications that should fall within the scope of the present application.

[0158] Clearly, a person skilled in the art can make various modifications and variations to this Application without departing from the spirit and scope of this Application. Thus, if such modifications and variations of this Application fall within the scope of the claims of this Application and their equivalents in the art, this Application also intends to include such modifications and variations. [Explanation of symbols]

[0159] 1 Starting board 2. Epitaxial layer 3 Bottom Gate 4. Ohmic contact region of the second doping type 5 Channel 1 6 Channel 2 7. Source Area 8 Top Gate 9. Dielectric layer 10 Coupling capacitance upper electrode 12 Source electrodes 13 Drain electrode 14 Metallic silicidal layer

Claims

1. First doping type substrate, Two second doping-type bottom gates (3) are formed within the substrate and are spaced apart in the lateral direction, A second doping-type top gate (8) formed in the substrate, wherein the top gate (8) is located above the gap between the two bottom gates and there is a gap between the top gate (8) and the bottom gate (3), A first doping-type channel (5) formed in the portion between the top gate (8) and the bottom gate (3), wherein the top gate (8) is located above the first doping-type channel (5), A dielectric layer (9) formed on the substrate and located above the top gate (8), The device comprises a coupling capacitance upper electrode (10) formed on the dielectric layer (9), The top gate (8) is indirectly controlled by the coupling capacitance upper electrode (10) across the dielectric layer (9), The top gate (8) is floating, and the coupled capacitance upper electrode (10), the dielectric layer (9), and the top gate (8) together constitute a gate structure. The second doping type top gate (8), the first doping type channel (5), and the bottom gate (3) form a JFET region. The top gate of the JFET region 1 is indirectly controlled by the coupling capacitance upper electrode (10) across the dielectric layer (9), and the JFET region 1 is indirectly controlled by the coupling capacitance upper electrode (10) across the dielectric layer (9). A vertical capacitively coupled gate-controlled junction field-effect transistor characterized by the following features.

2. The two bottom gates (3) and the portion located between the two bottom gates (3) form a JFET region 2. The top gate of JFET region 1 is indirectly controlled by the coupling capacitance upper electrode (10) across the dielectric layer (9), and JFET region 2 is indirectly controlled by the coupling capacitance upper electrode (10) across the dielectric layer (9). The vertical capacitively coupled gate-controlled junction field-effect transistor according to feature 1.

3. The device further comprises a first doping-type channel (6) formed between the two bottom gates, Here, the JFET region is specifically formed by a second doping type top gate (8), a portion of the substrate located between the top gate (8) and the bottom gate (3), and the bottom gate (3). Specifically, the JFET region 2 is formed by two bottom gates (3) and a channel 2 (6). The vertical capacitively coupled gate-controlled junction field-effect transistor according to feature 2.

4. A first doping-type channel (5) formed in the portion between the top gate (8) and the bottom gate (3) by ion implantation, wherein the top gate (8) is located above the first doping-type channel (5), The device further comprises a first doping-type channel (6) formed between the two bottom gates by ion implantation, Here, the JFET region 2 is specifically formed by two bottom gates (3) and a channel 2 (6). The vertical capacitively coupled gate-controlled junction field-effect transistor according to feature 2.

5. A drain electrode (13) provided on the lower surface of the substrate, Two first doping-type source regions (7) located on each of the two bottom gates, wherein the two source regions (7) are connected to the portion of the substrate located between the top gate (8) and the bottom gate (3), The system further comprises two source electrodes (12) connected to the same source region (7), Here, the first doping type substrate, the portion located below the gate structure and between the bottom gate (3), and the portion located below the gate structure and between the top gate (8) and the bottom gate (3) form an internal conductive path from the drain electrode to the two source electrodes within the substrate. A vertical capacitively coupled gate-controlled junction field-effect transistor as described in claim 3 or 4.

6. The device further comprises two second doping-type ohmic contact regions (4) provided on both sides of the two bottom gates (3), and the second doping-type ohmic contact regions (4) on the same side are connected to the bottom gates (3). The source electrode is located on the boundary between the same-side source region (7) and the second doping-type ohmic contact region (4), and the source electrode connects the same-side source region (7) and the second doping-type ohmic contact region (4). The vertical capacitively coupled gate-controlled junction field-effect transistor according to feature 5.

7. By controlling the doping of the second doping type bottom gate (3) and the second doping type top gate (8), when the voltage of the coupling capacitance upper electrode (10) is zero, the first doping type channel (5) becomes depleted, and the field-effect transistor becomes a normally-off device. Alternatively, by controlling the doping of the second doped bottom gate (3) and the second doped top gate (8), when the coupling capacitance upper electrode (10) voltage is zero, the first doped channel (5) becomes conductive, and the field-effect transistor is a normally-on device. The vertical capacitively coupled gate-controlled junction field-effect transistor according to feature 1.

8. The aforementioned substrate is A first doping type starting substrate (1) having the drain electrode (13) provided on its lower surface, The device comprises a first doping-type epitaxial layer (2), the bottom gate (3), channel 2 (6), channel 1 (5), top gate (8), source region (7), and second doping-type ohmic contact region (4) formed within the epitaxial layer (2). The coupling capacitance upper electrode (10) is located above the top gate (8), The vertical capacitively coupled gate-controlled junction field-effect transistor according to feature 6.

9. The starting substrate is a silicon carbide starting substrate, a silicon starting substrate, a diamond starting substrate, or a potassium oxide starting substrate. The dielectric layer is a dielectric layer made of a high dielectric constant material. The coupling capacitance upper electrode (10) is a polysilicon electrode or a metal electrode. The vertical capacitively coupled gate-controlled junction field-effect transistor according to feature 8.

10. The system further comprises a metal silicide layer (14) formed between the top gate (8) and the dielectric layer (9). The vertical capacitively coupled gate-controlled junction field-effect transistor according to feature 1.

11. The doping concentration of the top gate (8) is 1 × 10 １６ cm －3 That's all. The vertical capacitively coupled gate-controlled junction field-effect transistor according to feature 1.

12. The doping concentration of channel 1 (5) is greater than the doping concentration of the substrate. The doping concentration of channel 2 (6) is greater than the doping concentration of the substrate. The vertical capacitively coupled gate-controlled junction field-effect transistor according to feature 4.

13. The steps include forming a first doping type substrate, The steps include forming two second doping-type bottom gates (3) that are formed within the substrate and spaced apart in the lateral direction, The steps of forming a second doping-type top gate (8) formed in the substrate, wherein the top gate (8) is located above the gap between the two bottom gates and there is a gap between the top gate (8) and the bottom gate (3), A first doping-type channel (5) is formed in the portion between the top gate (8) and the bottom gate (3), wherein the top gate (8) is located above the channel (5), The steps include forming a dielectric layer (9) on the substrate and located above the top gate (8), The steps include forming a coupling capacitance upper electrode (10) on the dielectric layer (9), The steps of forming two first doping-type source regions (7), each located on one of the two bottom gates, wherein the two source regions (7) are connected to a portion of the substrate located between the top gate (8) and the bottom gate (3); The steps include forming two source electrodes (12) connected to the same side source region (7), The top gate (8) is floating, and the coupled capacitance upper electrode (10), the dielectric layer (9), and the top gate (8) together constitute the gate structure. A method for manufacturing a vertical capacitively coupled gate-controlled junction field-effect transistor.

14. The process further includes the step of forming a first doping-type channel (6) between the two bottom gates by ion implantation. A method for manufacturing a vertical capacitively coupled gate-controlled junction field-effect transistor as described in 13.

15. The dielectric layer is a dielectric layer made of a high dielectric constant material. The coupling capacitance upper electrode (10) is a polysilicon electrode or a metal electrode. A method for manufacturing a vertical capacitively coupled gate-controlled junction field-effect transistor as described in claim 13 or 14.

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