Different pixel refresh rates

Abstract

Generally, the subject matter described in this disclosure can be embodied in a method, a system, and a program product for operating a display device. The pixels of the display device are refreshed by turning off the light emission of the LED, programming a driving transistor that drives the LED, and turning on the light emission of the LED with a first time delay after programming the driving transistor while the display device is operating at a first refresh rate. The pixels of the display device are refreshed by turning off the light emission of the LED, programming a driving transistor that drives the LED, and turning on the light emission of the LED with a second time delay after programming the driving transistor while the display device is operating at a second refresh rate.

Description

Technical Field

[0005] ,

[0001] This document generally relates to display devices.

Background Art

[0002] An electronic device can include a display device on which visual images are displayed. The electronic device can change a refresh rate presented by a display panel when new image data is provided to the display panel. A high refresh rate can provide a smoother presentation of content to a user, but requires additional power consumption for a lower refresh rate.

Summary of the Invention

[0003] This document describes techniques, methods, systems, and other mechanisms for providing a display device in which pixel refresh characteristics are different at different refresh rates.

[0004] As an additional explanation of the embodiments described below, the present disclosure describes the following embodiments.

[0005] Embodiment 1 is a method for operating a display device, the method comprising refreshing a pixel of the display device by including: turning off the illumination of an LED while the display device is operating at a first refresh rate in which the illumination of the pixel's LED remains on for a first period of time; programming a driver transistor that drives the LED while the LED remains off and the display device is operating at the first refresh rate; and turning on the illumination of the LED with a first time delay after programming the driver transistor while the display device is operating at the first refresh rate. The method further comprises refreshing a pixel of the display device by including: turning off the illumination of an LED while the display device is operating at a second refresh rate in which the illumination of an LED remains on for a second period of time different from the first period; programming a driver transistor that drives the LED while the LED remains off and the display device is operating at the second refresh rate; and turning on the illumination of the LED with a second time delay different from the first time delay after programming the driver transistor while the display device is operating at the second refresh rate.

[0006] Embodiment 2 is the same method as Embodiment 1, wherein the first refresh rate is a refresh rate of 60 Hz, and the second refresh rate is a refresh rate of 90 Hz or 120 Hz.

[0007] Embodiment 3 is the method according to any one of Embodiments 1 and 2, wherein the second refresh rate is higher than the first refresh rate and the second time delay is greater than the first time delay, such that the second period is shorter than the first period.

[0008] Embodiment 4 is the method according to Embodiment 3, wherein, while the display device is operating at a first refresh rate, programming the drive transistor includes providing a first voltage to the gate of the drive transistor, the first voltage provided to the gate of the drive transistor decreases by a first percentage during a first time delay after programming the LED while the display device is operating at a first refresh rate, and while the display device is operating at a second refresh rate, programming the drive transistor includes providing a second voltage to the gate of the drive transistor, the second voltage provided to the gate of the drive transistor decreases by a second percentage during a second time delay after programming the LED while the display device is operating at a second refresh rate, the second percentage being a larger percentage than the first percentage as a result of the second time delay being larger than the first time delay.

[0009] Embodiment 5 is the method according to Embodiment 4, wherein the first voltage is the same as the second voltage as a result of the same intensity level being programmed to the pixels both during programming of the drive transistor while the display device is operating at a first refresh rate and during programming of the drive transistor while the display device is operating at a second refresh rate, the LED has a first peak intensity when the LED lights up after the first voltage is programmed to the gate of the drive transistor while the display device is operating at a first refresh rate, and the LED has a second peak intensity when the LED lights up after the second voltage is programmed to the gate of the drive transistor while the display device is operating at a second refresh rate, and the first peak intensity of the LED is greater than the second peak intensity of the LED.

[0010] Embodiment 6 is the method according to Embodiment 4, wherein the LED lights up at the same time that the programming of the drive transistor is completed while the display device is operating at a first refresh rate, such that the first time delay is zero.

[0011] Embodiment 7 includes programming a drive transistor while the display device is operating at a first refresh rate, which involves applying a first voltage to the gate of the drive transistor during the programming period. Programming a drive transistor while the display device is operating at a second refresh rate includes applying a second voltage to the gate of the drive transistor for the same programming period. The method is one of the embodiments 1 to 6.

[0012] Embodiment 8 is a method according to any one of Embodiments 1 to 7, wherein refreshing the pixels of a display device while the display device is operating at a first refresh rate includes (i) a preceding LED illumination immediately preceding the pixel refresh at the first refresh rate remaining on for a first period, and (ii) a succeeding LED illumination immediately following the pixel refresh at the first refresh rate remaining on for a first period, and refreshing the pixels of a display device while the display device is operating at a second refresh rate includes (i) a preceding LED illumination immediately preceding the pixel refresh at the second refresh rate remaining on for a second period, and (ii) a succeeding LED illumination immediately following the pixel refresh at the second refresh rate remaining on for a second period.

[0013] Embodiment 9 is a method according to any one of Embodiments 1 to 8, wherein refreshing the pixels of the display device while the display device is operating at a first refresh rate includes turning off the LEDs for a refresh period, and refreshing the pixels of the display device while the display device is operating at a second refresh rate includes turning off the LEDs for the same refresh period.

[0014] Embodiment 10 is the method according to Embodiment 9, wherein the second time delay is greater than the first time delay, the programming of the drive transistor occurs at a first position within the refresh period while the display device is operating at a first refresh rate, and the programming of the drive transistor occurs at a second position within the refresh period while the display device is operating at a second refresh rate, with the first position being located later within the refresh period relative to the second position.

[0015] Embodiment 11 is a method according to any one of Embodiments 1 to 10, wherein refreshing the pixels of the display device while the display device is operating at a first refresh rate includes keeping the light emission of the pixels off for a first refresh period, and refreshing the pixels of the display device while the display device is operating at a second refresh rate includes keeping the light emission of the pixels off for a second refresh period that is longer than the first refresh period.

[0016] Embodiment 12 is the same as Embodiment 11, wherein the second time delay is greater than the first time delay, the programming of the drive transistor starts a standby period after the light emission of the pixels is turned off while the display device is operating at a first refresh rate, and the programming of the drive transistor is performed during the same standby period after the light emission of the pixels is turned off while the display device is operating at a second refresh rate.

[0017] Embodiment 13 is a method according to any one of Embodiments 1 to 10, wherein programming a drive transistor while the display device is operating at a first refresh rate includes programming the drive transistor for a programming period, and programming a drive transistor while the display device is operating at a second refresh rate includes programming the drive transistor for the same programming period.

[0018] Embodiment 14 is a method according to any one of Embodiments 1 to 13, wherein the first time delay remains different from the second time delay regardless of the varying levels of ambient light incident on the computing device which includes a display device.

[0019] Embodiment 15 is a method according to any one of Embodiments 1 to 14, wherein programming the drive transistor while the display device is operating at a first refresh rate is performed after the drive transistor has been initialized to its initialization voltage while the display device is operating at a first refresh rate, and programming the drive transistor while the display device is operating at a second refresh rate is performed after the drive transistor has been initialized to its initialization voltage while the display device is operating at a second refresh rate.

[0020] Embodiment 16 is a method according to any one of Embodiments 1 to 15, wherein the first time delay represents the time delay after the transistor programming is completed while the display device is operating at a second refresh rate, and the second time delay represents the time delay after the transistor programming is completed while the display device is operating at a second refresh rate.

[0021] Embodiment 17 is a computing device that includes a display device and a circuit associated with the display device, and the circuit is configured to cause the display device to execute the method according to any one of Embodiments 1 to 16 by interacting with the display device.

[0022] Embodiment 18 is a method of operating a display panel, including operating a plurality of pixels of the display panel at a first refresh rate, turning on at least one pixel among the plurality of pixels with a first time delay after providing a signal to the driving transistor of the pixel while the display operates at the first refresh rate, and switching the operation of the plurality of pixels to a second refresh rate, where the second refresh rate is higher than the first refresh rate. The method further includes turning on the pixel with a second time delay after providing a signal to the driving transistor of the pixel while the display operates at the second refresh rate, and the second time delay is longer than the first time delay.

[0023] Details of one or more embodiments are described in the accompanying drawings and the following description. Other features, objectives, and advantages will become apparent from the description, the drawings, and the claims.

Brief Description of the Drawings

[0024] [Figure 1] Shows a diagram of an exemplary display system of an electronic device. [Figure 2] A - B show a diagram of a pixel circuit of a display device and a corresponding timing diagram. [Figure 3] A - B show the luminance of pixels over a single frame time for different refresh rates. [Figure 4A] Shows how a pixel transistor can be optically shielded. [Figure 4B] Shows a luminance graph and a corresponding timing diagram. [Figure 5A] Shows the luminance graphs for indoor and outdoor operations. [Figure 5B] Shows a chart indicating the luminance at different refresh rates and environmental settings. [Figure 6] A - C show timing diagrams that result in different time delays at different refresh rates. [Figure 7A] Shows a flowchart of a process for operating a display device having different pixel refresh characteristics at different refresh rates. [Figure 7B] Shows a flowchart of a process for operating a display device having different pixel refresh characteristics at different refresh rates. [Figure 8A] Shows a luminance graph and a corresponding timing diagram. [Figure 8B] Shows a look - up table used in conjunction with the timing diagram of Figure 8A. [Figure 9] Shows a block diagram of a computing device that can be used either as a client or as a server or multiple servers to implement the systems and methods described in this document.

Mode for Carrying Out the Invention

[0025] Like reference symbols in the various drawings refer to like elements. This document generally describes a mechanism for providing a display device in which pixel refresh characteristics are different at different refresh rates. For example, at different refresh rates, the programmed intensity values programmed into the pixels can be enabled to decay for different periods.

[0026] Display devices may be configured to operate at different refresh rates (e.g., 60Hz and 120Hz). Video content may appear more fluid at higher refresh rates, while energy consumption may be lower at lower refresh rates. Display devices typically operate at higher refresh rates when displaying video content (e.g., animation or video) and at lower refresh rates when displaying static content (e.g., static user interfaces or photographs).

[0027] The brightness of pixels on a display device can decay during the illumination period of a single frame (e.g., 1 / 60 second, 1 / 120 second). Lower refresh rates correlate to longer illumination times, and therefore, longer periods at decayed intensity. Consequently, the average brightness for a given intensity setting may be higher at higher refresh rates than at lower refresh rates. Users may perceive this difference in intensity as a step change in the display device's intensity (e.g., flicker) that occurs when the display device changes from one refresh rate to another.

[0028] To compensate for this difference, a display device may be adjusted or calibrated to output different initial brightness values ​​for different refresh rates for a given programmed pixel value. As a simple example, when a display device is operating at its highest refresh rate (e.g., shortest frame time), the programmed pixel value of each pixel may be reduced by 5% compared to when operating at its lowest refresh rate.

[0029] The problem is that the presence of strong ambient light can increase the amount of brightness attenuation that occurs in each frame. Photons from strong ambient light can interact with semiconductor components within the display device, potentially causing current leakage and increased brightness attenuation. In this way, brightness adjustment or calibration may not accurately compensate for the brightness difference between refresh rates when the display device is in the presence of strong ambient light. This means that individuals using a computing device outdoors on a sunny day are likely to occasionally see "flicker" when the refresh rate of the computing device changes.

[0030] Mechanisms to mitigate the influence of ambient light on the intensity of devices with a variable refresh rate may include varying the amount of time delay for different refresh rates between (1) pixels programmed with new image data and (2) these pixels that are tuned to be turned on to emit the image data. During this delay between programmed pixels (while the pixels are off) and on pixels, the intensity level programmed for each pixel is attenuated.

[0031] Allowing the programmed brightness values ​​of pixels to decay for a certain period before these pixels are turned on can result in a decrease in the initial brightness output by the pixels of a display device. Furthermore, because the decay is logarithmic, the most significant change in brightness between pixel emission in low ambient light environments and pixel emission in high ambient light environments occurs in the initial stages of decay. Therefore, by implementing different time delays between programming and emission at different refresh rates, the appearance of variable refresh rate "flicker" caused by strong ambient light incident on the display device can be mitigated.

[0032] The following diagrams provide additional details regarding the mechanisms for reducing variable refresh rate flicker. The descriptions of Figures 1 and 2A-B provide an overview of the operation of the display device and its components, while Figures 3A-8B illustrate how such components may operate to reduce variable refresh rate flicker in the presence of strong ambient light.

[0033] Figure 1 shows an example of a display system 100 of a computing device 190. The display system 100 is an OLED display system including an array of light-emitting pixels 112. Each light-emitting pixel contains an OLED. The OLED display is driven by drivers including a SCAN / EM driver 108 and a data driver 110. The SCAN / EM driver 108 may be an integrated, i.e., stacked row-line driver. Generally, the SCAN / EM driver 108 selects a row of pixels on the display, and the data driver 110 provides data signals (e.g., voltage data (VDATA)) to the pixels of the selected row to light up the OLEDs of the selected row according to the image data specified by the voltage data. Signal lines such as scan lines, EM (light-emitting) lines, and data lines may be used to control pixels and display an image on the display. Figure 1 shows a display system 100 with the SCAN / EM driver 108 on one side of the display, but the SCAN / EM driver 108 may be located on both the left and right sides of the display to improve driving performance (e.g., speed).

[0034] The pixel array 112 includes multiple light-emitting pixels, such as pixels P11 to P43. A pixel is a small element of the display that can change color based on image data supplied to it. Each pixel includes an OLED and circuitry that addresses and drives the OLED (e.g., the components shown in Figure 2A). Each pixel in the pixel array 112 can be individually addressed to produce different color intensities. Each pixel maintains a nearly stable brightness throughout the entire frame time, displaying light corresponding to the supplied image data. Frame time, or frame period, is the amount of time between the start of one frame and the start of the next. Frame time can be the reciprocal of the frame rate of the display system. For example, a frame rate of 60 frames per second (fps) corresponds to a frame time of 1 / 60th of a second, or 0.0167 seconds.

[0035] The pixel array 112 extends in a plane and includes rows and columns. Each row extends horizontally across the pixel array 112. For example, the first row 120 of the pixel array 112 contains pixels P11, P12, and P13. Each column extends vertically downward across the pixel array 112. For example, the first column 130 of the pixel array 112 contains pixels P11, P21, P31, and P41. Figure 1 shows only a few pixels for simplicity. In reality, the pixel array 112 may contain thousands or even millions of pixels. Increasing the number of pixels within a display of the same size results in higher image resolution.

[0036] The display system 100 includes a display driver integrated circuit (DDIC) 106 that receives display input data 102. The DDIC 106 may be, for example, a semiconductor integrated circuit or a state machine. The DDIC 106 generates signals with appropriate voltage, current, timing, and demultiplexing to display an image on the display 104 according to the display input data 102. In some examples, the DDIC may be a microcontroller and may incorporate RAM, flash memory, EEPROM, ROM, etc.

[0037] The DDIC 106 includes a timing controller 134, a clock signal generator 136, and a data signal generator 138. The DDIC 106 generates a clock signal 142. The clock signal 142 may, for example, control the display frame start time and display frame stop time for each frame presented by the display panel 104, where a frame represents a single image within a series of images presented by the display panel 104. In examples where each frame presented by the display panel includes multiple light emission cycles, the clock signal 142, or another signal not shown in Figure 1, can control the display light emission start time and display light emission stop time for each light emission cycle of the display panel 104. In some examples, a SCAN / EM driver 108, a data driver 110, or both may be integrated with the DDIC 106.

[0038] The SCAN / EM driver supplies SCAN and EM signals to rows of the pixel array 112. For example, the SCAN / EM driver 108 supplies scan signals to rows of pixels via scan lines S1 to S4 and EM signals via EM lines E1 to E4.

[0039] The data driver 110 supplies signals to the columns of the pixel array 112. For example, based on the image data signal 144 from the DDIC 106, the data driver 110 supplies data to the columns of pixels via data lines D1-D3, and the data is provided to one row at a time based on which row is currently selected by the scan / EM signal. For example, the data driver 110 specifies a data voltage for each pixel of the currently selected row, which is used according to the image data signal 144. The data driver 110 applies the selected data voltage via data lines D1-D3.

[0040] The clock signal 142 can be used to drive the SCAN / EM driver 108 and the data driver 110. Thus, the DDIC 106 controls the timing of the scan signal, EM signal, and data signal.

[0041] The display system 100 includes a power supply 150. The power supply 150 provides a first supply voltage ELVDD and a second supply voltage ELVSS, both of which are applied to each pixel of the pixel array 112. In some examples, the power supply 150 can be integrated with a DDIC 106.

[0042] Each pixel in the pixel array 112 can be addressed by a horizontal scan line, a horizontal EM line, and a vertical data line. For example, pixel P11 can be addressed by scan line S1, EM line E1, and data line D1. In another example, pixel P32 can be addressed by scan line S3, EM line E3, and data line D2.

[0043] The scan / em driver 108 and data driver 110 provide signals to the pixels that enable the pixels to generate an image on the display. The scan / em driver 108 and data driver 110 provide signals to the pixels via scan lines, light-emitting lines, and data lines. To provide signals to the pixels, the scan / em driver 108 selects scan lines and controls the light-emitting operation of the pixels. The data driver 110 provides data signals to pixels addressable by the selected scan lines to illuminate the selected OLED at an intensity specified by the image data.

[0044] Scanlines are addressed sequentially for each frame. The scan direction determines the order in which the scanlines are addressed. In the display system 100, the scan direction is from the top of the pixel array 112 to the bottom of the pixel array 112. For example, scanline S1 is addressed first, followed by scanline S2, then S3, and so on.

[0045] Figure 1 shows that each row is addressed by a single scan line and a single light-emitting line, although each row may be addressed by multiple scan lines (e.g., nSCAN and pSCAN). Figure 1 shows exemplary components of an OLED display, but the described technique may be applied to other flat panel display technologies that include arrays of pixels. For example, this technique can be applied to light-emitting diodes (LEDs), liquid crystal displays (LCDs), and plasma display panels (PDPs).

[0046] Figure 2A shows a diagram of a pixel circuit of a display device, which includes an LED and a corresponding driver circuit for the pixel circuit. For example, Figure 2A may show a more detailed diagram of a single pixel from the array of pixels shown in Figure 1. The components shown in Figure 2A may be referred to as “pixel circuits” in this disclosure, but the disclosure may also refer to such components simply as “pixels.” Furthermore, the pixels shown in Figure 2A may represent subpixels.

[0047] The pixel circuit may be an active-matrix OLED (AMOLED) pixel circuit. The pixel circuit receives the light emission signal EM, the SCAN signal, and the data voltage VDATA signal. The pixel circuit 200 receives the first supply voltage ELVDD, the second supply voltage ELVSS, and the initial reference voltage VINIT.

[0048] The pixel circuit includes an organic light-emitting diode (OLED). The OLED contains a layer of organic compound that emits light in response to an electric current. The organic layer is placed between two electrodes, namely the anode and the cathode. The OLED is driven by a drive transistor T1, which receives a supply voltage ELVDD and acts as a current source to drive the OLED and cause it to emit light.

[0049] The pixel also includes a storage capacitor C-ST and transistors T2-T7. The operation of the pixel is defined by the state of the control signals SCAN, EM, and VDATA. The OLED current, IOLED, is set by the voltage present at the gate terminal of the driving transistor T1, referred to as the "G" node. For example, the driving transistor T1 has a threshold voltage VTH between its gate terminal and source terminal, and a voltage between the gate and source terminals that exceeds the threshold voltage VTH causes the driving transistor T1 to form a conductive path from the source terminal to the drain terminal.

[0050] Figure 2B shows the timing diagram of the control signals for the pixels shown in Figure 2A. These control signals repeatedly transition during the operation of the display device 100 between the initialization stage, the programming stage, and the light emission stage.

[0051] At the end of the light emission stage, the EM signal transitions to the off state (for example, by changing from a low state to a high state). This transition turns off transistors T5 and T6, thereby cutting off the current supplied from ELVDD to the OLED, and thus stopping light emission by the OLED.

[0052] During the initialization stage, the SCAN[n-1] signal is turned on (for example, by changing from a high state to a low state), which turns on transistor T4 for a certain period of time and initializes the G node to the initialization voltage VINIT. The SCAN[n-1] signal may also be the SCAN[n] signal provided to the preceding row by the state machine of the SCAN / EM driver 108.

[0053] During the programming stage, the SCAN[n] signal is turned on (for example, by going low), which causes transistors T2, T3, and T7 to be turned on for a certain period of time. As a result, the voltage value on the voltage data VDATA line passes through transistors T2, T1, and T3 to the G node, setting the G node to a value based on the VDATA line (for example, the voltage on VDATA minus the effect of the transistor threshold voltage).

[0054] During the light emission stage, the EM signal is turned on (for example, by becoming low), thereby turning on transistors T5 and T6. Current flows from ELVDD through transistors T5, T1, and T6 to the anode of the OLED, and the current level is determined by the voltage present at the G node. Therefore, after the pixel transitions to the light emission stage of the frame, the level of current IOLED flowing through the OLED is based on the voltage set at the G node of the driving transistor (for example, the voltage level at the G node is programmed by the voltage data VDATA line). The intensity or brightness of the light emitted by the OLED is directly correlated with the amount of current IOLED applied to the OLED, with higher currents corresponding to greater light intensity compared to lower currents. The energy storage capacitor C-ST maintains the voltage at the G node so that the OLED continues to emit light at approximately the same level for the duration of the light emission stage.

[0055] The voltage at the G node may decrease slightly during the light emission stage. Therefore, the current applied to the OLED and the intensity of the light emitted by the OLED may decrease slightly during the light emission stage.

[0056] Figures 3A and 3B show the brightness of pixels over a single frame for different refresh rates. As mentioned earlier, the display of a computing device may support multiple refresh rates. For example, high refresh rates (e.g., 120Hz, 90Hz) may be used for moving images to provide high display performance, while low refresh rates (e.g., 60Hz or less) may be used for still images or slow moving images. In this way, computing devices can optimize the refresh rate for the presented content to provide both a high-quality user experience and good battery life.

[0057] The brightness provided by pixels in a display device may attenuate during illumination in each frame time. This non-ideal (non-flat) brightness response of the display over frame time can result in a brightness delta between refresh rates. This delta is shown in Figure 3A, which displays a brightness graph 300 showing the brightness of pixels programmed to a specific intensity value (e.g., full intensity) over the illumination period of a single frame time.

[0058] In Graph 300, a first pixel brightness 310 occurring during a 120Hz refresh rate results in a first average brightness intensity 312 over a 120Hz frame time, while a second pixel brightness 320 occurring during a 60Hz refresh rate results in a second average brightness intensity 322 over a 60Hz frame time. The second average brightness intensity 322 is lower than the first average brightness intensity 312. This difference in average brightness intensity manifests as refresh rate transition flicker (also known as variable refresh rate flicker or VRR flicker) when the system transitions from one refresh rate to another.

[0059] Display devices are often adjusted or calibrated so that pixels output different initial brightness levels for the same given image data at different refresh rates to reduce VRR flicker. Figure 3B shows a brightness graph 350 in which a first pixel brightness 360 occurring at a 120 Hz refresh rate starts emitting light in a frame at a lower intensity value than a second pixel brightness 370 occurring at a 60 Hz refresh rate, even though the brightness of both pixels presents the same image data at different time periods.

[0060] This results in a first average luminance intensity of 362 at a 120Hz refresh rate, which corresponds to a second average luminance intensity of 372 at a 60Hz refresh rate (e.g., they are the same). For example, if the video output by the display device is such that a given pixel continuously outputs at exactly the same intensity level (e.g., 52% intensity), then refresh rate calibration may reduce the value programmed for a given pixel in the display device circuit when the display device is operating at 120Hz to reduce VRR flicker. In other words, refresh rate-specific amplitude control may be employed to reduce VRR flicker.

[0061] The pixel transistors that control the individual pixel emission current / brightness (e.g., T1 and / or other transistors in Figure 2A) may be photosensitive. For example, when strong light is incident, the leakage current in the off state may increase. As shown in Figure 4A, the pixel transistors may be optically shielded from strong light shining from the front of the display (e.g., photon 400 is blocked by component 402). However, optical shielding does not provide adequate protection at all angles (e.g., as shown by photon 406, which bypasses all optical shielding), and there may also be reflected light from the back (e.g., as shown by photon 404). Thus, the pixel emission current of the IOLED may decrease when the display is exposed to strong ambient light.

[0062] Figure 4B shows the luminance graph 420 and the corresponding timing diagram 450. The luminance graph 420 shows how much greater the initial intensity of the first luminance profile 422 at a refresh rate of 60 Hz and under indoor lighting conditions is compared to the initial intensity of the second luminance profile 424 at a refresh rate of 90 Hz and under indoor lighting conditions. The lower initial intensity of the second luminance profile 424 is due to adjustments or calibrations applied by the computing device to produce the same average intensity for both luminance profiles 422 and 426.

[0063] Luminance graph 420 also shows how much greater the initial intensity of the third luminance profile 426 at a 60 Hz refresh rate and under outdoor light conditions is compared to the initial intensity of the fourth luminance profile 428 at a 90 Hz refresh rate and under outdoor light conditions. Luminance profiles under outdoor light conditions decay at a faster rate than those under indoor light conditions. As mentioned above, this faster decay results in different average intensity levels when the display device is in outdoor light conditions. For example, adjustments or calibrations may be developed for indoor light conditions and may not completely eliminate VRR flicker under outdoor light conditions (or other types of light conditions different from those for which the adjustments or calibrations were developed).

[0064] The timing diagram 450 in Figure 4B is similar to the timing diagram in Figure 2B, the main difference being that the timing diagram 450 shows the Vsync signal, which may transition to a different state once per frame to synchronize various signals. For example, the EM signal may trigger off the Vsync signal occurring during a specified period before or after the Vsync signal transition. Similarly, the SCAN signal may trigger off the Vsync signal.

[0065] Timing diagram 450 shows Δt_60[n], which represents the time delay between pixel programming and the start of the pixel's illumination period when the display device is operating at a 60Hz refresh rate. Specifically, the Δt_60[n] period may begin when pixel programming is complete or finished (specified by the end of the SCAN[n] pulse), and the Δt_60[n] period may end when the illumination period begins (specified by the start of the EM[n] pulse, which is performed in the downward transition of Figure 4B). Timing diagram 450 also shows Δt_90[n], which represents the time delay between pixel programming and the start of the pixel's illumination period when the display device is operating at a 90Hz refresh rate. In this example, for example, Δt_60[n] and Δt_90[n] are the same because the SCAN[n] signal pulses at the same position within the "off" portion of the EM signal at both the 60Hz and 90Hz refresh rates. In other words, the time gap between the Vsync signal and the SCAN signal is the same at both high and low refresh rates.

[0066] The attenuation of brightness during pixel emission is at least partially a result of current leakage from transistor T3 (see Figure 2B) after VDATA has been programmed to the pixel (e.g., after T3 is turned off). Thus, regardless of whether the pixel is emitting light or not, the voltage across the G electrode begins to attenuate when the VDATA programming period ends (e.g., when the VSYNC pulse ends).

[0067] Therefore, the initial brightness value of a pixel can be reduced by introducing a time delay between (1) the end of the VDATA programmed into the pixel and (2) the pixel's light emission being turned on. When this time delay is greater at a high refresh rate (e.g., 90 Hz) than at a low refresh rate (e.g., 60 Hz), the brightness delta between high and low refresh rates under strong ambient light is reduced. In other words, a display device configured to introduce different such time delays at different refresh rates and tuned or calibrated to reduce VRR flicker under indoor lighting conditions may provide moderate or indistinguishable VRR flicker under outdoor lighting conditions.

[0068] The use of different time delays, Δt_60[n] and Δt_90[n], is shown in Figure 5A. Because the time delay is larger at 90Hz, the initial luminance value at 90Hz differs between indoor and outdoor lighting conditions. As a result of setting this larger time delay, the average luminance at a 90Hz refresh rate under outdoor conditions more closely matches the average luminance at a 60Hz refresh rate under outdoor conditions than if the time delays were the same at different refresh rates.

[0069] The 90Hz time delay Δt_90[n] can be implemented regardless of the computing device's detection of ambient light levels. In other words, the 90Hz time delay Δt_90[n] can be implemented for all 90Hz refresh rates. If the computing device detects ambient light levels, this information may not be used when selecting when to implement the 90Hz time delay Δt_90[n]. In some examples, the 60Hz time delay Δt_60[n] is negligible or equal to zero, so the emission period begins simultaneously with (or even before) the end of the SCAN programming period.

[0070] Figure 5B includes a first set of graphs 560 showing how display devices with the same refresh characteristics at different refresh rates have a luminance difference of 29 nits between different refresh rates during outdoor operation. Figure 5B also includes a second set of graphs 580 showing how the same display device, with modified operation as described above to have different refresh characteristics at different refresh rates (e.g., different Δt_60[n] and Δt_90[n]), has a luminance difference of 11 nits between different refresh rates during outdoor operation. The modified operation reduces the luminance difference of nits, resulting in less perceived flicker under strong ambient light conditions.

[0071] Figure 6A shows a timing diagram for a pixel or row of a display device when the display device is operating at a refresh rate of 60 Hz. In this diagram, Δt_60[n] represents the time delay between the end of programming data to the pixel or row and the start of the illumination period.

[0072] Figure 6C shows the timing diagram for the same pixel or row of a display device when the display device is operating at a refresh rate of 90 Hz. In this diagram, Δt_90[n] represents the time delay between the end of data programming and the start of the illumination period. The brightness illustrated in Figure 5A can be achieved by operating with the timing schemes shown in Figures 6A and 6C for 60 Hz and 90 Hz, respectively. Different refresh rates may be used.

[0073] As shown in Figures 6A and 6C, the timing delay at 90 Hz is greater than that at 60 Hz, and as a result, the voltage programmed into the G node decays more at 90 Hz than at 60 Hz before the emission begins. The use of these two different timing schemes is achieved within the same refresh period (e.g., the same period during which the emission of a pixel or row of pixels is off), but the SCAN programming pulse at 90 Hz occurs earlier in the refresh period than that at 60 Hz.

[0074] Alternatively, the display device may use both the timing schemes in Figures 6B and 6C, with refresh rates of 60Hz and 90Hz, respectively. In this combination of timing schemes, the time delay Δt_90[n] at 90Hz is still greater than the time delay Δt_60[n] at 60Hz, but the refresh period lengths differ. In this example, the SCAN programming pulses during both the 60Hz and 90Hz refresh periods start for the same length of time after the respective refresh periods begin, but the 60Hz refresh period is shorter than the 90Hz refresh period.

[0075] Figures 7A and 7B show flowcharts of a process for operating display devices having different pixel refresh characteristics at different refresh rates. The process may be carried out by a display device, or a computing device including a display device, to achieve, for example, the luminance output shown by set 580 in the tables of Figures 5A and 5B.

[0076] In box 700, the display device operates at a first refresh rate. For example, the display device described with respect to Figures 1 and 2A-B can operate at a refresh rate of 60 Hz and repeatedly present frames, each frame including an initialization period, a programming period, and an illumination period (as shown in Figures 2B, 6A, and 6B).

[0077] In box 710, the LED of the pixel is turned on during the first period. For example, pixel P11 (Figure 1) may also be turned on during the illumination period labeled in Figure 2B, which is shown unlabeled in Figures 6A and 6B.

[0078] In box 712, the light emission of a pixel is on for the same duration in frames preceding and following a pixel refresh. For example, a pixel refresh (including the initialization and programming periods) shown in Figure 2B may be preceded by a light emission period of the same length, followed by another light emission period of the same length. As a result of the display device operating continuously at the same refresh rate for an extended period, frames may repeat sequentially hundreds of times with the same light emission period. Similar operation is shown in the timing diagrams of Figures 6A and 6B.

[0079] In box 720, the LED light emission of the pixel is turned off. For example, the EM signal (see Figure 2B) is turned "off" by transitioning from low to high. This signal transition causes the LED to stop emitting light, as described in Figures 2A and 2B. Similar operation is shown in the timing diagrams of Figures 6A and 6B.

[0080] In box 722, the pixels are initialized. For example, the SCAN[n-1] signal (see Figure 2B) can initialize various components of the pixel, as described in Figures 2A and 2B. Similar operation is shown in the timing diagrams of Figures 6A and 6B.

[0081] In box 724, a value is programmed into the driver transistor that drives the LED. For example, the DATA signal (Figure 2B) can be sent to the G node (Figure 2A) of the T1 transistor via the VDATA line, as described in Figures 2A and 2B. Similar operation is shown in the timing diagrams of Figures 6A and 6B.

[0082] In box 730, the LED is turned on with a first time delay after the programming of the driver transistor is complete, as described with respect to Figures 2A and 2B. Different examples of such time delays are shown in Δt_60[n] in Figures 6A and 6B.

[0083] In box 732, the voltage programmed into the drive transistor decreases at a first rate over a first time delay. For example, the luminosity graph in Figure 5A shows indoor and outdoor luminosity lines that decrease slightly over a period of Δt_60[n] (note that although the indoor and outdoor luminosity lines in Figure 5A are present during this period, the pixels are not emitting light during Δt_60[n]).

[0084] In box 734, the LED is turned on at the same time as programming is completed, such that the first delay is zero. For example, the period Δt_60[n] in Figures 6A-B can be zero, and as a result, the SCAN descending transition occurs simultaneously with the EM descending transition.

[0085] In box 740, a decision is made regarding whether to switch to a different refresh rate. For example, if high-speed video content is presented, the computing device or the display device located within it may decide to switch to a higher refresh rate. If the display device does not switch refresh rates, the operation of box 700 is performed again. If the display device switches to a different refresh rate, the operation of box 760 is performed.

[0086] In box 750, the display device operates at a second refresh rate different from the first refresh rate. For example, the display device described with respect to Figures 1 and 2A-B operates at a refresh rate of 90Hz or 120Hz and can repeatedly present frames in which each frame includes an initialization period, a programming period, and an illumination period (as shown in Figures 2B and 6C).

[0087] In box 760, the LED of the pixel is turned on during the first period. For example, pixel P11 (Figure 1) may also be turned on during the illumination period labeled in Figure 2B, which is shown unlabeled in Figure 6C.

[0088] In box 762, the second refresh rate is higher than the first refresh rate. For example, the second refresh rate of 90Hz or 120Hz may be higher than the first refresh rate of 60Hz.

[0089] In box 770, the LED light emission of the pixel is turned off. For example, the EM signal (see Figure 2B) is turned "off" by transitioning from low to high. This signal transition causes the LED to stop emitting light, as described in Figures 2A and 2B. A similar operation is shown in the timing diagram in Figure 6C.

[0090] In box 722, the pixels are initialized. For example, the SCAN[n-1] signal (see Figure 2B) can initialize various components of the pixel, as described in Figures 2A and 2B. Similar operation is shown in the timing diagram in Figure 6C.

[0091] In box 724, a value is programmed into the driver transistor that drives the LED. For example, the DATA signal (Figure 2B) can be sent to the G node (Figure 2A) of the T1 transistor via the VDATA line, as described in Figures 2A and 2B. Similar operation is shown in the timing diagram of Figure 6C.

[0092] In box 780, as explained with respect to Figures 2A and 2B, the LED is turned on with a second time delay after the programming of the driver transistor is complete. An example of such a time delay is shown by Δt_90[n] in Figure 6C.

[0093] In box 782, the voltage programmed into the drive transistor decreases at a second rate over a second time delay, and the second rate is greater than the first rate. For example, the luminosity graph in Figure 5A shows indoor and outdoor luminosity lines decreasing over a period of Δt_90[n], decreasing at a larger rate than the decrease over a period of Δt_60[n] (note that although the indoor and outdoor luminosity lines in Figure 5A are present within this period, the pixels are not emitting light during Δt_90[n]).

[0094] In box 784, the peak intensity of the LED emission is lower at the second refresh rate than at the first refresh rate for the same original display pixel value (e.g., 100% programmed intensity in the image data before any display or refresh rate-specific adjustments or calibrations). For example, Figure 5A shows how much higher the initial intensity of the LED at 90 Hz is compared to the initial intensity of the LED at 60 Hz.

[0095] In box 790, a decision is made regarding whether to switch to a different refresh rate. For example, if high-speed video content ends and a still image is presented, the computing device or a display device located within it may decide to switch to a lower refresh rate. If the display device does not switch refresh rates, the operation of box 750 is performed again. If the display device switches to a different refresh rate, the operation of box 700 is performed.

[0096] In some embodiments, ambient light detected by a light sensor may be used to trigger changes in the refresh rate characteristics. For example, when the ambient light level increases, a computing device (e.g., a display device within a computing device) may reduce the "on" time of light emission to mitigate VRR flicker. Figure 8A shows the luminance graph 810 and the corresponding timing figure 820. As the detected ambient light level increases, the computing device may reduce the light emission time at 90 Hz (tEM90). Since the reduced light emission on time may be relatively small (about 0.2 ms out of 11.1 ms at 90 Hz), the impact on the OLED's lifetime may be negligible.

[0097] The amount of reduced on-time of emission (tEM90) may follow the lookup table in Figure 8B. The on-time of 60Hz emission at low refresh rates may not change even if the detected ambient light level changes. For efficiency and accuracy of brightness control, when reducing the on-time of high refresh rate emission, the rising edge of the brightness waveform may be modified rather than the falling edge of the waveform. However, the falling edge of the waveform may still be shifted in some embodiments.

[0098] Figure 9 shows block diagrams of computing devices 900, 950, which may be used as either clients or servers or multiple servers to implement the systems and methods described herein. Computing device 900 is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. Computing device 950 is intended to represent various forms of mobile devices, such as personal digital assistants, mobile phones, smartphones, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are for illustrative purposes only and are not intended to limit the embodiments described and / or claimed herein.

[0099] The computing device 900 includes a processor 902, memory 904, a storage device 906, a high-speed controller 908 connected to memory 904 and a high-speed expansion port 910, and a low-speed controller 912 connected to a low-speed expansion port 914 and the storage device 906. Each of the components 902, 904, 906, 908, 910, and 912 is interconnected using various buses and may be mounted on a common motherboard or in other configurations as needed. The processor 902 can process instructions for execution within the computing device 900, including instructions for displaying graphical information of a GUI on an external input / output device such as a display 916 coupled to the high-speed controller 908, which is stored in memory 904 or the storage device 906. In other embodiments, multiple processors and / or multiple buses may be used as needed, along with multiple memories and multiple types of memory. Also, multiple computing devices 900 may be connected together (e.g., as a server bank, a group of blade servers, or a multiprocessor system) so that each device provides multiple parts of multiple operations as needed.

[0100] Memory 904 stores information within the computing device 900. In one embodiment, memory 904 is a volatile memory unit. In another embodiment, memory 904 is also a non-volatile memory unit. Memory 904 may also be another form of computer-readable medium, such as a magnetic disk or an optical disk.

[0101] The storage device 906 can provide high-capacity storage to the computing device 900. In one embodiment, the storage device 906 may be or include a computer-readable medium such as a floppy disk device, a hard disk device, an optical disk device, or a tape device, flash memory or other similar solid-state memory device, or an array of devices including a storage area network or other configuration. The computer program product may be tangibly embodied in the information carrier. The computer program product may also include instructions that perform one or more of the methods described above at runtime. The information carrier is a computer-readable or machine-readable medium such as memory 904, the storage device 906, or memory on the processor 902.

[0102] The high-speed controller 908 manages bandwidth-intensive operations of the computing device 900, and the low-speed controller 912 manages low-bandwidth-intensive operations. Such function assignments are merely examples. In one embodiment, the high-speed controller 908 is coupled to memory 904, a display 916 (e.g., via a graphics processor or accelerator), and a high-speed expansion port 910 that can accept various expansion cards (not shown). In this embodiment, the low-speed controller 912 is coupled to a storage device 906 and a low-speed expansion port 914. The low-speed expansion port, which may include various communication ports (e.g., USB, Bluetooth®, Ethernet®, Wireless Ethernet), may be coupled to one or more input / output devices such as a keyboard, pointing device, scanner, or to a network device such as a switch or router, for example, via a network adapter.

[0103] The computing device 900 can be implemented in many different forms, as shown in the figure. For example, it may be implemented as a standard server 920, or it may be implemented multiple times in a group of such servers. It may also be implemented as part of a rack server system 924. Additionally, it may be implemented in a personal computer such as a laptop computer 922. Alternatively, components of the computing device 900 may be combined with other components in a mobile device (not shown), such as device 950. Each of such devices may contain one or more computing devices 900, 950, and the entire system may consist of multiple computing devices 900, 950 communicating with each other.

[0104] The computing device 950 includes, among other components, a processor 952, memory 964, input / output devices such as a display 954, a communication interface 966, and a transceiver 968. The device 950 may also be provided with additional storage devices, such as a microdrive or other storage devices. Each of the components 950, 952, 964, 954, 966, and 968 are interconnected using various buses, and some of the components may be mounted on a common motherboard, or in other ways as needed.

[0105] The processor 952 can execute instructions within the computing device 950, including instructions stored in memory 964. The processor may be implemented as a chipset of chips including multiple separate analog and digital processors. Furthermore, the processor may be implemented using one of several architectures. For example, the processor may be a CISC (Combined Instruction Set Computer) processor, a RISC (Reduced Instruction Set Computer) processor, or a MISC (Minimum Instruction Set Computer) processor. The processor may provide coordination with other components of the device 950, such as user interface control, applications run by the device 950, and wireless communication by the device 950.

[0106] The processor 952 may communicate with the user via a control interface 958 and a display interface 956 coupled to the display 954. The display 954 may be, for example, a TFT (thin-film transistor liquid crystal display) display or an OLED (organic light-emitting diode) display, or other suitable display technology. The display interface 956 may include suitable circuitry for driving the display 954 to present graphic information and other information to the user. The control interface 958 may receive commands from the user and translate the commands for submission to the processor 952. Additionally, an external interface 962 communicating with the processor 952 may be provided to enable short-range communication of device 950 with other devices. The external interface 962 may, for example, provide wired communication in some embodiments, or wireless communication in other embodiments, and may use multiple interfaces.

[0107] Memory 964 stores information within the computing device 950. Memory 964 can be implemented as one or more computer-readable media, volatile memory units, or non-volatile memory units. Alternatively, an expansion memory 974 may be provided and connected to device 950 via an expansion interface 972, which may include, for example, a SIMM (Single In-Line Memory Module) card interface. Such an expansion memory 974 may provide additional storage space to device 950, or store applications or other information for device 950. Specifically, the expansion memory 974 may include instructions for performing or supplementing the aforementioned processes, and may also include secure information. Therefore, for example, the expansion memory 974 may be provided as a security module for device 950 and programmed with instructions that enable secure use of device 950. Furthermore, secure applications may be provided via a SIMM card along with additional information, such as placing identification information on the SIMM card in a hack-proof manner.

[0108] The memory may include, for example, flash memory and / or NVRAM memory, as described below. In one embodiment, the computer program product is tangibly embodied in an information carrier. The computer program product includes instructions that perform one or more of the methods described above at runtime. The information carrier is a computer-readable or machine-readable medium, such as memory 964, extended memory 974, or memory on processor 952, which may be received, for example, via transceiver 968 or external interface 962.

[0109] Device 950 may perform wireless communication via a communication interface 966, which may include digital signal processing circuitry if necessary. The communication interface 966 may provide communication in various modes or protocols, including, among many others, GSM® voice calls, SMS, EMS or MMS messaging, CDMA, TDMA, PDC, WCDMA®, CDMA2000 or GPRS. Such communication may be performed, for example, via a radio frequency transceiver 968. Additionally, short-range communication may be performed, such as using Bluetooth, WiFi, or other such transceivers (not shown). Additionally, a GPS (Global Positioning System) receiver module 970 may provide device 950 with additional navigation and location-related radio data, which may be used as needed by applications running on device 950.

[0110] Device 950 may also perform voice communication using an audio codec 960 that can receive voice information from the user and convert it into usable digital information. The audio codec 960 may also generate sounds that are audible to the user, such as through a speaker (e.g., in the handset of device 950). Such sounds may include sounds from voice telephone calls, recorded sounds (e.g., voice messages, music files, etc.), and sounds generated by applications running on device 950.

[0111] The computing device 950 can be implemented in many different forms, as shown in the figure. For example, it may be implemented as a mobile phone 980. Alternatively, it may be implemented as part of a smartphone 982, a personal digital assistant, or another similar mobile device.

[0112] Furthermore, the computing device 900 or 950 may include a Universal Serial Bus (USB) flash drive. The USB flash drive may store the operating system and other applications. The USB flash drive may include input / output components such as a USB connector that can be inserted into a USB port of a wireless transmitter or another computing device.

[0113] Various embodiments of the systems and technologies described herein may be implemented in digital electronic circuits, integrated circuits, specially designed ASICs (application-specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may be specific or general-purpose and may include embodiments in one or more computer programs that are executable and / or interpretable on a programmable system comprising at least one programmable processor, at least one input device, and at least one output device, coupled to receive data and instructions from and transmit data and instructions to a storage system.

[0114] These computer programs (also known as programs, software, software applications, or code) include machine instructions for a programmable processor and may be implemented in high-level procedural and / or object-oriented programming languages ​​and / or assembly / machine languages. As used herein, the terms “machine-readable medium” and “computer-readable medium” refer to any computer program product, apparatus and / or device (e.g., magnetic disks, optical disks, memory, programmable logic devices (PLDs)) used to provide machine instructions and / or data to a programmable processor that includes a machine-readable medium that receives machine instructions as machine-readable signals. The term “machine-readable signal” refers to any signal used to provide machine instructions and / or data to a programmable processor.

[0115] To provide user interaction, the systems and technologies described herein are implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user, and a keyboard and pointing device (e.g., a mouse or trackball) by which the user can provide input to the computer. Other types of devices may also be used to provide user interaction; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback), and input from the user may be received in any form, including acoustic, spoken language, or tactile input.

[0116] The systems and technologies described herein may be implemented in a computing system that includes backend components (e.g., as data servers), middleware components (e.g., application servers), or frontend components (e.g., a client computer having a graphical user interface or web browser through which a user can interact with the implementation of the systems and technologies described herein), or in a combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by digital data communications (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks ("LANs"), wide area networks ("WANs"), peer-to-peer networks (with ad-hoc or static members), grid computing infrastructure, and the Internet.

[0117] A computing system can include clients and servers. Clients and servers are generally far apart from each other and typically interact through a communication network. The client-server relationship arises from computer programs running on each computer that have a client-server relationship with each other.

[0118] Although several embodiments have been described in detail above, other modifications are possible. Furthermore, other mechanisms may be used to carry out the systems and methods described herein. Moreover, the logic flow shown in the figures does not require a specific order or sequence shown to achieve the desired result. Furthermore, other steps may be added to the described flow, or steps may be removed from the described flow, and other components may be added to the described system, or other components may be removed from the described system. Thus, other embodiments are within the scope of the following claims.

Claims

1. A method for operating a display device, While the display device is operating at a first refresh rate in which the light emission of the pixel LEDs remains on for a first period, To turn off the light emitted by the aforementioned LED, Programming the driver transistor that drives the LED while the LED remains off and the display device is operating at the first refresh rate, and While the display device is operating at the first refresh rate, the LED is turned on with a first time delay after the programming of the drive transistor. By including the above, the pixels of the display device are refreshed, While the display device is operating at a second refresh rate in which the LED remains lit for a second period different from the first period, To turn off the light emitted by the aforementioned LED, Programming the driver transistor that drives the LED while the LED remains off and the display device is operating at the second refresh rate, and While the display device is operating at the second refresh rate, after the programming of the drive transistor, the illumination of the LED is turned on with a second time delay different from the first time delay. By including the above, the pixels of the display device are refreshed, Equipped with, The second refresh rate is higher than the first refresh rate so that the second period is shorter than the first period. A method wherein the second time delay is greater than the first time delay.

2. The first refresh rate is a refresh rate of 60 Hz. The second refresh rate is a refresh rate of 90 Hz or a refresh rate of 120 Hz. The method according to claim 1.

3. Programming the drive transistor while the display device is operating at the first refresh rate includes providing a first voltage to the gate of the drive transistor. The first voltage supplied to the gate of the drive transistor decreases by a first rate during the first time delay after the programming of the LED while the display device is operating at a first refresh rate. Programming the drive transistor while the display device is operating at the second refresh rate includes providing a second voltage to the gate of the drive transistor. The second voltage supplied to the gate of the drive transistor decreases by a second rate during the second time delay after programming the LED while the display device is operating at the second refresh rate, and the second rate is greater than the first rate as a result of the second time delay being greater than the first time delay. The method according to claim 1.

4. During the programming of the drive transistor while the display device is operating at the first refresh rate, and during the programming of the drive transistor while the display device is operating at the second refresh rate, the same intensity level is programmed to the pixels, resulting in the first voltage being the same as the second voltage. The LED has a first peak intensity when the LED is turned on after the first voltage has been programmed into the gate of the drive transistor while the display device is operating at the first refresh rate. The LED has a second peak intensity when the LED is turned on after the second voltage has been programmed into the gate of the drive transistor while the display device is operating at the second refresh rate. The method according to claim 3, wherein the first peak intensity of the LED is greater than the second peak intensity of the LED.

5. The method according to claim 3, wherein the LED lights up at the same time that the programming of the drive transistor is completed while the display device is operating at a first refresh rate such that the first time delay is zero.

6. Programming the drive transistor while the display device is operating at the first refresh rate includes applying a first voltage to the gate of the drive transistor during the programming period. Programming the drive transistor while the display device is operating at the second refresh rate includes applying a second voltage to the gate of the drive transistor for the same programming period. The method according to any one of claims 1 to 5.

7. Refreshing the pixels of the display device while the display device is operating at the first refresh rate is: (i) The pre-illumination of the LED that precedes the refresh of the pixel at the first refresh rate remains on for the first period, (ii) The subsequent illumination of the LED immediately following the refresh of the pixel at the first refresh rate remains on for the first period, Refreshing the pixels of the display device while the display device is operating at the second refresh rate is: (i) The pre-illumination of the LED that precedes the refresh of the pixel at the second refresh rate remains on for the second period, (ii) The subsequent illumination of the LED immediately following the refresh of the pixel at the second refresh rate remains on for the second period, The method according to any one of claims 1 to 5.

8. Refreshing the pixels of the display device while the display device is operating at the first refresh rate includes the LED being turned off during the refresh period. Refreshing the pixels of the display device while the display device is operating at the second refresh rate includes turning off the illumination of the LEDs for the same refresh period. The method according to any one of claims 1 to 5.

9. The second time delay is greater than the first time delay. The programming of the drive transistor occurs at a first position within the refresh period while the display device is operating at the first refresh rate. The programming of the drive transistor occurs at a second position within the refresh period while the display device is operating at the second refresh rate. The method according to claim 8, wherein the first position is located later than the second position within the refresh period.

10. Refreshing the pixels of the display device while the display device is operating at the first refresh rate includes keeping the light emission of the pixels off for a first refresh period. Refreshing the pixels of the display device while the display device is operating at the second refresh rate includes keeping the light emission of the pixels off for a second refresh period that is longer than the first refresh period. The method according to any one of claims 1 to 5.

11. The second time delay is greater than the first time delay. The programming of the drive transistor starts a standby period after the light emission of the pixels is turned off while the display device is operating at the first refresh rate. The programming of the drive transistor is performed during the same standby period after the light emission of the pixels is turned off while the display device is operating at the second refresh rate. The method according to claim 10.

12. Programming the drive transistor while the display device is operating at the first refresh rate includes programming the drive transistor for a programming period. Programming the drive transistor while the display device is operating at the second refresh rate includes programming the drive transistor for the same programming period. The method according to any one of claims 1 to 5.

13. The method according to any one of claims 1 to 5, wherein the first time delay remains different from the second time delay regardless of the various levels of ambient light incident on the computing device including the display device.

14. Programming the drive transistor while the display device is operating at the first refresh rate is performed after the drive transistor has been initialized to its initialization voltage while the display device is operating at the first refresh rate. Programming the drive transistor while the display device is operating at the second refresh rate is performed after the drive transistor has been initialized to the initialization voltage while the display device is operating at the second refresh rate. The method according to any one of claims 1 to 5.

15. The first time delay represents the time delay after the programming of the drive transistor is completed while the display device is operating at the first refresh rate. The second time delay represents the time delay after the programming of the drive transistor is completed while the display device is operating at the second refresh rate. The method according to any one of claims 1 to 5.

16. Display devices and, The system comprises a circuit associated with the display device, and the circuit interacts with the display device, thereby enabling the display device to: While the display device is operating at a first refresh rate in which the light emission of the pixel LEDs remains on for a first period, To turn off the light emitted by the aforementioned LED, Programming the driver transistor that drives the LED while the LED remains off and the display device is operating at the first refresh rate, and While the display device is operating at the first refresh rate, the LED is turned on with a first time delay after the programming of the drive transistor. By including the above, the pixels of the display device are refreshed, While the display device is operating at a second refresh rate in which the LED remains lit for a second period different from the first period, To turn off the light emitted by the aforementioned LED, Programming the driver transistor that drives the LED while the LED remains off and the display device is operating at the second refresh rate, and While the display device is operating at the second refresh rate, after the programming of the drive transistor, the illumination of the LED is turned on with a second time delay different from the first time delay. By including the above, the pixels of the display device are refreshed, A computing device configured to perform the following actions.

17. A method for operating a display panel, The operation of multiple pixels of the aforementioned display panel at a first refresh rate, At least one of the plurality of pixels is turned on with a first time delay after providing a data signal to the drive transistor of the pixel to light up the pixel with an intensity specified by the image data, while the display panel is operating at the first refresh rate. The method further includes switching the operation of the plurality of pixels to a second refresh rate, wherein the second refresh rate is higher than the first refresh rate, and the method further includes A method comprising providing the data signal to the drive transistor of the pixel while the display panel is operating at the second refresh rate, and then turning on the pixel with a second time delay, wherein the second time delay is longer than the first time delay.

Images