Generation of quantum random numbers from a single-photon avalanche diode

Abstract

A system and method for random number generation is provided that includes receiving a first series of photons at a first single photon avalanche diode (SPAD), converting the first series of photons into a first series of electrical pulses by the first SPAD, the first series of electrical pulses having a first random time interval between each pulse of the first series of electrical pulses, and outputting a random binary stream based at least in part on the first series of electrical pulses by an output circuit in communication with the first SPAD. To generate random numbers, a system is provided that includes one or more SPADs, associated one or more quenching circuits, and output electronics configured to adjust thresholds, combine signals generated by an array of SPADs, condition signals, and output a stream of generated random numbers.

Description

[Technical Field]

[0001] This invention relates to random number generation and encryption of related communications, as well as the creation and use of unique keys based on the generated random numbers. [Background technology]

[0002] Data stores and computer devices are becoming targets for hackers who are finding new ways to exploit security vulnerabilities. A fundamental defensive tactic to prevent unauthorized access to data is to use encryption to make the data inaccessible if it is compromised or stolen. The basis of all encryption methods relies on the ability to generate random encryption keys. Asymmetric encryption, also known as public-key cryptography, uses a public key and a private key to encrypt and decrypt data. These keys are large numbers that are paired but not identical (asymmetric). Sometimes random numbers are used to generate session keys, and therefore randomness is important for ensuring the security of the system. Unfortunately, many encryption algorithms are not based on truly random numbers, but rather on predictable patterns. When a random number generator produces output that is predictable or fluctuating, it is possible to reverse-analyze it.

[0003] The development of hardware random number generators that utilize natural entropy sources as random seeds has led scientists to question the "randomness" and "quantum nature" of some of the technical claims associated with such devices. While all modern electronic devices are quantum to some extent, the randomness they generate can be considered classical noise.

[0004] The source of quantum random numbers must be a quantitative and measurable source of entropy. Quantum measurement inherently has an unknown, as explained by Heisenberg's famous uncertainty principle, which demonstrates that quantum systems are fundamentally probabilistic. Further literature, as explained in Bell's theorem, proves that quantum randomness is inherent in quantum measurement, and that the outcome of hidden or unknown variables does not determine the conclusion.

[0005] Constructing quantum electronic systems that separate quantum signals from classical noise is difficult. This difficulty is even more pronounced in terms of the variability seen in modern manufacturing techniques, particularly at the microchip level. Controlling, calculating, and measuring these signals is critically different from the illusion of randomness and actual quantum randomness. Improved quantum random number generators remain in demand. [Overview of the project]

[0006] The disclosed technology provides a system and method for generating random numbers usable as cryptographic keys.

[0007] According to certain exemplary implementations of the disclosed technology, a method for generating random numbers is provided. This method includes: receiving a first set of photons in a first single-photon avalanche diode (SPAD); converting the first set of photons into a first set of electrical pulses by the first SPAD, wherein the first set of electrical pulses has a first random time interval between each pulse of the first set of electrical pulses; and outputting a random binary stream at least partially based on the first set of electrical pulses by an output circuit communicating with the first SPAD.

[0008] A particular exemplary implementation of the disclosed technology includes a quantum random number generator. This quantum random number generator comprises one or more single-photon avalanche diodes (SPADs), each configured to receive a corresponding set of photons; one or more quenching circuits communicating with each of the corresponding SPADs, each configured to convert the corresponding set of photons into a corresponding set of electrical pulses, each having a corresponding random time interval between each pulse of the corresponding set of electrical pulses; and one or more output circuits communicating with the one or more quenching circuits, configured to output a random binary stream at least partially based on the corresponding set of electrical pulses.

[0009] Other features of the disclosed design and the benefits provided thereby will be described in more detail below with respect to the specific embodiments shown in the accompanying drawings, where similar elements refer to similar references. [Brief explanation of the drawing]

[0010] The above-described and other embodiments of the present invention will be further described below with reference to the accompanying drawings. Here, similar reference numerals indicate similar structural elements and features in various figures. The drawings are not necessarily to scale and are focused on illustrating the principles of the present invention. The drawings are for illustrative purposes only and do not limit to one or more implementations of the apparatus according to the present invention.

[0011] [Figure 1A] Figure 1A shows an example of a SPAD-based system for random number generation according to one embodiment of the present disclosure.

[0012] [Figure 1B] Figure 1B shows another example of a SPAD-based random number generation system equipped with a quenching circuit, according to one embodiment of the present disclosure.

[0013] [Figure 1C] FIG. 1C is a diagram showing various input pulses for generating an output signal of the exemplary device of FIG. 1A or FIG. 1B based on a series of photons received by a SPAD, according to an embodiment of the present disclosure.

[0014] [Figure 2A] FIG. 2A is a diagram showing an example of a device including an array of SPADs, according to an embodiment of the present disclosure.

[0015] [Figure 2B] FIG. 2B is a diagram showing various input pulses for generating an input signal of the exemplary SPAD array of FIG. 2A based on a series of photons received by the SPAD array, according to an embodiment of the present disclosure.

[0016] [Figure 3A] FIG. 3A is a diagram showing voltage threshold control of an output circuit, according to an embodiment of the present disclosure.

[0017] [Figure 3B] FIG. 3B is a diagram showing another voltage threshold control of an output circuit, according to an embodiment of the present disclosure.

[0018] [Figure 3C] FIG. 3C is a diagram showing yet another voltage threshold control of an output circuit, according to an embodiment of the present disclosure.

[0019] [Figure 4A] FIG. 4A is a diagram showing an example of a random binary stream output based on input voltage threshold control of an output circuit, according to an embodiment of the present disclosure.

[0020] [Figure 4B] FIG. 4B is a diagram showing an example of a random binary stream output based on input voltage threshold control of an output circuit, according to an embodiment of the present disclosure.

[0021] [Figure 5] Figure 5 shows an example of a random flip-flop (RFF) circuit with a voltage threshold control input according to one embodiment of the present disclosure.

[0022] [Figure 6] Figure 6 shows another example of a random binary stream output according to one embodiment of the present disclosure.

[0023] [Figure 7] Figure 7 is a flowchart of a method relating to a specific exemplary implementation of the disclosed technology. [Modes for carrying out the invention]

[0024] The disclosed technologies include methods and systems for generating random numbers by controlling quantum microelectronics to produce true random numbers. The systems and methods described herein may rely on the randomness of photons, the low detector efficiency of diodes, and the adjustment of threshold voltages in output circuits to generate random binary streams. Specific exemplary apparatuses, systems, and methods presented herein can enable entropy harvesting and random number generation.

[0025] Figure 1A shows an exemplary system 100A for random number generation according to one embodiment of the present disclosure. System 100A can detect an incident photon 102 using a single-photon avalanche diode ("SPAD") 110. The term "SPAD" defines a class of photodetectors capable of detecting low-intensity photon radiation (up to a single photon) and signaling the arrival time of the photon with high temporal resolution (tens of picoseconds). A SPAD is a semiconductor device based on a pn junction reverse-biased at a voltage higher than the breakdown voltage. A SPAD operates like an avalanche photodiode (APD) by detecting incident radiation using a photon-triggered avalanche current.

[0026] The fundamental difference between SPADs and APDs is that SPADs are specifically designed to operate at reverse bias voltages far above the breakdown voltage, while APDs typically operate at biases below the breakdown voltage. Under high reverse bias, the electric field at the pn junction of an SPAD is high enough that a single charge carrier injected into the depletion layer (as a result of an incident photon) can induce a self-sustaining avalanche. Once a self-sustaining avalanche occurs, the resulting "avalanche" current rapidly rises to steady-state levels.

[0027] According to certain exemplary implementations of the disclosed technology, the output of SPAD110 may be further adjusted / controlled by an output circuit 120 that communicates with SPAD110. The output circuit 120 may output a random binary stream 130 that can be used as a random seed (or sequence) for encryption. The random binary stream 130 can then be used, for example, by communication technology, encryption software, hardware, or any combination thereof. In certain exemplary implementations, the output circuit 120 may include an adjustable voltage threshold control input (as further described later with reference to Figure 5).

[0028] Figure 1B shows another exemplary SPAD-based random number generation system 100B, comprising a quenching circuit 140, according to one embodiment of the present disclosure. However, in certain implementations, the quenching circuit may be packaged with the SPAD 110 or the output circuit 120. As described above, once the incident photon 102 generates a self-sustaining avalanche within the SPAD 110, the current continues to flow until the avalanche current is extinguished by lowering the bias voltage to the breakdown voltage (or below). The bias voltage is then raised again above the breakdown voltage to enable the detection of another photon. Such trigger detection and bias control can be performed using the quenching circuit 140.

[0029] In certain exemplary implementations, the quenching circuit 140 may detect the rising edge of the avalanche current output from the SPAD 110. In certain exemplary implementations, the quenching circuit 140 may generate a standard output pulse synchronized with the avalanche build-up. In certain implementations, the quenching circuit 140 may extinguish the avalanche by lowering the bias voltage of the SPAD 110 to the breakdown voltage (or below), thereby "resetting" the SPAD 110 to enable detection of the subsequently arriving photon 102. According to certain exemplary implementations of the disclosed technology, it is possible to selectively reset the SPAD 110 after a photon has triggered (or not triggered) the avalanche in order to synchronize (or not synchronize) photon detection with a clock-based and / or adjustable decision threshold.

[0030] The disclosed technology can take advantage of the random nature of each photon received by the SPAD110, such that each photon is received at a random time interval. The collision of a first series of photons 102 with the SPAD110 causes a current avalanche, which may take the form of, for example, the exponential growth of charge carriers. The first series of photons 102 incident on the SPAD110 can then be converted into a first series of electrical pulses. The first series of electrical pulses may have a first random time interval between each pulse in the first series of pulses. The output circuit 120 can receive the first series of electrical pulses and generate a random binary stream 130 based at least partially on the first series of electrical pulses.

[0031] According to certain exemplary implementations of the disclosed technology, the SPAD110 can be coupled in any number of geometric shapes, including 2D and 3D arrays (as described with reference to Figure 2A below). The output circuit 120 may include multiple other inputs and / or outputs. For example, the random binary stream 130 generated by the output circuit 120 may be controlled or manipulated by an input threshold control voltage.

[0032] As will be explained below with reference to Figure 5, the output circuit 120 may include AND gates, OR gates, XOR gates, NOT gates, inverters, Schmitt triggers, NAND gates, NOR gates, XNOR gates, EXOR gates, EXNOR gates, multiplexers, flip-flops, and other logic gates, or combinations thereof.

[0033] As described above, Figure 1B further illustrates apparatus 100B comprising SPAD 110, output circuit 120, and quenching circuit 140 that electrically communicates with SPAD 110 and output circuit 120. In a particular exemplary implementation, SPAD 110 may include a pn junction operating at a bias voltage above the pn junction breakdown voltage when actively detecting a photon. At such a bias voltage, the electric field can become sufficiently high to induce a self-sustaining avalanche in a single charge carrier injected into the depletion layer (e.g., via photon reception). The resulting current can rapidly rise to a steady level and continue to flow until the avalanche can be extinguished by the quenching circuit 140 by reducing the bias voltage below the breakdown voltage. The bias voltage is then restored by the quenching circuit 140, and SPAD 110 and associated circuit configuration can be used for detecting another photon. This process can be repeated.

[0034] In certain exemplary implementations, the quenching operation can be performed using a suitable quenching circuit 140 capable of performing one or more of the following: (a) detecting the rising edge of the avalanche current; (b) generating a standard output pulse that is well synchronized with the rising edge of the avalanche; (c) extinguishing the avalanche by lowering the bias to the breakdown voltage (or below); and / or (d) returning the SPAD bias voltage to the operating level.

[0035] According to a particular exemplary implementation of the disclosed technology, SPAD110 can detect a first set of photons 102 that collide with SPAD110. The quenching circuit 140 then converts the first set of photons 102 into a first set of electrical pulses. The latency between rising edges of the electrical pulses may be random according to an exponential probability distribution function. In a particular exemplary implementation, the quenching circuit 140 can generate a randomized clock pulse input based at least partially on the first set of electrical pulses. In a particular exemplary implementation, the quenching circuit 140 may comprise other inputs, outputs, AND gates, OR gates, XOR gates, NOT gates, NAND gates, NOR gates, XNOR gates, EXOR gates, EXNOR gates, multiplexers, and other logic gates, or combinations thereof. The output circuit 120 receives the randomized clock pulse input and can generate a random binary stream 130 based at least partially on the first set of electrical pulses.

[0036] In some embodiments, it is possible to ensure unbiased operation by varying the dead time between quenchings of the SPAD 110 or the quenching circuit 140. In other embodiments, another control point to ensure unbiased operation may include operating the SPAD 110, the quenching circuit 140, the output circuit 120, the state indicator, the flip-flops, and the logic gates of the quenching circuit 140 and the output circuit 120 asynchronously by using different clocks and clock combinations.

[0037] Figure 1C shows a timing diagram 100C of various pulses related to the input pulse for generating the output signal of the exemplary apparatus in Figure 1A or Figure 1B based on a series of photons 102 received in the SPAD 110. This exemplary timing diagram 100C is based on the SPAD, a quenching circuit, and an output circuit (e.g., an output circuit 120 as described above with reference to Figure 1A or Figure 1B, or as described later with reference to Figure 5). For example, the output circuit may include toggle flip-flops and data flip-flops. A flip-flop is a basic circuit element that can store two states controlled by an input signal. A random flip-flop is a circuit that operates when the state of the clock pulse input changes from Low to High. The output of the random flip-flops can be individually clocked and the bits sampled to generate a random binary stream 130 of 1s and 0s. In some embodiments, the output circuit 120 may include a flip-flop, an input section, an output section, an AND gate, an OR gate, an XOR gate, a NOT gate, a NAND gate, a NOR gate, an XNOR gate, an EXOR gate, an EXNOR gate, a multiplexer, and other logic gates, flip-flops, or circuits, or combinations thereof.

[0038] As shown in Figure 1C, each SPAD pulse 112 (toggle flip-flop clock input) is characterized by a rising edge and a falling edge. The toggle flip-flop generates an output Q signal 114 in response to the SPAD pulse 112. The Q signal 114 may be supplied as input to a data flip-flop. As shown in Figure 1C, the output Q signal 114 of the toggle flip-flop is toggled High and Low by the rising edge of the SPAD pulse 112. A circuit clock signal 116 may be supplied to the clock input of the data flip-flop, and the data flip-flop may generate a DATA_OUT signal 118. According to a particular exemplary implementation of the disclosed technology, a random binary stream output 130 can be generated using the DATA_OUT signal 118 output from the data flip-flop. In a particular exemplary implementation, the DATA_OUT signal 118 of the data flip-flop may be clocked separately. In some implementations, for example, a "1" may be output to the random binary stream output 130 for each rising edge of the DATA_OUT signal 118. Conversely, a "0" may be output to the random binary stream output 130 for each falling edge of the DATA_OUT signal 118. If the state of the DATA_OUT signal 118 does not change, the previous state may be output to the random binary stream output 130. In other words, by sampling the DATA_OUT signal 118, it is possible to generate a random binary stream 130 of 1s and 0s as shown in Figure 1C.

[0039] Figure 2A shows a system 200A comprising an array of SPADs (110A, 110B, ..., 110n) with corresponding quenching circuits (140A, 140B, ..., 140n). The quenching circuits (140A, 140B, ..., 140n) supply n corresponding SPAD signals (SPAD1, SPAD2, ..., SPADn), which are input to an OR gate 150 to generate a randomized clock pulse input (SPADout) for an output circuit 120. Here, each SPAD in the array (110A, 110B, ..., 110n) detects its own set of photons 102 from multiple sets of photons 102-102' (as described above with reference to Figures 1A and 2A). A corresponding series of quenching circuits (140A, 140B, ..., 140n) may be used together with the corresponding SPAD (110A, 110B, ..., 110n) to detect each series of photons 102, 102' and convert them into a series of electrical pulses.

[0040] According to certain exemplary implementations of the disclosed technology, signals from the array of SPADs (110A, 110B, ..., 110n) can be combined using various circuits and / or gates to output a single randomized clock pulse input (SPADout) to the output circuit 120' as described above. Signals from each quenching circuit (140A, 140B, ..., 140n) can also be combined using other logic gates (including, but not limited to, AND gates, OR gates, XOR gates, NOT gates, NAND gates, NOR gates, XNOR gates, EXOR gates, EXNOR gates, multiplexers, and other logic gates, or combinations thereof). A single randomized clock pulse input can be supplied to the output circuit 120', which may include one or more flip-flops and / or other logic circuit equivalents, to generate a random binary stream 130 that is at least partially based on the randomized clock pulse input (SPADout). In some examples, a single randomized clock pulse input (SPADout) may be fed to a series of flip-flops to generate a random binary stream 130.

[0041] As shown in Figure 2A, the output circuit 120' may include a random flip-flop which may include one or more toggle flip-flops and one or more data flip-flops. The output circuit 120' may further include an analog-to-digital converter.

[0042] In some embodiments, control points can be provided in systems 100A, 100B, and / or 200A to ensure unbiased operation by, for example, changing the light intensity on SPAD110 or an array of SPADs (110A, 110B, ..., 110n) or switching them on and off. In certain exemplary implementations, blocks of SPAD subarrays can be used to provide differential distributions of illuminance from multiple light sources on these arrays. In certain embodiments, continuous health checks can be performed on SPAD110 or an array of SPADs (110A, 110B, ..., 110n) to measure response variations, dark counts, jitter, correlations, defects, and toggle on / off states. Dark count is the average rate of counts registered when no incident light is present on SPAD110. Health checks on the jitter timing of SPAD110 help determine the fast time response operation of SPAD110. By ensuring the overall health of the SPAD array (110A, 110B, ..., 110n), the unbiased operation of the random number generator can be verified. In another example, to ensure the unbiased operation of the random number generator, the SPAD array (110A, 110B, ..., 110n) can be arranged in a grid, and bias can be continuously monitored using columns, rows, or any combination to identify non-random operation. If an individual SPAD110 within the SPAD array (110A, 110B, ..., 110n) is malfunctioning, the non-random operation of that individual SPAD110 can be identified by comparing the output of that individual SPAD110 with that of adjacent SPADs (110A, 110B, ..., 110n), which can serve as another control point to ensure unbiased operation.

[0043] Figure 2B shows the timing of various pulses related to generating the output signal of the OR gate 150 based on a series of photons 102, 102' received in SPAD(110A, 110B, ..., 110n). In this figure, each SPAD in the array of SPADs (110A, 110B, ..., 110n) has a corresponding pulse train (112A, 112B, ..., 112n) with rising and falling edges. As shown in Figure 2A, a series of electrical pulses from each corresponding quenching circuit (140A, 140B, ..., 140n) can be input to the OR gate 150 and become a combined output 112' which can be used as a single randomized clock pulse input to the output circuit 120'. It is possible to combine multiple input pulse trains (112A, 112B, ..., 112n) using other logic gates (including, but not limited to, AND gates, OR gates, XOR gates, NOT gates, NAND gates, NOR gates, XNOR gates, EXOR gates, EXNOR gates, multiplexers, and other logic gates, or combinations thereof) to form a combined output 112'. In this example, the rising and falling edges of each SPAD in the SPAD array (110A, 110B, ..., 110n) are included as the rising and falling edges in the combined output 112', respectively.

[0044] Figures 3A to 3C show the threshold voltage V to control the threshold voltage level (122, 122A, 122B) when the output circuit (e.g., output circuit 120 shown in Figure 1A and / or Figure 1B, and / or output circuit 120' shown in Figure 2A) interprets the corresponding input signal received from the SPAD and / or other coupled logic (e.g., OR gate 150 shown in Figure 2A) as binary 0 or 1 for output. THR This shows various implementations for setting 302.

[0045] Figure 3A shows, for example, an input voltage below the set threshold voltage level 122 is interpreted as 0, and an input voltage above the set threshold voltage level 122 is interpreted as 1, with the voltage threshold V set to approximately 50% of the entire range of the normalized input voltage V(norm). THR It shows 302.

[0046] Figure 3B shows, for example, an input voltage below the set threshold voltage level 122A is interpreted as 0, and an input voltage above the set threshold voltage level 122A is interpreted as 1, with the voltage threshold V set to approximately 25% of the entire range of the normalized input voltage V(norm). THR It shows 302.

[0047] Figure 3C shows, for example, an input voltage below the set threshold voltage level 122B is interpreted as 0, and an input voltage above the set threshold voltage level 122B is interpreted as 1, with the voltage threshold V set to approximately 75% of the entire range of the normalized input voltage V(norm). THR It shows 302.

[0048] According to certain exemplary implementations of the disclosed technology, as shown in Figures 3A to 3C, the input signal (from a SPAD, etc.) may have a corresponding slew rate (i.e., a non-instantaneous rise or fall level), so the voltage threshold V THR By adjusting 302, the duration associated with outputs 1 and 0 can be changed. This provides a controllable method for further randomizing the decision point when interpreting inputs from one or more SPADs as 0 or 1 for output. In certain exemplary implementations, V THR The 302 can be controlled based on randomized inputs (including, but not limited to, the outputs of one or more SPADs).

[0049] Figures 4A and 4B show how the voltage threshold V THR302 further illustrates whether it can affect the random binary stream outputs 402A and 402B based on the toggled voltage threshold control input. FIG. 4A shows, for example, the set voltage threshold V THR The input voltage 404 less than 302 is interpreted as 0 (at each rising edge of the clock signal 406), and the input voltage higher than the set threshold voltage level 122 is interpreted as 1 (at each rising edge of the circuit clock signal 406). The voltage threshold V THR 302 is set at approximately 50% of the full range of the normalized input voltage. FIG. 4B shows, for example, the set voltage threshold V THR The input voltage 404 less than  302 is interpreted as 0 (at each rising edge of the clock signal 406), and the input voltage 404 higher than the set threshold voltage level 122 is interpreted as 1 (at each rising edge of the clock signal 406). The voltage threshold V THR 302 is set at approximately 75% of the full range of the normalized input voltage. The comparison of the random binary stream outputs 402A and 402B shows the difference at a specific bit 408 between the two random binary stream outputs 402A and 402B corresponding to the voltage threshold V THR 302. In a particular exemplary implementation, the voltage threshold V THR 302 can be controlled based on a randomized input (including but not limited to the output of one or more SPADs) to further randomize the (already randomized) binary stream output. In this regard, the voltage threshold V THR 302 can provide a desired additional level of randomization in the random number generator. In a particular exemplary implementation, the voltage threshold V THR 302 may be set to control the ratio of 0 to 1 of the randomized binary stream outputs 402A and 402B over a period of time.

[0050] Figure 5 shows an exemplary circuit 500 (including SPAD110) with various circuit components available to provide a DATA_OUT output 550 (i.e., a randomized binary stream output) based on the reception (and detection) of photons 102 by SPAD110. Other circuit components, arrangements, and / or control inputs may be utilized, but circuit 500 represents an exemplary embodiment usable in practical applications. This exemplary circuit 500 may include one or more field-effect transistors 502, 504, 506, and 510, one or more inverters 512 and 514, one or more Schmitt triggers 516, one or more NOR gates 518, one or more toggle flip-flops 520, and / or one or more data flip-flops 530. According to a particular exemplary implementation of the disclosed technology, the circuit 500 shown in Figure 5 has a voltage threshold control input V_THRESH 504 (for example, the voltage threshold control input is the voltage threshold V mentioned above). THR It can be considered a random flip-flop (RFF) circuit having (similar to or equivalent to) 302. The RFF circuit may also include various quenching control inputs V_CAS, V_Q, V_RECHARGE, and V_HOLD, which can be used to control the bias and quenching of SPAD110, for example, as described above. The RFF circuit may also include other controls such as BIT GEN CLK (similar to or equivalent to the circuit clock 406 described with reference to Figures 4A and 4B). In certain exemplary implementations, a TOGGLE input may be included as an input to the toggle flip-flop 520. In certain implementations, the Q output of the toggle flip-flop 520 may be used as a data input to the data flip-flop 530. The arrangement and interaction of the various components of circuit 500 will be understandable to a person skilled in the art with basic skills in the art of electronic circuit and logic design.

[0051] According to a particular exemplary implementation of the disclosed technology, a photon 102 can be detected by a SPAD 110, which generates a signal passing through a series of circuits and gates (which may form a quenching circuit) to generate a randomized clock pulse input 522 to a toggle flip-flop 520. The toggle flip-flop 520 is a sequential logic circuit that toggles its output depending on the input state. In this example, the output state of the toggle flip-flop 520 can be toggled High or Low by the rising edge of the randomized clock pulse 522 from the SPAD 110 and / or associated quenching circuit configuration. The toggle flip-flop 520 can supply its output (Q) to the data input (D) of a data flip-flop 530. The data flip-flop 530 can then capture the input value at a specified edge of the clock signal CLK supplied to the data flip-flop 520. The threshold voltage control input V_THRESH540 can be used to adjust the data flip-flop 530 to correspond to the rise and fall times of the output from the toggle flip-flop 520. A regular oscillating clock signal may be used as the clock input CLK of the data flip-flop 530. The data flip-flop 530 enables the output of the toggle flip-flop 520 to be synchronized with the clock. The data output 550 of the data flip-flop 530 can be clocked individually, and the corresponding output bits can be sampled to generate a random binary stream of 1s and 0s (see the random binary stream 130 in Figures 1A, 1B, 1C, and 2, and / or the random binary streams 402A and 402B in Figures 4A and 4B as described above).

[0052] In some embodiments, the reverse bias breakdown voltage of SPAD110 can be varied to modify and adjust the randomized clock pulse input 522 to the toggle flip-flop 520.

[0053] In some embodiments, as described above, the threshold voltage V_THRESH(VTHR It is possible to supply (302) to control the random binary stream output 550 and adjust the ratio of 1s to 0s in the random binary stream output 550. For example, the ratio of 1s to 0s in the random binary stream output 550 can be adjusted in the range of 0.01 to 100. In certain exemplary implementations, it may be desirable to set the ratio of 1s to 0s in the random binary stream output 550 to be approximately 1 (i.e., 1:1) over a given period of time. In certain exemplary implementations, an averaging circuit may be additionally used to provide feedback for controlling the threshold voltage.

[0054] In certain exemplary implementations, instead of supplying the output 523 from the toggle flip-flop 520 to the data flip-flop 530, the random binary stream 130 can be generated by directly measuring the voltage of the output 523 of the toggle flip-flop 530. In other embodiments, the toggle flip-flop 530 can be coupled with an analog-to-digital converter to generate the random binary stream 130. Figure 6 is a timing diagram 600 showing the generation of the random binary stream output 602. Figure 600 shows the SPAD pulse 604 (which may correspond to the input 522 of the toggle flip-flop 520 as described in Figure 5), the Q output 606 (which may correspond to the D input 523 of the data flip-flop 530 as described in Figure 5), the clock signal 608 (which may correspond to the clock signal 535 as described in Figure 5), and the DATA_OUT signal 610 (which may correspond to the DATA_OUT 550 as described in Figure 5). Figure 600 further illustrates a delay t612 that can be provided (or configurable) so that, for example, the timing of the evaluation of the SPAD pulse 604 occurs after a predetermined time has elapsed following the rising edge of the clock 608.

[0055]

[0056] In certain exemplary implementations, as shown in Figure 6, the Q output 606 may be toggled on with each rising edge of the SPAD pulse 604. In certain exemplary implementations, the DATA_OUT signal 610 may be generated based on a combination of the Q output 606 logic level, the clock 608 logic level, and the delay t612. Thus, according to certain exemplary implementations of the disclosed technology, the delay t612 may be used to further vary or randomize the DATA_OUT 610 compared to the Q output 606.

[0057] Figure 7 is a flowchart of Method 700 relating to a specific exemplary implementation of the disclosed technology. In block 702, Method 700 includes receiving a first set of photons in a first single-photon avalanche diode (SPAD). In block 704, Method 700 includes converting the first set of photons into a first set of electrical pulses by the first SPAD, the first set of electrical pulses having a first random time interval between each pulse of the first set of electrical pulses. In block 706, Method 700 includes outputting a random binary stream based at least in part on the first set of electrical pulses by an output circuit communicating with the first SPAD.

[0058] Certain exemplary implementations of the disclosed technology may include receiving a second set of photons in a second single-photon avalanche diode (SPAD). Some implementations include converting the second set of photons into a second set of electrical pulses by the second SPAD, where the second set of electrical pulses has a second random time interval between each pulse of the second set of electrical pulses. Furthermore, an output circuit may include outputting a random binary stream based at least partially on the first set of electrical pulses and the second set of electrical pulses.

[0059] Certain exemplary implementations of the disclosed technology may include adjusting the bias voltage of the SPAD using a quenching circuit in response to photon detection by the SPAD. In some implementations, the quenching circuit may be configured to convert a first set of photons into a first set of electrical pulses.

[0060] Certain exemplary implementations of the disclosed technology may include a quenching circuit generating randomized clock pulses based at least partially on a first set of electrical pulses.

[0061] In certain exemplary implementations, the output circuit may include one or more of the following: a toggle flip-flop (TFF), a data flip-flop (DFF), a random flip-flop (RFF), an analog-to-digital converter (ADC), or a combination thereof. In certain exemplary implementations, the RFF may include a TFF and / or a DFF. In some implementations, the input to the TFF may be a randomized clock pulse input generated at least partially based on a first set of electrical pulses.

[0062] Certain exemplary implementations of the disclosed technology may include toggling the output of a TFF based on the rising edge of a randomized clock pulse input. Certain exemplary implementations of the disclosed technology may also include toggling the output of a TFF based on the delay following the rising edge of a randomized clock pulse input. In some implementations, the output of the TFF may be provided as a data input to a DFF.

[0063] According to one exemplary implementation of the disclosed technology, it is possible to supply a regularly oscillating clock signal to the clock input of a DFF.

[0064] In some implementations, the DFF can further include a voltage threshold control input.

[0065] A specific exemplary implementation of the disclosed technology is a voltage threshold V THR It is possible to adjust the input to the output circuit and cause the output circuit to output a random binary stream so that the random binary stream outputs a controllable ratio of 1s and 0s. In certain exemplary implementations, V THR This can be controlled so that the average number of zeros output to the random binary stream is approximately equal to the average number of ones.

[0066] A specific exemplary implementation of the disclosed technology is a voltage threshold V THR It is possible to adjust this to control the input to the output circuit and cause the output circuit to output a random binary stream such that the random binary stream outputs an average number of zeros that are not equal to the average number of ones.

[0067] Certain exemplary implementations of the disclosed technology may include emitting a first set of photons from a light source in thermal equilibrium for detection by one or more SPADs. In certain exemplary implementations of the disclosed technology, the light source may include one or more of the following: light-emitting diodes (LEDs), pulsed lasers, and combinations thereof. In certain exemplary implementations, the light source may include ambient light.

[0068] Certain exemplary implementations of the disclosed technology may include digitizing one or more of a first set of electrical pulses and a random binary stream using an analog-to-digital converter (ADC). Some implementations may include varying the dead time for receiving a first set of photons in the SPAD, where the first set of photons includes a first random time interval between the arrival of each photon in the first set of photons.

[0069] A particular exemplary implementation of the disclosed technology may include receiving a second set of photons in a second single-photon avalanche diode (SPAD). A particular exemplary implementation of the disclosed technology may include converting the second set of photons into a second set of electrical pulses by the second SPAD, wherein the second set of electrical pulses has a second random time interval between each pulse of the second set of electrical pulses. A particular exemplary implementation of the disclosed technology may include outputting a random binary stream based at least partially on the first set of electrical pulses and the second set of electrical pulses by an output circuit. According to one exemplary implementation of the disclosed technology, the output circuit may include one or more of the following: NOT gates, AND gates, NAND gates, OR gates, NOR gates, XOR gates, XNOR gates, and combinations thereof.

[0070] The disclosed technology includes a quantum random number generator which may include one or more single-photon avalanche diodes (SPADs) configured to receive a corresponding set of photons, and one or more quenching circuits which each communicate with the corresponding one or more SPADs. The one or more quenching circuits may be configured to convert the corresponding set of photons into a corresponding set of electrical pulses, each corresponding set of electrical pulses may have a corresponding random time interval between each pulse of the corresponding set of electrical pulses. The system may include an output circuit which communicates with one or more quenching circuits. The output circuit may be configured to output a random binary stream which is at least partially based on the corresponding set of electrical pulses.

[0071] The descriptions contained herein are examples of embodiments of the disclosed technology and are not intended to limit the scope of the invention in any way. As described herein, this specification envisions many variations and modifications of random number generation systems, including additional communication functions, additional functions to meet end-user needs not specifically described herein, additional and / or alternative random number sources, additional and / or alternative schemes and means for generating random bitstreams, additional and / or alternative schemes for encrypting and / or encapsulating random numbers for secure transmission over insecure networks, additional and / or alternative schemes for creating virtual entropy sources, and so on. These modifications will be obvious to those skilled in the art in which the invention relates and are intended to be included in the claims described below.

Claims

1. A method for generating random numbers, In a first single-photon avalanche diode (SPAD), the steps include receiving a first series of photons, In a second single-photon avalanche diode (SPAD), the steps include receiving a second series of photons, A step of converting a first series of photons into a first series of electrical pulses using the first SPAD, wherein the first series of electrical pulses has a first random time interval between each pulse of the first series of electrical pulses. A step of converting the second series of photons into a second series of electrical pulses using the second SPAD, wherein the second series of electrical pulses has a second random time interval between each pulse of the second series of electrical pulses. A step of generating a pulse waveform having the first series of electrical pulses and the second series of electrical pulses, The output circuit that communicates with the first SPAD generates an output Q signal that toggles the state according to each electrical pulse in the pulse waveform, A method comprising the step of outputting a random binary stream based at least partially on the output Q signal using the output circuit.

2. A method for generating random numbers, In a first single-photon avalanche diode (SPAD), the steps include receiving a first series of photons, A step of converting a first series of photons into a first series of electrical pulses using the first SPAD, wherein the first series of electrical pulses has a first random time interval between each pulse of the first series of electrical pulses. The steps of generating a pulse waveform having the first series of electrical pulses, The output circuit that communicates with the first SPAD generates an output Q signal that toggles the state according to each electrical pulse in the pulse waveform, The output circuit outputs a random binary stream that is at least partially based on the output Q signal. A method comprising the step of adjusting the bias voltage of the first SPAD using a quenching circuit in response to photon detection by the first SPAD.

3. The method according to claim 2, wherein the quenching circuit is configured to convert the first series of photons into the first series of electrical pulses.

4. A method for generating random numbers, In a first single-photon avalanche diode (SPAD), the steps include receiving a first series of photons, A step of converting a first series of photons into a first series of electrical pulses using the first SPAD, wherein the first series of electrical pulses has a first random time interval between each pulse of the first series of electrical pulses. The steps of generating a pulse waveform having the first series of electrical pulses, The output circuit that communicates with the first SPAD generates an output Q signal that toggles the state according to each electrical pulse in the pulse waveform, The output circuit includes the step of outputting a random binary stream that is at least partially based on the output Q signal, The output circuit includes a toggle flip-flop (TFF) having a first clock input section and a first state output section. The TFF is configured to receive the pulse waveform at the first clock input unit and to provide the output Q signal at the first state output unit.

5. The output circuit includes a data flip-flop (DFF) having a second clock input, a state input, and a second state output. The DFF is configured to receive the output Q signal at the state input unit, receive the clock signal at the second clock input unit, and provide the output data signal at the second state output unit. The method according to claim 4, wherein the random binary stream is at least partially based on the output data signal, and the random binary stream is at least partially based on the output Q signal.

6. The method according to claim 5, wherein the clock signal includes a regularly oscillating clock signal to the second clock input section of the DFF.

7. The method of claim 5, further comprising the step of generating the random binary stream such that the 1s and 0s of the random binary stream correspond to the respective states of the output data signal.

8. The method according to claim 5, wherein the output data signal is at least partially based on the output Q signal, the clock signal, and a time delay from the clock signal.

9. The method of claim 8, further comprising the step of utilizing the time delay to further randomize the output data signal.

10. The TFF further includes a voltage threshold control input, In the aforementioned voltage threshold control input, the voltage threshold V ＴＨＲ The method according to claim 4, further comprising the step of adjusting so that the output circuit outputs a random binary stream such that the average number of zeros in the random binary stream is approximately equal to the average number of ones.

11. The aforementioned voltage threshold V ＴＨＲ The method according to claim 10, wherein is set to the ratio of the normalized voltage of the pulse waveform over the entire range.

12. The TFF further includes a voltage threshold control input, In the aforementioned voltage threshold control input, the voltage threshold V ＴＨＲ The method according to claim 4, further comprising the step of adjusting so that the output circuit outputs a random binary stream such that the random binary stream outputs an average number of zeros that are not equal to the average number of ones.

13. The TFF further includes a voltage threshold control input, Based on the randomized input, the voltage threshold V is set in the voltage threshold control input. ＴＨＲ The method according to claim 4, further comprising the step of adjusting.

14. The method according to claim 13, wherein the randomized input is at least partially based on the output from a second SPAD.

15. The TFF further includes a voltage threshold control input, and the output circuit includes an averaging circuit. The steps include: averaging the output data signal using the averaging circuit; Voltage threshold V is at least partially based on the feedback from the averaging circuit. ＴＨＲ The method of claim 5, further comprising the step of adjusting the

16. A method for generating random numbers, The first step is to emit a series of photons from a light source in thermal equilibrium, In a first single-photon avalanche diode (SPAD), the steps include receiving the first series of photons, A step of converting a first series of photons into a first series of electrical pulses using the first SPAD, wherein the first series of electrical pulses has a first random time interval between each pulse of the first series of electrical pulses. The steps of generating a pulse waveform having the first series of electrical pulses, The output circuit that communicates with the first SPAD generates an output Q signal that toggles the state according to each electrical pulse in the pulse waveform, A method comprising the step of outputting a random binary stream based at least partially on the output Q signal using the output circuit.

17. The method according to claim 16, wherein the light source includes one or more of a light-emitting diode (LED), a pulsed laser, and a combination thereof.

18. A method for generating random numbers, In a first single-photon avalanche diode (SPAD), the steps include receiving a first series of photons, A step of converting a first series of photons into a first series of electrical pulses using the first SPAD, wherein the first series of electrical pulses has a first random time interval between each pulse of the first series of electrical pulses. The steps of generating a pulse waveform having the first series of electrical pulses, The output circuit that communicates with the first SPAD generates an output Q signal that toggles the state according to each electrical pulse in the pulse waveform, The output circuit outputs a random binary stream that is at least partially based on the output Q signal. The first SPAD includes the step of changing the dead time for receiving a first series of photons, A method wherein the first series of photons has a first random time interval between the arrival of each photon in the first series of photons.

19. A method for generating random numbers, In a first single-photon avalanche diode (SPAD), the steps include receiving a first series of photons, In a second single-photon avalanche diode (SPAD), the steps include receiving a second series of photons, A step of converting a first series of photons into a first series of electrical pulses using the first SPAD, wherein the first series of electrical pulses has a first random time interval between each pulse of the first series of electrical pulses. A step of converting the second series of photons into a second series of electrical pulses using the second SPAD, wherein the second series of electrical pulses has a second random time interval between each pulse of the second series of electrical pulses. The steps of generating a pulse waveform having the first series of electrical pulses, The output circuit that communicates with the first SPAD generates an output Q signal that toggles the state according to each electrical pulse in the pulse waveform, The output circuit outputs a random binary stream that is at least partially based on the output Q signal. A method comprising the step of outputting the random binary stream, which is at least partially based on the first series of electrical pulses and the second series of electrical pulses, wherein the output circuit comprises one or more NOT gates, AND gates, NAND gates, OR gates, NOR gates, XOR gates, XNOR gates, and combinations thereof.

20. One or more single-photon avalanche diodes (SPADs) configured to receive a corresponding series of photons, One or more quenching circuits that communicate with one or more corresponding SPADs, each of which is configured to convert the corresponding series of photons into a corresponding series of electrical pulses, and each of the corresponding series of electrical pulses has a corresponding random time interval between each pulse of the corresponding series of electrical pulses, An output circuit that communicates with one or more quenching circuits, A pulse waveform is generated that is at least partially based on the corresponding series of electrical pulses of each of the one or more SPADs. An output Q signal is generated that toggles the state according to each electrical pulse in the pulse waveform. A quantum random number generator comprising: an output circuit configured to output a random binary stream based at least partially on the output Q signal.

21. The output circuit described above is A data output signal is generated by sampling the output Q signal based on the clock input. The quantum random number generator according to claim 20, configured to generate the random binary stream which is at least partially based on the data output signal, such that the random binary stream is at least partially based on the output Q signal.

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