Semiconductor equipment

Abstract

To provide a semiconductor device with high storage capacity.SOLUTION: A semiconductor device includes first to sixth insulators, first to third conductors, and first to third material layers. In the first conductor, the first insulator and the first material layer overlap. In a first region of the first material layer, the second material layer, the second conductor, the second insulator, and the third insulator overlap. The third material layer exists in a region including a second region of the first material layer and an upper surface of each of the second material layer, the second conductor, the second insulator, and the third insulator. The fourth insulator exists on the third material layer, the sixth insulator exists on the fourth insulator, and the fifth insulator exists on the sixth insulator. The third conductor exists on the fifth insulator that overlaps with the second region of the first material layer. The first to third material layers include an oxide containing indium, an element M (M represents aluminum, gallium, tin, or titanium), and zinc.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to objects, methods of operation, or methods of manufacture. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for testing them. [Background technology]

[0003] In recent years, electronic components such as central processing units (CPUs), graphics processing units (GPUs), memory devices, and sensors have been used in a wide range of electronic devices, including personal computers, smartphones, and digital cameras. These electronic components have undergone improvements in various aspects, including miniaturization and low power consumption.

[0004] In particular, the amount of data handled in the aforementioned electronic devices is increasing, and there is a demand for memory devices with large storage capacities. As a means of increasing storage capacity, for example, Patent Document 1 discloses a three-dimensional NAND memory element using a metal oxide as the channel formation region. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2016 / 149004 [Overview of the project] [Problems that the invention aims to solve]

[0006] The semiconductor layer of a transistor, which constitutes a memory element, can be divided into a channel formation region and a low-resistance region. In particular, when using a metal oxide as the semiconductor layer of a three-dimensional NAND memory, how to form the low-resistance region of the metal oxide is important. In a metal oxide used as the semiconductor layer of a transistor, regions with low carrier concentration (or, in this specification, may be described as intrinsic, substantially intrinsic, etc.) function as channel formation regions, and regions with high carrier concentration function as low-resistance regions. Therefore, in the fabrication of a three-dimensional NAND memory using a metal oxide as the semiconductor layer, differentiating between the channel formation region and the low-resistance region is a challenge. Furthermore, after differentiating between the channel formation region and the low-resistance region, it is preferable to deposit a highly barrier film in the channel formation region so that the carrier concentration in the channel formation region does not change due to the diffusion of impurities, etc. In addition, to increase the data capacity of the NAND memory, it is preferable to make each of the channel formation region and the low-resistance region smaller and increase the number of cell transistors per string. Furthermore, a cell transistor is an example of a memory cell and includes transistors with a structure capable of storing data.

[0007] One aspect of the present invention aims to provide a highly reliable semiconductor device. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a large data capacity. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device. Alternatively, one aspect of the present invention aims to apply a memory device having a novel semiconductor device. Alternatively, one aspect of the present invention aims to provide an electronic device having said memory device.

[0008] It should be noted that the problems addressed by one aspect of the present invention are not limited to those listed above. The problems listed above do not preclude the existence of other problems. These other problems are those not mentioned in this section, as described below. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the problems listed above and other problems. It should be noted that one aspect of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0009] (1) One aspect of the present invention is a semiconductor device comprising a columnar first conductor, a second conductor, a third conductor, a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, a sixth insulator, a first material layer, a second material layer, and a third material layer. The first material layer comprises a first region and a second region. The first insulator is positioned adjacent to the first conductor, and the first material layer is positioned adjacent to the first insulator. The second material layer is positioned adjacent to the first region of the first material layer, the second conductor is positioned adjacent to the second material layer, the second insulator is positioned adjacent to the second conductor, and the third insulator is positioned adjacent to the second insulator. The third material layer is positioned to cover the second material layer, the second conductor, the second insulator, the third insulator, and the second region of the first material layer. The fourth insulator is positioned adjacent to the third material layer, the sixth insulator is positioned adjacent to the fourth insulator, the fifth insulator is positioned adjacent to the sixth insulator, and the third conductor is positioned adjacent to the fifth insulator and overlapping the first region of the first material layer. The second insulator functions as a barrier insulating film to prevent the diffusion of oxygen into the second conductor, the fourth insulator functions as a tunnel insulating film, the sixth insulator functions as a charge storage layer, and the fifth insulator functions as a gate insulating film. The first material layer has an oxide containing indium, element M (where M is aluminum, gallium, tin, or titanium), and zinc. The second material layer has an oxide containing indium, element M, and zinc, and the third material layer has an oxide containing indium, element M, and zinc.

[0010] (2) One aspect of the present invention is a semiconductor device comprising a columnar first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, a first material layer, a second material layer, and a third material layer. The first material layer comprises a first region and a second region. The first insulator is positioned adjacent to the first conductor, the first material layer is positioned adjacent to the first insulator, the second material layer is positioned adjacent to the first region of the first material layer, the second conductor is positioned adjacent to the second material layer, the second insulator is positioned adjacent to the second conductor, and the third insulator is positioned adjacent to the second insulator. The third material layer is positioned to cover the second material layer, the second conductor, the second insulator, the third insulator, and the second region of the first material layer. The fourth insulator is positioned adjacent to the third material layer, the fourth conductor is positioned adjacent to the fourth insulator and overlapping the first region of the first material layer, the fifth insulator is positioned to cover the fourth conductor, and the third conductor is positioned adjacent to the fifth insulator and overlapping the first region of the first material layer. Furthermore, the second insulator functions as a barrier insulating film to prevent the diffusion of oxygen into the second conductor, the fourth insulator functions as a tunnel insulating film, the fourth conductor functions as a floating gate electrode, and the fifth insulator functions as a gate insulating film. The first material layer has an oxide containing indium, element M (where M is aluminum, gallium, tin, or titanium), and zinc; the second material layer has an oxide containing indium, element M, and zinc; and the third material layer has an oxide containing indium, element M, and zinc.

[0011] (3) Furthermore, in the configuration of (1) or (2) above, the first material layer may have a fourth material layer and a fifth material layer. In particular, it is preferable that the fourth material layer is located adjacent to the first insulator, the fifth material layer is located adjacent to the fourth material layer, the first region of the first material layer is located in the fifth material layer, and the second region of the first material layer is located in the fifth material layer. Furthermore, it is preferable that the ratio of the number of atoms of element M to indium contained in the second material layer is greater than the ratio of the number of atoms of element M to indium contained in the fifth material layer. Furthermore, it is preferable that the ratio of the number of atoms of element M to indium contained in the fourth material layer is greater than the ratio of the number of atoms of element M to indium contained in the fifth material layer.

[0012] (4) Furthermore, in any one of the configurations (1) to (3) above, the oxygen concentration in the second region of the first material layer may be higher than that in the first region of the first material layer.

[0013] (5) Furthermore, in any one of the configurations (1) to (4) above, the film thickness of the second region of the first material layer may be thinner than the film thickness of the first region of the first material layer.

[0014] (6) Furthermore, one aspect of the present invention is a storage device having any one of the semiconductor devices described in (1) to (5) above, and a peripheral circuit.

[0015] (7) Furthermore, one aspect of the present invention is an electronic device having any one of the above-mentioned storage devices (1) to (6) and a housing.

[0016] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices or may contain semiconductor devices.

[0017] Furthermore, when it is stated in this specification that X and Y are connected, it is assumed that this specification discloses the cases in which X and Y are electrically connected, functionally connected, and directly connected. Therefore, it is assumed that the disclosed connections are not limited to predetermined connections, such as those shown in the figures or text, but also include connections other than those shown in the figures or text. X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0018] One example of a case where X and Y are electrically connected is that one or more elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, display devices, light-emitting devices, loads, etc.) can be connected between X and Y. A switch has the function of controlling on / off states. In other words, a switch has the function of controlling whether or not current flows by being in a conductive state (on state) or a non-conductive state (off state).

[0019] One example of a functional connection between X and Y is when one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal conversion circuits (digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, such as operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y.

[0020] Furthermore, when it is explicitly stated that X and Y are electrically connected, this includes both cases where X and Y are electrically connected (i.e., connected with another element or circuit in between) and cases where X and Y are directly connected (i.e., connected without another element or circuit in between).

[0021] Furthermore, it can be expressed as, for example, "X, Y, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and the connection is in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Alternatively, it can be expressed as, "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Alternatively, it can be expressed as, "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using similar notation to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and their technical scope determined. Note that these notational methods are examples only and are not limited to them. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0022] Even if independent components are shown as electrically connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wire also functions as an electrode, a single conductive film possesses the functions of both a wire and an electrode. Therefore, in this specification, "electrically connected" includes cases where a single conductive film possesses the functions of multiple components.

[0023] Furthermore, in this specification, "resistive element" can refer to, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, "resistive element" includes wiring having a resistance value, transistors, diodes, coils, etc., through which current flows between the source and drain. Therefore, the term "resistive element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistive element." The resistance value can be, for example, preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Also, for example, 1Ω or more and 1 × 10 9 It may also be less than or equal to Ω.

[0024] Furthermore, in this specification, "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value, parasitic capacitance, the gate capacitance of a transistor, etc. Therefore, in this specification, "capacitive element" includes a circuit element comprising a pair of electrodes and a dielectric material contained between the electrodes. Also, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with terms such as "capacitance." Conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Also, the term "pair of electrodes" in "capacitance" can sometimes be replaced with terms such as "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05fF or more and 10pF or less. Alternatively, it may be, for example, 1pF or more and 10μF or less.

[0025] Furthermore, in this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain may be interchangeable. Also, in this specification, when describing the connection relationships of a transistor, the notation "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) is used. Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification, one of the gate or back gate of the transistor may be called the first gate, and the other of the gate or back gate of the transistor may be called the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, if a transistor has three or more gates, in this specification, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0026] Furthermore, in this specification, the term "node" can be replaced with terms such as terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration and device structure. Also, terminals, wiring, etc., can be replaced with "node."

[0027] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0028] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, if two wires are described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0029] "Electric current" refers to the phenomenon of electric charge movement (electrical conduction). For example, the statement "electrical conduction of positively charged elements is occurring" can be rephrased as "electrical conduction of negatively charged elements is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of electric charge movement associated with the movement of carriers (electrical conduction). Carriers here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., is the direction in which positive carriers move and is expressed as a positive current quantity. In other words, the direction in which negative carriers move is the opposite direction to the direction of the current and is expressed as a negative current quantity. Therefore, in this specification, if there is no specification regarding the positive or negative (or direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, descriptions such as "current is input to element A" can be rephrased as "current is output from element A."

[0030] Furthermore, the ordinal numbers "1st," "2nd," and "3rd" in this specification are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "1st" in one embodiment of this specification may be referred to as "2nd" in another embodiment or in the claims. Also, for example, a constituent element referred to as "1st" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0031] Furthermore, in this specification, terms indicating placement such as "above" and "below" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms explained in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0032] Furthermore, the terms "above" and "below" do not necessarily limit the positional relationship of the constituent elements to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other constituent elements are included between insulating layer A and electrode B.

[0033] Furthermore, in this specification, terms such as "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Alternatively, depending on the circumstances, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator."

[0034] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and vice versa. In addition, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" depending on the circumstances.

[0035] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" can be interchanged with each other depending on the circumstances or situation. For example, the term "wiring" may be changed to the term "signal line." Also, for example, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true; terms such as "signal line" and "power line" may be changed to the term "wiring." Terms such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true; terms such as "signal line" may be changed to the term "power line." In addition, the term "potential" applied to the wiring may be changed to the term "signal," depending on the circumstances or situation. Similarly, the reverse is also true; terms such as "signal" may be changed to the term "potential."

[0036] In this specification, semiconductor impurities refer to elements other than the main components that make up the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The presence of impurities can cause, for example, an increase in defect level density, a decrease in carrier mobility, and a decrease in crystallinity in the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, examples include hydrogen (which is also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that alter the properties of the semiconductor include, for example, Group 1 elements (excluding oxygen and hydrogen), Group 2 elements, Group 13 elements, and Group 15 elements.

[0037] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive (on) state or a non-conductive (off) state. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to any particular type, as long as it can control current.

[0038] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to a state in which the source and drain electrodes of the transistor can be considered to be electrically short-circuited. Conversely, the "non-conducting state" of the transistor refers to a state in which the source and drain electrodes of the transistor can be considered to be electrically disconnected. When a transistor is used simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0039] One example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and it operates by controlling the conduction and non-conductivity through the movement of these electrodes.

[0040] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Furthermore, "approximately parallel" or "roughly parallel" means a state in which two lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately perpendicular" or "roughly perpendicular" means a state in which two lines are positioned at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0041] According to one aspect of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large data capacity can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a storage device having a novel semiconductor device can be applied. Alternatively, according to one aspect of the present invention, an electronic device having said storage device can be provided.

[0042] The effects of one aspect of the present invention are not limited to those listed above. The effects listed above do not preclude the existence of other effects. These other effects are those described below and not mentioned in this section. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. One aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above. [Brief explanation of the drawing]

[0043] [Figure 1] Figure 1 is a cross-sectional view illustrating an example of a semiconductor device configuration. [Figure 2] Figures 2A and 2B are top views illustrating an example of a semiconductor device configuration. [Figure 3] Figures 3A to 3C are cross-sectional views illustrating an example of the configuration of a semiconductor device. [Figure 4] Figures 4A and 4B are top views illustrating an example of the configuration of a semiconductor device. [Figure 5] Figures 5A and 5B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 6] Figures 6A and 6B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 7] Figures 7A and 7B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 8]Figures 8A and 8B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 9] Figures 9A and 9B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 10] Figure 10A is a cross-sectional view illustrating an example of semiconductor device fabrication, and Figure 10B is a perspective view illustrating an example of semiconductor device fabrication. [Figure 11] Figures 11A and 11B are cross-sectional views illustrating an example of semiconductor device fabrication. [Figure 12] Figures 12A and 12B are cross-sectional views illustrating an example of semiconductor device fabrication. [Figure 13] Figures 13A and 13B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 14] Figure 14A is a cross-sectional view illustrating an example of the configuration of a semiconductor device, and Figure 14B is a cross-sectional view illustrating an example of the fabrication of a semiconductor device. [Figure 15] Figures 15A and 15B are top views illustrating an example of a semiconductor device configuration. [Figure 16] Figure 16 is a cross-sectional view illustrating an example of a semiconductor device configuration. [Figure 17] Figures 17A and 17B are top views illustrating an example of a semiconductor device configuration. [Figure 18] Figure 18 is a cross-sectional view illustrating an example of a semiconductor device configuration. [Figure 19] Figures 19A and 19B are top views illustrating an example of a semiconductor device configuration. [Figure 20] Figure 20 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 21] Figure 21 is a top view illustrating an example of a semiconductor device configuration. [Figure 22] Figure 22 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 23] Figure 23 is a top view illustrating an example of a semiconductor device configuration. [Figure 24]Figure 24 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 25] Figure 25 is a top view illustrating an example of a semiconductor device configuration. [Figure 26] Figure 26 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 27] Figures 27A and 27B are top views illustrating an example of a semiconductor device configuration. [Figure 28] Figure 28 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 29] Figures 29A and 29B are top views illustrating an example of a semiconductor device configuration. [Figure 30] Figures 30A to 30C are cross-sectional views illustrating an example of the configuration of a semiconductor device. [Figure 31] Figures 31A and 31B are top views illustrating an example of a semiconductor device configuration. [Figure 32] Figures 32A and 32B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 33] Figures 33A and 33B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 34] Figures 34A and 34B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 35] Figures 35A and 35B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 36] Figures 36A and 36B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 37] Figure 37A is a cross-sectional view illustrating an example of semiconductor device fabrication, and Figure 37B is a perspective view illustrating an example of semiconductor device fabrication. [Figure 38] Figures 38A and 38B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 39] Figures 39A and 39B are cross-sectional views illustrating examples of semiconductor device fabrication. [Figure 40]Figures 40A and 40B are cross-sectional views illustrating an example of a semiconductor device fabrication. [Figure 41] Figure 41 is a cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 42] Figure 42A is a cross-sectional view illustrating an example of the configuration of a semiconductor device, and Figure 42B is a cross-sectional view illustrating an example of the fabrication of a semiconductor device. [Figure 43] Figures 43A and 43B are top views illustrating an example configuration of a semiconductor device. [Figure 44] Figure 44 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 45] Figures 45A and 45B are top views illustrating an example configuration of a semiconductor device. [Figure 46] Figure 46 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 47] Figures 47A and 47B are top views illustrating an example of the configuration of a semiconductor device. [Figure 48] Figure 48 is a cross-sectional view illustrating an example of a semiconductor device configuration. [Figure 49] Figure 49 is a top view illustrating an example of a semiconductor device configuration. [Figure 50] Figure 50 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 51] Figure 51 is a top view illustrating an example of a semiconductor device configuration. [Figure 52] Figure 52 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 53] Figure 53 is a top view illustrating an example of a semiconductor device configuration. [Figure 54] Figure 54 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 55] Figures 55A and 55B are top views illustrating an example of the configuration of a semiconductor device. [Figure 56] Figures 56A and 56B are top views illustrating an example of a semiconductor device configuration. [Figure 57] Figures 57A and 57B are top views illustrating an example of a semiconductor device configuration. [Figure 58] Figures 58A and 58B are top views illustrating an example of a semiconductor device configuration. [Figure 59] Figure 59A illustrates the classification of IGZO crystal structures, Figure 59B illustrates the XRD spectrum of crystalline IGZO, and Figure 59C illustrates the micro-electron diffraction pattern of crystalline IGZO. [Figure 60] Figures 60A and 60B are circuit diagrams showing examples of semiconductor device configurations. [Figure 61] Figure 61 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 62] Figure 62 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 63] Figures 63A and 63B are timing charts showing examples of semiconductor device operation. [Figure 64] Figures 64A and 64B are timing charts showing examples of semiconductor device operation. [Figure 65] Figure 65A is a perspective view illustrating an example of a semiconductor device configuration, Figure 65B is a top view illustrating an example of a semiconductor device configuration, and Figure 65C is a cross-sectional view illustrating an example of a semiconductor device configuration. [Figure 66] Figure 66A is a perspective view illustrating an example of a semiconductor device configuration, Figure 66B is a top view illustrating an example of a semiconductor device configuration, and Figure 66C is a cross-sectional view illustrating an example of a semiconductor device configuration. [Figure 67] Figures 67A and 67B are cross-sectional views illustrating an example of a semiconductor device configuration. [Figure 68] Figures 68A and 68B are cross-sectional views illustrating an example of a semiconductor device configuration. [Figure 69] Figure 69 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 70] Figure 70 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 71]Figure 71A is a top view illustrating an example of the configuration of a semiconductor device, and Figures 71B to 71D are cross-sectional views illustrating an example of the configuration of a semiconductor device. [Figure 72] Figures 72A to 72C are perspective views illustrating an example of a semiconductor device configuration. [Figure 73] Figure 73 is a top view illustrating an example of a semiconductor device configuration. [Figure 74] Figure 74 is a block diagram illustrating an example of a storage device. [Figure 75] Figure 75A is a perspective view showing an example of a semiconductor wafer, Figure 75B is a perspective view showing an example of a chip, and Figures 75C and 75D are perspective views showing examples of electronic components. [Figure 76] Figure 76 is a block diagram illustrating the CPU. [Figure 77] Figures 77A to 77J are perspective views or schematic diagrams illustrating an example of a product. [Figure 78] Figures 78A to 78E are perspective views or schematic diagrams illustrating an example of a product. [Modes for carrying out the invention]

[0044] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, if a metal oxide can constitute a channel-forming region of a transistor having at least one of amplification, rectification, and switching functions, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0045] Furthermore, in this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Alternatively, metal oxides containing nitrogen may be called metal oxynitrides.

[0046] Furthermore, in this specification, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, if multiple configuration examples are shown within one embodiment, these configuration examples can be appropriately combined with each other.

[0047] Furthermore, any content described in one embodiment (even partial content) may be applied to, combined with, or substituted for at least one of the contents described in another embodiment (even partial content) and one or more other embodiments (even partial content).

[0048] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0049] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in the same embodiment, and at least one diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0050] The embodiments described herein will be explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention is not to be interpreted as being limited to the contents of the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in perspective views and the like, some components may be omitted in order to ensure clarity of the drawings.

[0051] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, an identifying symbol such as "_1", "[n]", or "[m,n]" may be added to the symbol.

[0052] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0053] (Embodiment 1) This embodiment describes an example of the configuration of a semiconductor device that functions as a memory device according to one aspect of the present invention, and an example of a method for manufacturing said semiconductor device. In this embodiment, we deal with a semiconductor device having a cell transistor including a charge storage layer.

[0054] <Example 1 of semiconductor device configuration> The configuration of a semiconductor device having cell transistors CTrA and CTrB will be explained using Figures 1, 2A, and 2B. Figure 1 is a cross-sectional view of the semiconductor device. Figure 2A is a top view of the area indicated by the dashed-dotted line M1-M2 in Figure 1, and Figure 2B is a top view of the area indicated by the dashed-dotted line M3-M4 in Figure 1. Note that in the cross-sectional view of Figure 1, the top view of Figure 2A, and the top view of Figure 2B, some elements have been omitted for clarity.

[0055] In Figure 1, the semiconductor device includes an insulator 411A positioned above a substrate (not shown), an insulator 411B positioned above insulator 411A, and an insulator 411C positioned above insulator 411B.

[0056] The substrate can be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon, semiconductor substrates made of germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0057] Furthermore, a flexible substrate may be used as the substrate. As a method for mounting transistors on a flexible substrate, one method involves fabricating the transistors on a non-flexible substrate, then peeling the transistors off and transferring them to the flexible substrate. In this case, a release layer should be provided between the non-flexible substrate and the transistors. A sheet, film, or foil made of woven fibers may be used as the substrate. The substrate may also be stretchable. The substrate may also have the property of returning to its original shape when bending or stretching is stopped, or it may not return to its original shape. For example, the substrate has a region with a thickness of 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. Making the substrate thinner can reduce the weight of the semiconductor device containing the transistors. Furthermore, making the substrate thinner may result in stretchability even when using glass, or the property of returning to its original shape when bending or stretching is stopped. Therefore, impacts applied to the semiconductor device on the substrate due to drops, etc., can be mitigated. In other words, it is possible to provide a robust semiconductor device.

[0058] Examples of flexible substrates include metals, alloys, resins, glass, or fibers thereof. A flexible substrate is preferable if its coefficient of thermal expansion is low, as this suppresses deformation due to the environment. For example, a flexible substrate with a coefficient of thermal expansion of 1 × 10⁻⁶ is preferable. -3 / K or less, 5×10 -5 / K or less, or 1 × 10 -5 Any material with a coefficient of thermal expansion of 1 / K or less should be used. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. In particular, aramid is suitable as a substrate for flexible substrates because of its low coefficient of thermal expansion.

[0059] In the manufacturing example described in this embodiment, since the process includes heat treatment, it is preferable to use a substrate made of a material with high heat resistance and a low coefficient of thermal expansion.

[0060] Furthermore, in Figures 1, 2A, and 2B, the semiconductor device has a region 491. Region 491 is a region in which an opening is formed during the manufacturing process of the semiconductor device, and an insulator, conductor, semiconductor, etc., are formed in this opening after the manufacturing process of the semiconductor device. For example, the opening can be cylindrical, as shown in Figures 2A and 2B. In Figure 2B, for example, an insulator 412a (insulator 412b, insulator 412c), a conductor 431a (conductor 431b, conductor 431c), a material layer 451a (material layer 451b, material layer 451c), a material layer 452, an insulator 413, and a conductor 432 are arranged in order from the side of the opening in region 491.

[0061] Furthermore, the semiconductor device has region 492A and region 492B. Regions 492A and 492B are regions where openings are formed during the manufacturing process of the semiconductor device, and insulators, conductors, etc., are formed in these openings after the manufacturing process of the semiconductor device. For example, these openings can be slit-shaped openings, as shown in Figures 2A and 2B. Region 492A includes a part of material layer 453, a part of insulator 414, a part of insulator 421, a part of insulator 415, a part of conductor 434a, a part of conductor 434b, and insulator 416A. Region 492B also includes a part of material layer 453, a part of insulator 414, a part of insulator 421, a part of insulator 415, a part of conductor 434a, a part of conductor 434b, and insulator 416B. Furthermore, in Figure 1, a portion of the conductor 434a, a portion of the insulator 414, a portion of the insulator 421, and a portion of the insulator 415 are arranged between the insulator 411A and the insulator 411B. Also, a region of the conductor 434b, a portion of the insulator 414, a portion of the insulator 421, and a portion of the insulator 415 are arranged between the insulator 411B and the insulator 411C.

[0062] Furthermore, the material layer 452 has region 471 and region 472. Region 471 is located adjacent to material layer 453, and region 472 is located adjacent to material layer 451a (material layer 451b, material layer 451c). Region 471 becomes a channel formation region for cell transistor CTrA (cell transistor CTrB) during the manufacturing process of the semiconductor device, and region 472 becomes a low-resistance region during the manufacturing process of the semiconductor device.

[0063] In the cell transistor CTrB, conductor 434b functions as the first gate electrode and a word line that supplies potential to the first gate electrode. In Figure 2A, the insulator 415 surrounded by conductor 434b functions as the gate insulating film, the insulator 421 surrounded by conductor 434b functions as the charge storage layer, and the insulator 414 surrounded by conductor 434b functions as the tunnel insulating film. Conductor 431b functions as either the source electrode or the drain electrode, and conductor 431c functions as the other of the source electrode or the drain electrode. In Figure 2A, the region of material layer 452 surrounded by conductor 434b functions as the channel formation region. Depending on the material contained in material layer 453, the region of material layer 453 in contact with material layer 452 may also function as the channel formation region. Insulator 413 functions as the gate insulating film, and conductor 432 functions as the second gate electrode and wiring that supplies potential to the second gate electrode.

[0064] Furthermore, in Figure 2A, by replacing conductor 434b with conductor 434a, it can be considered a top view of the cell transistor CTrA. In the cell transistor CTrA, conductor 434a functions as the first gate electrode and a word line that supplies potential to the first gate electrode. In Figure 2A, the insulator 415 surrounded by conductor 434a functions as the first gate insulating film. In Figure 2A, the insulator 421 surrounded by conductor 434a functions as a charge storage layer. In Figure 2A, the insulator 414 surrounded by conductor 434a functions as a tunnel insulating film. Conductor 431a functions as either the source electrode or the drain electrode, and conductor 431b functions as the other source electrode or drain electrode. In Figure 2A, the region of material layer 452 surrounded by conductor 434a functions as a channel-forming region. Depending on the material contained in material layer 453, the region of material layer 453 in contact with material layer 452 may also function as a channel-forming region. Furthermore, the insulator 413 functions as a second gate insulating film, and the conductor 432 functions as a second gate electrode and wiring that provides potential to the second gate electrode.

[0065] Insulator 412a, for example, functions as a barrier insulating film that suppresses the diffusion of impurities from insulator 411A (e.g., water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.)) into conductor 431a. In other words, insulator 412a can suppress the influence of these impurities on conductor 431a. Similarly, insulator 412b, for example, functions as a barrier insulating film that suppresses the diffusion of impurities from insulator 411B into conductor 431b, and insulator 412c, for example, functions as a barrier insulating film that suppresses the diffusion of impurities from insulator 411C into conductor 431c.

[0066] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0067] Next, we will describe the material layers 451a (material layers 451b, material layer 451c), material layer 452, and material layer 453 included in cell transistor CTrA and cell transistor CTrB.

[0068] Material layer 451a, for example, functions as a barrier film that suppresses the diffusion of impurities (e.g., water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.)) into material layer 452. By providing material layer 451a, which has the function of suppressing the permeation of impurities, between material layer 452 and conductor 431a, the electrical resistance between material layer 452 and conductor 431a can be reduced. Similarly, material layer 451b, for example, functions as a barrier film that suppresses the diffusion of impurities from material layer 452 into conductor 431b, and material layer 451c, for example, functions as a barrier film that suppresses the diffusion of impurities from material layer 452 into conductor 431c.

[0069] Furthermore, when cell transistors CTrA and CTrB in Figure 1 are OS transistors, it is preferable to use a metal oxide that functions as an oxide semiconductor as material layer 452, and it is preferable to use a material containing the metal elements and oxygen contained in the metal oxide as material layer 451a (material layer 451b, material layer 451c). Also, it is preferable to use a material containing the metal elements and oxygen contained in the metal oxide as material layer 453, similar to material layer 451.

[0070] In addition, when the cell transistors CTrA and CTrB in FIG. 1 are OS transistors, in the material layer 452, the region 471 that functions as a channel formation region has less oxygen deficiency (in this specification, etc., oxygen deficiency in a metal oxide may be referred to as V O (oxygen vacancy).) or a lower impurity concentration than the region 472 that functions as a low-resistance region, resulting in a high-resistance region with a low carrier concentration. Therefore, the region 471 can be said to be of i-type (intrinsic) or substantially i-type.

[0071] In a transistor using a metal oxide, if impurities or oxygen deficiency (V O ) are present in the region where the channel in the metal oxide is formed, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, hydrogen near the oxygen deficiency (V O ) may form a defect in which hydrogen enters the oxygen deficiency (V O ) (hereinafter, may be referred to as V O H.) and generate electrons that serve as carriers. Therefore, if the region where the channel in the oxide semiconductor is formed contains oxygen deficiency, the transistor tends to have normally-on characteristics (characteristics in which a channel exists even without applying a voltage to the gate electrode and current flows through the transistor). Therefore, in the region where the channel in the oxide semiconductor is formed, it is preferable that impurities, oxygen deficiency, and V O H are reduced as much as possible.

[0072] In addition, when the cell transistors CTrA and CTrB in FIG. 1 are OS transistors, the material layer 452 preferably has a plurality of layers including a material layer 452A and a material layer 452B as shown in FIG. 3A. Note that FIG. 3A is an enlarged view of the region where the cell transistor CTrA in FIG. 1 is formed.

[0073] The material layers 451a (material layers 451b, material layer 451c), material layer 452A, material layer 452B, and the material layer 453 formed in a later process can be, for example, one or more materials selected from indium, element M (for example, aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.), and zinc. In particular, metal oxides containing indium, gallium, and zinc have a high band gap and function as intrinsic (also called type I) or substantially intrinsic semiconductors.

[0074] Cell transistors CTrA and CTrB, in which the metal oxide in question is included in the channel-forming region, have a very low off-current characteristic. In other words, the leakage current in cell transistors CTrA and CTrB when they are in the off state can be reduced, which may reduce the power consumption of the semiconductor device.

[0075] For example, a metal oxide containing element M may be used as material layer 451a (material layer 451b, material layer 451c). It is preferable that the concentration of element M in material layer 451a (material layer 451b, material layer 451c) is higher than that in material layer 452B. Alternatively, gallium oxide may be used as material layer 451a (material layer 451b, material layer 451c). Furthermore, a metal oxide such as In (indium)-M-Zn (zinc) oxide may be used as material layer 451a (material layer 451b, material layer 451c). Specifically, it is preferable that the atomic ratio of element M to In in the metal oxide used in material layer 451a (material layer 451b, material layer 451c) is greater than the atomic ratio of element M to In in the metal oxide used in material layer 452B. Furthermore, the film thickness of material layer 451a (material layer 451b, material layer 451c) is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. It is also preferable that material layer 451a (material layer 451b, material layer 451c) is crystalline. When material layer 451a (material layer 451b, material layer 451c) is crystalline, the release of oxygen in material layer 452A and material layer 452B can be suitably suppressed. For example, if material layer 451a (material layer 451b, material layer 451c) has a crystalline structure such as hexagonal, the release of oxygen in material layer 452A and material layer 452B can be suppressed.

[0076] Furthermore, for example, it is preferable that material layer 452A and material layer 452B each be oxides with different chemical compositions. Specifically, it is preferable that the atomic ratio of element M to the main metal element in the metal oxide used in material layer 452B is greater than the atomic ratio of element M to the main metal element in the metal oxide used in material layer 452A. Also, it is preferable that the atomic ratio of element M to In in the metal oxide used in material layer 452B is greater than the atomic ratio of element M to In in the metal oxide used in material layer 452A. Furthermore, material layer 452B may be made with the same composition as material layer 451a (material layer 451b, material layer 451c).

[0077] Furthermore, for example, the atomic ratio of element M to the main metal element in material layer 453 may be greater than the atomic ratio of element M to the main metal element in the metal oxide used in material layer 452A. Also, the atomic ratio of element M to In in the metal oxide used in material layer 453 may be greater than the atomic ratio of element M to In in the metal oxide used in material layer 452A. In addition, the same composition as material layer 452A may be used for material layer 453.

[0078] Furthermore, if the cell transistors CTrA and CTrB in Figure 1 are OS transistors, the material layer 453 may consist of multiple layers, such as material layer 453A and material layer 453B, as shown in Figure 3B. Figure 3B is an enlarged view of the region where the cell transistor CTrA in Figure 1 is formed.

[0079] It is preferable that material layer 453A and material layer 453B each be oxides with different chemical compositions. Specifically, it is preferable that the atomic ratio of element M to the main metal element in the metal oxide used in material layer 453B is greater than the atomic ratio of element M to the main metal element in the metal oxide used in material layer 453A. Furthermore, material layer 453B may be made of the same composition as material layer 451a (material layer 451b, material layer 451c).

[0080] Furthermore, in the cell transistor CTrA shown in Figure 3B, if the material layer 452 has material layer 452A and material layer 452B as shown in Figure 3A, that is, if the material layer 452 has material layer 452A and material layer 452B and the material layer 453 has material layer 453A and material layer 453B as shown in the cell transistor CTrA shown in Figure 3C, then it is preferable that the atomic ratio of element M to the main component metal element in the metal oxide used in material layer 452B is greater than the atomic ratio of element M to the main component metal element in the respective metal oxides used in material layer 452A and material layer 453A. Also, it is preferable that the atomic ratio of element M to the main component metal element in the metal oxide used in material layer 453B is greater than the atomic ratio of element M to the main component metal element in the respective metal oxides used in material layer 452A and material layer 453A. Furthermore, it is preferable that the atomic ratio of element M to the main metal element in the metal oxide used in material layer 451a (material layer 451b, material layer 451c) is greater than the atomic ratio of element M to the main metal element in the respective metal oxides used in material layer 452A and material layer 453A.

[0081] Furthermore, in this case, the compositions of material layer 451a (material layer 451b, material layer 451c), material layer 452B, and material layer 453B may be equal to each other. Also, material layer 453A may have the same composition as material layer 452A.

[0082] Here, we will explain specific examples of atomic ratios of In, Ga, and Zn in the metal oxides contained in material layers 452A, 452B, and 453 of the cell transistor CTrA shown in Figure 3A or Figure 3C, assuming that the metal oxides are metal oxides containing In, gallium (hereinafter referred to as Ga), and zinc (hereinafter referred to as Zn).

[0083] For material layer 452B, as an example, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or In:Ga:Zn=1:1:0.5 may be used. Similarly, for material layer 452A, as an example, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or In:Ga:Zn=1:1:1 may be used. Similarly, for material layer 453, as an example, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 and an atomic ratio of Ga to Zn of Ga:Zn=2:1 or Ga:Zn=2:5 may be used.

[0084] Furthermore, as a specific example of a laminated structure for material layer 453 as shown in Figure 3C, material layer 453A may use a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or close to it, and material layer 453B may use a metal oxide with an atomic ratio of In:Ga:Zn=1:3:4 or close to it. Alternatively, material layer 453A may use a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or close to it, and material layer 453B may use a metal oxide with an atomic ratio of Ga and Zn of Ga:Zn=2:1 or close to it. Alternatively, material layer 453A may use a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or close to it, and material layer 453B may use a metal oxide with an atomic ratio of Ga and Zn of Ga:Zn=2:5 or close to it. Alternatively, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 4:2:3 or close to it may be used for material layer 453A, and gallium oxide may be used for material layer 453B.

[0085] Furthermore, for example, if the atomic ratio of In to element M in the metal oxide used in material layer 452B is smaller than the atomic ratio of In to element M in the metal oxide used in material layer 452A, then an In-Ga-Zn oxide with an atomic ratio of In, Ga, and Zn such as In:Ga:Zn=5:1:6 or nearby, In:Ga:Zn=5:1:3 or nearby, or In:Ga:Zn=10:1:3 or nearby can be used as material layer 452A.

[0086] In addition to the compositions mentioned above, the material layer 452A can be made of a metal oxide having, for example, a composition of In:Zn=2:1, In:Zn=5:1, In:Zn=10:1, or a composition close to any one of these. Alternatively, the material layer 452A can be made of, for example, indium oxide.

[0087] It is preferable to combine these material layers 451a (material layers 451b, material layer 451c), material layer 452A, material layer 452B, and material layer 453 (material layer 453A, material layer 453B) in a manner that satisfies the above-mentioned atomic ratio relationship. For example, in the case of the cell transistor CTrA in Figure 3A, it is preferable that material layers 452B and 453 be metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to it, and material layer 452A be a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition close to it. Furthermore, for example, in the case of the cell transistor CTrA in Figure 3C, it is preferable that material layers 452B and 453B be metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to it, and material layer 452A be a metal oxide having a composition of In:Ga:Zn=4:2:z where z is between 3 and 4.1 or close to it. Note that the above composition refers to the atomic ratio in the oxide formed on the substrate or the atomic ratio in the sputtering target. In addition, increasing the ratio of In in the composition of material layer 452A is preferable because it can increase the on-current or field-effect mobility of the transistor.

[0088] By the way, the composition of an oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=a:b:c (a+b+c=1) is said to be in the vicinity of the composition of an oxide with an atomic ratio of In:Ga:Zn=A:B:C (A+B+C=1) if a, b, and c are (aA) 2 +(bB) 2 +(cC) 2 ≤r 2This means that the following conditions are met, and r can be, for example, 0.20, preferably 0.10, and more preferably 0.05.

[0089] Under these conditions, by positioning material layer 452A in contact with material layer 452B, the diffusion of impurities and oxygen from the insulator 413 and / or conductor 432 to material layer 452A via material layer 452B can be suppressed. Similarly, by positioning material layer 453B in contact with material layer 452B, the diffusion of impurities and oxygen from the insulator 414, insulator 421, insulator 415, conductor 434a (conductor 434b), insulator 416A, etc., to material layer 453A and material layer 452A via material layer 453B can be suppressed. Similarly, by arranging material layer 451a (material layer 451b, material layer 451c) in contact with material layer 452A, it is possible to suppress the diffusion of impurities and oxygen from conductors 431a (conductors 431b, conductors 431c), insulators 412a (insulators 412b, insulators 412c), insulators 411A (insulators 411B, insulators 411C), etc., into material layer 452A via material layer 451a (material layer 451b, material layer 451c).

[0090] Furthermore, when applying transistors containing silicon in the channel formation region (hereinafter referred to as Si transistors) as cell transistors CTrA and CTrB in Figure 1, the material layer 452 can be, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or single-crystal silicon.

[0091] Furthermore, when Si transistors are applied to cell transistors CTrA and CTrB, the material layer 452 may consist of multiple layers or a single layer, as shown in Figures 3A and 3C. In the fabrication examples described herein, the material layer 452 is described as a single layer.

[0092] Furthermore, the material applicable to material layer 453 can be a metal oxide applicable to material layer 451 and / or material layer 452, or a material that functions as a tunnel insulating film, for example, a material applicable to the insulator 414 which will be described in detail later. Note that material layer 453 may consist of multiple layers or a single layer, as shown in Figures 3B and 3C.

[0093] When cell transistors CTrA and CTrB are Si transistors, it is preferable that the material layer 451 is a conductor containing impurities (elements or ions) to diffuse into the interface of material layer 452 on the formation surface of material layer 451 and the region near the interface.

[0094] The conductor can be made from a material containing one or more metallic elements selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and others.

[0095] Furthermore, when cell transistors CTrA and CTrB are configured as n-type transistors, n-type impurities (donors) are used. Examples of n-type impurities include phosphorus and arsenic. Also, in this example of a fabrication method, when cell transistors CTrA and CTrB are configured as p-type transistors, p-type impurities (acceptors) are used. Examples of p-type impurities include boron, aluminum, and gallium.

[0096] Furthermore, the material layer 451 may be a material capable of forming silicides at, for example, the interface of the material layer 452 on the forming surface of the material layer 451, and in the region near the interface. Examples of materials capable of forming silicides include nickel, cobalt, molybdenum, tungsten, and titanium.

[0097] Although Figures 1, 2A, and 2B show a configuration in which one region 491 is provided between region 492A and region 492B, one aspect of the present invention is not limited to this. For example, one aspect of the present invention may be a configuration in which multiple regions 491 are provided between region 492A and region 492B.

[0098] A specific example of this configuration is shown in Figure 4A. Figure 4A shows a top view of a semiconductor device in which multiple regions 491 are provided. This top view is an unfolded view of the semiconductor device shown in Figure 1 along the dashed line M3-M4, in which multiple regions 491 are provided. The semiconductor device shown in Figure 4A has multiple regions 492 in a slit shape, with multiple regions 491 provided between adjacent regions 492. As for the arrangement of the multiple regions 491, for example, the regions 491 may be arranged in a single row in a direction that is at an angle to the slit-shaped regions 492. Alternatively, the multiple regions 491 may be arranged in a staggered pattern. Note that the regions 492 may not be slit-shaped, but instead, for example, cylindrical. Figure 4B shows a configuration in which a cylindrical opening is provided in region 494 instead of a slit-shaped opening formed in region 492, and a material layer 453 and insulators 414 to 416 are formed in region 494. Furthermore, the shape of region 494 is not limited to a cylindrical shape; it may be a columnar shape with any two-dimensional shape, such as an ellipse or polygon, as its base. Also, the position of region 494 may be arranged along two or more different rows, rather than along a single row as region 492 in Figure 4A. Alternatively, the position of region 494 may be formed without following the above-mentioned regularity.

[0099] <<Example of semiconductor device fabrication 1>> Next, we will describe an example of a method for manufacturing the semiconductor device shown in Figures 1, 2A, and 2B.

[0100] First, a laminate 400 shown in Figure 5A is fabricated. The laminate 400, as an example, includes an insulator 411A, a sacrificial layer 401A, an insulator 411B, another sacrificial layer 401B, and an insulator 411C. The insulator 411A is placed on top of a substrate (not shown), the sacrificial layer 401A is placed on top of the insulator 411A, the insulator 411B is placed on top of the sacrificial layer 401A, the sacrificial layer 401B is placed on top of the insulator 411B, and the insulator 411C is placed on top of the sacrificial layer 401B.

[0101] Various materials can be used for sacrificial layers 401A and 401B. For example, silicon nitride, silicon oxide, aluminum oxide, etc. may be used as insulators. Alternatively, silicon, gallium, germanium, etc. may be used as semiconductors. Alternatively, aluminum, copper, titanium, tungsten, tantalum, etc. may be used as conductors. In other words, for sacrificial layers 401A and 401B, materials that can achieve a suitable etching selectivity ratio with the materials used in other parts should be used.

[0102] It is preferable that the insulators 411A to 411C are materials in which the concentration of impurities such as water or hydrogen has been reduced. For example, the amount of hydrogen desorbed from insulators 411A to 411C can be determined by thermal desorption spectroscopy (TDS) in the range of 50°C to 500°C, and the amount of desorption converted to hydrogen molecules can be converted to 2 × 10⁻¹⁰ per unit area of ​​any one of the insulators 411A to 411C. 15 molecular / cm² 2 The following is preferably 1 × 10 15 molecular / cm² 2 The following is more preferable: 5 x 10 14 molecular / cm² 2 The following conditions are acceptable. In addition, insulators 411A to 411C may be formed using an insulator that releases oxygen upon heating. However, the materials applicable to insulators 411A to 411C are not limited to those described above.

[0103] As insulators 411A to 411C, for example, an insulator containing one or more materials selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc. may be used in a single layer or in a multilayer structure. In addition, for example, a material containing silicon oxide or silicon oxynitride may be used. However, the materials applicable to insulators 411A to 411C are not limited to those described above.

[0104] In this specification, silicon oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride refers to a material in which the nitrogen content is greater than the oxygen content. Furthermore, in this specification, aluminum oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and aluminum nitride refers to a material in which the nitrogen content is greater than the oxygen content.

[0105] In the next step, as shown in Figure 5B, an opening is formed in region 491 of the laminate 400 shown in Figure 5A, for example, by resist mask formation and etching.

[0106] The resist mask can be formed using methods such as lithography, printing, or inkjet printing, as appropriate. Forming the resist mask using inkjet printing eliminates the need for a photomask, which can sometimes reduce manufacturing costs. Furthermore, the etching process can be performed using either dry etching or wet etching, or both.

[0107] Next, as shown in Figure 6A, an insulator 412 is formed on the side surface of the opening in region 491 so as to cover insulators 411A to 411C, sacrificial layer 401A, and sacrificial layer 401B.

[0108] Insulator 412 functions as a film for forming insulators 412a, 412b, and 412c in Figure 1 in a later step. Therefore, in this specification, the description of insulator 412 may be replaced with insulators 412a, 412b, and 412c as appropriate.

[0109] As described above, it is preferable that insulator 412 functions as a barrier insulating film that suppresses the diffusion of impurities (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.)) from insulator 411A (insulator 411B, insulator 411C) into material layer 452. In particular, it is preferable that insulator 412 be a barrier insulating film that prevents the permeation of oxygen atoms or oxygen molecules.

[0110] As the insulator 412, for example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. In particular, when an oxide semiconductor described later is used as the material layer 452, it is preferable to use aluminum oxide or the like as the insulator 412, which has high hydrogen capture and hydrogen fixation capabilities. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the insulator 411A (insulator 411B, insulator 411C) side to the material layer 452 via the conductor 431a (conductor 431b, conductor 431c) and material layer 451a (material layer 451b, material layer 451c).

[0111] Furthermore, although the insulator 412 is shown as a single layer in Figures 1, 2B, and 6A, the present invention is not limited to this. The insulator 412 shown in Figures 1, 2B, and 6A may be constructed by laminating multiple layers of the materials described above. For example, in Figures 1 and 2B, silicon oxide may be used for the insulator 412 in contact with the conductor 431a (conductor 431b, conductor 431c), and aluminum oxide or hafnium oxide may be used for the insulator 412 in contact with the insulator 411A (insulator 411B, insulator 411C).

[0112] Next, as shown in Figure 6B, a conductive film 431 is formed on the surface of the insulator 412.

[0113] Conductor 431 functions as a film for forming conductors 431a, 431b, and 431c in Figure 1 in a later step. Therefore, in this specification, the description of conductor 431 can be appropriately replaced with conductors 431a, 431b, and 431c.

[0114] Furthermore, as described above, since the conductor 431 functions as a film for forming conductors 431a, 431b, and 431c, the conductor 431 becomes the source electrode and drain electrode of cell transistors CTrA and CTrB, respectively, in a later process.

[0115] The conductor 431 is preferably a material with high conductivity. For example, the conductor 431 is preferably a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even after absorbing oxygen.

[0116] Furthermore, in particular when using an oxide semiconductor as the material layer 452, it is preferable to use a conductive material as the conductor 431 that has the function of suppressing the permeation of impurities such as water or hydrogen. In this case, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide as the conductor 431.

[0117] Furthermore, although the conductor 431 is shown as a single layer in Figures 1, 2B, and 6, the present invention is not limited to this. The conductor 431 shown in Figures 1, 2B, and 6 may, for example, be configured by laminating multiple layers of the materials described above. Specifically, for example, the conductor 431 may be configured by using a conductive material having the function of suppressing the permeation of impurities such as water or hydrogen in the first layer, and a conductive material that is resistant to oxidation, or a material that maintains conductivity even when absorbing oxygen, in the second layer.

[0118] Then, as shown in Figure 7A, a material layer 451 is formed on the surface where the conductor 431 is formed.

[0119] Material layer 451 functions as a film for forming material layers 451a, 451b, and 451c in Figure 1 in a later process. Therefore, in this specification, the description of material layer 451 can be appropriately replaced with material layers 451a, 451b, and 451c.

[0120] By forming a material layer 451 in contact with the surface of the conductor 431, a low-resistance region may be formed near the interface between the material layer 451 and the conductor 431. Furthermore, by applying heat treatment at this time, a compound may be formed between the components contained in the material layer 451 and the components contained in the conductor 431. In this fabrication example, it is assumed that appropriate materials have been selected for both the conductor 431 and the material layer 451 so that the compound has low resistance.

[0121] Regarding the materials applicable to material layer 451, please refer to the description of material layer 451a (material layer 451b, material layer 451c) in semiconductor device configuration example 1.

[0122] Next, as shown in Figure 7B, a material layer 452 is formed on the surface where the material layer 451 is formed.

[0123] As described above, a portion of the material layer 452 functions as the channel formation region for cell transistors CTrA and CTrB in Figure 1.

[0124] Regarding the materials applicable to material layer 452, please refer to the explanation in Semiconductor Device Configuration Example 1.

[0125] Next, as shown in Figure 8A, an insulator 413 is formed on the formation surface of the material layer 452.

[0126] As described above, the insulator 413 functions as the second gate insulating film for cell transistor CTrA and cell transistor CTrB, respectively, in Figure 1.

[0127] For the insulator 413, it is preferable to use, for example, silicon oxide or silicon oxynitride. Alternatively, for the insulator 413, for example, aluminum oxide, hafnium oxide, or an oxide having aluminum and hafnium can be used.

[0128] Furthermore, it is preferable that the insulator 413 functions as a barrier insulating film that suppresses the permeation of impurities (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrous oxide molecules (N2O, NO, NO2, etc.)), similar to the insulator 412.

[0129] Therefore, when cell transistors CTrA and CTrB in Figure 1 are OS transistors, that is, when a metal oxide that functions as an oxide semiconductor is used as the material layer 452, it is preferable to use an insulating material that has the function of suppressing oxygen permeation as the insulator 413. For example, it is preferable to use silicon nitride, silicon oxide nitride, silicon oxynitride, aluminum nitride, or aluminum oxide nitride as the insulator 413. By forming such an insulator 413, it is possible to prevent oxygen from detaching from the material layer 452 and diffusing into the insulator 413. This prevents the material layer 452 from becoming less resistive due to the detachment of oxygen from the material layer 452.

[0130] Furthermore, it is preferable to use an insulating material as the insulator 412 that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, aluminum oxide can be used as the insulator 412. However, the materials that can be applied to the insulator 412 are not limited to those described above, and as the insulator 412, for example, materials that can be applied to the above-described insulators 411A to 411C can be used as a film in which the concentration of impurities such as water and hydrogen has been reduced.

[0131] Furthermore, although the insulator 413 is shown as a single layer in Figures 1, 2B, and 8A, the present invention is not limited to this. The insulator 413 shown in Figures 1, 2B, and 8A may be configured by laminating multiple layers of the materials described above. For example, in Figures 1 and 2B, silicon oxide may be used for the insulator 412 in contact with the material layer 452, and aluminum oxide or hafnium oxide may be used for the insulator 412 in contact with the conductor 432.

[0132] In particular, consider the case where a metal oxide that functions as an oxide semiconductor is used as the material layer 452. For example, by depositing aluminum oxide by sputtering, oxygen is supplied to the insulator 413, and the oxygen supplied to the insulator 413 is supplied to the material layer 452. As oxygen is supplied to the material layer 452, the amount of oxygen contained in the oxide semiconductor increases, which prevents the oxide semiconductor from becoming less resistive.

[0133] Then, as shown in Figure 8B, the conductor 432 is formed on the surface of the insulator 413 so as to fill the remaining openings in region 491.

[0134] As described above, the conductor 432 functions as the second gate electrode of cell transistor CTrA and cell transistor CTrB, respectively, and as wiring that supplies potential to the second gate electrode in Figure 1.

[0135] As the conductor 432, for example, a material containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. In addition, as the conductor 432, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.

[0136] Furthermore, as the conductor 432, for example, a conductive material containing metal elements and oxygen included in a metal oxide applicable to the material layer 451 or material layer 452 may be used. Alternatively, a conductive material containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride can be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-added indium tin oxide can be used. In addition, indium gallium zinc oxide containing nitrogen can be used. By using such materials, it may be possible to capture hydrogen introduced from surrounding insulators, etc.

[0137] Furthermore, it is preferable to use a conductive material as the conductor 432 that has the function of suppressing the permeation of impurities such as water or hydrogen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide, and it may be in the form of a single layer or a laminate.

[0138] Furthermore, the conductor 432 may be a structure in which multiple of the above-mentioned materials are stacked. For example, it may be a stacked structure combining the aforementioned material containing a metal element and a conductive material containing oxygen. Alternatively, it may be a stacked structure combining the aforementioned material containing a metal element and a conductive material containing nitrogen. Alternatively, it may be a stacked structure combining the aforementioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen. Furthermore, by applying an insulator having an excess oxygen region as an insulator in contact with the periphery of the conductor, oxygen may diffuse in the region of the conductor in contact with the insulator. This may allow for the formation of a stacked structure combining the material containing a metal element and a conductive material containing oxygen. Similarly, by applying an insulator having an excess nitrogen region as an insulator in contact with the periphery of the conductor, nitrogen may diffuse in the region of the conductor in contact with the insulator. This may allow for the formation of a stacked structure combining the material containing a metal element and a conductive material containing nitrogen.

[0139] In the next step, as shown in Figure 9A, slit-shaped openings are formed in regions 492A and 492B by, for example, forming a resist mask and etching the laminate 400. In this step, the openings in regions 492A and 492B are described as slit-shaped, but as shown in Figure 4B, the openings in regions 492A and 492B may be cylindrical.

[0140] For details on resist mask formation, etching, etc., please refer to the explanation in Figure 5B.

[0141] Then, in the process shown in Figure 9B, the sacrificial layers 401A and 401B are removed from the sides of the openings formed in regions 492A and 492B using etching or the like, and the regions of the insulator 412, conductor 431 and material layer 451 surrounded by the sacrificial layer 401A, and the regions of the insulator 412, conductor 431 and material layer 451 surrounded by the sacrificial layer 401B are removed, forming recesses 493A and 493B in the laminate 400. In addition, as a result, insulator 412a (insulator 412b, insulator 412c), conductor 431a (conductor 431b, conductor 431c), and material layer 451a (material layer 451b, material layer 451c) are formed in the region overlapping with region 472 of the material layer 452.

[0142] Furthermore, recesses 493A and 493B may be formed together with the openings of regions 492A and 492B during the semiconductor device manufacturing process shown in Figure 9A. Also, the etching conditions and other factors may differ between the process of removing sacrificial layers 401A and 401B, a portion of the insulator 412, a portion of the conductor 431, and a portion of the material layer 451c. Therefore, in the process shown in Figure 9B, the etching conditions and other factors may be changed depending on the material to be removed.

[0143] Incidentally, when a material having a metal oxide is used as the material layer 452, that is, when the cell transistors CTrA and CTrB in Figure 1 are OS transistors, after the formation of the respective openings 492A and 492B, recesses 493A and 493B, a process may be performed to supply oxygen to the region 471 of the material layer 452 exposed to the recesses 493A and 493B from the respective openings of region 492A and 492B. In this case, Figure 10A shows the process 10, in which oxygen is supplied to region 471. Examples of processes for supplying oxygen include heat treatment in an oxygen atmosphere.

[0144] Furthermore, as the oxygen supply process 10, for example, microwave processing can be performed in an oxygen-containing atmosphere. In this case, microwaves, high-frequency waves such as RF, oxygen plasma, oxygen radicals, etc., are irradiated onto region 471. For microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating high-density plasma using microwaves. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. Also, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided to the material layer 452. Furthermore, the above microwave processing is preferably performed under reduced pressure, with a pressure of 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. Furthermore, the oxygen flow rate ratio (O2 / O2+Ar) should be 50% or less, preferably 10% to 30%. Furthermore, the processing temperature should be 750°C or less, preferably 500°C or less, for example, around 400°C. Alternatively, after oxygen plasma treatment, heat treatment may be performed continuously without exposure to the outside air.

[0145] As the oxygen supply process 10, by performing microwave processing in an oxygen-containing atmosphere, the oxygen gas is converted into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied to region 471 of the material layer 452 (material layer 452A when the configuration of cell transistors CTrA and CTrB is as shown in Figures 3A and 3C). At this time, microwaves or high-frequency waves such as RF can also be irradiated onto region 471. In other words, microwaves or high-frequency waves such as RF, oxygen plasma, etc., can be applied to region 472 shown in Figure 10A. Due to the action of plasma, microwaves, etc., the V of region 471 O H can be separated and hydrogen H can be removed from region 471. In other words, in region 471, "V O H → H + V O )」, and furthermore, "V O The reaction "+O→null" occurs, which can reduce the hydrogen concentration in region 471. Therefore, the oxygen deficiency in region 471, and VO This can reduce H and lower the carrier concentration.

[0146] On the other hand, in region 472 shown in Figure 10A, conductors 431a (conductors 431b, conductors 431c) are arranged so as to be superimposed. Conductors 431a (conductors 431b, conductors 431c) shield against the effects of microwaves, high-frequency waves such as RF, oxygen plasma, etc., so these effects do not extend to region 472. As a result, microwave processing does not affect region 472. O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration.

[0147] In this way, oxygen vacancies in region 471 of material layer 452 and V O By removing H, region 471 can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to region 472, which functions as a source or drain region, can be suppressed, thereby maintaining n-type configuration. This suppresses variations in the electrical properties of cell transistors CTrA and CTrB, and reduces variations in the electrical properties of cell transistors within the semiconductor device.

[0148] Furthermore, when a material containing silicon is used as the material layer 452, that is, when the cell transistors CTrA and CTrB in Figure 1 are Si transistors, after the formation of the openings 493A and 492B, recesses 493A and 493B, respectively, an impurity may be supplied to the region 471 of the material layer 452 exposed to the recesses 493A and 493B from the openings 492A and 492B, respectively. In this case, Figure 9A shows the process 10 in which impurities are supplied to the material layer 452 exposed to the recesses 493A and 493B. It is preferable to perform heat treatment on the semiconductor device while process 10 is being carried out. When the cell transistors CTrA and CTrB are n-type transistors, p-type impurities (acceptors) are used as impurities in order to make region 471 a p-type channel formation region. Examples of p-type impurities include boron, aluminum, and gallium. Furthermore, when the cell transistor CTr is a p-type transistor, an n-type impurity (donor) is used as an impurity to make region 471 an n-type channel formation region. Examples of n-type impurities include phosphorus and arsenic.

[0149] Furthermore, in material layer 452, the region not exposed to recesses 493A and 493B, that is, the region 472 in contact with material layers 451a, 451b, and 451c, may have lower resistance than region 471. This is because, for example, a low-resistance compound may be formed by the components contained in conductor 431a (conductor 431b, conductor 431c) and the components of material layer 452 near the interface with material layer 451a (material layer 451b, material layer 451c). Alternatively, the resistance of region 471 becomes higher than that of region 472 due to the process 10. For this reason, region 472 functions as a low-resistance region of cell transistor CTrA and cell transistor CTrB.

[0150] Furthermore, as described above, in the process of supplying oxygen and impurities to the material layer 452, instead of supplying them from the respective openings of region 492A and region 492B, oxygen may be supplied from the terminal outlet as shown in Figure 10B. Alternatively, the process of supplying oxygen to the material layer 452 may be a combination of supplying oxygen from the respective openings of region 492A and region 492B as shown in Figure 10A and supplying oxygen from the terminal outlet as shown in Figure 10B. Note that Figure 10B is a perspective view of the structure shown in Figure 10A.

[0151] In the next step, as shown in Figure 11A, a material layer 453 is formed on the sides of the openings in regions 492A and 492B shown in Figure 9B (the respective sides of insulators 411A to 411C), recesses 493A and 493B.

[0152] When a material having a metal oxide is used as material layer 452, that is, when cell transistors CTrA and CTrB in Figure 1 are OS transistors, it is preferable that the material applicable to material layer 453 be a metal oxide applicable to material layer 451 and / or material layer 452. The description of material layer 451 and material layer 452 formed in the processes shown in Figures 7A and 7B should be considered when determining the metal oxide.

[0153] Furthermore, the material layer 453 may have a configuration in which multiple metal oxides applicable to material layer 451 and / or material layer 452 are stacked.

[0154] Furthermore, after forming the material layer 453, as a process 10, oxygen may be supplied to the material layer 453 and the region of the material layer 452 in contact with the material layer 453 using microwave processing or the like, similar to the steps shown in Figures 10A and 10B (not shown).

[0155] Furthermore, when a material containing silicon is used as the material layer 452, that is, when the cell transistors CTrA and CTrB in Figure 1 are Si transistors, the material that can be applied to the material layer 453 can be a metal oxide that can be applied to the material layer 451 and / or the material layer 452, or a material that can be applied to the insulator 414 described later.

[0156] In Figure 11A, the thicknesses of material layer 453 and material layer 451c are shown to be equal, but the semiconductor device according to one aspect of the present invention is not limited to this. The thickness of material layer 453 may be thicker or thinner than the thickness of material layer 451c.

[0157] In the next step, as shown in Figure 11B, an insulator 414 is formed on the sides of the openings in regions 492A and 492B shown in Figure 11A, and in the recesses that are formed. In other words, an insulator 414 is formed on the formation surface of the material layer 453.

[0158] As mentioned above, insulator 414 functions as a tunnel insulating film for cell transistors CTrA and CTrB.

[0159] Preferably, the insulator 414 is silicon oxide or silicon oxynitride. Alternatively, the insulator 414 may be aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium. Furthermore, the insulator 414 may be an insulator formed by laminating these materials.

[0160] Furthermore, after forming the insulator 414, as a process 10, oxygen may be supplied to the material layer 453 and the region of the material layer 452 in contact with the material layer 453 via the insulator 414 using microwave processing or the like, similar to the steps shown in Figures 10A and 10B (not shown).

[0161] Furthermore, if at least one of the material layers 451 to 453 is a material containing a metal oxide, the insulator 414 can be an insulator formed by laminating a material applicable to the insulator 413 onto the aforementioned material. In particular, by using a material that has the function of suppressing the permeation of impurities such as oxygen, water, and hydrogen as the insulator 414, it may be possible to prevent the diffusion of water or hydrogen into the material layers 451 to 453 and the desorption of oxygen from the material layers 451 to 453. When microwave treatment is performed as the treatment 10, for example, silicon oxide or silicon oxynitride can be formed on the formation surface of the material layer 453, then the microwave treatment can be performed, and then a material that has the function of suppressing the permeation of impurities such as oxygen, water, and hydrogen can be formed to create the insulator 414.

[0162] In the next step, as shown in Figure 12A, an insulator 421 is formed on the sides of the openings in regions 492A and 492B shown in Figure 11B, and in the recesses that are formed. In other words, an insulator 421 is formed on the surface on which the insulator 414 is formed.

[0163] As mentioned above, the insulator 421 functions as a charge storage layer for cell transistors CTrA and CTrB.

[0164] For example, silicon nitride or silicon nitride oxide can be used as the insulator 421. However, the materials that can be applied to the insulator 421 are not limited to these. Conductors, semiconductors, etc., can sometimes be used as alternatives to the insulator 421.

[0165] In Figure 12A, the film thickness of the insulator 421 is shown in substantially the same way as the film thicknesses of the material layer 451a (material layer 451b, material layer 451c), the conductor 431a (conductor 431b, conductor 431c), and the insulator 412a (insulator 412b, insulator 412c), but the semiconductor device according to one aspect of the present invention is not limited thereto. The film thickness of the insulator 421 to fill a portion of each of the recesses 493A and 493B may be made thicker, as long as the insulator 415 and the conductors 434a and conductor 434b are formed in the recesses 493A and 493B in a later process. Also, the film thickness of the insulator 421 may be made thinner, as long as the insulator 421 functions as a charge storage layer.

[0166] In the next step, as shown in Figure 12B, an insulator 415 is formed on the sides of the openings in regions 492A and 492B shown in Figure 12A, and in the recesses that are formed. In other words, an insulator 415 is formed on the surface on which the insulator 421 is formed.

[0167] As mentioned above, insulator 415 functions as a gate insulating film for cell transistors CTrA and CTrB.

[0168] For the insulator 415, it is preferable to use, for example, silicon oxide or silicon oxynitride. Alternatively, for the insulator 415, for example, aluminum oxide, hafnium oxide, or an oxide having aluminum and hafnium can be used. Furthermore, the insulator 415 may be an insulator formed by laminating these materials. It is preferable that the insulator 415 is thicker than the insulator 414. By making the insulator 415 thicker than the insulator 414, charge can be transferred from the material layer 453 to the insulator 421 via the insulator 414.

[0169] In the next step, as shown in Figure 13A, a conductive film 434 is formed on the sides of the openings in regions 492A and 492B shown in Figure 12B, and in the recesses that are formed. In other words, a conductive film 434 is formed on the surface on which the insulator 415 is formed.

[0170] For example, the conductor 434 can be a material that can be applied to the aforementioned conductor 432.

[0171] In the next step, as shown in Figure 13B, the conductor 434 contained in regions 492A and 492B is removed by resist mask formation and etching, etc., so that the conductor 434 remains only in the aforementioned recesses. This forms conductors 434a and 434b. At this time, the exposed portion of the insulator 415 may also be removed.

[0172] For details on resist mask formation, etching, etc., please refer to the explanation in Figure 5B.

[0173] As described above, conductor 434a functions as the gate electrode of cell transistor CTrA and as a word line that supplies potential to said gate electrode. Similarly, as described above, conductor 434b functions as the gate electrode of cell transistor CTrB and as a word line that supplies potential to said gate electrode.

[0174] In the next step, as shown in Figure 1A, an insulator 416A is formed so as to fill the opening in region 492A, and an insulator 416B is formed so as to fill the opening in region 492B.

[0175] For example, the insulators 416A and 416B can be made from materials that are applicable to the insulator 413 described above.

[0176] By performing the steps described above, the semiconductor device shown in Figure 1A can be manufactured.

[0177] <Example of semiconductor device configuration 2> An example of a semiconductor device configuration that functions as a memory device according to one aspect of the present invention is not limited to the configurations shown in Figures 1, 2A, and 2B. Depending on the circumstances, the configuration of the semiconductor device may be a circuit configuration that is appropriately modified from Figures 1, 2A, and 2B as needed.

[0178] For example, the configurations of the semiconductor devices shown in Figures 1, 2A, and 2B may be changed to the configurations shown in Figures 14A, 15A, and 15B. Figure 14A is a cross-sectional view of a semiconductor device different from the configurations of Figures 1, 2A, and 2B. Figure 15A is a top view of the area along the dashed-dotted line N1-N2 shown in Figure 14, and Figure 15B is a top view of the area along the dashed-dotted line N3-N4 shown in Figure 14. Note that in the cross-sectional view of Figure 14, the top view of Figure 15A, and the top view of Figure 15B, some elements have been omitted for clarity.

[0179] In the semiconductor devices shown in Figures 14A, 15A, and 15B, the process shown in Figure 14B is performed instead of the process shown in Figure 9B, and a portion of the material layer 452 is removed by etching or the like to such an extent that the insulator 413 is not exposed in the recesses 493A and 493B. Thus, in a semiconductor device according to one aspect of the present invention, the thickness of the material layer 452 may differ between the region 471 of the material layer 452 in which the recesses 493A and 493B are formed and the region 472 of the material layer 452 superimposed on the conductor 431a (conductor 431b, conductor 431c).

[0180] <Example 3 of semiconductor device configuration> Furthermore, for example, the configurations of the semiconductor devices in Figures 1, 2A, and 2B may be changed to the configurations of the semiconductor devices shown in Figures 16, 17A, and 17B. Figure 16 is a cross-sectional view of a semiconductor device different from the configurations of the semiconductor devices in Figures 1, 2A, and 2B. Figure 17A is a top view of the area indicated by the dashed-dotted line P1-P2 in Figure 16, and Figure 17B is a top view of the area indicated by the dashed-dotted line P3-P4 in Figure 16. Note that in the cross-sectional view of Figure 16, the top view of Figure 17A, and the top view of Figure 17B, some elements have been omitted for clarity.

[0181] The semiconductor devices in Figures 16, 17A, and 17B are configured such that, after the process shown in Figure 13B, a resist mask is formed and etching is performed to remove the material layer 453, insulator 414, insulator 421, insulator 415, and conductor 434 contained in regions 492A and 492B. Then, an insulator 416A is deposited so as to fill the opening in region 492A, and an insulator 416B is deposited so as to fill the opening in region 492B.

[0182] In other words, the semiconductor devices in Figures 16, 17A, and 17B are configured such that, after the process shown in Figure 13B, the insulators 414, 421, 415, and material layer 453 are removed to the extent that the conductors 434a and 434b remain. At this time, a portion of the insulators 411A to 411C may also be removed. In Figure 16, the material layer 453a, insulators 414a, 421a, 415a, and conductor 434a are formed in recess 493A, and the material layer 453b, insulators 414b, 421b, 415b, and conductor 434b are formed in recess 493B.

[0183] Furthermore, the etching process after the steps shown in Figure 13B may be stopped until a portion of the insulator 415 is removed and the insulator 414 is exposed at the opening of region 492A, or until a portion of the insulator 414 is removed and the material layer 453 is exposed at the opening of region 492A, thereby forming the insulators 416A and 416B shown in Figure 1 on the sides of the respective openings of region 492A and region 492B (not shown).

[0184] For details on resist mask formation, etching, etc., please refer to the explanation in Figure 5B.

[0185] <Example of semiconductor device configuration 4> Furthermore, for example, the configuration of the semiconductor device shown in Figures 1, 2A, and 2B may be changed to the configuration of the semiconductor device shown in Figures 18, 19A, and 19B. Figure 18 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device shown in Figures 1, 2A, and 2B. Figure 19A is a top view of the area Q1-Q2 shown by the dashed-dotted line in Figure 18, and Figure 19B is a top view of the area Q3-Q4 shown by the dashed-dotted line in Figure 18. Note that in the cross-sectional view of Figure 18, the top view of Figure 19A, and the top view of Figure 19B, some elements have been omitted for clarity.

[0186] The semiconductor devices shown in Figures 18, 19A, and 19B are configured such that the process from Figure 11B onward is performed without performing the step of forming the material layer 453 shown in Figure 11A, as shown in Figure 9B or Figure 10A. If the insulator 414 functions sufficiently as a barrier insulating film to prevent the diffusion of impurities into the material layer 452, the material layer 453 does not need to be provided. In this case, since it is not necessary to provide the material layer 453, the process of manufacturing the semiconductor device can be shortened.

[0187] <Example of semiconductor device configuration 5> Furthermore, for example, the configurations of the semiconductor devices shown in Figures 1, 2A, and 2B may be changed to the configurations shown in Figures 20 and 21. Figure 20 is a cross-sectional view of a semiconductor device with a configuration different from that of Figures 1, 2A, and 2B. Figure 21 is a top view of the area indicated by the dashed-dotted line R3-R4 in Figure 20. Note that the top view of the area indicated by the dashed-dotted line R1-R2 in Figure 20 may have a configuration that is almost the same as that of Figure 2A. Note that in the cross-sectional view of Figure 20 and the top view of Figure 21, some elements have been omitted for clarity.

[0188] The semiconductor devices in Figures 20 and 21 are configured such that the process shown in Figure 6B does not involve the process of forming the material layer 451 shown in Figure 7A, but rather the process from Figure 7B onward. If the components and impurities contained in the material layer 452 do not diffuse into the conductor 431a (conductor 431b, conductor 431c) and the conductivity of the conductor 431a (conductor 431b, conductor 431c) does not decrease, then it is not necessary to provide the material layer 451 which functions as a barrier film for the components and impurities. In this case, since it is not necessary to provide the material layer 451, the process for manufacturing the semiconductor device can be shortened.

[0189] <Semiconductor device configuration example 6> Furthermore, for example, the configurations of the semiconductor devices shown in Figures 1, 2A, and 2B may be changed to the configurations shown in Figures 22 and 23. Figure 22 is a cross-sectional view of a semiconductor device with a configuration different from that of Figures 1, 2A, and 2B. Figure 23 is a top view of the area indicated by the dashed-dotted line S3-S4 in Figure 22. Note that the top view of the area indicated by the dashed-dotted line S1-S2 in Figure 22 may have a configuration that is almost the same as that of Figure 2A. Note that in the cross-sectional view of Figure 22 and the top view of Figure 23, some elements have been omitted for clarity.

[0190] The semiconductor devices in Figures 22 and 23 are configured such that the process from Figure 6B onward is performed without performing the step of forming the insulator 412 shown in Figure 6A in the process shown in Figure 5B. If the components and impurities contained in the insulator 411A (insulator 411B, insulator 411C) do not diffuse into the conductor 431a (conductor 431b, conductor 431c) and the conductivity of the conductor 431a (conductor 431b, conductor 431c) does not decrease, then it is not necessary to provide the insulator 412 which functions as a barrier insulating film for such components and impurities. In this case, since it is not necessary to provide the insulator 412, the process for manufacturing the semiconductor device can be shortened.

[0191] <Example of semiconductor device configuration 7> Furthermore, for example, the configurations of the semiconductor devices shown in Figures 1, 2A, and 2B may be changed to the configurations shown in Figures 24 and 25. Figure 24 is a cross-sectional view of a semiconductor device with a configuration different from that of Figures 1, 2A, and 2B. Figure 25 is a top view of the area indicated by the dashed-dotted line T3-T4 in Figure 24. Note that the top view of the area indicated by the dashed-dotted line T1-T2 in Figure 24 may have a configuration that is almost the same as that of Figure 2A. Note that in the cross-sectional view of Figure 24 and the top view of Figure 25, some elements have been omitted for clarity.

[0192] The semiconductor device shown in Figures 24 and 25 has a configuration in which a conductor is formed on the side surface of the opening of region 491 in the process shown in Figure 5B, and the processes from Figure 7B onward are performed without performing the processes from Figure 6A to Figure 7A. Note that a portion of the conductor is removed in the process of forming recesses 493A and 493B in Figure 9B. This forms the conductors 461a, 461b, and 461c shown in Figure 24.

[0193] It is preferable that the conductors 461a, 461b, and 461c are conductive materials such that a low-resistance region is formed near the interface with the material layer 452.

[0194] For example, if the material layer 452 is a material containing a metal oxide, the resistance values ​​of the conductors 461a, 461b, and 461c are 2.4 × 10⁻⁶. 3 [Ω / sq] or less, preferably 1.0 × 10 3 A metal, a nitride containing a metallic element, or an oxide containing a metallic element with a conductivity of [Ω / sq] or less is used. As the conductive material, for example, a metal film such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium, a nitride film containing a metallic element such as Al-Ti nitride or titanium nitride, or an oxide film containing a metallic element such as indium tin oxide or In-Ga-Zn oxide can be used.

[0195] Furthermore, the conductors 461a, 461b, and 461c are not limited to the conductive materials described above, as long as they serve to reduce the resistance of the material layer 452. For example, insulators such as silicon nitride may be used as substitutes for conductors 461a, 461b, and 461c.

[0196] Furthermore, in Figure 9B, after the steps of forming recesses 493A and 493B and conductors 461a, 461b, and 461c, heat treatment may be performed on the material layer 452 in the region where conductors 461a, 461b, and 461c are in contact, and a compound may be formed near the interface between the material layer 452 and conductors 461a, 461b, and 461c due to the components contained in conductors 461a, 461b, and 461c and the components contained in the material layer 452. This compound reduces the resistance of the region 472 of the material layer 452 that is in contact with conductors 461a, 461b, and 461c.

[0197] Furthermore, the heat treatment may be carried out in an atmosphere containing nitrogen. Through this heat treatment, metallic elements that are components of conductor 461a (conductor 461b, and conductor 461c) may diffuse into the material layer 452, or metallic elements that are components of the material layer 452 may diffuse into conductor 461a (conductor 461b, and conductor 461c), and the material layer 452 and conductor 461a, conductor 461b, and conductor 461c may form a metallic compound. In this case, the metallic elements of the material layer 452 and the metallic elements of conductor 461a, conductor 461b, and conductor 461c may be alloyed. When the metal elements of material layer 452 are alloyed with the metal elements of conductors 461a, 461b, and 461c, the metal elements become relatively stable, thus enabling the provision of a highly reliable semiconductor device.

[0198] Also, by this heat treatment, hydrogen in the material layer 452 diffuses into the region 472 of the material layer 452 in contact with the conductor 461a, the conductor 461b, and the conductor 461c. When it enters the oxygen vacancies existing in the region, it becomes a relatively stable state. Further, hydrogen in the oxygen vacancies existing in the region 471 of the material layer 452 exposed in the recess 493A and the recess 493B escapes from the oxygen vacancies by heat treatment at 250°C or higher, diffuses into the region 472, and enters the oxygen vacancies existing in the region 472 of the material layer 452, becoming a relatively stable state. Therefore, by heat treatment, the region 472 has lower resistance, and the region 471 is purified (reduction of impurities such as water and hydrogen) and has higher resistance.

[0199] Also, for example, when the material layer 452 is a material containing silicon, the material layer 452 may be in contact with the conductor 461a, the conductor 461b, and the conductor 461c, causing impurities (elements, ions, etc.) contained in the conductor 461a, the conductor 46ilb, and the conductor 461c to diffuse into the material layer 452. Also, at this time, depending on the situation or in some cases, it is preferable to perform heat treatment after the steps of forming the recesses 493A and 493B and forming the conductors 4il61a, the conductor 461b, and the conductor 461c in FIG. 9B. That is, impurity regions are formed on the surface of the material layer 452 in contact with the conductor 461a, the conductor 461b, and the conductor 461c and in the vicinity of the interface.

[0200] When the impurities contained in the conductors 461a, 461b, and 461c are n-type impurities (donors), an n-type impurity region may be formed in the region 472 of the material layer 452 or near the interfaces between the material layer 452 and the conductors 461a, 461b, and 461c. On the other hand, when the impurities contained in the conductors 461a, 461b, and 461c are p-type impurities (acceptors), a p-type impurity region may be formed in the region 472 of the material layer 452 or near the interfaces between the material layer 452 and the conductors 461a, 461b, and 461c. That is, carriers may be formed in the region 472 of the material layer 452 or near the interfaces between the region 472 of the material layer 452 and the conductors 461a, 461b, and 461c, and the region 472 may have a reduced resistance.

[0201] Also, by performing heat treatment, metal silicide may be formed near the interfaces between the conductors 461a, 461b, and 461c and the region 472 of the material layer 452 due to the conductive materials contained in the conductors 461a, 461b, and 461c and the components contained in the material layer 452. When metal silicide is formed near the interfaces between the conductors 461a, 461b, and 461c and the region 472 of the material layer 452, the interfaces between the conductors 461a, 461b, and 461c and the region 472 of the material layer 452 may have a reduced resistance.

[0202] Furthermore, when manufacturing the semiconductor devices shown in Figures 24 and 25, it is preferable not to perform heat treatment in a step prior to the step in Figure 9B in which recesses 493A and 493B are formed, as well as the step in which conductors 461a, 461b, and 461c are formed. This is because, in the step shown in Figure 5B, a conductor for forming conductors 461a, 461b, and 461c is deposited on the material layer 452, and if heat treatment is performed at this stage, the resistance may be reduced in the region of the material layer 452 that is in contact with the conductor. Therefore, when manufacturing the semiconductor devices shown in Figures 24 and 25, it is preferable to perform the heat treatment described above after the recesses 493A and 493B are formed, as well as the conductors 461a, 461b, and 461c are formed in Figure 9B.

[0203] <Example of semiconductor device configuration 8> Furthermore, for example, the configuration of the semiconductor device shown in Figures 1, 2A, and 2B may be changed to the configuration of the semiconductor device shown in Figures 26, 27A, and 27B. Figure 26 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device shown in Figures 1, 2A, and 2B. Also, Figure 27A is a top view of the area indicated by the dashed-dotted line U1-U2 in Figure 26, and Figure 27B is a top view of the area indicated by the dashed-dotted line U3-U4 in Figure 26. Note that in the cross-sectional view of Figure 26, the top view of Figure 27A, and the top view of Figure 27B, some elements have been omitted for clarity.

[0204] The semiconductor devices shown in Figures 26, 27A, and 27B are configured such that the process shown in Figure 8A does not involve the process of forming the conductor 432 shown in Figure 8B, but rather the process from Figure 9A onward.

[0205] In other words, the semiconductor devices shown in Figures 26, 27A, and 27B are configured without a second gate electrode and wiring that supplies potential to the second gate electrode.

[0206] Furthermore, an example of the configuration of a semiconductor device that functions as a memory device according to one aspect of the present invention may be a combination of the semiconductor device configuration examples 1 to 8 described above, selected as appropriate.

[0207] Furthermore, the insulators, conductors, semiconductors, and material layers disclosed in this specification can be formed by PVD (Physical Vapor Deposition) and CVD (Chemical Vapor Deposition) methods. Examples of PVD methods include sputtering, resistance heating deposition, electron beam deposition, and PLD (Pulsed Laser Deposition). Examples of CVD methods include plasma CVD and thermal CVD. In particular, examples of thermal CVD methods include MOCVD (Metal Organic Chemical Vapor Deposition) and ALD (Atomic Layer Deposition).

[0208] Thermal CVD (Chemical Vapor Deposition) is a film deposition method that does not use plasma, and therefore has the advantage of not generating defects due to plasma damage.

[0209] In the thermal CVD method, the raw material gas and oxidizer may be simultaneously introduced into a chamber, the chamber pressure may be reduced to atmospheric pressure or reduced pressure, and the reaction may occur near or on the substrate, resulting in film deposition on the substrate.

[0210] Furthermore, the ALD method may also be performed by maintaining atmospheric pressure or reduced pressure in the chamber, sequentially introducing the raw material gases for the reaction into the chamber, and repeating the order of gas introduction. For example, two or more types of raw material gases may be supplied to the chamber sequentially by switching each switching valve (also called a high-speed valve), and an inert gas (such as argon or nitrogen) may be introduced simultaneously with or after the first raw material gas to prevent mixing of multiple raw material gases, followed by the introduction of the second raw material gas. When an inert gas is introduced simultaneously, the inert gas acts as a carrier gas, and an inert gas may also be introduced simultaneously with the introduction of the second raw material gas. Alternatively, instead of introducing an inert gas, the first raw material gas may be discharged by vacuum evacuation before introducing the second raw material gas. The first raw material gas adsorbs onto the surface of the substrate to form a first thin layer, which then reacts with the second raw material gas introduced later to laminate a second thin layer on top of the first thin layer, forming a thin film. By controlling the order of gas introduction and repeating this process multiple times until the desired thickness is achieved, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness control is possible, making it suitable for fabricating fine FETs.

[0211] Thermal CVD methods such as MOCVD and ALD can form various films, including metal films, semiconductor films, and inorganic insulating films, as disclosed in the embodiments described above. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. However, the method is not limited to these combinations; triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0212] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes the ALD method, two types of gases are used: a raw material gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (such as hafnium alkoxide or hafnium amides like tetrakisdimethylamidehafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizing agent. Other materials include tetrakis(ethylmethylamide)hafnium.

[0213] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes the ALD method, two types of gases are used: a raw material gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizing agent. Other materials include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0214] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes the ALD method, hexachlorodisilane is adsorbed onto the film deposition surface, and radicals of oxidizing gases (O2, nitrous oxide) are supplied to react with the adsorbed material.

[0215] For example, when depositing a tungsten film using a film deposition apparatus that utilizes the ALD method, an initial tungsten film is formed by sequentially introducing WF6 gas and B2H6 gas repeatedly, and then the tungsten film is formed by sequentially introducing WF6 gas and H2 gas repeatedly. Note that SiH4 gas may be used instead of B2H6 gas.

[0216] For example, when depositing an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film deposition apparatus utilizing the ALD method, an In-O layer is formed by sequentially introducing In(CH3)3 gas and O3 gas, then a GaO layer is formed by sequentially introducing Ga(CH3)3 gas and O3 gas, and then a ZnO layer is formed by sequentially introducing Zn(CH3)2 gas and O3 gas. Note that the order of these layers is not limited to this example. Furthermore, mixed oxide layers such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed using these gases. Note that H2O gas obtained by bubbling water with an inert gas such as Ar may be used instead of O3 gas, but it is preferable to use O3 gas that does not contain H. Also, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Also, Zn(CH3)2 gas may be used.

[0217] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0218] (Embodiment 2) This embodiment describes an example of a semiconductor device configuration that functions as a memory device, according to an aspect of the present invention, which differs from Embodiment 1, and an example of a method for manufacturing the semiconductor device. This embodiment deals with a semiconductor device having a cell transistor including a floating gate electrode.

[0219] <Example of semiconductor device configuration 9> The configuration of a semiconductor device having cell transistors CTrA and CTrB will be explained using Figures 28, 29A, and 29B. Figure 28 is a cross-sectional view of the semiconductor device. Figure 29A is a top view of the area shown by the dashed-dotted line A1-A2 in Figure 28, and Figure 29B is a top view of the area shown by the dashed-dotted line A3-A4 in Figure 28. Note that in the cross-sectional view of Figure 28, the top view of Figure 29A, and the top view of Figure 29B, some elements have been omitted for clarity.

[0220] In FIG. 28, the semiconductor device includes an insulator 311A disposed above a substrate (not shown), an insulator 311B disposed above the insulator 311A, and an insulator 311C disposed above the insulator 311B.

[0221] For the substrate, for example, refer to the description of the substrate described in Embodiment 1.

[0222] Also, in FIGS. 28, 29A, and 29B, the semiconductor device has a region 391. The region 391 is a region where an opening is formed during the manufacturing process of the semiconductor device. In the opening, an insulator, a conductor, a semiconductor, etc. are formed through the manufacturing process of the semiconductor device. As an example, the opening can be a cylindrical opening as shown in FIGS. 29A and 29B. In FIG. 29B, in the region 391, as an example, in order from the side surface of the opening, an insulator 312a (insulator 312b, insulator 312c), a conductor 331a (conductor 331b, conductor 331c), a material layer 351a (material layer 351b, material layer 351c), a material layer 352, an insulator 313, and a conductor 332 are disposed.

[0223] Furthermore, the semiconductor device has region 392A and region 392B. Regions 392A and 392B are regions where openings are formed during the manufacturing process of the semiconductor device, and insulators, conductors, etc., are formed in these openings after the manufacturing process of the semiconductor device. For example, these openings can be slit-shaped openings, as shown in Figures 29A and 29B. Region 392A includes a part of material layer 353, a part of insulator 314, a part of insulator 315, a part of conductor 334a, a part of conductor 334b, and insulator 316A. Region 392B also includes a part of material layer 353, a part of insulator 314, a part of insulator 315, a part of conductor 334a, a part of conductor 334b, and insulator 316B. Furthermore, in Figure 28, between insulator 311A ​​and insulator 311B, there is a conductor 333a, a portion of conductor 334a, a portion of insulator 314, and a portion of insulator 315. Also, between insulator 311B and insulator 311C, there is a conductor 333b, a portion of conductor 334b, a portion of insulator 314, and a portion of insulator 315.

[0224] Furthermore, the material layer 352 has region 371 and region 372. Region 371 is located adjacent to material layer 351a (material layer 351b, material layer 351c), and region 372 is located adjacent to material layer 353. Region 371 becomes a channel formation region for cell transistor CTrA (cell transistor CTrB) during the manufacturing process of the semiconductor device, and region 372 becomes a low-resistance region during the manufacturing process of the semiconductor device.

[0225] In the cell transistor CTrB, conductor 334b ​​functions as the first gate electrode and a word line that supplies potential to the first gate electrode. In Figure 29A, the insulator 315 surrounded by conductor 334b ​​functions as the gate insulating film, conductor 333b functions as the floating gate electrode (sometimes called a floating gate electrode), and insulator 314 surrounded by conductor 333b functions as the tunnel insulating film. Conductor 331b functions as either the source electrode or the drain electrode, and conductor 331c functions as the other of the source electrode or the drain electrode. In Figure 29A, the region of material layer 352 surrounded by conductor 334b ​​functions as the channel-forming region. Depending on the material contained in material layer 353, the region of material layer 353 in contact with material layer 352 may also function as the channel-forming region. Insulator 313 functions as the gate insulating film, and conductor 332 functions as the second gate electrode and wiring that supplies potential to the second gate electrode.

[0226] Furthermore, in Figure 29A, by replacing conductor 333b with conductor 333a and conductor 334b ​​with conductor 334a, it can be considered a top view of the cell transistor CTrA. In the cell transistor CTrA, conductor 334a functions as the first gate electrode and a word line that supplies potential to the first gate electrode. In Figure 29A, the insulator 315 surrounded by conductor 334a functions as the first gate insulating film, conductor 333a functions as the floating gate electrode, and the insulator 314 surrounded by conductor 333a functions as the tunnel insulating film. Conductor 331a functions as either the source electrode or the drain electrode, and conductor 331b functions as the other source electrode or drain electrode. In addition, the region of the material layer 352 surrounded by conductor 334a in Figure 29A functions as the channel formation region. Furthermore, depending on the material contained in material layer 353, the region of material layer 353 in contact with material layer 352 may also function as a channel-forming region. In addition, insulator 313 functions as a second gate insulating film, and conductor 332 functions as a second gate electrode and wiring that provides potential to the second gate electrode.

[0227] Insulator 312a, for example, functions as a barrier insulating film that suppresses the diffusion of impurities from insulator 311A ​​(e.g., water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.)) into conductor 331a. In other words, insulator 312a can suppress impurities in conductor 331a. Similarly, insulator 312b, for example, functions as a barrier insulating film that suppresses the diffusion of impurities from insulator 311B into conductor 331b, and insulator 312c, for example, functions as a barrier insulating film that suppresses the diffusion of impurities from insulator 311C into conductor 331c.

[0228] Next, we will describe the material layers 351a (material layers 351b, material layer 351c), material layer 352, and material layer 353 included in cell transistor CTrA and cell transistor CTrB.

[0229] Material layer 351a, for example, functions as a barrier film that suppresses the diffusion of impurities (e.g., water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.)) into material layer 352. By providing material layer 351a, which has the function of suppressing the permeation of impurities, between material layer 352 and conductor 331a, the electrical resistance between material layer 352 and conductor 331a can be reduced. Similarly, material layer 351b, for example, functions as a barrier film that suppresses the diffusion of impurities from material layer 352 into conductor 331b, and material layer 351c, for example, functions as a barrier film that suppresses the diffusion of impurities from material layer 352 into conductor 331c.

[0230] Furthermore, when cell transistors CTrA and CTrB in Figure 28 are OS transistors, it is preferable to use a metal oxide that functions as an oxide semiconductor as material layer 352, and it is preferable to use a material containing the metal elements and oxygen contained in the metal oxide as material layer 351a (material layer 351b, material layer 351c). Also, it is preferable to use a material containing the metal elements and oxygen contained in the metal oxide as material layer 353, similar to material layer 351.

[0231] Furthermore, if cell transistors CTrA and CTrB in Figure 28 are OS transistors, then in the material layer 352, the region 371 that functions as a channel formation region has more oxygen vacancies (V) than the region 372 that functions as a low-resistance region. O Because the amount of ) is small or the impurity concentration is low, it becomes a high-resistance region with a low carrier concentration. Therefore, region 371 can be said to be type i (intrinsic) or substantially type i.

[0232] Furthermore, if the cell transistors CTrA and CTrB in Figure 28 are OS transistors, it is preferable that the material layer 352 consists of multiple layers, including material layer 352A and material layer 352B, as shown in Figure 30A. Note that Figure 30A is an enlarged view of the region where the cell transistor CTrA in Figure 28 is formed.

[0233] The material layers 351a (material layers 351b, material layer 351c), material layer 352A, material layer 352B, and the material layer 353 formed in a later process can be, for example, one or more materials selected from indium, element M (for example, aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.), and zinc. In particular, metal oxides containing indium, gallium, and zinc have a high band gap and function as intrinsic (also called type I) or substantially intrinsic semiconductors.

[0234] Cell transistors CTrA and CTrB, in which the metal oxide in question is included in the channel-forming region, have a very low off-current characteristic. In other words, the leakage current in cell transistors CTrA and CTrB when they are in the off state can be reduced, which may reduce the power consumption of the semiconductor device.

[0235] For example, a metal oxide containing element M may be used as material layer 351a (material layer 351b, material layer 351c). It is preferable that the concentration of element M in material layer 351a (material layer 351b, material layer 351c) is higher than that in material layer 352B. Alternatively, gallium oxide may be used as material layer 351a (material layer 351b, material layer 351c). Alternatively, a metal oxide such as In (indium)-M-Zn (zinc) oxide may be used as material layer 351a (material layer 351b, material layer 351c). Specifically, it is preferable that the atomic ratio of element M to In in the metal oxide used in material layer 351a (material layer 351b, material layer 351c) is greater than the atomic ratio of element M to In in the metal oxide used in material layer 352B. Furthermore, the film thickness of material layer 351a (material layer 351b, material layer 351c) is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. It is also preferable that material layer 351a (material layer 351b, material layer 351c) is crystalline. When material layer 351a (material layer 351b, material layer 351c) is crystalline, the release of oxygen in material layer 352A and material layer 352B can be suitably suppressed. For example, if material layer 351a (material layer 351b, material layer 351c) has a crystalline structure such as hexagonal, the release of oxygen in material layer 352A and material layer 352B can be suppressed.

[0236] Furthermore, for example, it is preferable that material layer 352A and material layer 352B each be oxides with different chemical compositions. Specifically, it is preferable that the atomic ratio of element M to the main component metal element in the metal oxide used in material layer 352B is greater than the atomic ratio of element M to the main component metal element in the metal oxide used in material layer 352A. Also, it is preferable that the atomic ratio of element M to In in the metal oxide used in material layer 352B is greater than the atomic ratio of element M to In in the metal oxide used in material layer 352A. Furthermore, material layer 352B may be made with the same composition as material layer 351a (material layer 351b, material layer 351c).

[0237] Furthermore, for example, the atomic ratio of element M to the main metal element in material layer 353 may be greater than the atomic ratio of element M to the main metal element in the metal oxide used in material layer 352A. Also, the atomic ratio of element M to In in the metal oxide used in material layer 353 may be greater than the atomic ratio of element M to In in the metal oxide used in material layer 352A. In addition, the same composition as material layer 352A may be used for material layer 353.

[0238] Furthermore, if the cell transistors CTrA and CTrB in Figure 28 are OS transistors, the material layer 353 may consist of multiple layers, such as material layer 353A and material layer 353B, as shown in Figure 30B. Note that Figure 30B is an enlarged view of the region where the cell transistor CTrA in Figure 28 is formed.

[0239] It is preferable that material layer 353A and material layer 353B each be oxides with different chemical compositions. Specifically, it is preferable that the atomic ratio of element M to the main metal element in the metal oxide used in material layer 353B is greater than the atomic ratio of element M to the main metal element in the metal oxide used in material layer 353A. Furthermore, material layer 353B may be composed of the same material as material layer 351a (material layer 351b, material layer 351c).

[0240] Furthermore, in the cell transistor CTrA shown in Figure 30B, if the material layer 352 has material layer 352A and material layer 352B as shown in Figure 30A, that is, if the material layer 352 has material layer 352A and material layer 352B and the material layer 353 has material layer 353A and material layer 353B as shown in the cell transistor CTrA shown in Figure 30C, then it is preferable that the atomic ratio of element M to the main component metal element in the metal oxide used in material layer 352B is greater than the atomic ratio of element M to the main component metal element in the respective metal oxides used in material layer 352A and material layer 353A. Also, it is preferable that the atomic ratio of element M to the main component metal element in the metal oxide used in material layer 353B is greater than the atomic ratio of element M to the main component metal element in the respective metal oxides used in material layer 352A and material layer 353A. Furthermore, it is preferable that the atomic ratio of element M to the main metal element in the metal oxide used in material layer 351a (material layer 351b, material layer 351c) is greater than the atomic ratio of element M to the main metal element in the respective metal oxides used in material layer 352A and material layer 353A.

[0241] Furthermore, in this case, the compositions of material layer 351a (material layer 351b, material layer 351c), material layer 352B, and material layer 353B may be equal to each other. Also, material layer 353A may have the same composition as material layer 352A.

[0242] Here, we will explain specific examples of atomic ratios of In, Ga, and Zn in the metal oxides contained in material layers 352A, 352B, and 353 of the cell transistor CTrA shown in Figure 30A or Figure 30C, assuming that the metal oxides contain In, gallium (hereinafter referred to as Ga), and zinc (hereinafter referred to as Zn).

[0243] For material layer 352B, as an example, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or In:Ga:Zn=1:1:0.5 may be used. Similarly, for material layer 352A, as an example, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or In:Ga:Zn=1:1:1 may be used. Similarly, for material layer 353, as an example, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 and an atomic ratio of Ga to Zn of Ga:Zn=2:1 or Ga:Zn=2:5 may be used.

[0244] Furthermore, as a specific example of a laminated structure for the material layer 353 as shown in Figure 30C, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or close to it may be used for material layer 353A, and a metal oxide with an atomic ratio of In:Ga:Zn=1:3:4 or close to it may be used for material layer 353B. Alternatively, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or close to it may be used for material layer 353A, and a metal oxide with an atomic ratio of Ga and Zn of Ga:Zn=2:1 or close to it may be used for material layer 353B. Alternatively, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or close to it may be used for material layer 353A, and a metal oxide with an atomic ratio of Ga and Zn of Ga:Zn=2:5 or close to it may be used for material layer 353B. Alternatively, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 4:2:3 or close to it may be used for material layer 353A, and gallium oxide may be used for material layer 353B.

[0245] Furthermore, for example, if the atomic ratio of In to element M in the metal oxide used in material layer 352B is smaller than the atomic ratio of In to element M in the metal oxide used in material layer 352A, then an In-Ga-Zn oxide with an atomic ratio of In, Ga, and Zn such as In:Ga:Zn=5:1:6 or nearby, In:Ga:Zn=5:1:3 or nearby, or In:Ga:Zn=10:1:3 or nearby can be used as material layer 352A.

[0246] In addition to the compositions mentioned above, the material layer 352A can be made of metal oxides having compositions such as In:Zn=2:1, In:Zn=5:1, In:Zn=10:1, or compositions close to any one of these. Alternatively, the material layer 352A can be made of, for example, indium oxide.

[0247] It is preferable to combine these material layers 351a (material layers 351b, material layer 351c), material layer 352A, material layer 352B, and material layer 353 (material layer 353A, material layer 353B) in a manner that satisfies the above-mentioned atomic ratio relationship. For example, in the case of the cell transistor CTrA shown in Figure 30A, it is preferable that material layers 352B and 353 be metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition in the vicinity of that, and material layer 352A be a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition in the vicinity of that. Furthermore, for example, in the case of the cell transistor CTrA in Figure 30C, it is preferable that material layers 352B and 353B be metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to it, and material layer 352A be a metal oxide having a composition of In:Ga:Zn=4:2:3 to In:Ga:Zn=4.1 or a composition close to it. Note that the above composition refers to the atomic ratio in the oxide formed on the substrate, or the atomic ratio in the sputtering target. In addition, increasing the ratio of In in the composition of material layer 352A is preferable because it can increase the on-current or field-effect mobility of the transistor.

[0248] By the way, the composition of an oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn=a:b:c (a+b+c=1) is said to be in the vicinity of the composition of an oxide with an atomic ratio of In:Ga:Zn=A:B:C (A+B+C=1) if a, b, and c are (aA) 2 +(bB) 2 +(cC) 2 ≤r 2This means that the following conditions are met, and r can be, for example, 0.20, preferably 0.10, and more preferably 0.05.

[0249] Under these conditions, by positioning material layer 352A in contact with material layer 352B, the diffusion of impurities and oxygen from the insulator 313 and / or conductor 332 to material layer 352A via material layer 352B can be suppressed. Similarly, by positioning material layer 353B in contact with material layer 352B, the diffusion of impurities and oxygen from the insulator 314, conductor 333a (conductor 333b), insulator 315, conductor 334a (conductor 334b), insulator 316A, etc., to material layer 353A and material layer 352A via material layer 353B can be suppressed. Similarly, by arranging material layer 351a (material layer 351b, material layer 351c) in contact with material layer 352A, it is possible to suppress the diffusion of impurities and oxygen from conductors 331a (conductors 331b, conductors 331c), insulators 312a (insulators 312b, insulators 312c), insulators 311A ​​(insulators 311B, insulators 311C), etc., into material layer 352A via material layer 351a (material layer 351b, material layer 351c).

[0250] Furthermore, when Si transistors are used as cell transistors CTrA and CTrB in Figure 28, the material layer 352 can be, for example, amorphous silicon (hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or monocrystalline silicon.

[0251] Furthermore, when Si transistors are applied to cell transistors CTrA and CTrB, the material layer 352 may consist of multiple layers or a single layer, as shown in Figures 30A and 30C. In the fabrication examples described herein, the material layer 352 is described as a single layer.

[0252] Furthermore, the material applicable to material layer 353 can be a metal oxide applicable to material layer 351 and / or material layer 352, or a material that functions as a tunnel insulating film, for example, a material applicable to the insulator 314 which will be described in detail later. Note that material layer 353 may consist of multiple layers or a single layer, as shown in Figures 30B and 30C.

[0253] When cell transistors CTrA and CTrB are Si transistors, it is preferable that the material layer 351 is a conductor containing impurities (elements or ions) to diffuse into the interface of material layer 352 on the formation surface of material layer 351 and the region near the interface.

[0254] The conductor can be made from a material containing one or more metallic elements selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and others.

[0255] Furthermore, when cell transistors CTrA and CTrB are configured as n-type transistors, n-type impurities (donors) are used. Examples of n-type impurities include phosphorus and arsenic. Also, in this example of a fabrication method, when cell transistors CTrA and CTrB are configured as p-type transistors, p-type impurities (acceptors) are used. Examples of p-type impurities include boron, aluminum, and gallium.

[0256] Furthermore, the material layer 351 may be a material capable of forming silicides at, for example, the interface of the material layer 352 on the formation surface of the material layer 351, and in the region near the interface. Examples of materials capable of forming silicides include nickel, cobalt, molybdenum, tungsten, and titanium.

[0257] Although Figures 28, 29A, and 29B show a configuration in which one region 391 is provided between region 392A and region 392B, one aspect of the present invention is not limited to this. For example, one aspect of the present invention may be a configuration in which multiple regions 391 are provided between region 392A and region 392B.

[0258] A specific example of this configuration is shown in Figure 31A. Figure 31A shows a top view of a semiconductor device in which multiple regions 391 are provided. This top view is an unfolded view of the semiconductor device shown in Figure 28 along the dashed line A3-A4, in which multiple regions 391 are provided. The semiconductor device shown in Figure 31A has multiple regions 392 in a slit shape, with multiple regions 391 provided between adjacent regions 392. As for the arrangement of the multiple regions 391, for example, multiple regions 391 may be arranged in a single row or as multiple rows in a direction that has an angle with respect to the slit-shaped regions 392. Another arrangement is, for example, multiple regions 391 may be arranged in a staggered pattern. Note that the regions 392 do not have to be slit-shaped; instead, they may be cylindrical, for example. Figure 31B shows a configuration in which a cylindrical opening is provided in region 394 instead of a slit-shaped opening formed in region 392, and a material layer 353 and insulators 314 to 316 are formed in region 394. Furthermore, the shape of region 394 is not limited to a cylindrical shape; it may be a columnar shape with any two-dimensional shape, such as an ellipse or polygon, as its base. Also, the position of region 394 may be along two or more different rows, rather than along a single row as region 392 in Figure 31A. Alternatively, the position of region 394 may be formed without following the regularity described above.

[0259] <<Example of Semiconductor Device Fabrication 2>> Next, we will describe an example of a method for manufacturing the semiconductor device shown in Figures 28, 29A, and 29B.

[0260] First, a laminate 300 as shown in Figure 32A is fabricated. The laminate 300, as an example, includes an insulator 311A, a sacrificial layer 301A, an insulator 311B, another sacrificial layer 301B, and an insulator 311C. The insulator 311A ​​is placed on top of a substrate (not shown), the sacrificial layer 301A is placed on top of the insulator 311A, the insulator 311B is placed on top of the sacrificial layer 301A, the sacrificial layer 301B is placed on top of the insulator 311B, and the insulator 311C is placed on top of the sacrificial layer 301B.

[0261] Various materials can be used for sacrificial layers 301A and 301B. For example, silicon nitride, silicon oxide, aluminum oxide, etc. may be used as insulators. Alternatively, silicon, gallium, germanium, etc. may be used as semiconductors. Alternatively, aluminum, copper, titanium, tungsten, tantalum, etc. may be used as conductors. In other words, for sacrificial layers 301A and 301B, materials that can achieve a suitable etching selectivity ratio with the materials used in other parts should be used.

[0262] It is preferable that the insulators 311A ​​to 311C are materials in which the concentration of impurities such as water or hydrogen has been reduced. For example, the amount of hydrogen desorbed from insulators 311A ​​to 311C is calculated by thermal desorption gas analysis (TDS) in the range of 50°C to 500°C, and the amount of desorption converted to hydrogen molecules is calculated per area of ​​any one of the insulators 311A ​​to 311C to be 2 × 10⁻⁶. 15 molecular / cm² 2 The following is preferably 1 × 10 15 molecular / cm² 2 The following is more preferable: 5 x 10 14 molecular / cm² 2 The following conditions are acceptable. In addition, insulators 311A ​​to 311C may be formed using an insulator that releases oxygen upon heating. However, the materials applicable to insulators 311A ​​to 311C are not limited to those described above.

[0263] As insulators 311A ​​to 311C, for example, an insulator containing one or more materials selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc. may be used in a single layer or in a multilayer structure. In addition, for example, a material containing silicon oxide or silicon oxynitride may be used. However, the materials applicable to insulators 311A ​​to 311C are not limited to those described above.

[0264] In the next step, as shown in Figure 32B, an opening is formed in region 391 of the laminate 300 shown in Figure 32A, for example, by forming a resist mask and etching.

[0265] The resist mask can be formed using methods such as lithography, printing, or inkjet printing, as appropriate. Forming the resist mask using inkjet printing eliminates the need for a photomask, which can sometimes reduce manufacturing costs. Furthermore, the etching process can be performed using either dry etching or wet etching, or both.

[0266] Next, as shown in Figure 33A, an insulator 312 is formed on the side surface of the opening in region 391 so as to cover insulators 311A ​​to 311C, sacrificial layer 301A, and sacrificial layer 301B.

[0267] In a later step, insulator 312 functions as a film for forming insulators 312a, 312b, and 312c in Figure 28. Therefore, in this specification, the description of insulator 312 may be replaced with insulators 312a, 312b, and 312c as appropriate.

[0268] As described above, it is preferable that the insulator 312 functions as a barrier insulating film that suppresses the diffusion of impurities (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.)) from the insulator 311A ​​(insulator 311B, insulator 311C) into the material layer 352. In particular, it is preferable that the insulator 312 be a barrier insulating film that prevents the permeation of oxygen atoms or oxygen molecules.

[0269] As the insulator 312, for example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. In particular, when an oxide semiconductor described later is used as the material layer 352, it is preferable to use aluminum oxide or the like as the insulator 312, which has high hydrogen capture and hydrogen fixation capabilities. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the insulator 311A ​​(insulator 311B, insulator 311C) side to the material layer 352 via the conductor 331a (conductor 331b, conductor 331c) and material layer 351a (material layer 351b, material layer 351c).

[0270] Furthermore, although the insulator 312 is shown as a single layer in Figures 28, 29B, and 33A, the present invention is not limited to this. The insulator 312 shown in Figures 28, 29B, and 33A may be constructed by laminating multiple layers of the materials described above. For example, in Figures 28 and 29B, silicon oxide may be used for the insulator 312 in contact with the conductor 331a (conductor 331b, conductor 331c), and aluminum oxide or hafnium oxide may be used for the insulator 312 in contact with the insulator 311A ​​(insulator 311B, insulator 311C).

[0271] Next, as shown in Figure 33B, a conductive film 331 is formed on the surface of the insulator 312.

[0272] Conductor 331 functions as a film for forming conductors 331a, 331b, and 331c in Figure 28 in a later step. Therefore, in this specification, the description of conductor 331 can be appropriately replaced with conductors 331a, 331b, and 331c.

[0273] Furthermore, as described above, since the conductor 331 functions as a film for forming conductors 331a, 331b, and 331c, the conductor 331 becomes the source electrode and drain electrode of cell transistors CTrA and CTrB, respectively, in a later process.

[0274] The conductor 331 is preferably a material with high conductivity. For example, the conductor 331 is preferably a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0275] Furthermore, in particular when using an oxide semiconductor as the material layer 352, it is preferable to use a conductive material as the conductor 331 that has the function of suppressing the permeation of impurities such as water or hydrogen. In this case, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide as the conductor 331.

[0276] Furthermore, although the conductor 331 is shown as a single layer in Figures 28, 29B, and 33, the present invention is not limited to this. The conductor 331 shown in Figures 28, 29B, and 33 may, for example, be configured by laminating multiple layers of the materials described above. Specifically, for example, the conductor 331 may be configured by using a conductive material having the function of suppressing the permeation of impurities such as water or hydrogen in the first layer, and a conductive material that is resistant to oxidation, or a material that maintains conductivity even when absorbing oxygen, in the second layer.

[0277] Then, as shown in Figure 34A, a material layer 351 is formed on the surface where the conductor 331 is formed.

[0278] Material layer 351 functions as a film for forming material layers 351a, 351b, and 351c in Figure 28 in a later step. Therefore, in this specification, the description of material layer 351 can be appropriately replaced with material layers 351a, 351b, and 351c.

[0279] By forming a material layer 351 in contact with the surface of the conductor 331, a low-resistance region may be formed near the interface between the material layer 351 and the conductor 331. Furthermore, by applying heat treatment at this time, a compound may be formed between the components contained in the material layer 351 and the components contained in the conductor 331. In this fabrication example, it is assumed that appropriate materials have been selected for both the conductor 331 and the material layer 351 so that the compound has low resistance.

[0280] Regarding the materials applicable to material layer 351, please refer to the description of material layer 351a (material layer 351b, material layer 351c) in semiconductor device configuration example 9.

[0281] Next, as shown in Figure 34B, a material layer 352 is formed on the surface where the material layer 351 is formed.

[0282] As described above, a portion of the material layer 352 functions as the channel formation region for cell transistors CTrA and CTrB in Figure 28.

[0283] For information on materials applicable to material layer 352, please refer to the explanation in semiconductor device configuration example 9.

[0284] Next, as shown in Figure 35A, an insulator 313 is formed on the surface where the material layer 352 is formed.

[0285] As described above, the insulator 313 functions as the second gate insulating film for cell transistor CTrA and cell transistor CTrB, respectively, in Figure 28.

[0286] For the insulator 313, it is preferable to use, for example, silicon oxide or silicon oxynitride. Alternatively, for the insulator 313, for example, aluminum oxide, hafnium oxide, or an oxide having aluminum and hafnium can be used.

[0287] Furthermore, it is preferable that the insulator 313 functions as a barrier insulating film that suppresses the permeation of impurities (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrous oxide molecules (N2O, NO, NO2, etc.)), similar to the insulator 312.

[0288] Therefore, when cell transistors CTrA and CTrB in Figure 28 are OS transistors, that is, when a metal oxide that functions as an oxide semiconductor is used as the material layer 352, it is preferable to use an insulating material that has the function of suppressing oxygen permeation as the insulator 313. For example, it is preferable to use silicon nitride, silicon oxide nitride, silicon oxynitride, aluminum nitride, or aluminum oxide nitride as the insulator 313. By forming such an insulator 313, it is possible to prevent oxygen from detaching from the material layer 352 and diffusing into the insulator 313. This prevents the material layer 352 from becoming less resistive due to the detachment of oxygen from the material layer 352.

[0289] Furthermore, it is preferable to use an insulating material as the insulator 312 that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, aluminum oxide can be used as the insulator 312. However, the materials that can be applied to the insulator 312 are not limited to those described above, and as the insulator 312, for example, materials that can be applied to the above-described insulators 311A ​​to 311C can be used as a film in which the concentration of impurities such as water and hydrogen has been reduced.

[0290] Furthermore, although the insulator 313 is shown as a single layer in Figures 28, 29B, and 35A, the present invention is not limited to this. The insulator 313 shown in Figures 28, 29B, and 35A may be configured by laminating multiple layers of the materials described above. For example, in Figures 28 and 29B, silicon oxide may be used for the insulator 312 in contact with the material layer 352, and aluminum oxide or hafnium oxide may be used for the insulator 312 in contact with the conductor 332.

[0291] In particular, consider the case where a metal oxide that functions as an oxide semiconductor is used as the material layer 352. For example, by depositing aluminum oxide by sputtering, oxygen is supplied to the insulator 313, and the oxygen supplied to the insulator 313 is supplied to the material layer 352. As oxygen is supplied to the material layer 352, the amount of oxygen contained in the oxide semiconductor increases, which prevents the oxide semiconductor from becoming less resistive.

[0292] Then, as shown in Figure 35B, the conductor 332 is formed on the surface of the insulator 313 so that the remaining openings in region 391 are filled.

[0293] As described above, the conductor 332 functions as the second gate electrode of cell transistor CTrA and cell transistor CTrB, respectively, and as wiring that provides potential to the second gate electrode in Figure 28.

[0294] As the conductor 332, for example, a material containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. In addition, as the conductor 332, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.

[0295] Furthermore, as the conductor 332, for example, a conductive material containing metal elements and oxygen included in a metal oxide applicable to the material layer 351 or material layer 352 may be used. Alternatively, a conductive material containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride can be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-added indium tin oxide can be used. In addition, indium gallium zinc oxide containing nitrogen can be used. By using such materials, it may be possible to capture hydrogen introduced from surrounding insulators, etc.

[0296] Furthermore, it is preferable to use a conductive material as the conductor 332 that has the function of suppressing the permeation of impurities such as water or hydrogen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide, and it may be in the form of a single layer or a laminate.

[0297] Furthermore, the conductor 332 may be a structure in which multiple of the above-mentioned materials are stacked. For example, it may be a stacked structure combining the aforementioned material containing a metal element and a conductive material containing oxygen. Alternatively, it may be a stacked structure combining the aforementioned material containing a metal element and a conductive material containing nitrogen. Alternatively, it may be a stacked structure combining the aforementioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen. Furthermore, by applying an insulator having an excess oxygen region as an insulator in contact with the periphery of the conductor, oxygen may diffuse in the region of the conductor in contact with the insulator. This may allow for the formation of a stacked structure combining the material containing a metal element and a conductive material containing oxygen. Similarly, by applying an insulator having an excess nitrogen region as an insulator in contact with the periphery of the conductor, nitrogen may diffuse in the region of the conductor in contact with the insulator. This may allow for the formation of a stacked structure combining the material containing a metal element and a conductive material containing nitrogen.

[0298] In the next step, as shown in Figure 36A, slit-shaped openings are formed in regions 392A and 392B by, for example, forming a resist mask and etching the laminate 300. In this step, the openings in regions 392A and 392B are described as slit-shaped, but as shown in Figure 31B, the openings in regions 392A and 392B may be cylindrical.

[0299] For details regarding the formation of the resist mask and the etching process, please refer to the explanation in Figure 32B.

[0300] Then, in the process shown in Figure 36B, using etching or the like, the sacrificial layers 301A and 301B are removed from the sides of the openings formed in regions 392A and 392B, and the regions of the insulator 312, conductor 331 and material layer 351 surrounded by the sacrificial layer 301A, and the regions of the insulator 312, conductor 331 and material layer 351 surrounded by the sacrificial layer 301B are removed, thereby forming recesses 393A and 393B in the laminate 300. In addition, as a result, insulator 312a (insulator 312b, insulator 312c), conductor 331a (conductor 331b, conductor 331c), and material layer 351a (material layer 351b, material layer 351c) are formed in the region overlapping with region 372 of the material layer 352.

[0301] Furthermore, recesses 393A and 393B may be formed together with the openings of regions 392A and 392B during the semiconductor device manufacturing process shown in Figure 36A. Also, the etching conditions and other factors may differ between the process of removing sacrificial layers 301A and 301B, a portion of the insulator 312, a portion of the conductor 331, and a portion of the material layer 351c. Therefore, in the process shown in Figure 36B, the etching conditions and other factors may be changed depending on the material to be removed.

[0302] Incidentally, when a material having a metal oxide is used as the material layer 352, that is, when the cell transistors CTrA and CTrB in Figure 28 are OS transistors, after the formation of the respective openings 392A and 392B, and recesses 393A and 393B, a process may be performed to supply oxygen to the region 371 of the material layer 352 exposed to the recesses 393A and 393B from the respective openings 392A and 392B. In this case, Figure 37A shows the process 10, in which oxygen is supplied to region 371. Examples of processes for supplying oxygen include heat treatment in an oxygen atmosphere.

[0303] Furthermore, as the oxygen supply process 10, for example, microwave processing can be performed in an oxygen-containing atmosphere. In this case, microwaves, high-frequency waves such as RF, oxygen plasma, oxygen radicals, etc., are irradiated onto region 371. For microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating high-density plasma using microwaves. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. Also, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided to the material layer 352. Furthermore, the above microwave processing is preferably performed under reduced pressure, with a pressure of 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. Furthermore, the oxygen flow rate ratio (O2 / O2+Ar) should be 50% or less, preferably 10% to 30%. Furthermore, the processing temperature should be 750°C or less, preferably 500°C or less, for example, around 400°C. Alternatively, after oxygen plasma treatment, heat treatment may be performed continuously without exposure to the outside air.

[0304] As the oxygen supply process 10, by performing microwave processing in an oxygen-containing atmosphere, the oxygen gas is converted into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied to region 371 of the material layer 352 (material layer 352A when the configuration of cell transistors CTrA and CTrB is as shown in Figures 30A and 30C). At this time, microwaves or high-frequency waves such as RF can also be irradiated onto region 371. In other words, microwaves or high-frequency waves such as RF, oxygen plasma, etc., can be applied to region 372 shown in Figure 37A. Due to the action of plasma, microwaves, etc., the V of region 371 O H can be separated and hydrogen H can be removed from region 371. In other words, in region 371, "V O H → H + V O )」, and furthermore, "V O The reaction "+O→null" occurs, which can reduce the hydrogen concentration in region 371. Therefore, the oxygen deficiency in region 371, and VO This can reduce H and lower the carrier concentration.

[0305] On the other hand, in region 372 shown in Figure 37A, conductors 331a (conductors 331b, conductors 331c) are arranged so as to be superimposed. Conductors 331a (conductors 331b, conductors 331c) shield against the effects of microwaves, high-frequency waves such as RF, oxygen plasma, etc., so these effects do not extend to region 372. As a result, microwave processing does not affect region 372. O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration.

[0306] In this way, oxygen vacancies in region 371 of material layer 352 and V are selectively removed. O By removing H, region 371 can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to region 372, which functions as a source or drain region, can be suppressed, thereby maintaining n-type configuration. This suppresses variations in the electrical properties of cell transistors CTrA and CTrB, and prevents variations in the electrical properties of cell transistors within the semiconductor device.

[0307] Furthermore, when a material containing silicon is used as the material layer 352, that is, when the cell transistors CTrA and CTrB in Figure 28 are Si transistors, after the formation of the openings 393A and 392B, recesses 393A and 393B, respectively, an impurity may be supplied to the region 371 of the material layer 352 exposed to the recesses 393A and 393B from the openings 392A and 392B, respectively. In this case, Figure 36A shows the process 10 in which impurities are supplied to the material layer 352 exposed to the recesses 393A and 393B. It is preferable to perform heat treatment on the semiconductor device while process 10 is being carried out. When the cell transistors CTrA and CTrB are n-type transistors, p-type impurities (acceptors) are used as impurities in order to make region 371 a p-type channel formation region. Examples of p-type impurities include boron, aluminum, and gallium. Furthermore, when the cell transistor CTr is a p-type transistor, an n-type impurity (donor) is used as an impurity to make region 371 an n-type channel formation region. Examples of n-type impurities include phosphorus and arsenic.

[0308] Furthermore, in material layer 352, the region not exposed to recesses 393A and 393B, that is, the region 372 in contact with material layers 351a, 351b, and 351c, may have lower resistance than region 371. This is because, for example, a low-resistance compound may be formed by the components contained in conductor 331a (conductor 331b, conductor 331c) and the components of material layer 352 near the interface with material layer 351a (material layers 351b, material layers 351c). Alternatively, the resistance of region 371 becomes higher than that of region 372 due to the process 10. For this reason, region 372 functions as a low-resistance region of cell transistor CTrA and cell transistor CTrB.

[0309] Furthermore, as described above, in the process of supplying oxygen and impurities to the material layer 352, instead of supplying them from the respective openings of region 392A and region 392B, oxygen may be supplied from the terminal outlet as shown in Figure 37B. Alternatively, the process of supplying oxygen to the material layer 352 may be a combination of supplying oxygen from the respective openings of region 392A and region 392B as shown in Figure 37A and supplying oxygen from the terminal outlet as shown in Figure 37B. Note that Figure 37B is a perspective view of the structure shown in Figure 37A.

[0310] In the next step, as shown in Figure 38A, a material layer 353 is formed on the sides of the openings in regions 392A and 392B shown in Figure 36B (the respective sides of insulators 311A ​​to 311C), recesses 393A and 393B.

[0311] When a material having a metal oxide is used as material layer 352, that is, when cell transistors CTrA and CTrB in Figure 28 are OS transistors, it is preferable that the material applicable to material layer 353 be a metal oxide applicable to material layer 351 and / or material layer 352. The description of material layer 351 and material layer 352 formed in the processes shown in Figures 34A and 34B should be considered when determining the metal oxide.

[0312] Furthermore, the material layer 353 may have a configuration in which multiple metal oxides applicable to material layer 351 and / or material layer 352 are stacked.

[0313] Furthermore, after forming the material layer 353, as a process 10, oxygen may be supplied to the material layer 353 and the region of the material layer 352 in contact with the material layer 353 using microwave treatment or the like, similar to the steps shown in Figures 37A and 37B (not shown).

[0314] Furthermore, when a material containing silicon is used as the material layer 352, that is, when the cell transistors CTrA and CTrB in Figure 28 are Si transistors, the material that can be applied to the material layer 353 can be a metal oxide that can be applied to the material layer 351 and / or the material layer 352, or a material that can be applied to the insulator 314 described later.

[0315] In Figure 38A, the thicknesses of material layer 353 and material layer 351c are shown to be equal, but the semiconductor device according to one aspect of the present invention is not limited to this. The thickness of material layer 353 may be thicker or thinner than the thickness of material layer 351c.

[0316] In the next step, as shown in Figure 38B, an insulator 314 is formed on the sides of the openings in regions 392A and 392B shown in Figure 38A, and in the recesses that are formed. In other words, an insulator 314 is formed on the formation surface of the material layer 353.

[0317] As described above, insulator 314 functions as a tunnel insulating film for cell transistors CTrA and CTrB.

[0318] As the insulator 314, it is preferable to use, for example, silicon oxide or silicon oxynitride. Alternatively, as the insulator 314, for example, aluminum oxide, hafnium oxide, or an oxide having aluminum and hafnium may be used. Furthermore, the insulator 314 may be an insulator formed by laminating these materials.

[0319] Furthermore, after forming the insulator 314, as a process 10, oxygen may be supplied to the material layer 353 and the region of the material layer 352 in contact with the material layer 353 via the insulator 314 using microwave processing or the like, similar to the steps shown in Figures 37A and 37B (not shown).

[0320] Furthermore, if at least one of the material layers 351 to 353 is a material containing a metal oxide, the insulator 314 can be an insulator formed by laminating a material applicable to the insulator 313 onto the aforementioned material. In particular, by using a material that has the function of suppressing the permeation of impurities such as oxygen, water, and hydrogen as the insulator 314, it may be possible to prevent the diffusion of water or hydrogen into the material layers 351 to 353 and the desorption of oxygen from the material layers 351 to 353. When microwave treatment is performed as the treatment 10, for example, silicon oxide or silicon oxynitride can be formed on the formation surface of the material layer 353, then the microwave treatment can be performed, and then a material that has the function of suppressing the permeation of impurities such as oxygen, water, and hydrogen can be formed to create the insulator 314.

[0321] In the next step, as shown in Figure 39A, a conductive film 333 is formed on the sides of the openings in regions 392A and 392B shown in Figure 38B, and in the recesses that are formed. In other words, the conductive film 333 is formed on the surface on which the insulator 314 is formed.

[0322] As the conductor 333, for example, a material applicable to the aforementioned conductor 332 can be used. However, the materials applicable to the conductor 333 are not limited to this. Insulators, semiconductors, etc., may be used as substitutes for the conductor 333.

[0323] In the next step, as shown in Figure 39B, the conductive material 333 in the remaining parts of recesses 393A and 393B, and the conductive material 333 contained in regions 392A and 392B are removed by resist mask formation and etching, etc., so that conductive material 333 remains in parts of recesses 393A and 393B. As a result, conductive material 333a is formed in recess 393A and conductive material 333b is formed in recess 393B.

[0324] As mentioned above, conductor 333a functions as the floating gate electrode of cell transistor CTrA. Similarly, as mentioned above, conductor 333b functions as the floating gate electrode of cell transistor CTrB.

[0325] For details regarding the formation of the resist mask and the etching process, please refer to the explanation in Figure 32B.

[0326] In Figure 39B, the film thicknesses of conductor 333a and conductor 333b are shown to be thicker than, for example, the film thicknesses of material layer 351a (material layer 351b, material layer 351c), conductor 331a (conductor 331b, conductor 331c), and insulator 312a (insulator 312b, insulator 312c), but the semiconductor device according to one embodiment of the present invention is not limited thereto. The film thickness of conductor 333a to fill a portion of recess 393A may be thicker, as long as insulator 315 and conductor 334a are formed in recess 393A in a later process. Also, the film thickness of conductor 333a may be thin, as long as conductor 333a functions as a floating gate electrode. Similarly, the thickness of the conductor 333b to fill a portion of the recess 393B may be increased if the insulator 315 and the conductor 334b ​​are formed in the recess 393B in a later step, and the thickness of the conductor 333b may be decreased if the conductor 333b functions as a floating gate electrode.

[0327] In the next step, as shown in Figure 40A, an insulator 315 is formed on the sides of the openings and recesses of regions 392A and 392B shown in Figure 39B. In other words, an insulator 315 is formed on the formation surface of the conductor 333a, the formation surface of the conductor 333b, and the formation surface of the insulator 314.

[0328] As mentioned above, insulator 315 functions as a gate insulating film for cell transistors CTrA and CTrB.

[0329] Preferably, the insulator 315 is silicon oxide or silicon oxynitride. Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium can be used as the insulator 315. The insulator 315 may also be an insulator formed by laminating these materials. Preferably, the insulator 315 is thicker than the insulator 314. By making the insulator 315 thicker than the insulator 314, charge can be transferred from the material layer 353 to the conductors 333a and 333b via the insulator 314.

[0330] In the next step, as shown in Figure 40B, a conductive film 334 is formed on the sides of the openings in regions 392A and 392B shown in Figure 39A, and in the recesses that are formed. In other words, the conductive film 334 is formed on the surface on which the insulator 315 is formed.

[0331] For example, the conductor 334 can be a material that can be applied to the aforementioned conductor 332.

[0332] In the next step, as shown in Figure 41, the conductor 334 contained in regions 392A and 392B is removed by resist mask formation and etching, etc., so that the conductor 334 remains only in the aforementioned recesses. This forms conductors 334a and 334b. At this time, the exposed portion of the insulator 315 may also be removed.

[0333] For details regarding the formation of the resist mask and the etching process, please refer to the explanation in Figure 32B.

[0334] As described above, conductor 334a functions as the gate electrode of cell transistor CTrA and as a word line that supplies potential to said gate electrode. Similarly, as described above, conductor 334b ​​functions as the gate electrode of cell transistor CTrB and as a word line that supplies potential to said gate electrode.

[0335] In the next step, as shown in Figure 28A, an insulator 316A is formed so as to fill the opening in region 392A, and an insulator 316B is formed so as to fill the opening in region 392B.

[0336] For example, the insulators 316A and 316B can be made from materials that are applicable to the insulator 313 described above.

[0337] By performing the steps described above, the semiconductor device shown in Figure 28A can be manufactured.

[0338] <Example of semiconductor device configuration 10> An example of a semiconductor device configuration that functions as a memory device according to one aspect of the present invention is not limited to the configurations shown in Figures 28, 29A, and 29B. Depending on the circumstances, the configuration of the semiconductor device may be a circuit configuration that appropriately modifies Figures 28, 29A, and 29B.

[0339] For example, the configuration of the semiconductor device shown in Figures 28, 29A, and 29B may be changed to the configuration of the semiconductor device shown in Figures 42A, 43A, and 43B. Figure 42A is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device shown in Figures 28, 29A, and 29B. Figure 43A is a top view of the area shown by the dashed line B1-B2 in Figure 42, and Figure 43B is a top view of the area shown by the dashed line B3-B4 in Figure 42. Note that in the cross-sectional view of Figure 42, the top view of Figure 43A, and the top view of Figure 43B, some elements have been omitted for clarity.

[0340] In the semiconductor devices shown in Figures 42A, 43A, and 43B, the process shown in Figure 42B is performed instead of the process shown in Figure 36B, and a portion of the material layer 352 is removed by etching or the like to such an extent that the insulator 313 is not exposed in the recesses 393A and 393B. Thus, in a semiconductor device according to one aspect of the present invention, the thickness of the material layer 352 may differ between the region 371 of the material layer 352 in which the recesses 393A and 393B are formed and the region 372 of the material layer 352 superimposed on the conductor 331a (conductor 331b, conductor 331c).

[0341] <Semiconductor device configuration example 11> Furthermore, for example, the configuration of the semiconductor device shown in Figures 28, 29A, and 29B may be changed to the configuration of the semiconductor device shown in Figures 44, 45A, and 45B. Figure 44 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device shown in Figures 28, 29A, and 29B. Also, Figure 45A is a top view of the area shown by the dashed-dotted line C1-C2 in Figure 44, and Figure 45B is a top view of the area shown by the dashed-dotted line C3-C4 in Figure 44. Note that in the cross-sectional view of Figure 44, the top view of Figure 45A, and the top view of Figure 45B, some elements have been omitted for clarity.

[0342] The semiconductor devices in Figures 44, 45A, and 45B are configured such that, after the process shown in Figure 40B, a resist mask is formed and etching is performed to remove the material layer 353, insulator 314, insulator 315, and conductor 334 contained in regions 392A and 392B, and an insulator 316A is deposited so as to fill the opening in region 392A, and an insulator 316B is deposited so as to fill the opening in region 392B.

[0343] In other words, the semiconductor devices in Figures 44, 45A, and 45B are configured such that, after the process shown in Figure 40B, the insulators 314, 315, and material layer 353 are removed to the extent that the conductors 334a and 334b ​​remain. At this time, a portion of the insulators 311A ​​to 311C may also be removed. In Figure 44, the material layer 353a, insulators 314a, insulators 315a, and conductors 334a are formed in recess 393A, and the material layer 353b, insulators 314b, insulators 315b, and conductors 334b ​​are formed in recess 393B.

[0344] Furthermore, the etching process after the steps shown in Figure 40B may be stopped until a portion of the insulator 315 is removed and the insulator 314 is exposed at the opening of region 392A, or until a portion of the insulator 314 is removed and the material layer 353 is exposed at the opening of region 392A, thereby forming the insulators 316A and 316B shown in Figure 28 on the sides of the respective openings of region 392A and region 392B (not shown).

[0345] For details regarding the formation of the resist mask and the etching process, please refer to the explanation in Figure 32B.

[0346] <Example of semiconductor device configuration 12> Furthermore, for example, the configuration of the semiconductor device shown in Figures 28, 29A, and 29B may be changed to the configuration of the semiconductor device shown in Figures 46, 47A, and 47B. Figure 46 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device shown in Figures 28, 29A, and 29B. Also, Figure 47A is a top view of the area shown by the dashed-dotted line D1-D2 in Figure 46, and Figure 47B is a top view of the area shown by the dashed-dotted line D3-D4 in Figure 46. Note that in the cross-sectional view of Figure 46, the top view of Figure 47A, and the top view of Figure 47B, some elements have been omitted for clarity.

[0347] The semiconductor devices shown in Figures 46, 47A, and 47B are configured such that the process shown in Figure 36B or Figure 37A does not involve the process of forming the material layer 353 shown in Figure 38A, but rather the process from Figure 38B onward. If the insulator 314 functions sufficiently as a barrier insulating film to prevent the diffusion of impurities into the material layer 352, the material layer 353 does not need to be provided. In this case, since it is not necessary to provide the material layer 353, the process of manufacturing the semiconductor device can be shortened.

[0348] <Example 13 of semiconductor device configuration> Furthermore, for example, the configurations of the semiconductor devices shown in Figures 28, 29A, and 29B may be changed to the configurations of the semiconductor devices shown in Figures 48 and 49. Figure 48 is a cross-sectional view of a semiconductor device with a configuration different from that of the semiconductor devices shown in Figures 28, 29A, and 29B. Figure 49 is a top view of the area indicated by the dashed-dotted line E3-E4 in Figure 48. Note that the top view of the area indicated by the dashed-dotted line E1-E2 in Figure 48 may have a configuration that is almost the same as that of Figure 29A. Note that in the cross-sectional view of Figure 48 and the top view of Figure 49, some elements have been omitted for clarity.

[0349] The semiconductor devices in Figures 48 and 49 are configured such that the process shown in Figure 33B does not involve the process of forming the material layer 351 shown in Figure 34A, but rather the process from Figure 34B onward. If the components and impurities contained in the material layer 352 do not diffuse into the conductor 331a (conductor 331b, conductor 331c) and the conductivity of the conductor 331a (conductor 331b, conductor 331c) does not decrease, then it is not necessary to provide the material layer 351 which functions as a barrier film for those components and impurities. In this case, since it is not necessary to provide the material layer 351, the process for manufacturing the semiconductor device can be shortened.

[0350] <Example of semiconductor device configuration 14> Furthermore, for example, the configurations of the semiconductor devices shown in Figures 28, 29A, and 29B may be changed to the configurations of the semiconductor devices shown in Figures 50 and 51. Figure 50 is a cross-sectional view of a semiconductor device with a configuration different from that of the semiconductor devices shown in Figures 28, 29A, and 29B. Figure 51 is a top view of the area indicated by the dashed-dotted line F3-F4 in Figure 50. Note that the top view of the area indicated by the dashed-dotted line F1-F2 in Figure 50 may have a configuration that is almost the same as that of Figure 29A. Note that in the cross-sectional view of Figure 50 and the top view of Figure 51, some elements have been omitted for clarity.

[0351] The semiconductor devices in Figures 50 and 51 are configured such that the process from Figure 33B onward is performed without performing the step of forming the insulator 312 shown in Figure 33A, as shown in Figure 32B. If the components and impurities contained in the insulator 311A ​​(insulator 311B, insulator 311C) do not diffuse into the conductor 331a (conductor 331b, conductor 331c) and the conductivity of the conductor 331a (conductor 331b, conductor 331c) does not decrease, then it is not necessary to provide the insulator 312 which functions as a barrier insulating film for such components and impurities. In this case, since it is not necessary to provide the insulator 312, the process for manufacturing the semiconductor device can be shortened.

[0352] <Example of semiconductor device configuration 15> Furthermore, for example, the configurations of the semiconductor devices shown in Figures 28, 29A, and 29B may be changed to the configurations of the semiconductor devices shown in Figures 52 and 53. Figure 52 is a cross-sectional view of a semiconductor device with a configuration different from that of the semiconductor devices shown in Figures 28, 29A, and 29B. Figure 53 is a top view of the area indicated by the dashed-dotted line G3-G4 in Figure 52. Note that the top view of the area indicated by the dashed-dotted line G1-G2 in Figure 52 may have a configuration that is almost the same as that of Figure 29A. Note that in the cross-sectional view of Figure 52 and the top view of Figure 53, some elements have been omitted for clarity.

[0353] The semiconductor device shown in Figures 52 and 53 is configured such that, in the process shown in Figure 32B, a conductor is formed on the side surface of the opening of region 391, and the processes from Figure 33A to 34A are omitted, and the processes from Figure 34B onward are performed. Note that a portion of the conductor is removed in the process of forming recesses 393A and 393B in Figure 36B. This results in the formation of conductors 361a, 361b, and 361c shown in Figure 52.

[0354] It is preferable that the conductors 361a, 361b, and 361c are conductive materials such that a low-resistance region is formed near the interface with the material layer 352.

[0355] For example, if the material layer 352 is a material containing a metal oxide, the resistance values ​​of the conductors 361a, 361b, and 361c are 2.4 × 10⁻⁶. 3 [Ω / sq] or less, preferably 1.0 × 10 3 A metal, a nitride containing a metallic element, or an oxide containing a metallic element with a conductivity of [Ω / sq] or less is used. As the conductive material, for example, a metal film such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium, a nitride film containing a metallic element such as Al-Ti nitride or titanium nitride, or an oxide film containing a metallic element such as indium tin oxide or In-Ga-Zn oxide can be used.

[0356] Furthermore, the conductors 361a, 361b, and 361c are not limited to the conductive materials described above, as long as they serve to reduce the resistance of the material layer 352. For example, insulators such as silicon nitride may be used as substitutes for conductors 361a, 361b, and 361c.

[0357] Furthermore, in Figure 36B, after the steps of forming recesses 393A and 393B and conductors 361a, 361b, and 361c, heat treatment may be performed on the material layer 352 in the region where the conductors 361a, 361b, and 361c are in contact, and a compound may be formed near the interface between the material layer 352 and the conductors 361a, 361b, and 361c due to the components contained in the conductors 361a, 361b, and 361c and the components contained in the material layer 352. This compound reduces the resistance of the region 372 of the material layer 352 that is in contact with the conductors 361a, 361b, and 361c.

[0358] Furthermore, the heat treatment may be carried out in an atmosphere containing nitrogen. Through this heat treatment, metallic elements that are components of conductor 361a (conductor 361b, and conductor 361c) may diffuse into the material layer 352, or metallic elements that are components of the material layer 352 may diffuse into conductor 361a (conductor 361b, and conductor 361c), and the material layer 352 and conductor 361a, conductor 361b, and conductor 361c may form a metallic compound. In this case, the metallic elements of the material layer 352 and the metallic elements of conductor 361a, conductor 361b, and conductor 361c may be alloyed. The metal elements in material layer 352 are alloyed with the metal elements in conductors 361a, 361b, and 361c, resulting in a relatively stable state for the metal elements, thus enabling the provision of a highly reliable semiconductor device.

[0359] Furthermore, through this heat treatment, hydrogen in the material layer 352 diffuses into the region 372 of the material layer 352 in contact with the conductors 361a, 361b, and 361c, and becomes relatively stable when it enters the oxygen vacancies present in that region. Also, hydrogen in the oxygen vacancies present in the region 371 of the material layer 352 exposed to the recesses 393A and 393B escapes from the oxygen vacancies through heat treatment at 250°C or higher, diffuses into region 372, and enters the oxygen vacancies present in region 372 of the material layer 352, becoming relatively stable. Therefore, through heat treatment, region 372 becomes less resistant, and region 371 is purified (reduced impurities such as water and hydrogen) and becomes more resistant.

[0360] Furthermore, for example, if the material layer 352 is a silicon-containing material, the material layer 352 comes into contact with the conductors 361a, 361b, and 361c, and impurities (elements, ions, etc.) contained in the conductors 361a, 361b, and 361c may diffuse into the material layer 352. In this case, depending on the situation, or in some cases, it is preferable to perform heat treatment after the process of forming the recesses 393A and 393B in Figure 36B and the conductors 361a, 361b, and 361c. In other words, an impurity region is formed on the surface of the material layer 352 that comes into contact with the conductors 361a, 361b, and 361c, and near the interface.

[0361] If the impurities contained in conductors 361a, 361b, and 361c are n-type impurities (donors), an n-type impurity region may be formed in region 372 of the material layer 352, or near the interface between the material layer 352 and conductors 361a, 361b, and 361c. On the other hand, if the impurities contained in conductors 361a, 361b, and 361c are p-type impurities (acceptors), a p-type impurity region may be formed in region 372 of the material layer 352, or near the interface between the material layer 352 and conductors 361a, 361b, and 361c. In other words, this can lead to the formation of carriers in region 372 of the material layer 352, or near the interface between region 372 of the material layer 352 and conductors 361a, 361b, and 361c, potentially reducing the resistance of region 372.

[0362] Furthermore, by heat treatment, metal silicide may be formed near the interface between the conductive material contained in conductors 361a, 361b, and 361c and the components contained in material layer 352 in region 372 of material layer 352. The formation of metal silicide near the interface between the conductive material contained in conductors 361a, 361b, and 361c in region 372 of material layer 352 may reduce the resistance of the area near the interface between the conductive material contained in conductors 361a, 361b, and 361c in region 372 of material layer 352.

[0363] Furthermore, when manufacturing the semiconductor devices shown in Figures 52 and 53, it is preferable not to perform heat treatment in a step prior to the step in Figure 36B in which recesses 393A and 393B are formed, as well as the step in which conductors 361a, 361b, and 361c are formed. This is because, in the step shown in Figure 32B, a conductor for forming conductors 361a, 361b, and 361c is deposited on the material layer 352, and if heat treatment is performed at this stage, the resistance may be reduced in the region of the material layer 352 that is in contact with the conductor. Therefore, when manufacturing the semiconductor devices shown in Figures 52 and 53, it is preferable to perform the heat treatment described above after the recesses 393A and 393B are formed, as well as the conductors 361a, 361b, and 361c are formed in Figure 36B.

[0364] <Semiconductor device configuration example 16> Furthermore, for example, the configuration of the semiconductor device shown in Figures 28, 29A, and 29B may be changed to the configuration of the semiconductor device shown in Figures 54, 55A, and 55B. Figure 54 is a cross-sectional view of a semiconductor device different from the configuration of the semiconductor device shown in Figures 28, 29A, and 29B. Also, Figure 55A is a top view of the area shown by the dashed-dotted line H1-H2 in Figure 54, and Figure 55B is a top view of the area shown by the dashed-dotted line H3-H4 in Figure 54. Note that in the cross-sectional view of Figure 54, the top view of Figure 55A, and the top view of Figure 55B, some elements have been omitted for clarity.

[0365] The semiconductor devices shown in Figures 54, 55A, and 55B are configured such that the process shown in Figure 35A does not involve the process of forming the conductor 332 shown in Figure 35B, but rather the process from Figure 36A onward.

[0366] In other words, the semiconductor devices shown in Figures 54, 55A, and 55B are configured without a second gate electrode and wiring that supplies potential to the second gate electrode.

[0367] Furthermore, an example of the configuration of a semiconductor device that functions as a memory device according to one aspect of the present invention may be a combination of the semiconductor device configuration examples 9 to 16 described above, selected as appropriate.

[0368] Furthermore, the insulators, conductors, semiconductors, material layers, etc., disclosed in this embodiment can be formed by the film formation method described in Embodiment 1.

[0369] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0370] (Embodiment 3) In this embodiment, we will describe an example configuration for increasing the memory capacity of the semiconductor device described in Embodiment 1 and Embodiment 2. While this embodiment uses the semiconductor device described in Embodiment 2 as an example, this embodiment can also be applied to the semiconductor device described in Embodiment 1.

[0371] Figures 56A and 56B are top views showing the configuration of a semiconductor device in which an insulator 319 is newly formed in region 391 and outside region 391, as shown in Figures 29A and 29B.

[0372] Specifically, in regions 391 and outside region 391 in Figures 29A and 29B, an opening is first formed, and then an insulator 319 is formed to fill the opening.

[0373] As the insulator 319, for example, a material applicable to insulators 311A ​​to 311C can be used. Specifically, as the insulator 319, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride, aluminum oxide nitride, etc. can be used. Alternatively, the insulator 319 may be a film having multiple layers rather than a single film.

[0374] In Figure 56A, the opening is formed, for example, so that region 391 is divided and the conductor 332 is divided into two parts: conductor 332_1 and conductor 332_2. In other words, by forming an opening in region 391, each of the conductor 332, insulator 313, material layer 352, material layer 353, insulator 314, conductor 333b, and insulator 315 contained within region 391 are divided into two parts. Figure 56A shows a configuration in which conductor 332 is divided into two parts, conductor 332_1 and conductor 332_2; insulator 313 is divided into two parts, insulator 313_1 and insulator 313_2; material layer 352 is divided into two parts, material layer 352_1 and material layer 352_2; material layer 353 is divided into two parts, material layer 353_1 and material layer 353_2; insulator 314 is divided into two parts, insulator 314_1 and insulator 314_2; conductor 333b is divided into two parts, conductor 333b_1 and conductor 333b_2; and insulator 315 is divided into two parts, insulator 315_1 and insulator 315_2.

[0375] Furthermore, by forming openings in region 391 and its surroundings as shown in Figure 56A, region 391 and its surroundings in Figure 29B will have the configuration shown in Figure 56B. Specifically, Figure 56B shows a configuration in which the conductor 332 is divided into two parts, conductor 332_1 and conductor 332_2; the insulator 313 is divided into two parts, insulator 313_1 and insulator 313_2; the material layer 352 is divided into two parts, material layer 352_1 and material layer 352_2; the material layer 351 is divided into two parts, material layer 351a_1 and material layer 351a_2; the conductor 331a is divided into two parts, conductor 331a_1 and conductor 331a_2; and the insulator 312a is divided into two parts, insulator 312a_1 and insulator 312a_2.

[0376] As shown in Figures 56A and 56B, by configuring the semiconductor device so that the region 391 is divided by the insulator 319, the number of cell transistors provided in region 391 can be doubled. In other words, the number of strings provided in region 391 can be doubled, so the semiconductor device having the configuration shown in Figures 56A and 56B can have a larger memory capacity than the semiconductor device having the configuration shown in Figures 29A and 29B.

[0377] Furthermore, the semiconductor device according to one aspect of the present invention is not limited to the configuration shown in Figures 56A and 56B. Although Figures 56A and 56B show a configuration in which region 391 is divided into two, a configuration in which region 391 is divided into three may also be used, for example, as shown in Figure 57A. Alternatively, a configuration in which region 391 is divided into four may also be used, for example, as shown in Figure 57B.

[0378] Figure 57A shows an example of a configuration in which region 391 in Figure 29B is divided into three parts. Specifically, Figure 57A shows a configuration in which conductor 332 is divided into three parts: conductor 332_1, conductor 332_2, and conductor 332_3; insulator 313 is divided into three parts: insulator 313_1, insulator 313_2, and insulator 313_3; material layer 352 is divided into three parts: material layer 352_1, material layer 352_2, and material layer 352_3; material layer 351a is divided into three parts: material layer 351a_1, material layer 351a_2, and material layer 351a_3; conductor 331a is divided into three parts: conductor 331a_1, conductor 331a_2, and conductor 331a_3; and insulator 312a is divided into three parts: insulator 312a_1, insulator 312a_2, and insulator 312a_3.

[0379] Furthermore, Figure 57B shows an example of a configuration in which region 391 in Figure 29B is divided into four parts. Specifically, in Figure 57A, the conductor 332 is divided into four parts: conductor 332_1, conductor 332_2, conductor 332_3, and conductor 332_4; the insulator 313 is divided into four parts: insulator 313_1, insulator 313_2, insulator 313_3, and insulator 313_4; the material layer 352 is divided into four parts: material layer 352_1, material layer 352_2, material layer 352_3, and material layer 352_4; and material layer 351 This diagram shows a structure in which material layer a is divided into four parts: material layer 351a_1, material layer 351a_2, material layer 351a_3, and material layer 351a_4; conductor 331a is divided into four parts: conductor 331a_1, conductor 331a_2, conductor 331a_3, and conductor 331a_4; and insulator 312a is divided into four parts: insulator 312a_1, insulator 312a_2, insulator 312a_3, and insulator 312a_4.

[0380] Furthermore, although the above examples show configurations in which the region 391 of the semiconductor device is divided into two, three, and four parts, a semiconductor device according to one aspect of the present invention may have a configuration in which the region 391 is divided into five or more parts.

[0381] Furthermore, one aspect of the present invention of a semiconductor device may be configured such that, instead of providing one opening for each region 391 as shown in Figures 56A and 56B, an opening is provided that spans two or more regions 391, and an insulator 319 is embedded in the opening. Specifically, as shown in Figure 58A, in a configuration in which multiple regions 391 are provided between two slit-shaped regions 392, an opening may be provided that is generally parallel to the slit-shaped regions 392 and spans the conductive material 332 of the multiple regions 391, and an insulator 319 is embedded in the opening.

[0382] Incidentally, in the configuration of Figure 58A, the word line electrically connected to the first gate of the cell transistor is provided between insulator 311A ​​and insulator 311B, and between insulator 311B and insulator 311C, as shown in Figure 28. Therefore, when an opening is provided that spans multiple regions 391 and an insulator 319 is provided in the opening, it is necessary to provide the opening so that the first gate and word line of the cell transistor are in a conductive state with the external circuit, etc. Specifically, in the configuration of Figure 58A, the insulator 319 is provided so as to be roughly parallel to the slit-shaped region 392, so that the first gate and word line of the cell transistor are in a conductive state with the external circuit, etc.

[0383] Furthermore, the position and shape of the opening and the insulator 319 are not particularly limited, as long as the first gate and word line of the cell transistor are configured to be conductive with an external circuit or the like. For example, as shown in Figure 58B, an opening may be provided in a direction that is at an angle to the slit-shaped region 392, and the insulator 319 may be provided in the opening. In this case, by ensuring that a part of the opening is not formed inside the regions 392 on both sides of the upper surface of Figure 58B, the first gate and word line of the cell transistor can be made conductive with an external circuit or the like, and the semiconductor device configured in Figure 58B can be operated. Conversely, if the opening extends inside the regions 392 on both sides, the first gate of the cell transistor will be in a non-conductive state with an external circuit or the like, and the semiconductor device in this case will not operate normally.

[0384] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0385] (Embodiment 4) This embodiment describes metal oxides (hereinafter also referred to as oxide semiconductors) that can be used in the OS transistor described in the above embodiment.

[0386] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0387] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 59A. Figure 59A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0388] As shown in Figure 59A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous materials. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and polycrystal). Note that single crystal, polycrystal, and completely amorphous materials are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal materials.

[0389] The structure within the thick frame shown in Figure 59A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0390] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 59B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" (the vertical axis represents intensity in arbitrary units (au)). The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 59B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 59B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 59B is 500 nm.

[0391] As shown in Figure 59B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 59B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0392] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 59C. Figure 59C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 59C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0393] As shown in Figure 59C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0394] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 59A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0395] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0396] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0397] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0398] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0399] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0400] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0401] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0402] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0403] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be considered an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0404] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0405] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0406] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0407] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0408] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0409] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0410] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0411] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0412] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0413] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0414] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0415] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0416] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0417] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm-3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations may be referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0418] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0419] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0420] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0421] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0422] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels within the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are compared by 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 17atoms / cm 3 The following applies:

[0423] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0424] In this specification, normally-on refers to a state in which a channel exists and current flows through the transistor even without applying a voltage to the gate. Normally-off refers to a state in which, when no potential is applied to the gate or when the gate is given a ground potential, the current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ -18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0425] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17atoms / cm 3 Do the following:

[0426] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons, which act as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0427] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0428] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0429] (Embodiment 5) In this embodiment, we will describe a NAND memory, which is an example of a semiconductor device described in Embodiment 1.

[0430] <Example of a semiconductor device circuit configuration> First, the circuit configuration of a NAND memory, which is an example of a semiconductor device, will be explained with reference to Figure 60A. Figure 60A shows the circuit diagram of a single-string NAND memory. A single-string NAND memory has memory cells MC[1] to MC[n], wiring WL[1] to WL[n] for controlling them, wiring BL and wiring SL, transistors STr and BTr for selecting the string, wiring SSL for controlling transistor STr, and wiring BSL for controlling transistor BTr. Wiring WL functions as wiring that applies potential to the control gate (sometimes simply referred to as the gate in this specification, etc.) of the cell transistor of the memory cell MC, which will be described later, and wiring SL and wiring BL may function as wiring that applies potential to the first terminal and / or second terminal of the cell transistor of the memory cell MC, which will be described later.

[0431] Each memory cell MC has a cell transistor CTr. Generally, a cell transistor is a transistor that operates with normally-on characteristics and has a control gate and a charge storage layer. The charge storage layer is provided in a region overlapping with the channel formation region via a tunnel insulating film, and the control gate is provided in a region overlapping with the charge storage layer via a blocking film. When a write potential is applied to the control gate of the cell transistor and a predetermined potential is applied to either the first or second terminal of the cell transistor, a tunnel current is generated, and electrons are injected from the channel formation region of the cell transistor into the charge storage layer. As a result, the threshold voltage of the cell transistor into which electrons have been injected into the charge storage layer becomes higher. NAND memory is a semiconductor device that utilizes this principle, and the detailed operating principle will be described later. Note that a floating gate may be used instead of a charge storage layer, and in Embodiment 2, the cell transistor included in the semiconductor device is described as a transistor having a floating gate.

[0432] The first terminal of the cell transistor CTr is electrically connected in series with the second terminal of the cell transistor CTr of the adjacent memory cell MC. In other words, the circuit configuration shown in Figure 1A consists of n cell transistors CTr electrically connected in series. In addition, the second terminal of the cell transistor CTr of memory cell MC[1] is electrically connected with the first terminal of transistor STr, and the first terminal of the cell transistor CTr of memory cell MC[n] is electrically connected with the first terminal of transistor BTr. Furthermore, the control gate of each cell transistor CTr of memory cells MC[1] through MC[n] is electrically connected with the respective wirings WL[1] through WL[n]. The second terminal of transistor STr is electrically connected with wiring SL, and the gate of transistor STr is electrically connected with wiring SSL. The second terminal of transistor BTr is electrically connected with wiring BL, and the gate of transistor BTr is electrically connected with wiring BSL.

[0433] The channel formation region of the cell transistor CTr preferably contains one or more materials selected from among silicon, germanium, gallium arsenide, silicon carbide (SiC), and metal oxides described in Embodiment 4. In particular, when the channel formation region contains one or more metal oxides selected from indium, element M (for example, aluminum, gallium, yttrium, tin, etc. as element M), and zinc, the metal oxide may function as a wide-bandgap semiconductor, and a cell transistor in which the metal oxide is included in the channel formation region has the characteristic of having a very low off-current. In other words, the leakage current in the cell transistor CTr when it is in the off state can be reduced, which may reduce the power consumption of the semiconductor device. Furthermore, the channel formation regions of transistor STr and transistor BTr can also contain the above-mentioned metal oxides.

[0434] Furthermore, the channel formation region of transistor STr and / or transistor BTr can have a different configuration from that of cell transistor CTr. For example, a material containing the aforementioned metal oxide can be applied to the channel formation region of cell transistor CTr, while a material containing silicon can be applied to the channel formation region of transistor STr and / or transistor BTr.

[0435] One aspect of the present invention is not limited to the semiconductor device shown in Figure 60A. Depending on the circumstances, or as needed, one aspect of the present invention may be a circuit configuration that appropriately modifies the semiconductor device shown in Figure 60A. For example, one aspect of the present invention may be a semiconductor device in which a back gate is provided on the cell transistor CTr, as shown in Figure 60B. The semiconductor device shown in Figure 60B has, in addition to the configuration of the semiconductor device shown in Figure 1A, a back gate is provided on the cell transistor CTr of the memory cells MC[1] to MC[n], and wiring BGL is electrically connected to each of the back gates. The semiconductor device shown in Figure 60B may not have wiring BGL electrically connected to each of the back gates of the cell transistor CTr of the memory cells MC[1] to MC[n], but rather may have wiring BGL electrically connected independently to each of the back gates, supplying each with a different potential. An example of the operation of the semiconductor device shown in Figure 60B will be described later.

[0436] By the way, if you want to further increase the memory capacity of the semiconductor devices shown in Figures 60A and 60B, you can arrange the semiconductor devices shown in Figures 60A and 60B in a matrix. For example, if you arrange the semiconductor devices shown in Figure 60A in a matrix, the circuit configuration will be as shown in Figure 61. In this specification, the multiple strings of NAND memory shown in Figure 61 will be referred to as one block of NAND memory.

[0437] The semiconductor device shown in Figure 61 is constructed by arranging the semiconductor devices shown in Figure 60A in m columns (where m is an integer greater than or equal to 1), with the wiring WL being electrically connected to the memory cells MC in the same row. In other words, the semiconductor device shown in Figure 61 is an n x m matrix-shaped semiconductor device with memory cells MC[1,1] to MC[n,m]. Therefore, the semiconductor device shown in Figure 61 is electrically connected by wiring WL[1] to WL[n], wiring BL[1] to BL[m], wiring BSL[1] to BSL[m], wiring SL[1] to SL[m], and wiring SSL[1] to SSL[m]. Specifically, the control gate of the cell transistor CTr of the memory cell MC[j,i] (where j is an integer greater than or equal to 1 and n, and i is an integer greater than or equal to 1 and m) is electrically connected to wiring WL[j]. Wiring SL[i] is electrically connected to the second terminal of transistor STr[i], and wiring BL[i] is electrically connected to the second terminal of transistor BTr.

[0438] Note that Figure 61 only shows memory cells MC[1,1], memory cells MC[1,i], memory cells MC[1,m], memory cells MC[j,1], memory cells MC[j,i], memory cells MC[j,m], memory cells MC[n,1], memory cells MC[n,i], memory cells MC[n,m], wiring WL[1], wiring WL[j], wiring WL[n], wiring BL[1], wiring BL[i], wiring BL[m], wiring BSL[1], wiring BSL[i], wiring BSL[m], wiring SL[1], wiring SL[i], wiring SL[m], wiring SSL[1], wiring SSL[i], wiring SSL[m], cell transistor CTr, transistor BTr[1], transistor BTr[i], transistor BTr[m], transistor STr[1], transistor STr[i], and transistor STr[m].

[0439] Furthermore, Figure 62 shows the semiconductor device shown in Figure 60B arranged in m rows (where m is an integer greater than or equal to 1). The semiconductor device shown in Figure 62 has a configuration in which each transistor in all memory cells (MCs) is provided with a back gate. Therefore, the semiconductor device shown in Figure 62 has wiring BGL[1] to BGL[m] for electrically connecting to each back gate. For details regarding the semiconductor device shown in Figure 62, please refer to the description of the semiconductor device shown in Figure 61.

[0440] The semiconductor devices shown in Figures 61 and 62 are configured by arranging Figures 60A and 60B in a matrix, respectively, but the present invention is not limited to this. Depending on the circumstances or as needed, the circuit configuration can be changed. For example, in Figures 61 and 62, wiring BSL[1] to wiring BSL[m] are shown as wiring to control transistors BTr[1] to transistors BTr[m], respectively, but they may also be configured as a single wire electrically connected to the respective gates of transistors BTr[1] to transistors BTr[m]. Similarly, the wiring to control transistors STr[1] to transistors STr[m] may also be configured as a single wire electrically connected to the respective gates of transistors STr[1] to transistors STr[m], instead of wiring SSL[1] to wiring SSL[m].

[0441] <<Example of operation>> Next, an example of the operation method of the semiconductor device shown in Figures 60A and 60B will be explained using Figures 63A, 63B, 64A, and 64B. Note that a semiconductor device according to one embodiment of the present invention may be capable of handling not only binary data, but also multi-level or analog data. Therefore, in this explanation of the operation method, the data handled for writing and reading will not be limited to binary data.

[0442] In addition, the low-level potential and high-level potential used in the following description do not mean specific potentials, and if the wiring is different, the specific potentials may also be different. For example, each of the low-level potential and high-level potential applied to the wiring BSL may be a potential different from the low-level potential and high-level potential applied to the wiring BL.

[0443] Potential V PGM is a potential that can inject electrons into the charge storage layer of the cell transistor CTr by being applied to the control gate of the cell transistor CTr. The potential V PS is a potential that can turn on the cell transistor CTr by being applied to the control gate of the cell transistor CTr.

[0444] In addition, in this operation method example, it is assumed that a potential within the range where the cell transistor CTr operates normally is applied in advance to the wiring BGL shown in FIG. 60B, unless otherwise specified. Therefore, the operations of the semiconductor devices shown in FIGS. 60A and 60B can be considered similarly to each other.

[0445] [Write operation] FIG. 63A is a timing chart showing an operation example of writing data to a semiconductor device. The timing chart of FIG. 63A shows changes in the magnitudes of the potentials of the wiring WL[p] (p is an integer from 1 to n), the wiring WL[j] (where j here is an integer from 1 to n and not p), the wiring BSL, the wiring SSL, and the wiring BL. Note that the timing chart of FIG. 63A shows an operation example of writing data to the memory cell MC[p].

[0446] Before time T10, a low-level potential is supplied to the wiring BL.

[0447] Also, between time T10 and time T13, a low-level potential is always supplied to the wiring SSL. As a result, a low-level potential is applied to the gate of the transistor STr, so the transistor STr is turned off.

[0448] Between time T10 and time T11, a high-level potential is supplied to wiring BSL. This applies a high-level potential to the gate of transistor BTr, causing transistor BTr to turn on. Furthermore, when transistor BTr is turned on, a low-level potential supplied from wiring BL is applied to the first terminal of cell transistor CTr of memory cell MC[n].

[0449] Between time T11 and time T12, the wiring WL[j] has a potential V PS This supplies a potential V to the control gate of the cell transistor CTr in the memory cell MC[j]. PS A low-level potential supplied from wiring BL is applied. At this time, in memory cell MC[n], the first terminal of the cell transistor CTr is applied, so the cell transistor CTr in memory cell MC[n] is turned ON. In addition, the low-level potential supplied from wiring BL is applied to the first terminal of the cell transistor CTr in memory cell MC[n-1]. In other words, the cell transistors CTr in memory cell MC[j] are sequentially turned ON.

[0450] Furthermore, between time T11 and time T12, the wiring WL[p] has a potential V PGM This supplies a potential V to the control gate of the cell transistor CTr in the memory cell MC[p]. PGM A low-level potential supplied from wiring BL is applied. Furthermore, due to the aforementioned operation, a low-level potential supplied from wiring BL is applied to the first terminal of the cell transistor CTr of the memory cell MC[p], causing electrons to be injected from the channel formation region of the cell transistor CTr of the memory cell MC[p] into the charge storage layer. This enables data to be written to the memory cell MC[p]. Note that the injection of electrons from the channel formation region of the cell transistor CTr of the memory cell MC[p] into the charge storage layer causes the threshold voltage of the cell transistor CTr to rise.

[0451] Up to time T12, the low-level potential supplied from wiring BL is applied to the first terminal of transistor STr. Between time T12 and time T13, the low-level potential is applied to wiring WL[j] and wiring WL[p].

[0452] From time T13 onward, a low-level potential is supplied to wiring BSL. This applies a low-level potential to the gate of transistor BTr, causing it to turn off. Although not shown in the timing chart in Figure 63A, at this time, transistor BTr can also be turned off by not supplying a low-level potential to wiring BSL and instead setting the potential of wiring BL to a high level.

[0453] Through the above operations, data can be written to the semiconductor devices shown in Figures 60A and 60B.

[0454] [Read operation] Figure 63B is a timing chart showing an example of data reading operation from a semiconductor device. The timing chart in Figure 63A shows the changes in the magnitude of the potentials of wiring WL[p], wiring WL[q] (where q is an integer between 1 and n and not p), wiring WL[j] (where j is an integer between 1 and n and not p or q), wiring BSL, wiring SSL, and wiring SL, and I is the current flowing between wiring SL and wiring BL. READ This shows the change in size. The timing chart in Figure 63B shows an example of data reading operation from memory cell MC[p] and memory cell MC[q]. It is assumed that electrons are injected into the charge storage layer of the cell transistor CTr of memory cell MC[p], and that electrons are not injected into the charge storage layer of the cell transistor CTr of memory cell MC[q].

[0455] Prior to time T20, a low-level potential is supplied to wiring SL.

[0456] Between time T20 and time T21, a high-level potential is supplied to wiring BSL and wiring SSL. As a result, a high-level potential is applied to the gates of transistor BTr and transistor STr, so that transistor BTr and transistor STr are turned on. Also, when transistor STr is turned on, a low-level potential supplied from wiring SL is applied to the second terminal of cell transistor CTr of memory cell MC[1].

[0457] Between time T21 and time T22, potential V PS is supplied to wiring WL[q] and wiring WL[j]. As a result, potential V PS is applied to the control gates of cell transistors CTr of memory cell MC[q] and memory cell MC[j]. At this time, if a low-level potential supplied from wiring SL is applied to the second terminal of cell transistor CTr of memory cell MC[q] and / or memory cell MC[j], that cell transistor CTr is turned on.

[0458] On the other hand, between time T21 and time T22, a low-level potential is supplied to wiring WL[p]. As a result, a low-level potential is applied to the control gate of cell transistor CTr of memory cell MC[p]. Also, since electrons are injected into the charge storage layer of cell transistor CTr of memory cell MC[p], the threshold voltage of cell transistor CTr of memory cell MC[p] has increased. For the above reasons, cell transistor CTr of memory cell MC[p] is turned off, and no current flows between wiring SL and wiring BL. At this time, by measuring the amount of current flowing through wiring BL and indicating that no current flows between wiring SL and wiring BL, it can be said that electrons are injected into the charge storage layer of cell transistor CTr of memory cell MC[p].

[0459] Between time T22 and time T23, a low-level potential is supplied to wiring WL[p], wiring WL[q], and wiring WL[j]. This applies a low-level potential to the control gates of the respective cell transistors CTr in memory cells MC[1] through MC[n].

[0460] Between time T23 and time T24, the potential V is present in the wiring WL[j]. PS This supplies a potential V to the control gate of the cell transistor CTr in the memory cell MC[j]. PS A voltage is applied. At this time, if a low-level potential supplied from the wiring SL is applied to the first terminal of the cell transistor CTr of the memory cell MC[j], the cell transistor CTr will be in the ON state.

[0461] Furthermore, between time T23 and time T24, the wiring WL[p] has a potential V PS This supplies a potential V to the control gate of the cell transistor CTr in the memory cell MC[p]. PS A voltage is applied. Incidentally, since electrons are injected into the charge storage layer of the cell transistor CTr of the memory cell MC[p], the threshold voltage of the cell transistor CTr of the memory cell MC[p] is rising, but the control gate of the cell transistor CTr has a potential V PS Because the current is applied, in this example of operation, the cell transistor CTr is assumed to be effectively in the ON state.

[0462] Then, between time T23 and time T24, a low-level potential is supplied to wiring WL[q]. This applies a low-level potential to the control gate of the cell transistor CTr of the memory cell MC[j]. Since the cell transistor CTr of the memory cell MC operates with normally-on characteristics, even if a low-level potential supplied from wiring SL is applied to the first terminal of the cell transistor CTr of the memory cell MC[j], the cell transistor CTr remains in the ON state.

[0463] In other words, since the cell transistors CTr in each memory cell MC[1] through MC[n] are in the ON state, current flows between their respective source and drain. Therefore, by measuring the amount of current flowing through the wiring BL at this time and showing that current is flowing between the wiring SL and the wiring BL, it can be said that no electrons have been injected into the charge storage layer of the cell transistor CTr of memory cell MC[q].

[0464] Between time T24 and time T25, a low-level potential is supplied to wiring WL[p], wiring WL[q], and wiring WL[j]. This applies a low-level potential to the control gates of the respective cell transistors CTr in memory cells MC[1] through MC[n].

[0465] From time T25 onward, a low-level potential is supplied to wiring BSL and wiring SSL. This applies a low-level potential to the gates of transistors BTr and STr, causing them to turn off.

[0466] In other words, when reading data from a memory cell MC, a low-level potential is applied to the control gate of the cell transistor CTr of the relevant memory cell MC, and a high-level potential is applied to the control gates of the cell transistor CTr of the other memory cell MCs. By measuring the amount of current flowing between the wiring SL and wiring BL, the data held in the memory cell MC can be read.

[0467] Through the above operations, data can be written to and read from the semiconductor device shown in Figures 60A and 60B.

[0468] [Erase operation] Figure 64A is a timing chart showing an example of an operation to erase data held in a semiconductor device. The timing chart in Figure 64A shows the changes in the magnitude of the potentials of wiring WL[j] (where j is an integer between 1 and n), wiring BSL, wiring SSL, wiring BL, and wiring SL. Generally, erasure operations for NAND memory are performed in units of one block, and this operation example follows that convention. However, one aspect of the present invention is not limited to this, and for example, the erasure operation may be performed for each string.

[0469] Prior to time T30, a low-level potential is supplied to wiring BL and wiring SL.

[0470] Furthermore, a low-level potential is constantly supplied to the wiring WL[j] between time T30 and time T33.

[0471] Between time T30 and time T31, a high-level potential is supplied to wiring BSL and wiring SSL. As a result, a high-level potential is applied to the gates of transistors BTr and STr, causing transistors BTr and STr to turn on. Furthermore, as transistors BTr and STr turn on, a low-level potential supplied from wiring SL is applied to the second terminal of cell transistor CTr in memory cell MC[1], and a low-level potential supplied from wiring BL is applied to the first terminal of cell transistor CTr in memory cell MC[n].

[0472] Between time T31 and time T32, the potential V is present in wiring BL and wiring SL. ER It is supplied. ER This is set to a potential higher than the high-level potential flowing through wiring BL and wiring SL. As a result, the potential of the channel formation region of all cell transistors CTr in memory cell MC[1] to memory cell MC[n] rises, and electrons injected into the charge storage layer of each cell transistor CTr are drawn out to the channel formation region.

[0473] Between time T32 and time T33, a low-level potential is supplied to wiring BL and wiring SL.

[0474] From time T33 onward, a low-level potential is supplied to wiring BSL and wiring SSL. This applies a low-level potential to the gates of transistors BTr and STr, causing them to turn off.

[0475] By performing the above steps, data can be erased from the semiconductor devices shown in Figures 60A and 60B.

[0476] Furthermore, in the semiconductor device shown in Figure 60B, a different erasure operation can be performed by using wiring BGL. An example of this operation is shown in Figure 64B.

[0477] Before time T40, a low-level potential is supplied to wiring BL and wiring SL.

[0478] Furthermore, a low-level potential is continuously supplied to the wiring WL[j] between time T40 and time T45.

[0479] Between time T40 and time T41, a low-level potential is supplied to wiring BSL and wiring SSL. This applies a low-level potential to the gates of transistors BTr and STr, causing them to turn off. As a result, the second terminal of transistor STr and the first terminal of transistor BTr become floating.

[0480] Furthermore, between time T40 and time T41, the wiring BGL has a potential V BGER It is supplied. Potential V BGER The potential is set to be very high. The second terminal of transistor STr and the first terminal of transistor BTr are in a floating state, and the potential of wiring BGL is VBGER As a result, the potential of the channel formation region of all cell transistors CTr in memory cell MC[1] to memory cell MC[n] is boosted by capacitive coupling. Therefore, electrons injected into the charge storage layer of each cell transistor CTr are drawn out to the channel formation region.

[0481] Between time T41 and time T42, a high-level potential is supplied to wiring BSL and wiring SSL. As a result, a high-level potential is applied to the gates of transistors BTr and STr, causing transistors BTr and STr to turn on.

[0482] Between time T42 and time T43, a high-level potential is supplied to wiring BL. This allows electrons extracted from the charge storage layer of the cell transistor CTr to flow into wiring BL.

[0483] Between time T43 and T44, a low-level potential is supplied to wiring BL. Subsequently, between time T44 and T45, a low-level potential is supplied to wirings BSL and SSL. As a result, a low-level potential is applied to the gates of transistors BTr and STr, causing them to turn off. Finally, from time T45 onward, a low-level potential is supplied to wiring BGL.

[0484] As described above, data can also be erased from the semiconductor device shown in Figure 60B by using wiring BGL.

[0485] <Example of semiconductor device structure> Next, we will describe an example of the structure of a semiconductor device shown in Figure 61 or Figure 62.

[0486] Figures 65A to 65C are examples of schematic diagrams showing a part of the semiconductor device shown in Figure 61 or Figure 62. Figure 65A shows a perspective view of a part of the semiconductor device, and Figure 65B shows a top view of Figure 65A. Furthermore, Figure 65C shows a cross-sectional view corresponding to the dashed line Z1-Z2 in Figure 65B.

[0487] The semiconductor device has a structure in which wiring WL and an insulator (areas not shown with hatching in Figures 65A to 65C) are stacked.

[0488] An opening is formed in the structure that penetrates both the insulator and the wiring WL simultaneously. To provide a memory cell MC in the region AR through which the wiring WL penetrates, an insulator, a conductor, and a semiconductor are formed in the opening. The conductor functions as the source or drain electrode of the cell transistor CTr of the memory cell MC, and the semiconductor functions as the channel formation region of the cell transistor CTr. Alternatively, the conductor may be omitted, and a channel formation region and a low-resistance region may be formed in the semiconductor, with the low-resistance region being used as the source or drain electrode of the cell transistor CTr. In Figures 65A to 65C, the region in the opening where the insulator, conductor, and semiconductor are formed is shown as region HL. In particular, in Figure 65A, the region HL located inside the structure is shown with a dashed line. If the transistor in the memory cell MC is provided with a back gate, the conductor in region HL may also function as wiring BGL for electrical connection to the back gate.

[0489] In other words, Figure 65C shows that the semiconductor device shown in either Figure 60A or Figure 60B is formed in region SD1, and the semiconductor device shown in Figure 61 or Figure 62 is formed in region SD2.

[0490] Incidentally, the region TM where the wiring WL is exposed functions as a connection terminal for supplying potential to the wiring WL. In other words, by electrically connecting the wiring to region TM, a potential can be supplied to the gate of the cell transistor CTr.

[0491] Note that the wiring WL corresponds to the conductors 434a and 434b in the semiconductor device shown in Figures 1, 2A, and 2B of Embodiment 1. In this case, the charge storage layer of the semiconductor device is formed between the wiring WL and region HL, although this is not shown in the figure.

[0492] Furthermore, the wiring WL corresponds to the conductors 334a and 334b ​​in the semiconductor device shown in Figures 28, 29A, and 29B of Embodiment 2. In this case, the floating gate electrode of the semiconductor device is formed between the wiring WL and region HL, although it is not shown in the figure.

[0493] The shape of region TM is not limited to the configuration examples shown in Figures 65A to 65C. In one embodiment of the present invention, the configuration of a semiconductor device may be such that an insulator is formed on region TM as shown in Figures 65A to 65C, an opening is provided in the insulator, and a conductor PG is formed to fill the opening (Figures 66A to 66C). Wiring ER is formed on the conductor PG, thereby electrically connecting wiring ER and wiring WL. In Figure 66A, the conductor PG provided inside the structure is shown with a dashed line, and the dashed line of region HL is omitted.

[0494] Furthermore, peripheral circuits for the memory cell array, such as read circuits and precharge circuits, may be formed on the lower layer of the semiconductor device. In this case, Si transistors may be formed on a silicon substrate or the like to constitute the peripheral circuits, and then a semiconductor device according to one aspect of the present invention, as described in Embodiment 1 or Embodiment 2, may be formed on the peripheral circuits. Figures 67A and 69 are cross-sectional views in which the peripheral circuits are composed of planar Si transistors and a semiconductor device according to one aspect of the present invention is formed on the upper layer. Figures 68A and 70 are cross-sectional views in which the peripheral circuits are composed of FIN-type Si transistors and a semiconductor device according to one aspect of the present invention is formed on the upper layer. Note that the semiconductor devices shown in Figures 67A and 68A apply the configuration of the semiconductor device in Figure 1 as an example, and the semiconductor devices shown in Figures 69 and 70 apply the configuration of the semiconductor device in Figure 28 as an example.

[0495] Figures 67A, 68A, 69, and 70 illustrate semiconductor devices that include a conductor 1221 for electrically connecting to either the source or drain of a cell transistor at one end of a string, conductors 1222 and 1223, insulators 1202 and 1203, which are electrically connected to the back gate electrodes of the cell transistors included in the string.

[0496] The conductor 1221 is provided so as to be in contact with the insulator 412, the conductor 431, and the material layer 451 on the upper surface of the cell transistor laminate. The insulator 1202 is formed so as to cover the cell transistor laminate and the conductor 1221. The insulator 1202 has an opening so as to expose the back gate electrode (conductor 432) of the cell transistor, and the conductor 1222 is provided so as to fill this opening. The conductor 1223 is provided so as to be in contact with the conductor 1222. The insulator 1203 is formed so as to cover the conductor 1223, the insulator 1202, and the cell transistor laminate.

[0497] For conductors 1221, 1222, and 1223, it is preferable to use materials that can be applied to conductor 432, for example.

[0498] For insulators 1202 and 1203, it is preferable to use materials that can be applied to insulator 412, for example. In particular, it is preferable that insulators 1202 and 1203 have a barrier insulating film that suppresses the diffusion of impurities from the outside (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.)) into the laminate of the cell transistor.

[0499] Note that the semiconductor devices in Figures 67A, 68A, 69, and 70 omit the transistors corresponding to transistors STr and BTr, but these transistors may be provided between the laminate having the cell transistors and the insulator 1202, and between the laminate having the cell transistors and the insulator 1201.

[0500] In Figures 67A, 68A, 69, and 70, the Si transistors constituting the peripheral circuit are formed on the substrate 1700. An element isolation layer 1701 is formed between multiple Si transistors. Conductors 1712 are formed as the source and drain of the Si transistors. Conductors 1730 are formed extending in the channel width direction and are connected to other Si transistors or conductors 1712 (not shown).

[0501] As the substrate 1700, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates made of silicon germanium, and SOI substrates can be used.

[0502] Furthermore, the substrate 1700 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a laminated film, paper containing fibrous material, or a base film. Alternatively, a semiconductor element may be formed on one substrate and then transferred to another substrate. Figures 67A, 68A, 69, and 70 show an example in which a single-crystal silicon wafer is used as the substrate 1700.

[0503] Here, we will explain the details of the Si transistor. The planar Si transistors shown in Figures 67A and 69 are shown as cross-sectional views in the channel length direction, and the planar Si transistor shown in Figure 67B is shown as a cross-sectional view in the channel width direction. The Si transistor has a channel formation region 1793 provided in the well 1792, a low-concentration impurity region 1794 and a high-concentration impurity region 1795 (collectively referred to simply as the impurity region), a conductive region 1796 provided in contact with the impurity region, a gate insulating film 1797 provided on the channel formation region 1793, a gate electrode 1790 provided on the gate insulating film 1797, and sidewall insulating layers 1798 and 1799 provided on the side surface of the gate electrode 1790. Note that metal silicide or the like may be used for the conductive region 1796.

[0504] Furthermore, the FIN-type Si transistors shown in Figures 68A and 70 are shown in cross-sectional views in the channel length direction, while the FIN-type Si transistor shown in Figure 68B is shown in cross-sectional views in the channel width direction. In the Si transistors shown in Figures 68A, 68B, and 70, the channel formation region 1793 has a convex shape, and the gate insulating film 1797 and gate electrode 1790 are provided along its side and top surfaces. In this embodiment, a case in which a convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor layer having a convex shape may also be formed by processing an SOI substrate.

[0505] An insulator 1201 is formed on top of the circuit formed on the substrate 1700 by a Si transistor, a conductor 1712, a conductor 1730, etc. Furthermore, a conductor 1211 for electrical connection to the circuit is embedded in the insulator 1201. Incidentally, when a metal oxide is included in the channel formation region of the cell transistor CTr, it is preferable to use insulators that have barrier properties against hydrogen, etc., as the insulator 1201 and the conductor 1211. This is to suppress the diffusion of hydrogen from the Si transistor to the cell transistor CTr via the insulator 1201 and / or the conductor 1211.

[0506] As the insulator 1201, any material applicable to the insulators 411A to 411C described above can be used.

[0507] For the conductor 1211, for example, tantalum nitride, which has hydrogen barrier properties, can be used. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from the Si transistor while maintaining conductivity as a wiring.

[0508] Note that the reference numerals shown in Figures 68A, 68B, 69, and 70 are the same as the reference numerals shown in Figures 67A and 67B.

[0509] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0510] (Embodiment 6) This embodiment describes a semiconductor device with a configuration different from that described in Embodiment 1.

[0511] As an example, the configuration of the cell transistors and memory cell array of a semiconductor device will be explained with reference to Figures 71A to 71D, 72A to 72C, and 73. Figure 71A is a top view of the memory cell array 700, and Figure 71B is a cross-sectional view of the area indicated by the dashed line Y1-Y2 in Figure 71A. Figure 71C is a cross-sectional view of the area indicated by the dashed line Y3-Y4 in Figure 71A, illustrating the memory string. Figure 71D is an enlarged cross-sectional view of the area enclosed by the dashed line in Figure 71B, and Figures 72A and 72B are enlarged perspective views of the area enclosed by the dashed line in Figure 71B, illustrating the cell transistor 710 that functions as a memory cell. Figure 72C is an enlarged perspective view of the area enclosed by the dashed line in Figure 71C, illustrating the transistor that functions as a selection transistor. In the following explanation, for convenience, a Cartesian coordinate system consisting of the x, y, and z axes will be set up as shown in Figures 71A to 71C. Here, the x and y axes are taken parallel to the upper surface of the substrate 720 on which the memory cell array 700 is installed, and the z axis is taken perpendicular to the upper surface of the substrate 720.

[0512] The memory cell array 700 has a laminate on a substrate 720 in which conductors 701 (conductors 701_1 to conductors 701_m: m is a natural number of 2 or more) or conductors 702 and insulating films are alternately stacked. Inside the opening formed to penetrate the laminate, there are insulators 703 (insulators 703_1 to 703_4), and inside the insulators 703 there are oxides 704 (oxides 704_1 to 704_4), and the upper ends of oxides 704_1 to 704_4 are electrically connected. The structure has conductors 705 (conductors 705_1 to conductors 705_4), conductors 706 (conductors 706_1 to conductors 706_4) which are electrically connected to the lower ends of oxides 704_1 to oxides 704_4, conductors 707 (conductors 707_1 to conductors 707_m) which are electrically connected to conductors 701_1 to conductors 701_m, and conductors 708 (conductors 708_1 to conductors 708_m) which are electrically connected to conductors 707_1 to conductors 707_m. In Figure 71B, more than four rows of conductors 701 are shown to represent multiple conductors 701, but this embodiment is not limited to Figure 71B, and it is sufficient to have at least two rows of conductors 701.

[0513] Furthermore, in Figure 71A, the memory cell array 700 has a stack on the SOL side that is connected to the source line SOL and a stack on the BIL side that is electrically connected to the bit line BIL. The source line SOL and the bit line BIL will be described later.

[0514] Here, as shown in Figures 71A and 71B, the conductor 701 is provided extending in the x-axis direction. Also, as shown in Figures 71B and 71C, the insulator 703 and oxide 704 are provided extending in the z-axis direction. In other words, it is preferable that the conductor 701 and the insulator 703 and oxide 704 are provided intersecting each other perpendicularly. Also, as shown in Figure 71B, the conductor 707 is provided extending in the z-axis direction. The conductor 708 may also be provided extending in the y-axis direction. Furthermore, a conductor that functions as a bit line BIL connected to the conductor 705 may be provided extending in the y-axis direction. Alternatively, a portion of the conductor 705 may function as a bit line BIL, and the conductor 705 may be provided extending in the y-axis direction.

[0515] The oxide 704 is formed in a columnar shape and is provided extending in the z-axis direction. The insulator 703 is provided so as to surround the side periphery of the columnar oxide 704. The conductor 707 is also formed in a columnar shape and is provided extending in the z-axis direction.

[0516] The columnar oxide 704 is electrically connected to the conductor 706 at its lower end in the z-axis direction and to the conductor 705 at its upper end. Furthermore, as shown in Figure 71C, the conductor 706 is electrically connected to the lower ends of two adjacent columnar oxides 704, and the upper ends of these two columnar oxides 704 are each electrically connected to electrically isolated conductors 705.

[0517] Here, the region near the intersection of the conductor 701, the insulator 703, and the oxide 704 functions as a cell transistor. Similarly, the region near the intersection of the conductor 702, the insulator 703, and the oxide 704 functions as a selection transistor. The channel length direction of these cell transistors and selection transistors is parallel to the z-axis. The cell transistors or selection transistors are electrically connected in series, forming a memory string.

[0518] It should be noted that the configuration of the semiconductor device shown in this embodiment is just one example, and the present invention is not limited to the number and arrangement of circuit elements and wiring, etc., as shown in the drawings etc., relating to this embodiment. The number and arrangement of circuit elements and wiring, etc., of the semiconductor device relating to this embodiment can be appropriately designed and determined in accordance with the circuit configuration and driving method.

[0519] The substrate 720 on which the memory cell array 700 is provided preferably has an insulating surface. As the substrate having an insulating surface, a semiconductor substrate with an insulating film formed on its surface, an insulating substrate, or a conductive substrate with an insulating material formed on its surface may be used. The semiconductor substrate, insulating substrate, or conductive substrate used as the substrate 720 can, for example, be a substrate that can be used in the semiconductor device described in Embodiment 1.

[0520] Conductor 701 functions as the gate of the cell transistor and is electrically connected to the word line. That is, conductors 701, 707, and 708 also function as part of the word line. Here, it is preferable that the conductor 701 is provided in a stepped manner, as shown in Figure 71B, with the lower conductor 701 extending towards Y2 from the upper conductor 701. By providing the conductor 701 in this way, a portion of the upper surface of the lower conductor 701 does not overlap with the upper conductor 701, so that the corresponding region of each layer of conductor 701 can be connected to each conductor 707.

[0521] As the conductor 701, conductive materials such as silicon with impurities added or metals can be used. When silicon is used as the conductor 701, amorphous silicon or polysilicon can be used. In addition, p-type or n-type impurities may be added to the silicon to make it conductive. Furthermore, as a conductive material containing silicon, silicide containing titanium, cobalt, or nickel can be used as the conductor 701. Furthermore, when a metallic material is used as the conductor 701, a material containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used.

[0522] Conductor 702 is provided on top of conductor 701. Conductor 702 functions as the gate of a selection transistor (bit-line selection transistor: SDT, and source-line selection transistor: SST). Conductor 702 can be made of the same material as conductor 701. Alternatively, conductor 702 may be made of the same material as conductor 701, or a different material. Depending on the application of conductor 701 and conductor 702, the materials used for conductor 701 and conductor 702 should be determined by considering factors such as the work function.

[0523] As insulating films provided on the upper and lower layers of conductors 701 and 702, insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, metal nitride oxides, etc., can be used. Silicon oxide, silicon oxidized nitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or resins are suitable for use as insulating films because they have a low dielectric constant. Oxidized nitrides refer to materials in which the oxygen content is higher than the nitrogen content, and nitride oxides refer to materials in which the nitrogen content is higher than the oxygen content. Metal oxidized nitrides refer to materials in which the oxygen content is higher than the nitrogen content, and metal nitride oxides refer to materials in which the nitrogen content is higher than the oxygen content.

[0524] On the other hand, it is also possible to use aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium as the insulating film. However, because these have a high dielectric constant, parasitic capacitance may occur between the conductors 701 or between the conductors 701 and conductors 702. The material used for the insulating film can be determined according to the device design and application.

[0525] As shown in Figure 72A, the insulator 703 has an insulator 703a, an insulator 703b, and an insulator 703c. Insulator 703a is provided on the conductor 701 side, insulator 703c is provided on the oxide 704 side, and insulator 703b is provided between insulator 703a and insulator 703c. In particular, in a cell transistor near the region where the conductor 701 and the insulators 703 and oxide 704 intersect, insulator 703a functions as a gate insulating layer, insulator 703b functions as a charge storage layer, and insulator 703c functions as a tunnel insulating layer.

[0526] As shown in Figure 72C, the select transistor does not need to have a charge storage layer and a tunnel insulating layer. Therefore, in the bit line side transistor (SDT) and the source line side transistor (SST), the insulator 703 may be configured to have only an insulator 703a, without insulators 703b and 703c. Also, in Figures 72A and 72C, the oxide 704 has a two-layer structure of oxide 704a and oxide 704b, but it is not limited to this. As shown in Figure 72B, the oxide 704 may have a three-layer structure of oxide 704a, oxide 704b, and oxide 704c, or a multilayer structure of four or more layers. In addition, an insulator 711 may be provided inside the oxide 704b.

[0527] It is preferable to use silicon oxide or silicon oxynitride as the insulator 703a. Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Furthermore, these can be laminated to form the insulator 703a.

[0528] The insulator 703b is preferably made of a material that functions as a charge storage layer, and silicon nitride or silicon nitride oxide is preferred. Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used.

[0529] It is preferable to use silicon oxide or silicon oxynitride as the insulator 703c. Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. These can also be laminated to form the insulator 703c. Furthermore, it is preferable that the insulator 703c is thinner than the insulator 703a. As will be described in detail later, during data writing or erasing to the cell transistor, charge transfer occurs between the oxide 704 and the insulator 703b through the insulator 703c. In other words, the insulator 703c functions as a tunnel insulating layer.

[0530] In particular, when forming an insulator 703 in an opening provided in a laminate having a conductor 701, a conductor 702, and an insulating film, the insulator 703 formed at the bottom of the opening needs to be removed by anisotropic etching using dry etching or the like. During anisotropic etching, the insulator 703c is exposed to plasma, radicals, gases, chemicals, etc., on its sides as well. If the sides of the insulator 703c are damaged by these, trap centers may be generated in the insulator 703c, which may affect the electrical characteristics of the transistor. In order to suppress the generation of trap centers, the sides of the insulator 703c are required to have high resistance to damage caused by etching. In this case, it is preferable to use aluminum oxide, a laminate of silicon oxide and aluminum oxide, or a laminate of silicon oxynitride and aluminum oxide as the insulator 703c.

[0531] Insulators 703a, 703b, and 703c can be formed using methods such as ALD or CVD. Furthermore, in order to prevent contamination of the interfaces of insulators 703a, 703b, and 703c, it is preferable to deposit the films continuously without exposure to the atmosphere, either in the same chamber or using a multi-chamber deposition apparatus having multiple chambers.

[0532] For oxide 704, it is preferable to use a metal oxide that functions as an oxide semiconductor. More preferably, it is preferable to use an oxide semiconductor with high field-effect mobility. Compared to semiconductors made of silicon or the like, such oxide semiconductors have better on-characteristics for transistors and can achieve high mobility.

[0533] For example, as oxide 704, a metal oxide such as In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. In particular, In-Ga-Zn oxide is preferred. Alternatively, In-Ga oxide or In-Zn oxide may be used as oxide 704.

[0534] By applying oxide semiconductors with high field-effect mobility to semiconductor devices, it may be possible to speed up operations such as writing, reading, or erasing.

[0535] Preferably, the oxide 704 has an oxide 704a provided on the insulator 703c side and an oxide 704b provided inside the oxide 704a, as shown in Figures 71D, 72A, and 72C. Figure 71D is an enlarged view of the cell transistor 710 enclosed by the dashed line in Figure 71B. In this case, it is preferable to use an oxide 704a with a relatively wider energy gap than oxide 704b. Here, an oxide with a wide energy gap is sometimes called a wide-gap oxide, and an oxide with a narrow energy gap is sometimes called a narrow-gap oxide.

[0536] When oxide 704a is a wide-gap diode and oxide 704b is a narrow-gap diode, it is preferable that the energy at the lower end of the conduction band of oxide 704a is higher than the energy at the lower end of the conduction band of oxide 704b. In other words, it is preferable that the electron affinity of oxide 704a is smaller than that of oxide 704b.

[0537] Furthermore, it is preferable that oxides 704a and 704b be combinations with different atomic ratios of each metal atom. Specifically, it is preferable that the atomic ratio of element M in the constituent elements of the metal oxide used in oxide 704a is greater than the atomic ratio of element M in the constituent elements of the metal oxide used in oxide 704b. It is also preferable that the atomic ratio of element M to In in the metal oxide used in oxide 704a is greater than the atomic ratio of element M to In in the metal oxide used in oxide 704b. Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used in oxide 704b is greater than the atomic ratio of In to element M in the metal oxide used in oxide 704a.

[0538] For oxide 704a, as described in Embodiment 1, metal oxides having compositions such as In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1, or compositions close to these, can be used. For oxide 704b, metal oxides having compositions such as In:Ga:Zn=4:2:3 to In:Ga:Zn=4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3, or compositions close to these, can be used. For oxide 704b, metal oxides having compositions such as In:Zn=5:1 or In:Zn=10:1, or compositions close to these, can be used. In addition, indium oxide can be used for oxide 704b.

[0539] It is preferable to combine these oxides 704a and 704b in such a way that they satisfy the above-mentioned atomic ratio relationship. For example, it is preferable that oxide 704a be a metal oxide having a composition of In:Ga:Zn=1:3:4 or a composition close to it, and oxide 704b be a metal oxide having a composition of In:Ga:Zn=4:2:3 to In:Ga:Zn=4.1 or a composition close to it. Note that the above composition refers to the atomic ratio in the oxide formed on the substrate, or the atomic ratio in the sputtering target.

[0540] Furthermore, oxides 704a and 704b may be formed using sputtering, plasma CVD, thermal CVD (such as ALD or MOCVD), etc. In addition, to prevent contamination of the interface between oxides 704a and 704b, it is preferable to deposit the films continuously without exposure to the atmosphere, either in the same chamber or using a multi-chamber type deposition apparatus having multiple chambers. For this reason, it is more preferable to deposit oxides 704a and 704b continuously with insulators 703a, 703b, and 703c.

[0541] Furthermore, it is preferable to use CAAC-OS as oxide 704a, as described in Embodiment 4, and CAC-OS as oxide 704b. When CAAC-OS is used as oxide 704a, it is preferable that the c-axis is parallel to the xy-plane shown in Figure 71A, etc., that is, perpendicular to the z-axis, and oriented toward the center from the side of the opening.

[0542] Here, at the junction of oxide 704a and oxide 704b, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junction of oxide 704a and oxide 704b can be said to change continuously or to be a continuous junction. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 704a and oxide 704b.

[0543] Specifically, by having oxides 704a and 704b share a common element other than oxygen (which serves as the main component), a mixed layer with a low defect level density can be formed. For example, if oxide 704b is In-Ga-Zn oxide, then In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc., can be used as oxide 704a. This reduces the defect level density at the interface between oxide 704a and oxide 704b. As a result, the influence of interface scattering on carrier conduction is reduced, and the cell transistor 710 can obtain a high on-current.

[0544] A more detailed explanation of the metal oxides that can be used as oxide 704 will be provided later.

[0545] As shown in Figures 71D and 72A, the oxide 704b is arranged so as to be surrounded by the oxide 704a. In this configuration, when carriers flow through the oxide 704 in the direction from conductor 705 to conductor 706, or from conductor 706 to conductor 705, the carriers mainly flow in the component having a narrow gap. Therefore, when using the above configuration, a high current driving force, i.e., a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0546] Furthermore, by providing oxide 704a between oxide 704b and insulator 703c, the oxide 704b, which serves as the carrier path, and the insulator 703c do not come into direct contact, thereby suppressing the formation of trap centers. Trap centers formed at the interface between the semiconductor (oxide semiconductor) and the insulator can capture electrons and cause the transistor's threshold voltage to fluctuate in the positive direction, potentially adversely affecting the transistor's reliability and on / off characteristics. Therefore, transistors using this oxide are not affected by the electrical characteristics caused by trap centers, resulting in higher current driving force in the on state, i.e., a larger on-current, and higher field-effect mobility. In addition, this transistor and the semiconductor device using this transistor can achieve high reliability.

[0547] In Figures 71D and 72A, the oxide 704 is provided such that oxide 704a surrounds oxide 704b, but this embodiment is not limited to this. Figure 72B shows a different example of the cell transistor 710. In Figure 72B, in the cell transistor 710, oxide 704a is provided inside insulators 703a, 703b, and 703c, oxide 704b is provided inside oxide 704a, and oxide 704c is provided inside oxide 704b. In addition, an insulator 711 may be embedded inside oxide 704c. Note that the insulator 711 is not necessarily provided, and the inside of oxide 704c may be a cavity.

[0548] The oxide 704b may be provided sandwiched between the oxide 704a and the oxide 704c. In this case, it is preferable that the oxide 704c has a wide gap, similar to the oxide 704a. By providing a wide-gap oxide 704c, the carriers flowing through the oxide 704 can be confined to the oxide 704b, thereby obtaining a high current-driving force, i.e., a large on-current, and high field-effect mobility in the on-state of the transistor.

[0549] Furthermore, when an insulator 711 is provided inside the oxide 704c, it is preferable that the insulator 711 is a material that can supply oxygen to the oxide 704, or a material that can supply impurities such as hydrogen and nitrogen. By using an oxide that contains as little hydrogen and nitrogen as possible as the insulator 711, it may be possible to supply oxygen to the oxide 704. By supplying oxygen to the oxide 704, impurities such as hydrogen and water contained in the oxide 704 can be removed, and the oxide 704 becomes highly purified. By using an oxide with the impurities reduced as much as possible as the oxide 704, cell transistors and semiconductor devices using such transistors can achieve high reliability.

[0550] Furthermore, by using an oxide containing hydrogen or nitrogen as the insulator 711, it may be possible to supply hydrogen or nitrogen to the oxide 704. By supplying hydrogen or nitrogen to the oxide 704, the resistance value of the oxide 704 may decrease. By lowering the resistance value of the oxide 704 to a level that does not hinder circuit operation, the cell transistor can be operated at a lower drive voltage. In addition, a high current driving force, i.e., a large on-current, and a high field-effect mobility can be obtained in the on state of the cell transistor.

[0551] In Figures 71A, 72A, and 72B, the opening formed in the laminate where the cell transistor 710 is provided has a circular top surface, but is not limited to this. For example, the top surface may be elliptical, triangular, quadrilateral, or other polygonal shape. If it is polygonal, the corners may be rounded. The top surface shapes of the insulator 703 and oxide 704 may also change to match the top surface shape of the opening. Furthermore, the opening may be shaped such that the cross-sectional area of ​​the lower opening (conductor 706 side) is smaller than the cross-sectional area of ​​the upper opening (conductor 705 side).

[0552] A cell transistor is constructed from an oxide 704, an insulator 703, and a conductor 701 (any one of conductors 701_1 to 701_m). Figure 71 shows an example in which m stages (where m is a natural number greater than or equal to 4) of cell transistors are stacked.

[0553] The conductor 705 is electrically connected to the oxide 704 and functions as part of the source line SOL or the bit line BIL. It is preferable to use a conductive material containing a metallic element as the conductor 705. It is also preferable to form a metal compound layer containing the metallic element of the conductor 705 and the components of the oxide 704 at the interface between the conductor 705 and the oxide 704. The formation of this metal compound is preferable because it reduces the contact resistance between the conductor 705 and the oxide 704. Alternatively, the conductor 705 can absorb oxyg...

Claims

[Claim 1] A first conductor having a columnar shape and functioning as the first gate electrode of a transistor, In a plan view, the first insulator has a region surrounding the periphery of the first conductor, In a plan view, a first oxide semiconductor having a region surrounding the periphery of the first insulator and having a channel formation region for the transistor, In a plan view, a metal oxide having a region surrounding the periphery of the first oxide semiconductor, In a plan view, a second conductor having a region surrounding the periphery of the metal oxide and functioning as one of the source electrode and drain electrode of the transistor, In a plan view, a third conductor having a region surrounding the periphery of the metal oxide and functioning as the other of the source electrode and drain electrode of the transistor, In a plan view, a second oxide semiconductor having a region surrounding the periphery of the first oxide semiconductor, In a plan view, a second insulator having a region surrounding the periphery of the second oxide semiconductor and containing oxygen and silicon, In a plan view, a third insulator having a region surrounding the periphery of the second insulator and containing nitrogen and silicon, In a plan view, the fourth conductor has a region that surrounds the periphery of the first oxide semiconductor via the second oxide semiconductor, the second insulator and the third insulator, and functions as the second gate electrode of the transistor. In a cross-sectional view, the second conductor and the third conductor are arranged spaced apart from each other. In a cross-sectional view, the second oxide semiconductor has a region located between the second conductor and the third conductor. In a cross-sectional view, the metal oxide has a region located between the first oxide semiconductor and the second conductor. In a cross-sectional view, the metal oxide has a region located between the first oxide semiconductor and the third conductor. In a cross-sectional view, the second insulator has a region located between the second conductor and the third conductor. A semiconductor device wherein, in a cross-sectional view, the third insulator has a region located between the second conductor and the third conductor.

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