Semiconductor device structure, and method for forming said semiconductor device structure

Abstract

To provide a semiconductor device structure that further can effectively miniaturize an integrated circuit and improve performance.SOLUTION: A semiconductor device structure comprises: a semiconductor substrate having an original semiconductor surface and an active region; a shallow trench isolation (STI) region 284 surrounding the active region; a transistor formed based on the active region and comprising a dummy gate structure 280, a first conductive region 3291, a second conductive region 3292, and a channel region between the first and second conductive regions; an underground interconnection (UGI) structure 282 extending beyond the transistor; and a connecting plug 3072 electrically connecting the UGI structure 282 to the first conductive region 3291 of the transistor. The first conductive region 3291 includes an epitaxial semiconductor material. The UGI structure 282 is disposed below the original semiconductor surface and within the STI region 284.SELECTED DRAWING: Figure 22

Description

Detailed Description of the Invention

[0001] [Background] <Technical Field> The present disclosure relates to semiconductor structures. More particularly, the present disclosure relates to semiconductor device structures and methods of forming such semiconductor device structures.

[0002] <Description of Related Art> In state-of-the-art integrated circuits, many transistors are connected by multiple conductive interconnects (e.g., metal or polysilicon wires). This facilitates signal transmission between the gate, source, and drain regions (GSD) of the transistor. All of these conductive interconnects are connected to the GSD via numerous contact holes and plugs. This presents significant challenges and difficulties in achieving chip design goals such as area reduction, power consumption reduction, noise reduction, and improved integrated circuit performance, especially when the dimensions of the integrated circuit on the die must be significantly reduced to meet the miniaturization requirements of Moore's Law. An example of the area penalty is as follows: The size of the source or drain diffusion region must be designed to be larger than the size of the contact holes used to connect the conductive interconnects to the source or drain region. This design aims to avoid unavoidable photolithographic misalignment resulting from the limitations of lithography equipment. Misalignment in photolithography can cause contact holes to form outside the edge (border) located below the source or drain region. This inevitably increases the diffusion area of ​​the transistor and thus the die area. This increased die area results in greater capacitance, which imposes a significant penalty on the AC performance of the circuit. As a result, power consumption and noise increase. How to introduce better self-aligned contact structures and techniques to connect transistors to the initial interconnect (metal) layer with the minimum surface area required for signal transmission and reception is a critical challenge for further effectively miniaturizing integrated circuits and improving their performance.

[0003] Furthermore, the monolithic integration capability of silicon chips is rapidly growing from GSI (Giga Scale Integration: integrating billions of transistors on a die) to TSI (Terra Scale Integration: integrating trillions of transistors on a die), and chip performance continues to improve dramatically. Along with this, the power consumption required to operate such a vast number of transistors is increasing rapidly. This is unfortunate because, due to the current limited heat dissipation capacity (for example, silicon dioxide has very low thermal conductivity, and silicon does not have very high thermal conductivity), it increases the junction temperature of transistors, and consequently, the overall chip temperature. This material and device structural problem creates a negative cyclical effect: the increase in die temperature slows down the transistor speed. Therefore, to accelerate transistor performance, the design is forced to increase the power supplied to the circuit. However, this mechanism significantly increases the die temperature, ultimately worsening the heat dissipation problem. In fact, such insufficient heat dissipation, which causes temperature increases related to chip operation, is considered the most serious problem that the entire chip industry must solve in order to avoid hindering the integration of more devices onto a die. However, progress in reducing the temperature of GSI chips has not improved as much as expected. In reality, as technology nodes become smaller, transistor dimensions inevitably become smaller (for example, the minimum feature size is reduced from 7nm to 5nm, then to 3nm, and so on), the ratio of oxide film to the total size of the transistor increases, and the heat dissipation capacity of the entire device junction becomes even more concentrated. Many heat dissipation methods have been devised, such as covering the entire chip with heat dissipation pads located higher on the outside of the chip, or using liquid cooling circulation outside the packaged chip. However, both methods are very expensive, inefficient, and fail to effectively reduce the transistor junction temperature.

[0004] [overview] Embodiments of this disclosure provide a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate having an original semiconductor surface and an active region, a shallow trench isolation (STI) region surrounding the active region, and a transistor formed on the active region. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel region located between the first and second conductive regions. The semiconductor device structure includes an interconnection structure extending beyond the transistor and a connection plug electrically connecting the interconnection structure to the first conductive region of the transistor. The first conductive region includes an epitaxial semiconductor material. The interconnection structure is located below the original semiconductor surface and inside the STI region. The connection plug is located inside the active region, and the epitaxial semiconductor material of the first conductive region is located above the upper surface of the connection plug. Alternatively, the connecting plug is located inside the STI region, and the epitaxial semiconductor material of the first conductive region is connected to the first sidewall of the connecting plug.

[0005] According to one aspect of this disclosure, the interconnection structure is insulated from the semiconductor substrate by an insulating region. The insulating region includes a first spacer located on the first side of the interconnection structure and a second spacer located on the second side of the interconnection structure. The material of the first spacer is different from the material of the second spacer.

[0006] According to one aspect of the present disclosure, the second side wall of the connecting plug is aligned with the side wall of the interconnecting portion and is in contact with the side wall of the interconnecting portion.

[0007] According to one aspect of this disclosure, the semiconductor device structure includes a trench within the active region. A connecting plug is located inside the trench. The connecting plug contains titanium nitride (TiN) and tungsten (W).

[0008] According to one aspect of this disclosure, the semiconductor device structure includes a thin slot within the STI region. A connector plug is located inside the thin slot. The connector plug contains a highly doped semiconductor material or TiN. The epitaxial semiconductor material of the first conductive region is further present above the upper surface of the connector plug. The second sidewall of the connector plug is located opposite to the first sidewall of the connector plug.

[0009] According to one aspect of this disclosure, the transistor is a fin field-effect transistor (FinFET), a GAA transistor, or a CFET. The STI region has an upper surface located lower than the original semiconductor surface.

[0010] According to one aspect of the present disclosure, the first conductive region comprises selectively epitaxially grown material.

[0011] According to one aspect of the present disclosure, the connecting plug is located inside the active region. The first conductive region extends only from the vertical side wall of the active region, which is located directly beneath the spacer structure covering the gate structure.

[0012] According to one aspect of the present disclosure, the connection plug is located inside the STI region. The first conductive region extends from the vertical side wall of the active region located directly below the spacer structure covering the gate structure, and from the horizontal surface of the active region located near the upper surface of the STI region.

[0013] According to one aspect of the present disclosure, the semiconductor device structure includes a metal cap (M0) covering a first conductive region.

[0014] Embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate having an original semiconductor surface and an active region, a shallow trench isolation (STI) region surrounding the active region, and a transistor formed on the active region. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel region located between the first and second conductive regions. The semiconductor device structure includes an interconnection structure extending beyond the transistor. The interconnection structure is located below the original semiconductor surface and inside the STI region. The semiconductor device structure includes a connection plug that electrically connects the interconnection structure to the first conductive region of the transistor. The semiconductor device structure includes a metal cap (M0). The metal cap covers the first conductive region and the epitaxial semiconductor material of the connection plug.

[0015] According to one aspect of this disclosure, the interconnection structure is insulated from the semiconductor substrate by an insulating region. The insulating region includes a first spacer located on the first side of the interconnection structure and a second spacer located on the second side of the interconnection structure. The material of the first spacer is different from the material of the second spacer.

[0016] According to one aspect of this disclosure, the side wall of the connecting plug is aligned with and in contact with the side wall of the interconnection structure.

[0017] According to one aspect of this disclosure, the semiconductor device structure includes a trench inside the active region. A connecting plug is located inside the trench. The connecting plug contains tungsten.

[0018] According to one aspect of this disclosure, the transistor is a FinFET. The channel region includes a fin structure. The STI region has an upper surface located lower than the original semiconductor surface.

[0019] According to one aspect of this disclosure, the first conductive region includes an epitaxial semiconductor material.

[0020] According to one aspect of the present disclosure, the connection plug is located inside the active region. The first conductive region extends from the vertical side wall of the fin structure located directly below the spacer structure covering the gate structure, and from the horizontal surface of the active region located near the upper surface of the STI region.

[0021] According to one aspect of this disclosure, the transistor is a gate-all-around (GAA) transistor, the channel region comprises a plurality of nanosheets, and the STI region has an upper surface located lower than the upper surfaces of the plurality of nanosheets.

[0022] According to one aspect of this disclosure, the first conductive region includes an epitaxial semiconductor material.

[0023] According to one aspect of the present disclosure, the connecting plug is located inside the active region. The first conductive region extends from the vertical sidewalls of a plurality of nanosheets located directly beneath the spacer structure covering the gate structure, and from the horizontal surface of the active region located near the upper surface of the STI region.

[0024] Embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes preparing a semiconductor substrate having an original surface, forming an active region based on the semiconductor substrate, forming a STI region surrounding the active region, forming a plurality of asymmetric spacers inside the STI region, and forming an interconnect structure between the plurality of asymmetric spacers. The interconnect structure is located inside the STI region and below the original surface of the semiconductor substrate. The method includes forming a connection plug that contacts an interconnect layer. The connection plug is located inside the active region or inside the STI region. The method includes forming a first conductive region of a transistor based on the active region. The first conductive region contacts the connection plug.

[0025] According to one aspect of the present disclosure, the asymmetric spacer includes a first spacer and a second spacer. The material of the first spacer is different from the material of the second spacer.

[0026] According to one aspect of the present disclosure, the first spacer is fabricated by silicon oxycarbide nitride (SiOCN) or nitride. The second spacer is fabricated by silicon dioxide (SiO2).

[0027] According to one aspect of the present disclosure, the step of forming the connection plug includes forming a trench inside the active region by etching a part of the active region to expose the first spacer, removing the exposed first spacer based on the trench to expose the sidewall of the interconnect structure, and forming a conductive material inside the trench and contacting the conductive material with the sidewall of the interconnect structure.

[0028] According to one aspect of the present disclosure, the conductive material includes TiN and tungsten.

[0029] According to one aspect of the present disclosure, the conductive material includes tungsten.

[0030] According to one aspect of the present disclosure, the step of forming the connection plug includes etching a part of the active region so that the upper surface of the first spacer is exposed, exposing the horizontal surface of the active region located near the upper surface of the STI region, removing the first spacer based on the exposed upper surface of the first spacer to form a thin slot, and exposing the side wall of the interconnect layer, and forming a conductive material inside the thin slot and bringing the conductive material into contact with the side wall of the first interconnect layer.

[0031] According to one aspect of the present disclosure, the conductive material includes a highly doped semiconductor material or TiN.

[0032] According to one aspect of the present disclosure, the step of forming the asymmetric spacer includes forming a first spacer covering the side wall of the active region and a temporary spacer (temporary spacer, provisional spacer) covering the side wall of another active region adjacent to the active region. The first spacer and the temporary spacer are located inside the STI region. The first spacer and the temporary spacer contain the same material. And the step of forming the asymmetric spacer includes forming a sacrificial layer inside the STI region to cover the first spacer and the temporary spacer, removing the sacrificial layer and the temporary spacer to expose the side wall of another active region, and forming a second spacer covering the exposed side wall of another active region.

[0033] According to one aspect of the present disclosure, the step of forming the second spacer includes oxidizing the exposed side wall of another active region.

[0034] According to one aspect of the present disclosure, the step of removing the sacrificial layer and the temporary spacer includes forming a patterned photoresist layer, exposing a part of the sacrificial layer and the temporary spacer, and removing the exposed sacrificial layer and the temporary spacer.

[0035] According to one aspect of the present disclosure, the method described above includes forming a metal cap that covers the first conductive region and the connecting plug.

[0036] The embodiments described above and other embodiments of this disclosure will be better understood in relation to the following detailed description of (one or more) non-limiting embodiments. The following description will be made with reference to the accompanying drawings.

[0037] [Brief description of the drawing] Figures 1A to 9 illustrate a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure.

[0038] Figures 10A to 17C illustrate a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure.

[0039] Figures 18 to 22C show a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure.

[0040] Figures 23 to 26 show a method for electrically connecting an underground interconnection structure to a transistor according to a second embodiment of the connection of this disclosure.

[0041] Figures 27-28 show a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the third connection of this disclosure.

[0042] Figures 29 to 37A show a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fourth connection of this disclosure.

[0043] Figures 38 to 48A show a method for electrically connecting an underground interconnection structure to a transistor, according to a fifth embodiment of the connection of this disclosure.

[0044] Figures 49 to 57A show a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the sixth connection of this disclosure.

[0045] [Detailed explanation] Hereafter, various embodiments will be described in more detail with reference to the attached drawings. These drawings are provided for illustrative and explanatory purposes only, and not for limiting purposes. For clarity, components may not be drawn to scale. Furthermore, some components and / or reference figures may be omitted from some drawings. It is assumed that elements and configurations in one embodiment can be usefully incorporated into another embodiment without further explanation. In the following methods for forming semiconductor device structures, one or more additional operations may exist between the operations described. The order of the operations may differ. In the drawings, the same / similar reference figures are used to indicate identical / similar elements.

[0046] The ordinal numbers such as “first,” “second,” etc., used in this specification and the appended claims to describe elements do not suggest or represent any particular position, arrangement order, or manufacturing order in the structure. The ordinal numbers are used solely to clearly distinguish multiple elements having the same name. The spatial terms such as “on,” “above,” “over,” “upper,” “top,” “below,” “beneath,” “under,” and “lower,” used in this specification and the appended claims, may be used to describe relative spatial or positional relationships between one or more elements and another, as illustrated in the drawings. These spatial or positional relationships may be direct or indirect, unless otherwise specified. The spatial terms are intended to encompass different orientations of the structure, in addition to the orientation depicted in the drawings. The structure may be inverted or rotated at various angles, and the spatial descriptions used herein may be interpreted accordingly.

[0047] Furthermore, as used herein and in the claims, the terms “electrically connected” and “electrically coupled” may refer to current flowing through multiple elements or to an operational relationship between multiple elements. An operational relationship may mean, for example, that one element is used to drive another element, even if there is no direct current flowing between these two elements.

[0048] This disclosure focuses on underground interconnection (UGI) structures within semiconductor substrates for signal transmission or heat dissipation applications. Signal transmission includes power signal transmission and data signal transmission. UGI structures can be manufactured by monolithic processes for manufacturing transistors. For example, the transistor may be a fin field-effect transistor (FinFET), a gate-all-around (GAA) transistor, a complementary FET (CFET), or a planar transistor. The underground interconnection structure may be an underground interconnection line (UGI line) or an underground interconnection pad (UGI pad).

[0049] [Formation of UGI structure beneath the original semiconductor surface]

[0050] <Embodiment for the first process>

[0051] Figures 1A to 9 illustrate exemplary methods for manufacturing a UGI structure according to a first embodiment of the present disclosure.

[0052] Figure 1A shows a schematic top view of the structure at a certain stage of the manufacturing method. Figure 1B shows a schematic cross-sectional view of the structure at the same stage, illustrated along line BB' shown in Figure 1A. Figure 1C shows a schematic cross-sectional view of the structure at the same stage, illustrated along line CC' shown in Figure 1A. Referring to Figures 1A to 1C, the pad-oxide layer 1204 and the pad-nitride layer 1206 are formed by a deposition process to define the active region. A portion of the semiconductor substrate 1202 located outside the active region is removed. The semiconductor substrate 1202 may contain a semiconductor material such as silicon, or may be fabricated from such a semiconductor material. Next, an oxide layer is formed by the deposition process, and an etch-back process is performed on the oxide layer to form a shallow trench isolation (STI) region 1214. The STI region 1214 may surround the active region.

[0053] Figure 2A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 2B shows a schematic cross-sectional view of the structure at the stage, illustrated along line BB' shown in Figure 2A. Figure 2C shows a schematic cross-sectional view of the structure at the stage, illustrated along line CC' shown in Figure 2A. Referring to Figures 2A to 2C, the thermal oxide layer 1205 grows along the exposed sidewalls of the active region. The thermal oxide layer 1205 may be formed by oxidizing the exposed sidewalls of the active region. The thermal oxide layer 1205 may have a length of about 89 nm to 200 nm along the Z direction. The thermal oxide layer 1205 may have a thickness of about 2.5 nm along the Y direction. Depending on the pitch of the active region, the distance between thermal oxide layers 1205 in different active regions along the Y direction may be about 13 nm. The upper surface of the thermal oxide layer 1205 may be located below the upper surface of the pad oxide layer 1204 and the lower surface of the pad nitride layer 1206 in the Z direction. Part of the STI region 1214 may be exposed, or the bottom of the STI region 1214 may be covered by the thermal oxide layer 1205. In this stage, a portion of the thermal oxide layer 1205 located to the left of the active region can be considered a temporary spacer. Another portion of the thermal oxide layer 1205 located to the right of this active region (opposite the left side) can be considered a second spacer.

[0054] Figure 3A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 3B shows a schematic cross-sectional view of the structure at the same stage, illustrated along line BB' shown in Figure 3A. Figure 3C shows a schematic cross-sectional view of the structure at the same stage, illustrated along line CC' shown in Figure 3A. Referring to Figures 3A to 3C, the SOD material 1207 fills the space between multiple active regions by the deposition process. The top surface of the SOD material 1207 and the top surface of the pad nitride layer 1206 can be made coplanar by performing a planarization process, such as a chemical-mechanical planarization (CMP) process, to remove a portion of the SOD material 1207 above the pad nitride layer 1206. The SOD material 1207 can be considered a sacrificial layer. The SOD material 1207 may cover the second spacer and temporary spacer described in Figures 2A to 2C.

[0055] Figure 4A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 4B shows a schematic cross-sectional view of the structure at the same stage, illustrated along line BB' shown in Figure 4A. Figure 4C shows a schematic cross-sectional view of the structure at the same stage, illustrated along line CC' shown in Figure 4A. Referring to Figures 4A to 4C, a photoresistance layer 1306 is formed. The photoresistance layer 1306 is patterned to cover a portion of the active region and expose a portion of the SOD material 1207. More than half of the active region may be covered by the photoresistance layer 1306.

[0056] Figure 5A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 5B shows a schematic cross-sectional view of the structure at the stage, illustrated along line BB' shown in Figure 5A. Figure 5C shows a schematic cross-sectional view of the structure at the stage, illustrated along line CC' shown in Figure 5A. Referring to Figures 5A to 5C, a narrow slot is formed by removing a portion of the SOD material 1207 not covered by the photoresistance layer 1306 and the thermal oxide layer 1205 (i.e., a temporary spacer) covered by this portion of the SOD material 1207. The narrow slot is formed between the remaining SOD material 1207 and the active region. The narrow slot may have a width of 2 nm to 6 nm (e.g., 3 nm) along the Y direction. After removing the portion of the SOD material 1207 not covered by the photoresistance layer 1306 and the underlying thermal oxide layer 1205, one sidewall of the active region is exposed within the narrow slot.

[0057] Figure 6A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 6B shows a schematic cross-sectional view of the structure at the same stage, illustrated along line BB' shown in Figure 6A. Figure 6C shows a schematic cross-sectional view of the structure at the same stage, illustrated along line CC' shown in Figure 6A. Referring to Figures 6A to 6C, the photoresistance layer 1306 is removed, and a different material (e.g., SiOCN) 1209 is formed inside the narrow slot by a deposition process, distinct from the thermal oxide layer 1205. The top surfaces of the SiOCN material 1209, the SOD material 1207, and the pad nitride layer 1206 can be made coplanar by performing a planarization process such as a CMP process to remove a portion of the SiOCN material 1209 above the pad nitride layer 1206 and the SOD material 1207. Therefore, an asymmetric spacer containing different materials (e.g., a thermal oxide layer 1205 and a SiOCN material 1209) is formed inside the STI region 1214. From another perspective, the asymmetric spacer covers the two side walls of the active region, respectively. The SiOCN material 1209 can be considered the first spacer. The asymmetric spacer may include the first spacer and the second spacer.

[0058] Figure 7A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 7B shows a schematic cross-sectional view of the structure at the same stage, illustrated along line BB' shown in Figure 7A. Figure 7C shows a schematic cross-sectional view of the structure at the same stage, illustrated along line CC' shown in Figure 7A. Referring to Figures 7A to 7C, the SOD material 1207 is removed, creating a space between the thermal oxide layer 1205 and the SiOCN material 1209. Then, conductive layers (such as the TiN layer 1303 and the tungsten layer 1305) are sequentially formed in the space by a deposition process. Subsequently, an etch-back process is performed to remove portions of the TiN layer 1303 and the tungsten layer 1305. After the etch-back process, the remaining tungsten layer 1305 can be defined as an underground interconnect (UGI) structure. The remaining TiN layer 1303 can be defined as a barrier layer. The TiN layer 1303 is located between the tungsten layer 1305 and the thermal oxide layer 1205. The TiN layer 1303 is also located between the tungsten layer 1305 and the SiOCN material 1209. The TiN layer 1303 is also located between the tungsten layer 1305 and the STI region 1214. The distance between the top surface of the thermal oxide layer 1205 and the top surface of the tungsten layer 1305 along the Z direction can be 39 nm to 150 nm. The distance between the top surface of the tungsten layer 1305 and the top surface of the STI region 1214 along the Z direction can be 50 nm to 150 nm. The thickness of the STI region 1214 along the Z direction can be 20 nm to 50 nm.

[0059] Figure 8A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 8B shows a schematic cross-sectional view of the structure at the same stage, illustrated along line BB' shown in Figure 8A. Figure 8C shows a schematic cross-sectional view of the structure at the same stage, illustrated along line CC' shown in Figure 8A. Referring to Figures 8A to 8C, a SiN layer 1307 and an HDP (high density plasma) oxide layer 1309 are sequentially formed above the tungsten layer 1305 and the TiN layer 1303. As a result, an STI region located between multiple active regions is completed. In this way, an underground wiring structure is provided inside the STI region. Figure 9 shows a three-dimensional schematic diagram of the structure. The manufacturing step of forming a transistor inside the active region may be performed after the stages shown in Figures 8A to 8C.

[0060] <Embodiment for the second process>

[0061] Figures 10A to 17C illustrate a method for manufacturing an underground interconnection structure inside an STI region according to a second embodiment of the present disclosure.

[0062] Figure 10A shows a schematic top view of the structure at a stage of the manufacturing method, and Figure 10B shows a schematic cross-sectional view of the structure at the same stage, illustrated along line BB' shown in Figure 10A. Figure 10C shows a schematic cross-sectional view of the structure at the same stage, illustrated along line CC' shown in Figure 10A. Referring to Figures 10A to 10C, the active region is defined by the formation of a pad-oxide layer 2204 and a pad-nitride layer 2206 by a deposition process. A portion of the semiconductor substrate 2202 located outside the active region is removed. The semiconductor substrate 2202 may contain a semiconductor material such as silicon, or may be manufactured from such a semiconductor material. Next, an oxide layer is formed by the deposition process, and a shallow trench isolation (STI) region 2214 is formed by performing an etch-back process on the oxide layer. The STI region 2214 may surround the active region. The width of the pad nitride layer 2206 along the Y direction may be 12 nm. The distance between two adjacent active regions along the Y direction can be 18 nm. The distance between the lower surface of the pad oxide layer 2204 and the upper surface of the STI region 2214 along the Z direction can be 150 nm to 200 nm.

[0063] Figure 11A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 11B shows a schematic cross-sectional view of the structure at the same stage, illustrated along line BB' shown in Figure 11A. Figure 11C shows a schematic cross-sectional view of the structure at the same stage, illustrated along line CC' shown in Figure 11A. Referring to Figures 11A to 11C, the SiOCN material 2209 is formed by a deposition process along the sidewalls of the semiconductor substrate 2202, the sidewalls of the pad oxide layer 2204, the sidewalls of the pad nitride layer 2206, and the top surface of the pad nitride layer 2206. The thickness of the SiOCN material 2209 along the Y direction may be 4 nm. The distance D23 between multiple sidewalls of the SiOCN material 2209 along the Y direction may be 10 nm. A portion of the STI region 2214 is then exposed. At this stage, a portion of the SiOCN material 2209 located to the right of the active region can be considered a temporary spacer. Furthermore, another portion of the SiOCN material 2209 located on the left side (opposite the right side) of this active region can be considered as the first spacer.

[0064] Figure 12A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 12B shows a schematic cross-sectional view of the structure at the same stage, illustrated along line BB' shown in Figure 12A. Figure 12C shows a schematic cross-sectional view of the structure at the same stage, illustrated along line CC' shown in Figure 12A. Referring to Figures 12A to 12C, the SOD material 2207 fills the space between multiple active regions by the deposition process. The top surface of the SOD material 2207 and the top surface of the pad nitride layer 2206 can be made coplanar by performing a planarization process, such as a CMP process, to remove a portion of the SOD material 2207 above the pad nitride layer 2206. The SOD material 2207 can be considered a sacrificial layer. The SOD material 2207 may cover the first spacer and temporary spacer described in Figures 11A to 11C.

[0065] Figure 13A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 13B shows a schematic cross-sectional view of the structure at the stage, illustrated along line BB' shown in Figure 13A. Figure 13C shows a schematic cross-sectional view of the structure at the stage, illustrated along line CC' shown in Figure 13A. Referring to Figures 13A to 13C, a photoresistance layer 2306 is formed. The photoresistance layer 2306 is patterned to cover a portion of the active region and expose a portion of the SOD material 2207 and a portion of the SiOCN material 2209 (i.e., a temporary spacer). For example, more than half of the active region may be covered by the photoresistance layer 2306.

[0066] Figure 14A shows a schematic top view of the structure at a stage of the manufacturing method, and Figure 14B shows a schematic cross-sectional view of the structure at the same stage, illustrated along line BB' shown in Figure 14A. Figure 14C shows a schematic cross-sectional view of the structure at the same stage, illustrated along line CC' shown in Figure 14A. Referring to Figures 14A to 14C, the portion of the SiOCN material 2209 not covered by the photoresistance layer 2306 (i.e., temporary spacer) and the SOD material 2207 have been removed, and the photoresistance layer 2306 has been removed. A slot 2210 is formed between the remaining SiOCN material 2209 and the active region. After the above removal, one side wall of each active region is exposed inside the slot 2210.

[0067] Figure 15A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 15B shows a schematic cross-sectional view of the structure at the stage, illustrated along line BB' shown in Figure 15A. Figure 15C shows a schematic cross-sectional view of the structure at the stage, illustrated along line CC' shown in Figure 15A. Referring to Figures 15A to 15C, the thermal oxide layer 2205 grows along the exposed sidewall of the active region and inside the slot 2210. The thermal oxide layer 2205 may be formed by oxidizing the exposed sidewall of the active region. In the Z direction, the upper surface of the thermal oxide layer 2205 may be located lower than the upper surface of the pad oxide layer 2204 and the lower surface of the pad nitride layer 2206. In this way, an asymmetric spacer containing different materials (such as the thermal oxide layer 2205 and the SiOCN material 2209) is formed inside the STI region 2214. From another perspective, the asymmetric spacer covers two sidewalls of each active region (or two sidewalls of each STI region). The thermal oxide layer 2205 can be considered a second spacer. The asymmetric spacer may include a first spacer and a second spacer.

[0068] Figure 16A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 16B shows a schematic cross-sectional view of the structure at the stage, illustrated along line BB' shown in Figure 16A, and Figure 16C shows a schematic cross-sectional view of the structure at the stage, illustrated along line CC' shown in Figure 16A. Referring to Figures 16A to 16C, the deposition process sequentially forms the TiN layer 2303 and the tungsten layer 2305 inside the slot 2210, and then an etch-back process is performed to remove a portion of the TiN layer 2303 and a portion of the tungsten layer 2305. After the etch-back process, a photolithography process is performed to separate the TiN layer 2303 and the tungsten layer 2305 into multiple remaining TiN layers 2303 and remaining tungsten layers 2305. The remaining tungsten layers 2305 can be defined as an underground interconnect (UGI) structure. The remaining TiN layer 2303 can then be designated as a barrier layer.

[0069] Figure 17A shows a schematic top view of the structure at a stage of the manufacturing method. Figure 17B shows a schematic cross-sectional view of the structure at the stage, illustrated along line BB' shown in Figure 17A. Figure 17C shows a schematic cross-sectional view of the structure at the stage, illustrated along line CC' shown in Figure 17A. Referring to Figures 17A to 17C, a SiN layer 2307 and an HDP (high-density plasma) oxide layer 2309 are sequentially formed above the tungsten layer 2305 and the TiN layer 2303. Thus, a structure is provided that includes an underground interconnect structure within the STI region. The manufacturing step of forming a transistor within the active region may be performed after the stages shown in Figures 17A to 17C.

[0070] The methods shown in Figures 1A to 17C provide an underground interconnection structure (e.g., tungsten layer 1305 shown in Figure 8C and tungsten layer 2305 shown in Figure 17C) located below the original semiconductor surface and within the STI region. The UGI structure may extend along the STI region. The UGI structure is insulated from the semiconductor substrate. Optionally, some UGI structures may be electrically connected to a transistor. In one embodiment, the UGI structure may be electrically connected to the source or drain terminal of the transistor by a self-alignment or self-construction method via a connection plug located within the active region housing the transistor. It is important in this disclosure to form multiple asymmetric spacers along the sidewalls of the active region (e.g., the thermal oxide layer 1205 and SiOCN material 1209 shown in Figure 8C, and the thermal oxide layer 2205 and SiOCN material 2209 shown in Figure 17C), and to form UGI structures between the multiple asymmetric spacers and below the original semiconductor surface. UGI structures located inside the semiconductor substrate may form a UGI mesh that extends to other preliminary STI regions or larger STI regions, away from the active region of the semiconductor substrate. The UGI mesh may be understood as a middle-side signal delivery network ("Mid-side Signal Network") and / or a heat dissipation network. The use of a UGI mesh inside a chip or semiconductor substrate may result in greater misalignment tolerance, deriving from larger STI regions that have more space for signal paths. The use of a UGI mesh may shorten the path connecting back-side TSVs to the UGI mesh, improving IR drop in signal transmission. Furthermore, the use of UGI mesh can enhance heat dissipation and improve the aforementioned drawbacks in ICs primarily formed by transistors.

[0071] [Electrical connection between UGI structure and fin field-effect transistor]

[0072] The following description uses a FinFET as an example to illustrate a method for electrically connecting a UGI structure to the source or drain terminal of a transistor. The source or drain terminal of the FinFET may be formed by a selective epitaxy growth process. The techniques described herein are also applicable to the electrical connection of a UGI structure to the source / drain terminals of a GAA transistor, CFET, or planar transistor (the source / drain terminals of a planar transistor may be formed by an ion implantation process).

[0073] <Embodiment for the first connection>

[0074] Figures 18 to 22C illustrate a method for electrically connecting an underground interconnect structure to a transistor according to this embodiment of the present disclosure. In one embodiment, the manufacturing steps illustrated with reference to Figures 18 to 22C may be performed after the manufacturing steps illustrated with reference to Figures 1A to 9, or after the manufacturing steps illustrated with reference to Figures 10A to 17C.

[0075] Figure 18 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. Figure 18A shows a schematic cross-sectional view of the structure illustrated along line AA shown in Figure 18. Figure 18B shows a schematic cross-sectional view of the structure illustrated along line BB shown in Figure 18. Figure 18C shows a schematic cross-sectional view of the structure illustrated along line CC shown in Figure 18. Referring to Figures 18 to 18C, after forming the structure including the UGI structure 282 protected by the asymmetric spacer 283 inside the STI region 284, a dummy gate structure 280 (or, in some cases, a real gate structure) and a spacer structure 281 covering the dummy gate structure 280 are formed based on a standard foundry process (construction process). Subsequently, a portion of the active region (or fin structure) located outside the spacer structure 281 and above the upper surface 284U of the STI region 284 is exposed (or made exposed). The dummy gate structure 280 may include a cap nitride layer 2804, a cap oxide layer 2801, a semiconductor layer 2802, and a high-k dielectric layer 2803, which are stacked along the Z direction. The semiconductor layer 2802 may be located between the cap oxide layer 2801 and the high-k dielectric layer 2803. The cap oxide layer 2801 may contain an oxide. The semiconductor layer 2802 may contain a semiconductor material such as polycrystalline silicon. The high-k dielectric layer 2803 may contain a dielectric material having a high dielectric constant. The spacer structure 281 may be a composite of a first spacer material 2811 and a second spacer material 2812 different from the first spacer material 2811. In one embodiment, the first spacer material 2811 may be an oxide, and the second spacer material 2812 may be a nitride. The spacer structure 281 may cover a plurality of side walls located on opposite sides of the dummy gate structure 280. The UGI structure 282 may be any conductive material (e.g., the tungsten layer 1305 shown in Figure 8C, or the tungsten layer 2305 shown in Figure 17C). The STI region 284 may be the STI region 1214 shown in Figure 8C, or the STI region 2214 shown in Figure 17C.The asymmetric spacer 283 includes a first spacer 2831 covering the first side of the UGI structure 282 and a second spacer 2832 covering the second side of the UGI structure 282. The first side of the UGI structure 282 is opposite to the second side of the UGI structure 282. The material of the first spacer 2831 is different from the material of the second spacer 2832. The first spacer 2831 and the second spacer 2832 may be arranged alternately along the Y direction. The first spacer 2831 may be the SiOCN material 1209 shown in Figure 8C or the SiOCN material 2209 shown in Figure 17C. The second spacer 2832 may be the thermal oxide layer 1205 shown in Figure 8C or the thermal oxide layer 2205 shown in Figure 17C.

[0076] Next, the exposed portion of the active region and other fin structures made of silicon located below the exposed portion of the active region (below the upper surface 284U of the STI region 284) are removed by the etching process. As a result, a trench 285 is formed, and the aforementioned asymmetric spacer 283 is exposed. The vertical sidewall of the active region having a crystal orientation (110), located directly below the spacer structure 281 covering the dummy gate structure 280, is also exposed. The trench 285 is located inside the active region.

[0077] Figures 19A to 19C are schematic cross-sectional views of a structure at a certain stage of the manufacturing method, obtained by cutting the structure at different angles. The cross-sectional view in Figure 18A and the cross-sectional view in Figure 19A are obtained at approximately the same angle and position. The cross-sectional view in Figure 18B and the cross-sectional view in Figure 19B are obtained at approximately the same angle and position. The cross-sectional view in Figure 18C and the cross-sectional view in Figure 19C are obtained at approximately the same angle and position. Referring to Figures 19A to 19C, a thermal oxidation process forms a thermal oxide layer 296 at the bottom of the trench 285. The aforementioned vertical sidewalls of the active region having a crystal orientation (110) are also oxidized. Next, the first spacer 2831, one of the multiple asymmetric spacers 283 exposed by the trench 285, is removed by an etching process, exposing the sidewalls of the UGI structure 282. The second spacer 2832 is left in place (as shown in Figure 19B). In some embodiments, if a nitride spacer (e.g., TiN layer 1303 shown in Figure 8C, or TiN layer 2303 shown in Figure 17C) is used, the nitride spacer is removed along with the first spacer 2831. The thermal oxide layer 296 may contain silicon dioxide (SiO2).

[0078] Figures 20A to 20C are schematic cross-sectional views of a structure at a certain stage of the manufacturing method, obtained by cutting the structure at different angles. The cross-sectional view in Figure 18A and the cross-sectional view in Figure 20A are obtained at approximately the same angle and position. The cross-sectional view in Figure 18B and the cross-sectional view in Figure 20B are obtained at approximately the same angle and position. The cross-sectional view in Figure 18C and the cross-sectional view in Figure 20C are obtained at approximately the same angle and position. Referring to Figures 20A to 20C, a TiN film 3071 and a conductive film 3072 are formed inside the trench 285 by an atomic layer deposition process. The TiN film 3071 may be formed on the top surface and sidewalls of the thermal oxide layer 296. The conductive film 3072 may be formed on the top surface and sidewalls of the TiN film 3071. The TiN film 3071 may exist between the conductive film 3072 and the thermal oxide layer 296. The TiN film 3071 and the conductive film 3072 may form a connecting plug 307 for electrically connecting the exposed sidewalls of the UGI structure 282. As shown in Figure 20B, the connecting plug 307 may be in contact with the exposed sidewalls of the UGI structure 282. The conductive film 3072 may contain a conductive material such as tungsten (W), or may be made of such a conductive material. The connecting plug 307 is formed inside the active region. Part of the thermal oxide layer 296 is covered by the connecting plug 307. On the other hand, as shown in Figure 20C, another part of the thermal oxide layer 296 is exposed.

[0079] Figures 21A to 21C are schematic cross-sectional views of the structure at a certain stage of the manufacturing method, obtained by cutting the structure at different angles. The cross-sectional view in Figure 18A and the cross-sectional view in Figure 21A are obtained at approximately the same angle and position. The cross-sectional view in Figure 18B and the cross-sectional view in Figure 21B are obtained at approximately the same angle and position. The cross-sectional view in Figure 18C and the cross-sectional view in Figure 21C are obtained at approximately the same angle and position. Referring to Figures 21A to 21C, the exposed portion of the thermal oxide layer 296 is removed by the etching process, exposing a portion of the vertical sidewall of the active region having a crystal orientation (110).

[0080] Figure 22 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. Figure 22A shows a schematic cross-sectional view of the structure illustrated along line AA shown in Figure 22. Figure 22B shows a schematic cross-sectional view of the structure illustrated along line BB shown in Figure 22. Figure 22C shows a schematic cross-sectional view of the structure illustrated along line CC shown in Figure 22. Referring to Figures 22 to 22C, a selective epitaxy growth (SEG) process forms a first lightly doped region 3281, a second lightly doped region 3282, a first conductive region (or first heavily doped region) 3291, and a second conductive region (or second heavily doped region) 3292, based on the exposed portion of the vertical sidewall of the active region having a crystal orientation (110). The exposed portion of the vertical side wall of the active region may be located directly below the spacer structure 281. The first light-doped region 3281 and the second light-doped region 3282 may be formed on the exposed portion of the vertical side wall of the active region and below the spacer structure 281. The first light-doped region 3281 may be in contact with the first conductive region 3291. The second light-doped region 3282 may be in contact with the second conductive region 3292. The first conductive region 3291 is connected to (or made to be in contact with) the connection plug 307. The connection plug 307 is then connected to the UGI structure 282. Thus, the UGI structure 282 is electrically connected to the first conductive region 3291 via the connection plug 307. The second conductive region 3292 is connected to (or made to be in contact with) the connection plug 307. The connection plug 307 is then connected to the UGI structure 282. Therefore, the UGI structure 282 is electrically connected to the second conductive region 3292 via the connecting plug 307. The first lightly doped region 3281 and the second lightly doped region 3282 may contain doped semiconductor material (e.g., N-type silicon). The first conductive region 3291 and the second conductive region 3292 may also contain doped semiconductor material (e.g., N-type silicon).The first conductive region 3291 and the second conductive region 3292 may be highly doped. The first conductive region 3291 may function as either the source or the drain of the FinFET. The second conductive region 3292 may function as the other either the source or the drain of the FinFET. In one embodiment, after forming the structure shown in Figure 22, a conventional gate-last process may be performed to replace the dummy gate structure 280 with the gate structure of the FinFET to complete the formation of the FinFET. The FINFET may include a channel region defined between the drain and the source.

[0081] <Embodiment for the second connection>

[0082] Figures 23 to 26 illustrate a method for electrically connecting an underground interconnect structure to a transistor according to this embodiment of the present disclosure. In some embodiments, the manufacturing steps illustrated with reference to Figures 23 to 26 may be performed after the manufacturing steps illustrated with reference to Figures 1A to 9, or after the manufacturing steps illustrated with reference to Figures 10A to 17C.

[0083] Figure 23 shows a three-dimensional schematic diagram of a structure at a stage of the manufacturing method of the present invention. Figure 23A shows a schematic cross-sectional view of the structure illustrated along line AA shown in Figure 23. Figure 23B shows a schematic cross-sectional view of the structure illustrated along line BB shown in Figure 23. Figure 23C shows a schematic cross-sectional view of the structure illustrated along line CC shown in Figure 23. Referring to Figures 23 to 23C, after forming a structure including a UGI structure 332 protected by an asymmetric spacer 333 inside the STI region 334, a dummy gate structure 330 and a spacer structure 331 covering the side wall of the dummy gate structure 330 are formed based on a standard foundry process. Then, a portion of the active region (or fin structure) located outside the spacer structure 331 and above the upper surface 334U of the STI region 334 is exposed. The dummy gate structure 330 may include a cap nitride layer 3304, a cap oxide layer 3301, a semiconductor layer 3302, and a high-k dielectric layer 3303, which are stacked along the Z direction. The cap oxide layer 3301 may contain an oxide. The semiconductor layer 3302 may contain a semiconductor material such as polycrystalline silicon. The high-k dielectric layer 3303 may contain a dielectric material having a high dielectric constant. The spacer structure 331 may be a composite of a first spacer material 3311 and a second spacer material 3312 different from the first spacer material 3311, similar to the spacer structure 281 described in Figure 18. Therefore, the details of the spacer structure 331 are omitted. The UGI structure 332 may be a tungsten layer 1305 with a TiN layer, as shown in Figure 8C or Figure 17C. The STI region 334 may be the STI region 1214 shown in Figure 8C, or the STI region 2214 shown in Figure 17C. The asymmetric spacer 333, like the asymmetric spacer 283 in Figure 18, includes a first spacer 3331 located on the first side of the UGI structure 332 and a second spacer 3332 located on the second side of the UGI structure 332. Therefore, details of the asymmetric spacer 333 are omitted.

[0084] Next, the exposed active region located above the upper surface 334U of the STI region 334 is removed by the etching process. As a result, the horizontal surface of the active region having a crystal orientation (100) located near the upper surface 334U of the STI region 334 is exposed. The vertical side wall of the active region having a crystal orientation (110) located directly below the spacer structure 331 covering the dummy gate structure 330 is also exposed. The upper surface of the first spacer 3331 is also exposed. The horizontal surface of the active region having a crystal orientation (100) may be located in the Z direction lower than the upper surface 334U of the STI region 334 and higher than the upper surface of the UGI structure 332.

[0085] Figures 24A to 24C are schematic cross-sectional views obtained by cutting a structure at a certain stage of the manufacturing method at different angles. The cross-sectional view in Figure 23A and the cross-sectional view in Figure 24A are obtained at approximately the same angle and position. The cross-sectional view in Figure 23B and the cross-sectional view in Figure 24B are obtained at approximately the same angle and position. The cross-sectional view in Figure 23C and the cross-sectional view in Figure 24C are obtained at approximately the same angle and position. Referring to Figures 24A to 24C, based on the exposed upper surface of the first spacer 3331, the first spacer 3331 covering the dummy gate structure 330 outside the spacer structure 331 is removed by the etching process. As a result, a thin slot 345 is formed inside the STI region 334, and the side wall of the UGI structure 332 is exposed. The second spacer 3332 remains (see Figure 24B). In one embodiment, if a nitride spacer (e.g., TiN layer 1303 shown in Figure 8C, or TiN layer 2303 shown in Figure 17C) is used, the nitride spacer is removed along with the first spacer 3331. Then, a portion of the fin structure is exposed inside the thin slot 345.

[0086] Figure 25 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. Figure 25A shows a schematic cross-sectional view of the structure illustrated along line AA shown in Figure 25. Figure 25B shows a schematic cross-sectional view of the structure illustrated along line BB shown in Figure 25. Figure 25C shows a schematic cross-sectional view of the structure illustrated along line CC shown in Figure 25. Referring to Figures 25 to 25C, a connection plug 3595 is formed inside the thin slot 345 by the atomic layer deposition process. The connection plug 3595 may contact the exposed sidewall of the UGI structure 332. The connection plug 3595 may be formed inside the STI region 334 along the sidewall of the active region. The connection plug 3595 may contain a conductive material such as titanium nitride, formed by ALD (atomic layer deposition).

[0087] Next, a first lightly doped semiconductor region 3581, a second lightly doped semiconductor region 3582, a first heavily doped semiconductor region 3591, and a second heavily doped semiconductor region 3592 are formed by a selective epitaxy growth (SEG) process based on the exposed horizontal surface of the active region having a crystal orientation (100) and the exposed vertical sidewall of the active region having a crystal orientation (110). The first lightly doped semiconductor region 3581 and the second lightly doped semiconductor region 3582 may be formed on the exposed horizontal surface of the active region having a crystal orientation (100) and on the exposed vertical sidewall of the active region having a crystal orientation (110). The first lightly doped semiconductor region 3581 and the second lightly doped semiconductor region 3582 may be in contact with the horizontal surface and the vertical sidewall. The first heavily doped semiconductor region 3591 may be in contact with the first lightly doped semiconductor region 3581. The second double-doped semiconductor region 3592 may be in contact with the second lightly doped semiconductor region 3582. The UGI structure 332 is electrically connected to the first double-doped semiconductor region 3591. In another example, the UGI structure 332 is electrically connected to the second double-doped semiconductor region 3592. The first lightly doped semiconductor region 3581 and the second lightly doped semiconductor region 3582 may contain doped semiconductor material (e.g., N-type silicon). The first double-doped semiconductor region 3591 and the second double-doped semiconductor region 3592 may contain heavily doped semiconductor material. In one embodiment, after forming the structure shown in Figure 25, a conventional gate-last process may be performed to replace the dummy gate structure 330 with a gate structure having a FinFET to complete the formation of the FinFET. In one embodiment, as shown in Figure 26, the gate structure of the FinFET is formed by removing the cap nitride layer 3304, the cap oxide layer 3301, the semiconductor layer 3302, and the high-k dielectric layer 3303 and replacing them with a gate dielectric material 3601 and a gate conductive material 3602. The FINFET may include a channel region defined between the drain and the source.

[0088] <Embodiment of the third connection>

[0089] Figures 27-28 illustrate a method for electrically connecting an underground interconnect structure to a transistor according to this embodiment of the present disclosure. In some embodiments, the manufacturing steps illustrated with reference to Figures 27-28 may be performed after the manufacturing steps illustrated with reference to Figures 24A-24C.

[0090] Figure 27 shows a three-dimensional schematic diagram of a structure at a stage of the manufacturing process. Figure 27A shows a schematic cross-sectional view of the structure along line AA shown in Figure 27, Figure 27B shows a schematic cross-sectional view of the structure along line BB shown in Figure 27, and Figure 27C shows a schematic cross-sectional view of the structure along line CC shown in Figure 27.

[0091] Next, based on the exposed horizontal surface of the active region having a crystal orientation (100) and the exposed vertical sidewall of the active region having a crystal orientation (110), a first lightly doped semiconductor region 3581, a second lightly doped semiconductor region 3582, a first heavily doped semiconductor region 3591, and a second heavily doped semiconductor region 3592 are formed by a selective epitaxial growth (SEG) process. During the formation of the first heavily doped semiconductor region 3591, a connecting plug 3795 grown by SEG using a heavily doped semiconductor material may also be formed inside the thin slot 345.

[0092] The first heavily doped semiconductor region 3591 and the connecting plug 3795 are electrically connected to each other. Thus, the UGI structure 332 is electrically connected to the first heavily doped semiconductor region 3591 via the connecting plug 3795. After the formation of the structure shown in Figure 27, the formation of the FinFET can be completed by performing the conventional gate-last process shown in Figure 28, which replaces the dummy gate structure 330 with the gate structure of the FinFET. Details of the FinFET are explained in Figure 26.

[0093] <Embodiment for the fourth connection>

[0094] Figures 29 to 37A illustrate a method for electrically connecting an underground interconnect structure to a transistor according to this embodiment of the present disclosure. In one embodiment, the manufacturing steps illustrated with reference to Figures 29 to 37A may be performed after the manufacturing steps illustrated with reference to Figures 1A to 9, or after the manufacturing steps illustrated with reference to Figures 10A to 17C.

[0095] Figure 29 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. After forming the structure, including the UGI structure 392 protected by the asymmetric spacer 393, inside the STI region 394, a dummy gate structure 390 and a spacer structure 391 covering the sidewall of the dummy gate structure 390 are formed based on a standard foundry process. Then, outside the spacer structure 391, a portion of the active region (or fin structure) is exposed. The structure of the dummy gate structure 390 may be the same as the structure of the dummy gate structure 280 or the structure of the dummy gate structure 330. The spacer structure 391 may be the same as the spacer structure 281 or the spacer structure 331. The UGI structure 392 may be a tungsten layer 1305 with a TiN layer, as shown in Figure 8C or Figure 17C. The STI region 394 may be the STI region 1214 shown in Figure 8C or the STI region 2214 shown in Figure 17C. The asymmetric spacer 393 includes a first spacer 3931 located on the first side of the UGI structure 392 and a second spacer 3932 located on the second side of the UGI structure 392. The first spacer 3931 may be the SiOCN material 1209 shown in Figure 8C or the SiOCN material 2209 shown in Figure 17C. The second spacer 3932 may be the thermal oxide layer 1205 shown in Figure 8C or the thermal oxide layer 2205 shown in Figure 17C. The thickness of the spacer structure 391 in the X direction may be greater than the thickness of the spacer structure 281 and the spacer structure 331. The width of the spacer structure 391 in the Y direction may be determined by the position of the UGI structure 392. Next, as shown in Figure 29, the active region not covered by the dummy gate structure 390 and the spacer structure 391 is partially removed.

[0096] Figure 30 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. The lithography patterning photomask 405 is formed to cover a first portion of the exposed portion of the active region. A trench 406 is formed inside the active region by removing a second portion of the exposed portion of the active region (which is not covered by the lithography patterning photomask 405, is located below the upper surface 394U of the STI region 394, and is made of silicon) by an etching process. In this embodiment, the first and second portions of the exposed portion of the active region may be located on opposite sides of the dummy gate structure 390 in the X direction. The asymmetric spacer 393 is exposed by the trench 406. The vertical sidewall of the active region having a crystal orientation (110) is located below the spacer structure 391. The horizontal surface of the active region having a crystal orientation (100) is exposed by the trench 406.

[0097] Figure 31 shows a three-dimensional schematic diagram illustrating the structure at a stage of the manufacturing method. A thermal oxide layer 416 is formed by a thermal oxidation process at the bottom of the trench 406 (i.e., on the horizontal surface of the active region having a crystal orientation (100)) and on the vertical sidewall of the active region having a crystal orientation (110), located directly below the spacer structure 391.

[0098] Figure 32 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. A first spacer 3931, one of several asymmetric spacers 393 exposed by a trench 406, is removed by an etching process, exposing the sidewall of the UGI structure 392. The second spacer 3932 is left. After the sidewall of the UGI structure 392 is exposed, a connecting plug 427 is formed inside the trench 406 to connect the exposed sidewall of the UGI structure 392. In one embodiment, the connecting plug 427 may include a TiN film and a conductive film. The conductive film may contain tungsten(W) or may be made of tungsten(W). In this example, the connecting plug 427, which is self-aligned with the UGI structure 392, is formed inside the active region.

[0099] Figure 33 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. A portion of the thermal oxide layer 416 covering the vertical sidewall of the active region having a crystal orientation (110) is removed by the etching process. Then, a portion of the vertical sidewall of the active region located above the upper surface 394U of the STI region 394 is exposed.

[0100] Figure 34 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. The lithography patterning photomask 405 has been removed. Spacer structure 441 may be formed based on the requirements for electrical performance and the UGI process window by reducing the thickness of spacer structure 391 in the X direction. The excess portion 448 of the fin structure is exposed outside spacer structure 441. In another embodiment, spacer structure 441 is not formed by thinning spacer structure 391. In another embodiment, spacer structure 391 is removed and then spacer structure 441 is formed using a low-k dielectric material.

[0101] Figure 35 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. The excess portion 448 of the fin structure (which may be made of silicon) may be removed by an anisotropic etching process. The horizontal surface of the active region having a crystal orientation (100) located near the upper surface 394U of the STI region 394 and the vertical side wall of the active region having a crystal orientation (110) located directly below the spacer structure 441 are exposed. The exposed vertical side wall of the active region may be slightly recessed relative to the surface of the spacer structure 441.

[0102] Figure 36 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. Based on the exposed horizontal surface of the active region having a crystal orientation (100) and the exposed vertical sidewall of the active region having a crystal orientation (110) located directly below the spacer structure 441, the first lightly doped region 4681, the second lightly doped region 4682, the first conductive region (or first highly doped semiconductor region) 4691, and the second conductive region (or second highly doped semiconductor region) 4692 are formed by a selective epitaxial growth (SEG) process, completing the formation of the source and drain of the FinFET. Thus, the UGI structure 392 is electrically connected to the first conductive region 4691 via the connecting plug 427.

[0103] Figure 37 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. Figure 37A shows a schematic cross-sectional view of the structure illustrated along line AA shown in Figure 37. The dummy gate structure 390 is replaced by the real gate structure 470 of the FinFET. For example, the real gate structure 470 of the FinFET may be a high-k metal gate (HKMG) structure. To further connect the first conductive region 4691 and the connecting plug 427, a metal cap (M0) 475 covering the first conductive region 4691 may be formed by a conventional metal zero (M0) layer process. This reduces contact resistance. In this way, a conventional FinFET having a connecting plug 427 to the UGI structure 392 is completed. The FINFET may include a defined channel region between the drain and the source. The metal cap 475 may include a titanium nitride (TiN) layer and a tungsten (W) layer located on the titanium nitride layer.

[0104] <Embodiment for the fifth connection>

[0105] Figures 38 to 48A illustrate a method for electrically connecting an underground interconnect structure to a transistor according to several embodiments of the present disclosure. In one embodiment, the manufacturing steps illustrated with reference to Figures 38 to 48A may be performed after the manufacturing steps illustrated with reference to Figures 1A to 9, or after the manufacturing steps illustrated with reference to Figures 10A to 17C.

[0106] Figure 38 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. After forming the structure, including the UGI structure 482 protected by the asymmetric spacer 483, inside the STI region 484, a dummy gate structure 480 and a spacer structure 481 covering the sidewall of the dummy gate structure 480 are formed based on a standard foundry process. Then, outside the spacer structure 481, a portion of the active region (or fin structure) is partially removed. The structure of the dummy gate structure 480 may be the same as the structure of the dummy gate structure 280 or the structure of the dummy gate structure 330. The structure of the spacer structure 481 may be the same as the structure of the spacer structure 281 or the structure of the spacer structure 331. The UGI structure 482 may be the tungsten layer 1305 shown in Figure 8C or the tungsten layer 2305 shown in Figure 17C. The STI region 484 may be the STI region 1214 shown in Figure 8C, or the STI region 2214 shown in Figure 17C. The asymmetric spacer 483 includes a first spacer 4831 located on the first side of the UGI structure 482 and a second spacer 4832 located on the second side of the UGI structure 482. The bottom surface 480B of the dummy gate structure 480 in the STI region 484 is located lower than the top surface 484U of the STI region 484.

[0107] Figure 39 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. A lithographic patterning photomask 495 is formed to cover a first portion of the exposed part of the active region. A second portion of the exposed part of the active region (which is not covered by the lithographic patterning photomask 495, is located below the upper surface 484U of the STI region 484, and is made of silicon) is further etched down by an etching process. As a result, a trench 496 is formed inside the active region. The asymmetric spacer 483 is exposed by the trench 496. The vertical sidewall of the active region having a crystal orientation (110) and the horizontal surface of the active region having a crystal orientation (100) are exposed by the trench 496.

[0108] Figure 40 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. A thermal oxidation process forms a thermal oxide layer 506 on the bottom surface of the trench 496 (i.e., on the horizontal surface of the active region having a crystal orientation (100)) and on the vertical side wall of the active region having a crystal orientation (110), located directly below the spacer structure 481.

[0109] Figure 41 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. A first spacer 4831, one of several asymmetric spacers 483 exposed by a trench 496, is removed by an etching process, exposing the sidewall of the UGI structure 482. The second spacer 4832 is left. After the sidewall of the UGI structure 482 is exposed, a connecting plug 517 is formed inside the trench 496 to connect the exposed sidewall of the UGI structure 482. In one embodiment, the connecting plug 517 may include a TiN film and a conductive film. The conductive film may contain tungsten (W) or may be made of tungsten (W).

[0110] Figure 42 is a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. A portion of the thermal oxide layer 506 covering the vertical sidewall of the active region having a crystal orientation (110) is removed by the etching process. As a result, a portion of the vertical sidewall of the active region located above the upper surface 484U of the STI region 484 is exposed.

[0111] Figure 43 is a three-dimensional schematic diagram of a structure at a stage of the manufacturing method. The lithography patterning photomask 495 is removed. To form the structure shown in Figure 43, several spacer structures 481 located on the opposite side of the dummy gate structure 480 may be removed. In the structure shown in Figure 43, the excess portion 538 of the fin structure located outside the dummy gate structure 480 is exposed. A recess 539 is formed inside the STI region 484. The sidewalls of the dummy gate structure 480 and the sidewalls of the excess portion 538 may be exposed by the recess 539. The recess 539 may be located on the opposite side of the dummy gate structure 480. In another embodiment, in order to redefine the length of the channel region based on electrical performance requirements and the UGI process window, the thickness in the X direction of the removed spacer structures 481 may be reduced to form thinner spacer structures.

[0112] Figure 44 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. Dielectric elements 549 may be formed inside the recess 539 by a deposition process and an etch-back process. The upper surface of the dielectric element 549 may be aligned with the upper surface 484U of the STI region 484. The upper surface of the dielectric element 549 may be coplanar with the upper surface 484U of the STI region 484.

[0113] Figure 45 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. Spacer structures 551 are formed on a plurality of side walls located opposite each other of the dummy gate structure 480 and on the dielectric element 549 in order to redefine the length of the channel region based on the requirements for electrical performance and the UGI process window. The spacer structures 551 may cover the plurality of side walls located opposite each other of the dummy gate structure 480. The spacer structures 551 may contain a low-k dielectric material or may be fabricated from a low-k dielectric material.

[0114] Figure 46 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. A portion of the fin structure (which may be made of silicon and not covered by the spacer structure 551) may be removed by an anisotropic etching process. As a result, the horizontal surface of the active region having a crystal orientation (100) located near the upper surface 484U of the STI region 484, and the vertical side wall of the active region having a crystal orientation (110) located directly below the spacer structure 551 are exposed.

[0115] Figure 47 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. Based on the exposed horizontal surface of the active region having a crystal orientation (100) and the exposed vertical sidewall of the active region having a crystal orientation (110) located directly beneath the spacer structure 551, the first lightly doped region 5781, the second lightly doped region 5782, the first conductive region (or first highly doped semiconductor region) 5791, and the second conductive region (or second highly doped semiconductor region) 5792 are formed by the selective epitaxy growth (SEG) process. This completes the formation of the source and drain of the FinFET as described above. The first conductive region 5791 is connected to (or in contact with) the connection plug 517. The connection plug 517 is connected to the UGI structure 482. Thus, the UGI structure 482 is electrically connected to the first conductive region 5791 via the connection plug 517.

[0116] Figure 48 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. Figure 48A shows a schematic cross-sectional view of the structure illustrated along line AA shown in Figure 48. The dummy gate structure 480 is replaced with the actual gate structure 580 of the FinFET. For example, the actual gate structure 580 of the FinFET may be a high-k metal gate (HKMG). The bottom 580B of the gate structure 580 in the STI region 484 is located lower than the bottom of the first conductive region 5791 and the bottom of the second conductive region 5792. To further connect the first conductive region 5791 and the connector plug 517, a metal cap (M0) 585 covering the first conductive region 5791 may be formed by a conventional metal zero (M0) layer process. This reduces contact resistance. In this way, a conventional FinFET having a connector plug 517 for the UGI structure 482 is completed.

[0117] <Form of the sixth connection>

[0118] The following description uses a GAA transistor as an example to explain how to electrically connect a UGI structure to the source or drain terminal of a transistor. The source or drain terminal of the GAA transistor may be formed by a selective epitaxy growth process.

[0119] Figures 49 to 57A illustrate a method for electrically connecting an underground interconnect structure to a transistor according to several embodiments of the present disclosure. In one embodiment, the manufacturing steps illustrated with reference to Figures 49 to 57A may be performed after the manufacturing steps illustrated with reference to Figures 1A to 9, or after the manufacturing steps illustrated with reference to Figures 10A to 17C. The method in this embodiment differs from the methods in the embodiments described above in that it involves exposing the vertical sidewalls of a semiconductor nanosheet located below the spacer structure of a GAA transistor (as shown in Figures 49 to 55), rather than exposing the vertical sidewalls of a fin structure located directly below the spacer structure of a FinFET transistor (e.g., Figures 27 to 33).

[0120] Figure 49 shows a three-dimensional schematic diagram of the structure at one stage of the manufacturing method. After forming a structure including a UGI structure 592 protected by an asymmetric spacer 593 inside an STI region 594, a dummy gate structure 590 and a spacer structure 591 covering the sidewalls of the dummy gate structure 590 are formed on a nanosheet stack (nanosheet laminate) 595 based on a standard foundry process. Then, a portion of the active region located outside the spacer structure 591 is partially removed. The nanosheet stack 595 includes semiconductor nanosheets 5951 and sacrificial nanosheets 5952 that are alternately stacked along the Z direction. The material of the semiconductor nanosheets 5951 may be different from the material of the sacrificial nanosheets 5952. The semiconductor nanosheets 5951 may contain a semiconductor material such as silicon, or may be fabricated from such a semiconductor material. The sacrificial nanosheets 5952 may contain silicon germanium (SiGe), or may be fabricated from SiGe. The nanosheet stack 595 may be formed by an epitaxial growth process. In the structure shown in Figure 49, the vertical sidewall of the semiconductor nanosheet 5951 located below the spacer structure 591 is exposed. The exposed vertical sidewall of the semiconductor nanosheet 5951 may have a crystal orientation (110). The structure of the dummy gate structure 590 may be the same as the structure of the dummy gate structure 280, or the same as the structure of the dummy gate structure 330. The spacer structure 591 does not have to cover the top surface of the dummy gate structure 590. The structure of the spacer structure 591 may be the same as the structure of the spacer structure 281, or the same as the structure of the spacer structure 331. The UGI structure 592 may be the tungsten layer 1305 with a TiN layer shown in Figure 8C, or the tungsten layer 2305 with a TiN layer shown in Figure 17C. The STI region 594 may be the STI region 1214 shown in Figure 8C, or the STI region 2214 shown in Figure 17C.As described above, the asymmetric spacer 593 includes a first spacer 5931 located on the first side of the UGI structure 592 and a second spacer 5932 located on the second side of the UGI structure 592. The nanosheet stack 595, the dummy gate structure 590, and the spacer structure 591 may be located above the upper surface 594U of the STI region 594.

[0121] Figure 50 is a three-dimensional schematic diagram showing the structure at a stage of the manufacturing method. A lithography patterning photomask 605 is formed to cover a first portion of the exposed part of the active region. A second portion of the exposed part of the active region (this second portion is not covered by the lithography patterning photomask 605, is located below the upper surface 594U of the STI region 594, and is made of silicon) is further etched down by an etching process. This forms a trench 606 inside the active region. The asymmetric spacer 593 is exposed by the trench 606. The vertical sidewall of the active region having a crystal orientation (110), located below the spacer structure 591, is exposed. The horizontal surface of the active region having a crystal orientation (100) is then exposed by the trench 606.

[0122] Figure 51 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. The thermal oxidation process forms a thermal oxide layer 616 at the bottom of the trench 606 (i.e., on the horizontal surface of the active region), on the sidewall of the trench 606 (i.e., on the vertical sidewall of the active region located directly beneath the spacer structure 591), and on the exposed vertical sidewall of the semiconductor nanosheet 5951 located directly beneath the spacer structure 591.

[0123] Figure 52 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. A first spacer 5931, one of several asymmetric spacers 593 exposed by a trench 606, is removed by an etching process, exposing the side wall of the UGI structure 592. The second spacer 5932 is left in place. After the side wall of the UGI structure 592 is exposed, a connecting plug 627 is formed inside the trench 606 to connect the exposed side wall of the UGI structure 592.

[0124] Figure 53 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. A portion of the thermal oxide layer 616 covering the vertical sidewall of the semiconductor nanosheet 5951 located directly beneath the spacer structure 591 is removed by the etching process. As a result, the vertical sidewall of the semiconductor nanosheet 5951 having a crystal orientation (110) located directly beneath the spacer structure 591 is exposed.

[0125] Figure 54 shows a three-dimensional schematic diagram of the structure at one stage of the manufacturing method. The lithography patterning photomask 605 is removed. Spacer structure 641 may be formed based on the requirements for electrical performance and the UGI process window by reducing the thickness of spacer structure 591 in the X direction. Thus, the excess portion 648 of the semiconductor nanosheet 5951 is exposed outside of spacer structure 641. At this stage, sacrificial nanosheet 5952 located between multiple semiconductor nanosheets 5951 may be removed. In another embodiment, spacer structure 641 is not formed by thinning spacer structure 591. In another embodiment, spacer structure 641 is formed by removing spacer structure 591 and then using a low-k dielectric material.

[0126] Figure 55 is a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. The excess portion 648 of the semiconductor nanosheet 5951 may be removed by an anisotropic etching process. Thus, the horizontal surface of the active region having a crystal orientation (100) located near the upper surface 594U of the STI region 594, and the vertical sidewall of the semiconductor nanosheet 5951 having a crystal orientation (110) located directly below the spacer structure 641 are exposed. The exposed vertical sidewall of the semiconductor nanosheet 5951 may be slightly recessed relative to the surface of the spacer structure 641.

[0127] Figure 56 is a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. Based on the exposed horizontal surface of the active region having a crystal orientation (100) and the exposed vertical sidewall of the semiconductor nanosheet 5951 having a crystal orientation (110), the first light-doped region 6681, the second light-doped region 6682, the first conductive region (or first highly-doped semiconductor region) 6691, and the second conductive region (or second highly-doped semiconductor region) 6692 are formed by the selective epitaxy growth (SEG) process described above. In this way, the formation of the source and drain of the GAA transistor is completed. The first light-doped region 6681 and the second light-doped region 6682 may be formed on the exposed vertical sidewall of the semiconductor nanosheet 5951. The first light-doped region 6681 and the second light-doped region 6682 may be in contact with the exposed vertical sidewall of the semiconductor nanosheet 5951. The first conductive region 6691 may be formed on the sidewall of the first lightly doped region 6681. The second conductive region 6692 may be formed on the sidewall of the second lightly doped region 6682. The first conductive region is connected to (or in contact with) the connection plug 627. The connection plug 627 is connected to the UGI structure 592. Thus, the UGI structure 592 is electrically connected to the first conductive region 6691. The first conductive region 6691 can function as either the source or the drain of the GAA transistor. The second conductive region 6692 can function as either the source or the drain of the GAA transistor.

[0128] Figure 57 shows a three-dimensional schematic diagram of the structure at a stage of the manufacturing method. Figure 57A shows a schematic cross-sectional view of the structure illustrated along line AA shown in Figure 57. The dummy gate structure 590 is replaced by the gate structure 670 of the GAA transistor. For example, the gate structure 670 of the GAA transistor may be a high-k metal gate (HKMG). To further connect the first conductive region 6691 and the connecting plug 627, a metal cap (M0) 675 covering the first conductive region 6691 may be formed by a conventional metal zero (M0) layer process. This reduces contact resistance. In this way, a conventional GAA transistor having a connecting plug 627 for the UGI structure 592 is completed.

[0129] An underground interconnect structure and a connection plug (located inside the active region or along the side wall of the active region) that connects the underground interconnect structure to the transistors of an integrated circuit (such as a planar transistor, FinFET, GAA transistor, or complementary FET (CFET)) can realize an intermediate-side signal transmission network in an integrated circuit. The underground interconnect structure and its connection according to this disclosure free up layout space for conventional metal layers located above the original semiconductor surface, simplifies the layout of conventional metal layers located above the original semiconductor surface, and reduces IR drop related to signal transmission. Furthermore, backside signal transmission can be effectively realized for semiconductor circuit chips based on the underground interconnect structure and its connection to the transistors of an integrated circuit according to this disclosure.

[0130] Furthermore, if the underground interconnect structure located within the STI region includes a heat dissipation material having a higher thermal conductivity than Si or SiO2, the underground interconnect structure and its connections according to this disclosure may be applied to a heat dissipation network. In particular, the underground interconnect structure located within the semiconductor substrate extends away from the active region toward other spare regions or larger STI regions. Thermal vias may be located above the other spare regions or larger STI regions. Alternatively, through-silicon vias may be located below the other spare regions or larger STI regions.

[0131] It should be noted that the structures and methods described above are provided for illustrative purposes only. This disclosure should not be limited to the configurations and procedures (techniques) disclosed as described above. Other embodiments with different configurations of known elements are applicable, and the illustrated structures may be adjusted and modified based on the practical needs of actual applications. Naturally, it should be noted that the configurations in each figure are drawn for illustrative purposes only, and not for limitation. Therefore, it is known to those skilled in the art that the relevant elements and layers in the semiconductor structure, the shape or positional relationships of the elements, and the details of the procedure may be adjusted or modified according to the practical requirements and / or manufacturing steps of actual applications.

[0132] This disclosure is described in terms of one or more exemplary embodiments for illustrative purposes, but it should be understood that this disclosure is not limited to these examples. On the contrary, this disclosure is intended to cover a variety of modifications and similar arrangements and procedures. Accordingly, the appended claims should be interpreted most broadly to encompass all of the modifications and similar arrangements and procedures described above. [Brief explanation of the drawing]

[0133] [Figure 1A]This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 1B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 1C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 2A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 2B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 2C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 3A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 3B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 3C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 4A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 4B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 4C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 5A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 5B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 5C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 6A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to a first process embodiment. [Figure 6B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 6C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 7A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 7B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 7C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 8A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 8B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 8C]This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 9] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the first process of this disclosure. [Figure 10A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 10B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 10C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 11A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 11B] This disclosure describes a method for forming an underground interconnection structure within an STI domain, relating to an implementation of the second process of this disclosure. [Figure 11C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 12A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 12B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 12C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 13A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 13B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 13C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 14A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 14B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 14C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 15A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 15B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 15C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 16A] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 16B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 16C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 17A]This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 17B] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 17C] This disclosure describes a method for forming an underground interconnection structure within an STI area according to an embodiment of the second process of this disclosure. [Figure 18] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 18A] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 18B] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 18C] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 19A] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 19B] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 19C] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 20A] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 20B] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 20C] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 21A] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 21B] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 21C] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 22] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 22A] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 22B] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 22C] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the first connection of this disclosure. [Figure 23] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 23A] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 23B] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 23C]This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 24A] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 24B] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 24C] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 25] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 25A] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 25B] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 25C] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 26] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the second connection of this disclosure. [Figure 27] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the third connection of this disclosure. [Figure 27A] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the third connection of this disclosure. [Figure 27B] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the third connection of this disclosure. [Figure 27C] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the third connection of this disclosure. [Figure 28] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the third connection of this disclosure. [Figure 29] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor, according to an embodiment of the fourth connection of this disclosure. [Figure 30] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor, according to an embodiment of the fourth connection of this disclosure. [Figure 31] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor, according to an embodiment of the fourth connection of this disclosure. [Figure 32] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor, according to an embodiment of the fourth connection of this disclosure. [Figure 33] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor, according to an embodiment of the fourth connection of this disclosure. [Figure 34] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor, according to an embodiment of the fourth connection of this disclosure. [Figure 35] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor, according to an embodiment of the fourth connection of this disclosure. [Figure 36] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor, according to an embodiment of the fourth connection of this disclosure. [Figure 37] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor, according to an embodiment of the fourth connection of this disclosure. [Figure 37A]This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor, according to an embodiment of the fourth connection of this disclosure. [Figure 38] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 39] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 40] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 41] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 42] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 43] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 44] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 45] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 46] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 47] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 48] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 48A] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the fifth connection of this disclosure. [Figure 49] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the sixth connection of this disclosure. [Figure 50] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the sixth connection of this disclosure. [Figure 51] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the sixth connection of this disclosure. [Figure 52] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the sixth connection of this disclosure. [Figure 53] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the sixth connection of this disclosure. [Figure 54] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the sixth connection of this disclosure. [Figure 55] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the sixth connection of this disclosure. [Figure 56] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the sixth connection of this disclosure. [Figure 57] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the sixth connection of this disclosure. [Figure 57A] This disclosure describes a method for electrically connecting an underground interconnection structure to a transistor according to an embodiment of the sixth connection of this disclosure.

Claims

1. A semiconductor device structure, A semiconductor substrate having an original semiconductor surface and an active region, The shallow trench isolation (STI) region surrounding the active region, A transistor formed based on the active region, An interconnection structure extending beyond the aforementioned transistor, It is equipped with a connection plug, The aforementioned transistor is Gate structure and First conductive region and The second conductive region and It comprises a channel region located between the first conductive region and the second conductive region, The first conductive region contains an epitaxial semiconductor material, The interconnection structure is located below the original semiconductor surface and within the STI region. The connecting plug electrically connects the interconnection structure to the first conductive region of the transistor. The connecting plug is located inside the active region, and the epitaxial semiconductor material of the first conductive region is located above the upper surface of the connecting plug. or The connecting plug is located inside the STI region, the epitaxial semiconductor material of the first conductive region is connected to the first side wall of the connecting plug, and the connecting plug is in contact with the interconnection structure only at the side wall of the interconnection structure. Semiconductor device structure.

2. The interconnection structure is insulated from the semiconductor substrate by an insulating region. The insulating region comprises a first spacer located on the first side of the interconnection structure and a second spacer located on the second side of the interconnection structure. The material of the first spacer is different from the material of the second spacer. The semiconductor device structure according to claim 1.

3. The second side wall of the connecting plug is aligned with the side wall of the interconnection structure and is in contact with the side wall of the interconnection structure. The semiconductor device structure according to claim 1.

4. The semiconductor device structure further includes a trench within the active region, The aforementioned connection plug is located inside the trench, The aforementioned connecting plug contains titanium nitride (TiN) and tungsten (W). The semiconductor device structure according to claim 3.

5. The semiconductor device structure further includes a thin slot inside the STI region, The aforementioned connection plug is located inside the thin slot, The aforementioned connection plug contains a highly doped semiconductor material or TiN. The epitaxial semiconductor material in the first conductive region is located above the upper surface of the connecting plug, The second side wall of the connector plug is located on the opposite side from the first side wall of the connector plug. The semiconductor device structure according to claim 3.

6. The transistor is a Finn field-effect transistor (FinFET), a GAA transistor, or a CFET. The STI region has an upper surface located at a lower position than the original semiconductor surface. The semiconductor device structure according to claim 1.

7. The first conductive region comprises selectively epitaxially grown material. The semiconductor device structure according to claim 6.

8. The aforementioned connection plug is located inside the active area, The first conductive region extends only from the vertical side wall of the active region located directly beneath the spacer structure covering the gate structure. The semiconductor device structure according to claim 7.

9. The aforementioned connection plug is located inside the STI region, The first conductive region extends from the vertical side wall of the active region located directly below the spacer structure covering the gate structure, and extends from the horizontal surface of the active region located near the upper surface of the STI region. The semiconductor device structure according to claim 7.

10. The device further comprises a metal cap (M0) covering the first conductive region. The semiconductor device structure according to claim 1.

11. A semiconductor device structure, A semiconductor substrate having an original semiconductor surface and an active region, The shallow trench isolation (STI) region surrounding the active region, A transistor formed based on the active region, An interconnection structure extending beyond the aforementioned transistor, The connecting plug, It is equipped with a metal cap (M0), The aforementioned transistor is Gate structure and First conductive region and The second conductive region and It comprises a channel region located between the first conductive region and the second conductive region, The interconnection structure is located below the original semiconductor surface and within the STI region. The connecting plug electrically connects the interconnection structure to the first conductive region of the transistor. The metal cap covers the epitaxial semiconductor material of the first conductive region and the connecting plug. Semiconductor device structure.

12. The interconnection structure is insulated from the semiconductor substrate by an insulating region. The insulating region comprises a first spacer located on the first side of the interconnection structure and a second spacer located on the second side of the interconnection structure. The material of the first spacer is different from the material of the second spacer. The semiconductor device structure according to claim 11.

13. The side wall of the connecting plug is aligned with the side wall of the interconnection structure and is in contact with the side wall of the interconnection structure. The semiconductor device structure according to claim 11.

14. The semiconductor device structure further includes a trench within the active region, The aforementioned connection plug is located inside the trench, The aforementioned connecting plug contains tungsten. The semiconductor device structure according to claim 13.

15. The aforementioned transistor is a FinFET, The channel region is equipped with a fin structure, The STI region has an upper surface located at a lower position than the original semiconductor surface. The semiconductor device structure according to claim 11.

16. The first conductive region includes an epitaxial semiconductor material. The semiconductor device structure according to claim 15.

17. The aforementioned connection plug is located inside the active area, The first conductive region extends from the vertical side wall of the fin structure located directly below the spacer structure covering the gate structure, and extends from the horizontal surface of the active region located near the upper surface of the STI region. The semiconductor device structure according to claim 16.

18. The aforementioned transistor is a gate-all-around (GAA) transistor, The channel region comprises multiple nanosheets, The STI region has an upper surface located lower than the upper part of the plurality of nanosheet structures. The semiconductor device structure according to claim 11.

19. The first conductive region includes an epitaxial semiconductor material. The semiconductor device structure according to claim 18.

20. The aforementioned connection plug is located inside the active area, The first conductive region extends from both vertical sidewalls of the plurality of nanosheets located directly beneath the spacer structure covering the gate structure, and extends from the horizontal surface of the active region located near the upper surface of the STI region. The semiconductor device structure according to claim 19.

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