Semiconductor structures and semiconductor devices

Abstract

To provide a semiconductor structure and a semiconductor device that has bulk conduction, does not form an inversion electron layer, has a small tunneling effect, little gate leakage, low power consumption, a higher electron or hole drift velocity, and higher carrier transfer efficiency.SOLUTION: A semiconductor structure 10 includes at least a gate structure region 200 and a source region 300 and a drain region 400 located on both sides of the gate structure region, and the gate structure region includes at least a channel region 100 and a gate region arranged from the inside to the outside, the channel region covers the inner cavity of the gate region, the channel region is in close contact with the source region, the drain region and the gate region, respectively, and the drain region, the source region and the channel region are doped with the same type of ions.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This application relates to the semiconductor technology field, and more specifically, to semiconductor structures and semiconductor devices. [Background technology]

[0002] With the dramatic advancements in semiconductor technology, the scale of integrated circuits (CMOS, Complementary Metal-Oxide-Semiconductor) is expanding in the modern electronics and information industry. The main reason for this is the continuous reduction in feature dimensions of CMOS devices, and the most advanced 5nm semiconductor process has already entered mass production. However, the continuous increase in power consumption of integrated circuit chips, along with the continuous improvement in integration density, is posing a challenge to the development of integrated circuits.

[0003] In addition to the increasingly high demands for manufacturing precision in processes, another important influencing factor is short-channel effects (SCE). Short-channel effects refer to the effects that appear in metal oxide semiconductor field-effect transistors when the conductive channel length is reduced to around 10 to 15 nanometers. Short-channel effects mainly include a decrease in threshold voltage due to the decrease in channel length, a decrease in drain-induced barrier, surface scattering of carriers, and carrier velocity saturation effects. Due to the existence of short-channel effects, it is currently not possible to further reduce the feature dimensions of semiconductor devices. To mitigate short-channel effects, the industry has adopted special device structures, for example, proposing FinFETs (Fin Field-Effect Transistors) and encircling gate electrode field-effect transistors under the 14nm node, and introducing GAA (Gate-All-Around Transistors) devices under the 5nm node to improve the impact of short-channel effects on devices. [Overview of the project] [Problems that the invention aims to solve]

[0004] Currently, GAA devices are being applied in a wider range of applications, but they still have PN junctions, which means they have problems such as impurity diffusion and limit their device size. In addition, because GAA devices are surface channel devices, they also have problems such as surface mobility and hot carrier effects.

[0005] Therefore, semiconductor devices that can further break through feature dimensions are needed. [Means for solving the problem]

[0006] To solve the above technical problems, the present invention provides a semiconductor structure and a semiconductor device in its embodiments.

[0007] In the first embodiment of the present invention, a semiconductor structure is provided, the semiconductor structure is, It includes at least a gate structure region and a source region and a drain region located on both sides of the gate structure region, Here, the gate structure region is The apparatus includes at least a channel region and a gate region that are provided from the inside out, wherein the channel region covers the internal cavity of the gate region, the channel region is in close contact with the source region, the drain region, and the gate region, and the drain region, the source region, and the channel region are doped with the same type of ion.

[0008] In one selectable embodiment of the present application, the gate structure region is The dielectric layer is provided between the gate region and the channel region and is in close contact with the gate region, the channel region, the drain region, and the source region, respectively.

[0009] In one selectable embodiment of the present application, the gate structure region is The system further includes a buffer barrier region located between the channel region and the dielectric layer, and in close contact with the dielectric layer, the channel region, the drain region, and the source region, respectively.

[0010] In one selectable embodiment of the present application, the ion doping concentration of the buffer barrier region is 1e17 / cm³. 3 The following applies:

[0011] In one selectable embodiment of the present application, the ion doping concentration in the buffer barrier region is lower than the ion doping concentrations in the drain region and the source region, and / or the ion doping concentration in the buffer barrier region is an order of magnitude lower than the ion doping concentration in the channel region.

[0012] In one selectable embodiment of the present application, the thickness of the buffer barrier region is 0.3 to 5 nm.

[0013] In one selectable embodiment of the present application, the ion doping concentration in the gate region is 1 e16 / cm³. 3 ~1e20 / cm 3 And / or, the ion doping concentration in the channel region is 1e17 / cm³. 3 ~5e19 / cm 3 And / or the ion doping concentration in the drain region and the source region is 1 e18 / cm³. 3 ~5e20 / cm 3 That is the case.

[0014] In one selectable embodiment of the present application, the ion doping concentrations in the drain region, the source region, and the channel region are equal.

[0015] In one selectable embodiment of the present application, the ion doping concentrations in the drain region, the source region and the channel region are 1 e17 / cm³. 3 That's all.

[0016] In one selectable embodiment of the present application, the drain region, the source region, and the channel region are integrally formed.

[0017] In one selectable embodiment of the present application, when the semiconductor structure is an N-type device, the gate region is a metal with a metal work function of 4.5 eV to 5.2 eV, or when the semiconductor structure is a P-type device, the gate region is a metal with a metal work function of 4.0 eV to 4.5 eV.

[0018] In one selectable embodiment of the present application, the semiconductor structure is a FinFET device or a GAA device.

[0019] In a second aspect of the embodiment of the present application, a semiconductor device is provided, and the semiconductor device has any one of the above semiconductor structures.

[0020] <000​​​​​​​​​​​​​​​​In the first embodiment, the drain region, source region, and channel region in the embodiment of the present application are all ion-doped of the same type, resulting in a homojunction device structure. There are no interfacial effects between the regions, converting conventional interfacial conduction into bulk conduction, which increases the electron or hole drift rate, improves carrier transport efficiency, and allows for even higher electron or hole drift rates, further improving the operational efficiency of the semiconductor structure and the reliability of the device.

[0024] In the second embodiment, the drain region, source region, and channel region in the embodiment of the present application are all doped with the same type of ion, thereby converting conventional interfacial conduction to bulk conduction, and the channel region is directly controlled by the gate region.

[0025] When no voltage is applied to the gate region, or when the applied voltage is set to 0, the energy band difference between the gate region and the channel region (the electron affinity energy of a silicon device (the difference from the bottom of the conduction band to the vacuum level) is 4.05 eV) causes the device channel region to self-deplete due to the influence of the gate region, forming a self-depleted non-inverting semiconductor structure. That is, only when a voltage is applied to the gate region does current flow from the highly doped region of the drain region through the channel region to the source region, i.e., the channel region opens. On the other hand, when no voltage is applied to the gate region, the channel region remains closed, forming a normally-off device structure, which consumes less energy compared to conventional normally-on devices.

[0026] In the third embodiment, the semiconductor structure in the embodiment of the present application is bulk conductive, and since there is no PN junction structure in the device and no PN junction depletion layer, the effect of threshold voltage reduction due to the PN junction structure can be eliminated, meaning that the feature dimensions of the device can be further reduced, and experiments have shown that the current demand for a device channel length of 10 nm or less can be met.

[0027] In the fourth embodiment, the semiconductor structure according to the embodiment of the present invention is bulk conduction, and the on-current is away from the interface, so there is no problem of reduced interface mobility. Furthermore, because the on-current is away from the interface, the tunnel current is also reduced, gate leakage can be reduced, and the reliability and stability of the device structure can be improved.

[0028] In the fifth embodiment, the semiconductor structure according to the embodiment of the present invention is a non-inverting device, and since electrons in the channel region do not flow to the surface inversion layer, gate leakage of the device can be avoided. At the nanoscale, tunnel current due to the tunneling effect is the main source of gate leakage, and since the thickness of the gate dielectric of the device is limited, high-k dielectric technology has been developed, and by adopting a high-k dielectric, the thickness of the gate dielectric can be increased without reducing the gate control capability. In contrast, the semiconductor structure according to the embodiment of the present invention can reduce tunnel current because current does not flow to the surface inversion layer, and high-k dielectric can not be used, proposing a new direction for technology. [Brief explanation of the drawing]

[0029] The accompanying drawings shown herein are for further understanding of the present application and constitute part of the present application. Exemplary embodiments and descriptions thereof are used to illustrate the present application and do not constitute an unreasonable limitation of the present application. [Figure 1] This is a process flow diagram of a conventional GAA. [Figure 2] This is a schematic diagram showing the structure of a semiconductor structure according to an embodiment of the present invention. [Figure 3] This is a schematic diagram showing a simulated structure of a semiconductor structure according to an embodiment of the present invention. [Figure 4] This is a schematic diagram showing a cross-section of the gate structure region in the semiconductor structure according to the embodiment of the present invention. [Figure 5] This is a graphic showing the simulation results of the electron density in the vertical channel region in the ON state of the semiconductor structure according to the embodiment of the present invention. [Figure 6] These are the energy bands and electron distribution diagrams of the buffer barrier region and channel region in the off state when the semiconductor structure according to the embodiment of the present application is an N-type device. [Figure 7] This figure shows the transfer characteristic curve and gate leakage current curve for a device with a total gate width of 1 mm when the semiconductor structure according to the embodiment of the present application is an N-type device. [Figure 8] This figure shows the transfer characteristic curves at different Vd values ​​for a device with a total gate width of 1 mm, where the semiconductor structure according to the embodiment of the present application is an N-type device. [Figure 9] These are the energy bands and electron distribution diagrams of the buffer barrier region and channel region when the semiconductor structure according to the embodiment of the present application is a P-type device, in the off state. [Figure 10] This figure shows the transfer characteristic curve and gate leakage current curve for a device with a total gate width of 1 mm when the semiconductor structure according to the embodiment of the present application is a P-type device. [Figure 11] This figure shows the transfer characteristic curves at different Vd values ​​for a device with a total gate width of 1 mm, where the semiconductor structure according to the embodiment of this application is a P-type device. [Figure 12] This is a schematic diagram showing the structure of a semiconductor device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0030] With the dramatic advancements in semiconductor technology, the scale of integrated circuits (CMOS, Complementary Metal-Oxide-Semiconductor) is expanding in the modern electronics and information industry. The main reason for this is the continuous reduction in feature dimensions of CMOS devices, and the most advanced 5nm semiconductor process has already entered mass production. However, the continuous increase in power consumption of integrated circuit chips, along with the continuous improvement in integration density, is posing a challenge to the development of integrated circuits.

[0031] In addition to the increasingly high demands for manufacturing precision in processes, another important influencing factor is short-channel effects (SCE). Short-channel effects refer to the effects that appear in metal oxide semiconductor field-effect transistors when the conductive channel length is reduced to around 10 to 15 nanometers. Short-channel effects mainly include a decrease in threshold voltage due to the decrease in channel length, a decrease in drain-induced barrier, surface scattering of carriers, and carrier velocity saturation effects. Due to the existence of short-channel effects, it is currently not possible to further reduce the feature dimensions of semiconductor devices. To mitigate short-channel effects, the industry has adopted special device structures, for example, proposing FinFETs (Fin Field-Effect Transistors) and encircling gate electrode field-effect transistors under the 14nm node, and introducing GAA (Gate-All-Around Transistors) devices under the 5nm node to improve the impact of short-channel effects on devices.

[0032] Although GAA devices are now being applied in a wider range of applications, they still have PN junctions, which means they have problems such as impurity diffusion and limit their device size. Furthermore, because GAA devices are surface channel devices, they also have problems with surface mobility and hot carrier effects. For example, current GAA devices have the following defects:

[0033] (1) The existence of short-channel and narrow-channel effects that affect the threshold voltage When the channel length is shortened to a certain extent, the proportion of the source and drain depletion regions that occupy the entire channel increases, and the amount of charge required to form a surface inversion layer on the silicon surface beneath the gate decreases, thus lowering the threshold voltage. On the other hand, the charge in the portion of the depletion region that extends laterally across the channel width within the substrate increases the threshold voltage, and when the channel width decreases to about the same extent as the depletion layer width, the decrease in the threshold voltage becomes significant, indicating that the threshold voltage of short-channel devices is very sensitive to changes in channel length.

[0034] (2) Mobility field correlation effect and carrier velocity saturation effect At low electric fields, mobility is constant, and carrier velocity increases linearly with respect to the electric field. At high electric fields, mobility decreases, and once the carrier velocity reaches saturation, the correlation with the electric field disappears. In current devices, a surface inversion layer exists in the ON state, and the electron layer resides at the device interface, where it is affected by interfacial scattering. Interfacial mobility determines the drain saturation current characteristics of the device. At the semiconductor surface, mobility decreases due to the effects of surface scattering and Coulomb scattering, reducing the surface carrier saturation velocity of the device. Furthermore, the electric field perpendicular to the gate interface is very strong, further reducing carrier mobility.

[0035] (3) No degradation of subthreshold characteristics and no interruption of the device Leakage current in the subthreshold region degrades the off-state characteristics of MOSFET devices and increases static power consumption. Furthermore, in dynamic circuits and memory cells, it can cause confusion in the logic state. Therefore, the drain-induced barrier drop (DIBL) effect due to short channels is a fundamental physical effect that determines the dimensional limits of short-channel MOS devices. The DIBL effect occurs when a high voltage is applied to the drain; because the gate is very short, the source is simultaneously affected by the drain electric field, lowering the barrier at the source junction. Simultaneously, the drain depletion layer expands and connects to the depletion region of the source junction, thereby preventing the device from turning off. The drain voltage affects the gate turn-off, and the potential is affected. While a normal turn-off would not affect the drain voltage if it increases, the short-channel effect causes the current to increase in proportion to the change in drain voltage, with larger drain currents.

[0036] (4) Gate dielectric layer tunneling and gate leakage of the device Tunneling current, in microelectronics technology, is the current generated by the quantum tunneling effect of carriers when the thickness of a semiconductor barrier or silica thin film becomes thin enough to approach the wavelength of the carrier's de Broglie wave. When device dimensions are reduced to the nanometer level, the tunneling current in the gate oxide layer due to the tunneling effect can no longer be ignored and becomes an important factor influencing device miniaturization. In the case of an inverting device, device carriers are present at the device interface, and are most concentrated at the device interface, at which point the device's tunneling current is very strong.

[0037] (5) 3D Integration and Annealing Process The device process requires ion implantation and annealing, but annealing conflicts with low-temperature processes. Temperature presents two problems. First, diffusion occurs, and miniaturization is not possible due to diffusion in the PN junction. Second, high-temperature processes cannot be used after metal and silicide processing, damaging the silicide and metal structures.

[0038] (6) The GAA process flow is complex overall, as shown in Figure 1. Therefore, semiconductor devices that can further break through feature dimensions are needed.

[0039] In response to the above-mentioned problems, embodiments of this application provide semiconductor structures and semiconductor devices. To make the purpose, technical solutions, and advantages of this application clearer, embodiments and semiconductor devices of this application will be described in more detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are used solely for interpreting this application and not to limit it.

[0040] The sequence numbers assigned to components in this specification, such as "First," "Second," etc., are used solely to identify the described objects and do not have any sequential or technical meaning. In this application, "connected" and "joined" include direct and indirect connections (joins) unless otherwise specified. In this description, the directions or positional relationships indicated by the terms "up," "down," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inside," "outside," "clockwise," and "counterclockwise" are based solely on the directions or positional relationships shown in the drawings, for the purpose of facilitating and simplifying the description herein, and should not be understood as indicating or implying that the shown devices or elements have a specific direction, are configured in a specific direction, or need to operate in a specific direction, and therefore should not be understood as limiting this application.

[0041] In this application, unless otherwise explicitly stated and limited, the presence of a first feature "above" or "below" a second feature may mean that the first and second features are in direct contact or indirectly in contact via an intermediate medium. Furthermore, the presence of a first feature "above," "above," and "on the top surface" of a second feature may mean that the first feature is directly above or diagonally above the second feature, or simply that the horizontal height of the first feature is greater than that of the second feature. The presence of a first feature "below," "below," and "on the bottom surface" of a second feature may mean that the first feature is directly below or diagonally below the second feature, or simply that the horizontal height of the first feature is lower than that of the second feature.

[0042] Referring together to Figures 2 to 4, the embodiment of the present application provides a semiconductor structure 10 which includes at least a gate structure region 30 and a source region 300 and a drain region 400 located on both sides of the gate structure region 30, respectively.

[0043] Refer to Figures 2 and 3. Figure 2 is a diagram showing the three-dimensional structure of the semiconductor structure 10 according to an embodiment of the present application, and Figure 3 is a diagram showing the simulated structure of the semiconductor structure 10 according to an embodiment of the present application, including the x-direction along the plane, the y-direction along the longitudinal direction, and the z-direction along the vertical direction (or referred to as the depth direction or height direction). Figure 4 is a cross-sectional view of the semiconductor structure 10 in the yz direction of Figure 3. The gate structure region 30 includes at least the following:

[0044] A channel region 100 and a gate region 200 are provided from the inside out, the channel region 100 covers the internal cavity of the gate region 200, the channel region 100 is in close contact with the source region 300, the drain region 400, and the gate region 200, respectively, and the drain region 400, the source region 300, and the channel 100 are doped with the same type of ion.

[0045] Here, the gate region 200 may be a metal gate or a first ion-doped type, and the embodiments of this application are not specifically limited. The gate region 200 may include a top gate and a bottom gate, for example, as shown in Figure 4, the bottom gate and top gate are located on the surface of the channel region 100, and the top gate and bottom gate may be manufactured at one time to simplify the process. The source region 300 and drain region 400 may be highly doped regions to improve the flow of conduction electrons or the movement of holes. The type of first ion doping is different from the type of second ion doping. That is, the type of first ion doping may be N-type doping and the type of second ion doping may be P-type doping, or the type of first ion doping may be P-type doping and the type of second ion doping may be N-type doping.

[0046] In the first embodiment, the drain region 400, source region 300, and channel region 100 in the embodiment of the present application are all ion-doped of the same type, resulting in a homojunction device structure, where there are no interfacial effects between the regions, converting conventional interfacial conduction to bulk conduction, increasing the electron or hole drift rate, improving carrier transport efficiency, and obtaining an even higher electron or hole drift rate, thereby further improving the operating efficiency and reliability of the semiconductor structure 10. Here, bulk conduction refers to the conduction of electrons or holes along the interior of the device layer and is distinguished from interfacial conduction of an electric field or inversion electron layer formed at the interface.

[0047] In the second embodiment, the drain region 400, source region 300, and channel region 100 in the embodiment of the present application are all ion-doped of the same type, thereby converting conventional interfacial conduction to bulk conduction, and the channel region 100 is directly controlled by the gate region.

[0048] When no voltage is applied to the gate region, or when the applied voltage is set to 0, the device channel region 100 is self-depleted due to the influence of the gate region, as indicated by the energy band difference between the gate region and the channel region 100 (the silicon device electron affinity energy (difference from the bottom of the conduction band to the vacuum level) is 4.05 eV). This forms a self-depleted non-inverting semiconductor structure 10. That is, only when a voltage is applied to the gate region does current flow from the highly doped region of the drain region 400 through the channel region 100 to the source region 300, thus opening the channel region 100. On the other hand, when no voltage is applied to the gate region, the channel region 100 remains closed, forming a normally-off device structure, which consumes less energy compared to conventional normally-on devices.

[0049] In the third embodiment, the semiconductor structure 10 in the embodiment of the present application is bulk conductive, and since there is no PN junction structure in the device and no PN junction depletion layer, the effect of threshold voltage reduction due to the PN junction structure can be eliminated, that is, the feature dimensions of the device can be further reduced, and experiments have shown that the current demand for a device channel length of 10 nm or less can be met.

[0050] In the fourth embodiment, the semiconductor structure 10 according to the embodiment of the present application is bulk conductive, and the on-current is away from the interface, so there is no problem of reduced interface mobility. Furthermore, because the on-current is away from the interface, the tunnel current is also reduced, gate leakage can be reduced, and the reliability and stability of the device structure can be improved.

[0051] In the fifth embodiment, the semiconductor structure 10 according to the embodiment of the present application is a non-inverting device, and since electrons in the channel region do not flow to the surface inversion layer, gate leakage of the device can be avoided. At the nanoscale, tunnel current due to the tunneling effect is the main source of gate leakage, and since the thickness of the gate dielectric of the device is limited, high-k dielectric technology has been developed, and by employing high-k dielectric, the thickness of the gate dielectric can be increased without reducing the gate control capability. In contrast, the semiconductor structure 10 according to the embodiment of the present application can reduce tunnel current because current does not flow to the surface inversion layer, and high-k dielectric can not be used, proposing a new direction for technology.

[0052] Please refer to Figures 2 and 4. In any embodiment of the present application, the gate structure region 30 is The device further includes a dielectric layer 500 provided between the gate region 200 and the channel region 100, and in close contact with the gate region 200, the channel region 100, the drain region 400, and the source region 300, respectively.

[0053] The dielectric layer 500 may be made of an insulating material such as silicon dioxide, and this dielectric layer 500 completely encloses the gate region 200, i.e., there is a thin dielectric layer between the gate region 200 and the channel region 100. Similarly, there is a thin dielectric layer between the bottom gate region and the channel, and this structure forms an all-around gate structure, i.e., the dopant of the channel region 100 is covered all around by the dielectric layer 500 so that only the portion electrically connected to the source region 300 and the drain region 400 is exposed.

[0054] Refer to Figures 2 and 4. In any embodiment of the present application, the gate structure region 30 further includes a buffer barrier region 600, which is located between the channel region 100 and the dielectric layer 500 and is in close contact with the dielectric layer 500, the channel region 100, the drain region 400, and the source region 300, respectively.

[0055] The buffer barrier region 600 is used to separate the gate region 200 from the channel region 100, and / or to separate the bottom gate region from the channel region 100. This buffer barrier region 600 may be a low-doping region, that is, its ion doping concentration is lower than that of the drain region 400 and the source region 300. By providing this buffer barrier region 600, the device prevents the formation of a surface inversion electron layer at the contact interface between the channel region 100 and the gate region 200, thereby avoiding performance loss due to a decrease in surface mobility, effectively preventing the occurrence of electron tunneling phenomena, reducing gate region current, preventing interface scattering, and improving the reliability and stability of the device.

[0056] In other words, by providing a buffer barrier region 600 between the gate region 200 and the channel region 100, the device prevents the formation of a surface inversion type electron layer at the contact interface between the channel region 100 and the gate region 200, thereby avoiding performance loss due to a decrease in surface mobility, effectively preventing the appearance of electron tunneling phenomena, reducing the gate region current, preventing interface scattering, and further enhancing the reliability and stability of the device.

[0057] In other words, the buffer barrier region 600 is ion-doped in the same way as the channel region 100, drain region 400, and source region 300, and can be grown and formed simultaneously. This reduces process complexity, avoids heat treatments such as conventional annealing, improves the yield of device structure manufacturing, and enhances the reliability and stability of the finished device's performance.

[0058] In any embodiment of the present application, the ion doping concentration of the buffer barrier region 600 is lower than the ion doping concentrations of the drain region 400 and the source region 300, and / or the ion doping concentration of the buffer barrier region 600 is an order of magnitude lower than the ion doping concentration of the channel region 100.

[0059] That is, the drain region 400 and the source region 300 are high ion-doped regions, the buffer barrier region 600 is a low ion-doped region, an ion concentration difference is formed between the two, and the electron flow formed between the source region 300 and the drain region 400 is prevented from scattering from the channel region 100 to the buffer barrier region 600, and the reliability and performance stability of the device structure can be further ensured.

[0060] In any embodiment of the present application, the ion doping concentration of the buffer barrier region 600 is 1e17 / cm 3 or less, it is a low-concentration doped region, the buffer barrier region 600 has a thickness of 0.3 nm to 5 nm, and the buffer barrier region 600 is made of a silicon material.

[0061] Referring to FIG. 5. FIG. 5 is a graph of the electron density simulation result of the vertical channel region 100 when the device structure is in the on state, taking the case where the width of the channel region 100 is 1 nm and the thickness of the buffer barrier region 600 is 0.5 nm as an example. The abscissa is the position along the vertical direction of the channel, the unit is micrometer, where the coordinate origin is the channel center position, the ordinate is the electron concentration, and the unit is / cm 3 . In the channel of the on-state device, electrons are concentrated inside the device channel region 100, but in the buffer barrier region 600 of the device, the electron concentration decreases by more than one digit, indicating that the device is in the internal on state.

[0062] In any embodiment of the present application, the ion doping concentration of the gate region 200 is 1e16 / cm 3 ~1e20 / cm 3 and / or the ion doping concentration of the channel region 100 is 1e17 / cm 3 ~5e19 / cm 3 and / or the ion doping concentration of the drain region 400 and the source region 300 is 1e18 / cm 3 ~5e20 / cm 3 is.

[0063] The device structure obtained using the concentration parameter range described above exhibits better self-depletion effects, better bulk conduction performance, smaller negative effects, and improved stability and reliability of the device structure.

[0064] In any embodiment of the present application, the ion doping concentrations in the drain region 400, the source region 300, and the channel region 100 are equal.

[0065] In other words, the channel region 100, drain region 400, and source region 300 are doped with the same type of ion and can be grown and formed simultaneously. This reduces process complexity, avoids heat treatments such as conventional annealing, improves the yield of device structure manufacturing, and enhances the reliability and stability of the finished device's performance.

[0066] In any embodiment of the present application, the ion doping concentrations of the drain region 400, the source region 300, and the channel region 100 are 1e17 / cm³. 3 That's all.

[0067] In other words, the channel region 100, drain region 400, and source region 300 are produced from the same material, the desired ions are implanted into the initial material, and additional ion doping is not required during manufacturing. The channel region 100, drain region 400, and source region 300 can be grown and formed simultaneously, reducing process complexity, avoiding conventional thermal processes such as annealing, improving the yield of device structure manufacturing, and enhancing the reliability and stability of the finished device's performance.

[0068] In any embodiment of this specification, the drain region 400, the source region 300, and the channel region 100 are formed integrally. That is, the channel region 100, the drain region 400, and the source region 300 can be grown and formed simultaneously, simplifying the process, reducing process complexity, avoiding heat treatments such as conventional annealing, improving the yield of device structure manufacturing, and enhancing the reliability and stability of the finished device's performance. Furthermore, by converting conventional interfacial conduction to bulk conduction, there are no interfacial effects between each region, resulting in higher electron or hole drift rates, improved carrier surface transfer efficiency, and ultimately higher electron or hole drift rates, further improving the operational efficiency and device reliability of the semiconductor structure 10.

[0069] In any embodiment of the present invention, when the semiconductor structure 10 is an N-type device, the gate region 200 is a metal with a metal work function of 4.5 eV to 5.2 eV.

[0070] Refer to Figure 6. Figure 6 shows the energy bands and electron distribution diagrams of the buffer barrier region 600 and channel region when the metal work function of the gate region 200 is 4.5 eV to 5.2 eV in the off state of an N-type device. Figure 6(a) is the energy band diagram, where the horizontal coordinate is the position along the vertical direction of the channel, in micrometers, the coordinate origin is the channel center position, and the vertical coordinate is the electron concentration, in units of / cm. 3 Figure 6(b) shows the electron distribution diagrams of the buffer barrier region 600 and the channel region, where the horizontal coordinate is the position along the vertical direction of the channel, the unit is micrometers, the coordinate origin is the channel center position, and the vertical coordinate is the channel electron concentration. As can be seen from Figures 6(a) and 6(b), when the metal work function of the gate region 200 is 4.5eV to 5.2eV, the Fermi level of the semiconductor layer is located in the middle. In silicon materials, at this time, as shown in the figure, the Fermi level is close to 0.5eV from both the conduction band and the valence band, there are almost no electrons and holes in the semiconductor layer, and the device performance is excellent.

[0071] Refer to Figure 7. Figure 7 shows the simulation results for an N-type device with a channel width of 7 nm and a gate width of 1 mm. Figure 7(a) is the transfer characteristic curve, where the horizontal axis is the gate voltage and the vertical axis is the drain current. Figure 7(b) is the gate leakage IgVg diagram, where the horizontal axis is the gate voltage and the vertical axis is the gate current. As can be seen from Figures 7(a) and 7(b), the change in channel current between the on and off states of the device structure is six orders of magnitude, but the gate leakage current of the device is kept below 100 uA, indicating excellent device performance.

[0072] Refer to Figure 8. Figure 8 shows the IdVg curves for an N-type device at different Vd values. As can be seen from Figure 8, the device exhibits small current differences at different drain voltages, indicating good DIBL (drain-induced barrier reduction) characteristics.

[0073] In any embodiment of the present invention, when the semiconductor structure 10 is a P-type device, the gate region 200 is a metal with a metal work function of 4.0 eV to 4.5 eV.

[0074] Refer to Figure 9. Figure 9 shows the energy bands and hole distribution diagrams for the buffer barrier region 600 and channel region when the metal work function of the gate region 200 is 4.0 eV to 4.5 eV in the off state of a P-type device. Figure 9(a) is the energy band diagram, where the horizontal coordinate is the position along the vertical direction of the channel, in micrometers, the coordinate origin is the channel center position, and the vertical coordinate is the electron concentration, in units of / cm². 3 Figure 9(b) shows the hole distribution diagram of the buffer barrier region 600 and the channel region, where the horizontal coordinate is the position along the vertical direction of the channel, the unit is micrometers, the coordinate origin is the channel center position, and the vertical coordinate is the channel hole concentration. As can be seen from Figures 9(a) and 9(b), when the metal work function of the gate region 200 is 4.0eV to 4.5eV, it is in an off state, the Fermi level is located in the center of the band gap, there are few holes, the device is completely off, and the device performance is excellent.

[0075] Refer to Figure 10. Figure 10 shows the simulation results for a P-type device with a channel width of 7 nm and a gate width of 1 mm. Figure 10(a) is the transfer characteristic curve, where the horizontal axis is the gate voltage and the vertical axis is the drain current. Figure 10(b) is the gate leakage IgVg diagram, where the horizontal axis is the gate voltage and the vertical axis is the gate current. As can be seen from Figures 10(a) and 10(b), the change in channel current between the on and off states of the device structure is five orders of magnitude, but the gate leakage current of the device is kept below 100 uA, indicating excellent device performance.

[0076] Refer to Figure 11. Figure 11 shows the IdVg curves for a P-type device at different Vd values. As can be seen from Figure 11, the device exhibits small current differences at different drain voltages, indicating good DIBL (drain-induced barrier reduction) characteristics.

[0077] In any embodiment of the present invention, the semiconductor structure 10 is a FinFET device or a GAA device.

[0078] Referring to the description of the beneficial effects of the semiconductor structure 10 described above, according to the embodiments of the present application, it is possible to provide a semiconductor device 20 that is bulk conductive, does not form an inversion electron layer, has a small tunnel effect, low gate leakage, low power consumption, higher electron or hole drift velocity, higher carrier transport efficiency, and has small feature dimensions, thereby breaking the limits of current device dimensions.

[0079] Refer to Figure 12. Embodiments of the present application provide a semiconductor device 20, which is a semiconductor device 20. It has one of the above semiconductor structures 10.

[0080] Referring to the description of the beneficial effects of the semiconductor structure 10 described above, according to the embodiment of the present application, it is possible to provide a semiconductor structure 10 that is bulk conductive, does not form an inversion electron layer, has a small tunnel effect, low gate leakage, low power consumption, higher electron or hole drift velocity, higher carrier transport efficiency, and has small feature dimensions, thereby breaking through the limits of current device dimensions.

[0081] As shown in Figure 12, in any embodiment of the present application, there are multiple semiconductor structures 10, the conductivity types of the multiple semiconductor structures 10 are not completely identical, and the multiple semiconductor structures 10 are insulated from each other by an insulating layer 22. In actual products, the multiple semiconductor devices 10 may be stacked or arranged in any direction, and Figure 12 does not specifically limit the structure of the semiconductor device 20 and the arrangement of the semiconductor devices 10 provided in the embodiments of the present application.

[0082] In other words, two types of semiconductor devices 20, N-type and P-type, can be realized simultaneously in the same device. For example, by 3D integration, a three-dimensionally integrated complementary FET device can be generated, forming a logic unit that can realize logic functions. Firstly, in this embodiment, by integrating two types of semiconductor devices 20, N-type and P-type, within the same three-dimensional structure, the integration density can be increased and the area reduced. Secondly, delays due to wiring can be reduced, improving device performance. In Figure 12, using the example of having two types of devices, the first conductivity type device is located between the bottom insulating layer 22 and the intermediate insulating layer 22 of the substrate layer 21, and the second conductivity type device is located on the intermediate insulating layer 22. The two types of devices are complementary NFETs and PFETs, and the number of NFETs and PFETs may be multiple. The metal layers of the NFETs and PFETs are metal layers with different work functions.

[0083] Referring to the description of the beneficial effects of the semiconductor structure 10 above, according to the embodiments of the present application, it is possible to provide a complementary FET device or GAA device that is bulk conductive, does not form an inversion electron layer, has a small tunnel effect, low gate leakage, low power consumption, higher electron or hole drift velocity, higher carrier transport efficiency, and has small feature dimensions, thereby breaking the limits of current device dimensions.

[0084] In any embodiment of the present application, the semiconductor device 20 described above is The semiconductor structure further includes a first semiconductor structure 23 and a second semiconductor structure 24 stacked on the surface of a substrate layer 21 along a vertical direction, wherein the first semiconductor structure includes a plurality of semiconductor structures of a first conductivity type, and the second semiconductor structure includes a plurality of semiconductor structures of a second conductivity type, and the first conductivity type and the second conductivity type are different. For example, the first conductivity type may be N-type and the second conductivity type may be P-type, or the first conductivity type may be P-type and the second conductivity type may be N-type.

[0085] As described in the above embodiments, according to the embodiments of the present application, it is possible to provide N-type and P-type complementary semiconductor devices that exhibit bulk conduction, do not form an inversion electron layer, have a small tunneling effect, low gate leakage, low power consumption, higher electron or hole drift velocity, higher carrier transport efficiency, and smaller feature dimensions, thereby breaking through the limits of current device dimensions.

[0086] In any embodiment of the present invention, the semiconductor device 20 described above is The device further includes an insulating layer 22 provided between the first semiconductor structure 23 and the second semiconductor structure 24, the insulating layer 22 penetrating the gate region 200. The first semiconductor structure 23 and the second semiconductor structure 24 are separated by the insulating layer 22, ensuring their relative independence, avoiding mutual interference, and improving the stability and reliability of the device.

[0087] While each step in a flowchart is shown sequentially as indicated by the arrows, it should be understood that these steps are not necessarily executed in the order indicated by the arrows. Unless expressly stated herein, there are no strict restrictions on the order in which these steps are executed, and they may be executed in a different order. Furthermore, at least some of the steps in the diagram may include multiple substeps or stages, and these substeps or stages do not necessarily have to be executed and completed at the same time, but may be executed at different times, and the execution order of these substeps or stages is not necessarily sequential, but may be executed sequentially or alternately with at least some of the other steps or substeps or stages of other steps.

[0088] Any combination of the technical features of the embodiments described above is possible, and for the sake of brevity, not all possible combinations of the technical features of the embodiments described above have been described. However, as long as there is no inconsistency among these combinations of technical features, they should all be considered to fall within the scope described herein.

[0089] The embodiments described above merely illustrate some of the present invention, and while their descriptions are relatively specific and detailed, they cannot be understood as limiting the scope of the patent application. It should be noted that a person skilled in the art can make several modifications and improvements without departing from the spirit of the present invention, and these fall within the scope of protection. Therefore, the scope of the patent application should be limited by the attached claims. [Explanation of Symbols]

[0090] 10 Semiconductor Structures 100 channel area 200 gate region 300 source area 400 Drain area 600 Buffer barrier area 500 Dielectric layer 30 Gate structure region 20 Semiconductor Devices 21 Substrate layer 22 Insulating layer 23. First Semiconductor Structure 24. Second Semiconductor Structure

Claims

1. It includes at least a gate structure region and a source region and a drain region located on both sides of the gate structure region, Here, the gate structure region is It includes at least a channel region and a gate region provided from the inside out, the channel region covering the internal cavity of the gate region, the channel region being connected to the source region, the drain region and the gate region, respectively, and the drain region, the source region and the channel region being doped with the same type of ion. The gate structure region is A dielectric layer is provided between the gate region and the channel region, and is connected to the gate region, the drain region and the source region, respectively. The system further includes buffer barrier regions located between the channel region and the dielectric layer, and connected to the dielectric layer, the channel region, the drain region, and the source region, respectively. The channel region is connected to the gate region via the dielectric layer and the buffer barrier region. A semiconductor structure characterized by the following features.

2. The ion doping concentration in the buffer barrier region is 1 e17 / cm². ３ The following is: The semiconductor structure according to feature 1.

3. The ion doping concentration in the buffer barrier region is smaller than the ion doping concentrations in the drain region and the source region, and / or the ion doping concentration in the buffer barrier region is an order of magnitude smaller than the ion doping concentration in the channel region. The semiconductor structure according to claim 1 or 2.

4. The thickness of the buffer barrier region is 0.3 to 5 nm. The semiconductor structure according to feature 1.

5. The ion doping concentration in the gate region is 1 e16 / cm². ３ ~1e20 / cm ３ And / or, the ion doping concentration in the channel region is 1 e17 / cm³. ３ ~5e19 / cm ３ And / or the ion doping concentration in the drain region and the source region is 1 e18 / cm³. ３ ~5e20 / cm ３ That is, The semiconductor structure according to feature 1.

6. The ion doping concentrations in the drain region, the source region, and the channel region are equal. The semiconductor structure according to feature 1.

7. The ion doping concentrations in the drain region, source region, and channel region are 1 e17 / cm³. ３ That's all. The semiconductor structure according to feature 6.

8. The drain region, the source region, and the channel region are integrally formed. The semiconductor structure according to claim 1, 6, or 7.

9. When the semiconductor structure is an N-type device, the gate region is a metal with a metal work function of 4.5 eV to 5.2 eV, or When the semiconductor structure is a P-type device, the gate region is a metal with a metal work function of 4.0 eV to 4.5 eV. The semiconductor structure according to feature 1.

10. The semiconductor structure is a FinFET device or a GAA device. The semiconductor structure according to feature 1.

11. A semiconductor structure having the structure described in any one of claims 1 to 2, 4 to 7, or 9 to 10. Semiconductor devices.

12. The number of the aforementioned semiconductor structures is multiple, and the conductivity types of the multiple aforementioned semiconductor structures are not completely identical. The semiconductor device according to feature 11.

13. The aforementioned semiconductor device is The present invention further comprises a first semiconductor structure and a second semiconductor structure stacked on the surface of a substrate layer along a vertical direction, wherein the first semiconductor structure comprises a plurality of semiconductor structures of a first conductivity type, and the second semiconductor structure comprises a plurality of semiconductor structures of a second conductivity type, and the first conductivity type and the second conductivity type are different. The semiconductor device according to feature 11.

14. The aforementioned semiconductor device is The insulating layer provided between the first semiconductor structure and the second semiconductor structure, further comprising an insulating layer that penetrates the gate region within the semiconductor structure, The semiconductor device according to feature 13.

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