Gate structure, semiconductor device, and method for manufacturing a semiconductor device

Abstract

The present invention discloses a gate structure, a semiconductor device, and a method for manufacturing a semiconductor device. The gate structure includes a gate portion and a field plate portion. The field plate portion includes at least two field plate sub-portions. In the direction from the gate portion to the field plate portion, the gate portion and the field plate portion are divided into two portions by a first plane. Within two adjacent field plate sub-portions, in the plane where the bottom surface of the gate portion away from the lower field plate sub-portion is located, the projection of the terminal point of the lower surface of the lower field plate sub-portion is located on one side closest to the first plane of the projection of the terminal point of the lower surface of the upper field plate sub-portion, and the terminal point of the lower surface of the upper field plate sub-portion overlaps with the terminal point where the upper surface of the lower field plate sub-portion is connected to the lower surface of the upper field plate sub-portion. In the gate structure of the present invention, two adjacent field plate sub-portions are connected non-vertically, optimizing the electric field distribution and improving the reliability and stability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductors, and more particularly to a gate structure, a semiconductor device, and a method for manufacturing a semiconductor device.

Background Art

[0002] In the field of 5G communication, a high bandwidth and high frequency of semiconductor high-frequency devices are required. However, the gate structure design and process flow strongly depend on the frequency characteristics of semiconductor devices and directly affect the operating frequency of semiconductor devices. Furthermore, the gate structure design has a great influence on the electric field of the device, so it is very important for maintaining the reliability and stability of semiconductor devices.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention provides a gate structure, a semiconductor device, and a method for manufacturing a semiconductor device, which satisfy the requirements of further improving the bandwidth and high-frequency performance of the semiconductor device, as well as improving the reliability and stability of the semiconductor device.

Means for Solving the Problems

[0004] According to a first aspect of the present invention, the gate structure includes a gate portion and a field plate portion. The field plate portion includes at least two field plate sub-parts. Within two adjacent field plate sub-parts, the field plate sub-part away from the gate portion is the upper field plate sub-part, and the field plate sub-part close to the gate portion is the lower field plate sub-part. In the direction from the gate portion to the field plate portion, the gate portion and the field plate portion are divided into two parts by a first plane. In one part, in the plane where the bottom surface of the gate portion away from the lower field plate sub-part is located, the projection of the end point of the lower surface of the lower field plate sub-part is located on one side of the projection of the tip point of the lower surface of the upper field plate sub-part that is close to the first plane, and the tip point of the lower surface of the upper field plate sub-part coincides with the endpoint where the upper surface of the lower field plate sub-part is connected to the lower surface of the upper field plate sub-part. The upper surface of one field plate sub-part is a surface that is away from the gate portion, and the lower surface of one field plate sub-part is a surface that is close to the gate portion. On the same side surface of the same field plate sub-part, one tip is an endpoint that is close to the first plane of the surface of the field plate sub-part, and one end is an endpoint that is away from the first plane of the surface of the field plate sub-part.

[0005] According to a second aspect of the present invention, the gate structure includes a gate portion and a field plate portion. In the direction from the gate portion to the field plate portion, the gate portion and the field plate portion are divided into two parts by a first plane. In one part, the gate portion includes a bottom surface away from the field plate portion and a first side surface adjacent to the bottom surface. In the plane where the bottom surface of the gate portion is located, the projection of the end point where the gate portion is connected to the field plate portion is located on the side away from the first plane of the projection of the end point where the bottom surface is connected to the first side surface. In the two parts, the distance relationship between the end point where the gate portion is connected to the field plate portion and the end point where the bottom surface is connected to the first side surface is M0 < L0 and MO' < L0. In the plane where the bottom surface of the gate portion is located, M0 is the distance between the projection of the end point where the gate portion located on one side of the first plane is connected to the field plate portion and the projection of the end point where the bottom surface is connected to the first side surface, M0' is the distance between the projection of the end point where the gate portion located on the other side of the first plane is connected to the field plate portion and the projection of the end point where the bottom surface is connected to the first side surface, and L0 is the distance between the projection of the end point where the bottom surface located on one side of the first plane is connected to the first side surface and the projection of the end point where the bottom surface located on the other side of the first plane is connected to the first side surface.

[0006] According to a third aspect of the present invention, a semiconductor device includes a substrate, a semiconductor layer formed on one side of the substrate, a passivation layer formed on one side of the semiconductor layer away from the substrate, and the gate structure according to the first aspect or the second aspect. The gate structure is formed on one side of the passivation layer away from the substrate. The field plate portion is formed on one side of the gate portion away from the semiconductor layer.

[0007] According to a fourth aspect of the present invention, a method for manufacturing a semiconductor device is for manufacturing the semiconductor device according to the third aspect. The manufacturing method includes forming a semiconductor layer on one side of the substrate; forming a passivation layer on one side of the semiconductor layer away from the substrate; A first photoresist is applied to the passivation layer using a first photoresist, the passivation layer is etched to form a first layer opening hole within the passivation layer, the opening size of the first photoresist before etching is L1+L1′+L0+M0+M0′ in the direction perpendicular to the direction from the substrate to the passivation layer, the opening size of the first photoresist after etching is L1+L1′+L0+M0+M0′+M1+M1′, and the size of the first layer opening hole in the direction from the substrate to the passivation layer is D1. Using a second photoresist, a second photoresist is applied to the passivation layer based on the first layer opening, the passivation layer is etched to form a second layer opening located below the first layer opening within the passivation layer, the opening size of the second photoresist before etching is L0 in the direction perpendicular to the direction from the substrate to the passivation layer, the opening size of the second photoresist after etching is L0+M0+M0′, the size of the second layer opening is D0 in the direction from the substrate to the passivation layer, and the semiconductor layer is exposed at the second layer opening. The method includes depositing a gate structure to form a gate portion and a field plate portion, completely filling the second layer opening hole with the gate portion, and covering the gate portion with the field plate portion to completely fill the first layer opening hole.

[0008] According to a fifth aspect of the present invention, a method for manufacturing a semiconductor device is for manufacturing the semiconductor device of the third aspect. The manufacturing method is: Forming a semiconductor layer on one side of the substrate, A passivation layer is formed on one side of the semiconductor layer that is away from the substrate, A first photoresist is applied to the passivation layer using a photoresist, the passivation layer is etched to form a first layer opening hole within the passivation layer, the opening size of the photoresist before etching is L0 in the direction perpendicular to the direction from the substrate to the passivation layer, the opening size of the photoresist after etching is L0+M0+M0′, and the size of the first layer opening hole in the direction from the substrate to the passivation layer is D0. By selective etching, the photoresist after etching is spread, and in the direction perpendicular to the direction from the substrate to the passivation layer, the aperture size of the spread photoresist is L1 + L1' + L0 + M0 + M0', Using the expanded photoresist, a second photoresist is applied to the passivation layer based on the first layer opening, the passivation layer is etched to cause the first layer opening to descend overall in the direction of the substrate, a second layer opening is formed in the passivation layer above the first layer opening, the opening size of the expanded photoresist after etching is L1+L1′+L0+M0+M0′+M1+M1′ in the direction perpendicular to the direction from the substrate to the passivation layer, the size of the second layer opening is D1 in the direction from the substrate to the passivation layer, and the semiconductor layer is exposed at the first layer opening. The method includes depositing a gate structure to form a gate portion and a field plate portion, completely filling the first layer opening hole with the gate portion, and covering the gate portion with the field plate portion to completely fill the second layer opening hole.

[0009] An embodiment of the present invention includes a gate structure and a field plate section. The field plate section includes at least two field plate subsections. In the direction from the gate section to the field plate section, the gate section and the field plate section are divided into two parts by a first plane. Within two adjacent field plate subsections, in the plane where the bottom surface of the gate section away from the lower field plate subsection is located, the projection of the end point of the lower surface of the lower field plate subsection lies on one side close to the first plane of the projection of the tip point of the lower surface of the upper field plate subsection, and the tip point of the lower surface of the upper field plate subsection coincides with the endpoint where the upper surface of the lower field plate subsection is connected to the lower surface of the upper field plate subsection. By connecting adjacent field plate subsections non-vertically, the electric field distribution is optimized to improve the reliability and stability of the semiconductor device.

[0010] Furthermore, the content described herein is not intended to determine the main or important features of the embodiments of the present invention, nor does it limit the scope of the invention. Other features of the present invention will be readily apparent through the following description. [Brief explanation of the drawing]

[0011] To more clearly explain the technical concepts in the embodiments of the present invention, the drawings necessary for use in the description of the embodiments will be briefly described below. However, the drawings described below represent only some embodiments of the present invention, and it will be clear to those skilled in the art that other drawings can be obtained based on these drawings without any creative effort. [Figure 1] This figure shows the configuration of a gate structure according to the first embodiment of the present invention. [Figure 2] This figure shows the configuration of a gate structure according to the first embodiment of the present invention. [Figure 3] This figure shows the configuration of a gate structure according to the first embodiment of the present invention. [Figure 4] This figure shows the configuration of a gate structure according to the first embodiment of the present invention. [Figure 5]It is a diagram showing the configuration of a gate structure according to a second embodiment of the present invention. [Figure 6] It is a diagram showing the configuration of a gate structure according to a second embodiment of the present invention. [Figure 7] It is a diagram showing the configuration of a semiconductor device according to a third embodiment of the present invention. [Figure 8] It is a diagram showing the configuration of a semiconductor device according to a third embodiment of the present invention. [Figure 9] It is a flowchart of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. [Figures 10A-10F] It is a diagram showing the configuration of an intermediate structure formed in the manufacturing process of a semiconductor device according to a fourth embodiment of the present invention. [Figure 11] It is a flowchart of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. [Figures 12A-12F] It is a diagram showing the configuration of an intermediate structure formed in the manufacturing process of a semiconductor device according to a fifth embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0012] In order to enable those skilled in the art to better understand the content of the present invention, hereinafter, in combination with the drawings of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be described more clearly and in detail. The following embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work should be included in the protection scope of the present invention.

[0013] In addition, the terms "including" and "having" in the specification, claims and the above drawings of the present invention, and any variations thereof, are intended to include non-exclusively. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, and may further include steps or units not listed, or may further include other steps or units specific to these processes, methods, products or devices.

[0014] During the design and manufacturing process of semiconductor devices, the design of the gate portion and the gate field plate is particularly important and plays an important role in the reliability and operational performance stability of semiconductor devices. According to the conventional design of the gate field plate, when the function of relaxing the electric field is restricted and the electric field of the gate is reduced, it is necessary to increase the length of the field plate or shorten the distance between the field plate and the two-dimensional electron gas channel. However, these two methods increase the electric field in the gate field plate, resulting in a risk of dielectric breakdown at the field plate location, and also increase the gate capacitance, which affects the bandwidth and high-frequency performance.

[0015] Therefore, how to further improve the bandwidth and high-frequency performance of semiconductor devices, while improving the reliability and stability of semiconductor devices, and realizing large-scale commercial production and manufacturing has become a problem to be solved.

[0016] Hereinafter, in combination with FIGS. 1 to 12F, the gate structure, semiconductor device, and semiconductor device manufacturing method according to embodiments of the present invention will be described.

[0017] First Embodiment Figure 1 shows the configuration of a gate structure according to a first embodiment of the present invention. As shown in Figure 1, the gate structure 10 includes a gate portion 11 and a field plate portion 12. The field plate portion 12 includes at least two field plate sub-parts. Of two adjacent field plate sub-parts, the field plate sub-part that is further away from the gate portion 11 is the upper field plate sub-part, and the field plate sub-part that is closer to the gate portion 11 is the lower field plate sub-part. In the direction from the gate portion 11 to the field plate portion 12, the gate portion 11 and the field plate portion 12 are divided into two parts by a first plane (the plane on which the dashed line is located in Figure 1): the part to the left of the dashed line and the part to the right of the dashed line. In one portion (either the portion to the left of the dashed line or the portion to the right of the dashed line), in the plane where the bottom surface of the gate portion 11 separates from the lower field plate sub-portion is located, the projection of the end point of the lower surface of the lower field plate sub-portion is located on one side of the projection of the tip point of the lower surface of the upper field plate sub-portion that is close to the gate portion 11 (or the first plane), and the tip point of the lower surface of the upper field plate sub-portion coincides with the endpoint where the upper surface of the lower field plate sub-portion is connected to the lower surface of the upper field plate sub-portion.

[0018] The first plane may be a bisecting plane perpendicular to the plane on which the bottom surface of the gate portion is located, or it may be just a plane perpendicular to the plane on which the bottom surface of the gate portion is located, but the present invention is not limited to these.

[0019] The upward direction is away from the gate portion 11, and the downward direction is close to the gate portion 11. The upper surface of one field plate sub-part is a surface away from the gate portion 11, and the lower surface of one field plate sub-part is a surface close to the gate portion 11. On the same side surface of the same field plate sub-part, one tip point is the endpoint of the side surface of the field plate sub-part in the direction close to the gate portion 11, i.e., the endpoint close to the first plane of the side surface, and one end point is the endpoint of the side surface of the field plate sub-part in the direction away from the gate portion 11, i.e., the endpoint away from the first plane of the side surface. In other words, one tip point of one surface is paired with an end point.

[0020] In this embodiment, the field plate portion 12 includes a first field plate sub-port 121 (i.e., a lower field plate sub-port) and a second field plate sub-port 122 (i.e., an upper field plate sub-port) that are aligned in the direction away from the gate portion 11. As shown in Figure 1, in the portion to the left of the dashed line, the end point 1212' of the lower surface of the first field plate sub-port 121 is located on one side close to the gate portion 11 (or the first plane) of the leading point 1221' of the lower surface of the second field plate sub-port 122, and the leading point 1221' of the lower surface of the second field plate sub-port 122 coincides with the endpoint 1213' where the upper surface of the first field plate sub-port 121 connects to the lower surface of the second field plate sub-port 122. Similarly, in the portion to the right of the dashed line, the above positional relationships exist at each endpoint, so the details are omitted here.

[0021] FIG. 2 is a diagram showing the configuration of a gate structure according to the first embodiment of the present invention. Referring to FIG. 2, FIG. 2 exemplarily shows that the field plate portion 12 includes a first field plate sub-portion 121, a second field plate sub-portion 122... a Nth field plate sub-portion 12N along the direction in which the field plate portion 12 is separated from the gate portion 11. As shown in FIG. 2, in two adjacent field plate sub-portions, the field plate sub-portion that is separated from the gate portion 11 is the Xth field plate sub-portion 12X, and the field plate sub-portion that is close to the gate portion 11 is the (X - 1)th field plate sub-portion 12(X - 1). Note that 1 < X ≦ N. The end point of the lower surface of the (X - 1)th field plate sub-portion 12(X - 1) (i.e., the lower field plate sub-portion) is located on the side close to the gate portion 11 of the tip point of the lower surface of the Xth field plate sub-portion 12X (i.e., the upper field plate sub-portion). The tip point of the lower surface of the Xth field plate sub-portion 12X (i.e., the upper field plate sub-portion) overlaps with the end point where the upper surface of the (X - 1)th field plate sub-portion 12(X - 1) is connected to the lower surface of the Xth field plate sub-portion 12X.

[0022] Two adjacent field plate sub-portions are connected non-vertically, that is, the side surface of the lower field plate sub-portion is connected non-vertically to the lower surface of the upper field plate sub-portion, thereby optimizing the distribution of the electric field and improving the reliability and stability of the semiconductor device.

[0023] In an alternative embodiment, the side surface of the uppermost Nth field plate sub-portion 12N (i.e., the field plate sub-portion that is farthest from the gate portion 11) may be a side surface perpendicular to the upper surface of the adjacent lower field plate sub-portion (i.e., the (N - 1)th field plate sub-portion 12(N - 1)), or may be a side surface that is not perpendicular to the upper surface of the adjacent lower field plate sub-portion (i.e., the (N - 1)th field plate sub-portion 12(N - 1)).

[0024] In other embodiments, the field plate portion may include a plurality of field plate sub-portions, and preferably includes N field plate sub-portions. Note that N ∈ [2, 4] and N is an integer.

[0025] FIGS. 1 and 2 exemplarily show a connection form of two adjacent field plate sub-portions. In one embodiment, as shown in FIG. 3, two adjacent field plate sub-portions are connected by a curve. That is, the side surfaces of the lower field plate sub-portion and the upper field plate sub-portion are both curved surfaces. In an alternative embodiment, as shown in FIG. 4, two adjacent field plate sub-portions are connected by a polyhedral surface. That is, the side surfaces of the lower field plate sub-portion and the upper field plate sub-portion are both polyhedral surfaces.

[0026] In an alternative embodiment, when the field plate portion 12 shown in FIG. 2 includes three field plate sub-portions, that is, when N = 3, the side surface of the uppermost third field plate sub-portion 123 may be a side surface perpendicular to the upper surface of the adjacent lower field plate sub-portion 122, or may be a curved surface.

[0027] On the right side of the dashed line, the positional relationship between two adjacent field plate sub-portions is M(X - 1) < L(X - 1) and M(X - 1) < D(X - 1). Note that X is an integer greater than or equal to 2. Similarly, on the left side of the dashed line, the above-described positional relationship also exists between two adjacent field plate sub-portions, so the details are omitted here.

[0028] Optionally, taking FIG. 1 as an example, on the right side of the dashed line, the positional relationship between two adjacent field plate sub-portions is M1 < L1 and M1 < D1.

[0029] In the plane where the bottom surface of the gate portion 11 is located, M1 is the distance between the projection of the tip point 1221 of the lower surface of the second field plate sub - portion 122 (i.e., the upper field plate sub - portion) and the projection of the end point 1212 of the lower surface of the first field plate sub - portion 121 (i.e., the lower field plate sub - portion), and L1 is the distance between the projection of the tip point 1211 of the lower surface of the first field plate sub - portion 121 (i.e., the lower field plate sub - portion) and the projection of the end point 1212 of the lower surface thereof. In the plane perpendicular to the plane where the bottom surface of the gate portion 11 is located, D1 is the distance between the projection of the tip point 1221 of the lower surface of the second field plate sub - portion 122 (i.e., the upper field plate sub - portion) and the projection of the end point 1212 of the lower surface of the first field plate sub - portion 121 (i.e., the lower field plate sub - portion).

[0030] According to such an installation, a non - vertical continuation of two adjacent field plate sub - portions can be realized. Thereby, the parasitic capacitance of the source or drain can be reduced, and the bandwidth and high - frequency performance of the semiconductor device can be improved.

[0031] On the right - hand side of the dashed line, the positional relationship between two adjacent field plate sub - portions is L(X - 1)<LX. X is an integer greater than or equal to 2. Similarly, on the left - hand side of the dashed line, in two adjacent field plate sub - portions, since the above - mentioned positional relationship exists, the details are omitted here.

[0032] Optionally, taking FIG. 1 as an example, on the right - hand side of the dashed line, the positional relationship between two adjacent field plate sub - portions is L1<L2.

[0033] In the plane where the bottom surface of the gate portion 11 is located, L1 is the distance between the projection of the tip point 1211 of the lower surface of the first field plate sub - portion 121 (i.e., the lower field plate sub - portion) and the projection of the end point 1212 of the lower surface thereof, and L2 is the distance between the projection of the tip point 1221 of the lower surface of the second field plate sub - portion 122 (i.e., the upper field plate sub - portion) and the projection of the end point 1222 of the lower surface thereof.

[0034] This type of installation optimizes the electric field distribution beneath the field plate, reducing the risk of dielectric breakdown in the field plate.

[0035] The above example shows the positional relationship between two adjacent field plate sub-sections when the field plate section includes two field plate sub-sections. However, when the field plate section includes multiple field plate sub-sections, the positional relationship between any two adjacent field plate sub-sections in the multiple field plate sub-sections also satisfies the above relationship, and therefore, the details of this are omitted in this invention. The connection points (also referred to as endpoints) mentioned in this invention are used only for cross-sectional views, but since the connection surfaces are specifically used for oblique view structures, this does not limit the scope of protection of this invention.

[0036] Selectively, referring to Figure 2, the positional relationship between the first field plate sub-part 121 adjacent to the gate part 11 and the gate part 11 (also referred to as the size relationship of the first field plate sub-part 121 adjacent to the gate part 11 and located on different sides of the gate part 11) is L1 = L1'. The positional relationship between the Nth field plate sub-part 12N furthest from the gate part 11 and the N-1st field plate sub-part 12(N-1) (also referred to as the size relationship of the Nth field plate sub-part 12N furthest from the gate part 11, located on different sides of the N-1st field plate sub-part 12(N-1) adjacent to the Nth field plate sub-part 12N furthest from the gate part 11) is LN = LN'. With such an installation, the electric field at one end of the gate part close to the source can be optimized to improve the reliability and stability of the semiconductor device. In this embodiment, the structure of the gate part 11 satisfies M0 = M0'. In this embodiment, both the gate portion 11 and the field plate portion 12 have a symmetrical structure.

[0037] In other embodiments, the positional relationship between the gate portion 11 and the first field plate sub-port 121 adjacent to the gate portion 11 is L1 > L1', and the positional relationship between the Nth field plate sub-port 12N, which is furthest from the gate portion 11, and the N-1st field plate sub-port 12(N-1) is LN > LN'. Since the gate-drain voltage is much larger than the gate-source voltage when the semiconductor device is operating, designing with L1 > L1' and LN > LN' avoids the introduction of parasitic capacitance in L1' and LN', further improving the bandwidth and high-frequency performance of the semiconductor device. In this embodiment, the structure of the gate portion 11 satisfies M0 > M0'. Both the gate portion 11 and the field plate portion 12 in this embodiment have an asymmetric structure.

[0038] In other embodiments, the structure of the gate portion 11 satisfies M0=M0′, the positional relationship between the gate portion 11 and the first field plate sub-port 121 adjacent to the gate portion 11 is L1>L1′, and the positional relationship between any pair of adjacent field plate sub-ports in the plurality of field plate sub-ports (for example, the Xth field plate sub-port 12X and the X-1st field plate sub-port 12(X-1)) is LX>LX′, where X is 2 or greater and N or less. With such an installation, the electric field at one end of the gate portion close to the source can be optimized to improve the reliability and stability of the semiconductor device. In this embodiment, the structure of the gate portion 11 is symmetrical, and the field plate portion 12 is asymmetrical.

[0039] In other embodiments, the structure of the gate portion 11 satisfies M0=M0′, the positional relationship between the gate portion 11 and the first field plate sub-port 121 adjacent to the gate portion 11 is L1=L1′, and the positional relationship between any pair of adjacent field plate sub-ports in the plurality of field plate sub-ports (for example, the Xth field plate sub-port 12X and the X-1st field plate sub-port 12(X-1)) is LX>LX′, where X is 2 or greater and N or less. With such an installation, the electric field at one end of the gate portion close to the source can be optimized to improve the reliability and stability of the semiconductor device. In this embodiment, both the gate portion 11 and the first field plate sub-port 121 have a symmetric structure, while the other field plate sub-ports among the plurality of field plate sub-ports, other than the first field plate sub-port 121, have an asymmetric structure.

[0040] In the plane where the bottom surface of the gate portion 11 is located, L1 is the distance between the projection of the leading edge and the projection of the end point of the lower surface of the first field plate sub-part 121 located on one side of the first plane (to the right of the dashed line) and adjacent to the gate portion 11, L1' is the distance between the projection of the leading edge and the projection of the end point of the lower surface of the first field plate sub-part 121 located on the other side of the first plane (to the left of the dashed line) and adjacent to the gate portion 11, LN is the distance between the projection of the leading edge and the projection of the end point of the lower surface of the Nth field plate sub-part 12N located on one side of the first plane (to the right of the dashed line) and furthest from the gate portion 11, and LN' is the distance between the projection of the leading edge and the projection of the end point of the lower surface of the Nth field plate sub-part 12N located on the other side of the first plane (to the left of the dashed line) and furthest from the gate portion 11.

[0041] The gate structure according to the embodiment of the present invention is widely applicable to fields such as high-frequency microwaves and power supply electronics. In particular, it shows remarkable advantages in gallium nitride electronic devices, which have a large band gap, high electron drift rate, high dielectric breakdown field strength, and excellent thermal conductivity. The quality and stability of the formed metal electrodes are excellent, significantly improving the electrical performance of the electrodes and better meeting the high performance requirements of rapidly developing fields such as electronic communications.

[0042] Second Example Figure 5 shows the configuration of a gate structure according to a second embodiment of the present invention. Referring to Figure 5, in the portion to the right of the dashed line, the gate portion 11 includes a bottom surface 110 that separates from the field plate portion 12, and a first side surface 111 adjacent to the bottom surface 110. Similarly, in the portion to the left of the dashed line, the gate portion 11 also includes a first side surface (not shown).

[0043] In the portion to the right of the dashed line, in the plane where the bottom surface 110 of the gate portion 11 is located, the projection of the endpoint 1112 where the gate portion 11 is connected to the first field plate sub-part 121 in the field plate portion 12 is located on one side away from the gate portion 11 (or the first plane shown by the dashed line) of the projection of the endpoint 1111 where the bottom surface 110 is connected to the first side surface 111. In the portion to the left of the dashed line, the projection of the endpoint 1112' where the gate portion 11 is connected to the first field plate sub-part 121 in the field plate portion 12 is located on one side away from the gate portion 11 (or the first plane shown by the dashed line) of the projection of the endpoint 1111' where the bottom surface 110 is connected to the first side surface 111.

[0044] The first side is located on one side of the end point 1111 of the bottom surface of the gate portion 11, away from the plane on which the bottom surface is located and close to the plane on which the field plate portion 12 is located.

[0045] In this embodiment, endpoints 1111 and 1111', and endpoints 1112 and 1112' are substantially indistinguishable, solely to distinguish whether the endpoints are located on the same side of the first plane. Endpoints 1111 and 1112 are on the same side, while endpoints 1111' and 1112' are on opposite sides.

[0046] In the two parts, the positional relationship between the upper surface of the gate part 11 and the bottom surface 110 of the gate part 11 (also referred to as the distance relationship between the end point where the gate part 11 is connected to the field plate part 12 and the end point where the bottom surface 110 is connected to the first side surface) is M0 < L0 and MO' < L0. Preferably, the positional relationship between the upper surface of the gate part 11 and the bottom surface 110 of the gate part 11 is M0 < L0 / 4 and MO' < L0 / 4.

[0047] The structure of the gate part 11 satisfies M0 = MO', so that this gate structure can be more appropriately applied in the field of high-frequency communication.

[0048] In other embodiments, in the two parts, the positional relationship between the upper surface of the gate part 11 and the bottom surface 110 of the gate part 11 (also referred to as the distance relationship between the end point where the gate part 11 is connected to the field plate part 12 and the bottom surface 110 of the gate part 11) is M0 ≤ D0 and MO' ≤ D0.

[0049] In the plane where the bottom surface of the gate part 11 is located, M0 is the distance between the projection of the end point 1112 where the gate part 11 located on one side of the first plane (i.e., the right side of the dashed line) is connected to the first field plate sub-part 121 in the field plate part 12 and the projection of the end point 1111 where the bottom surface 110 is connected to the first side surface 111. MO' is the distance between the projection of the end point 1112' where the gate part 11 located on the other side of the first plane (i.e., the left side of the dashed line) is connected to the first field plate sub-part 121 in the field plate part 12 and the projection of the end point 1111' where the bottom surface 110 is connected to the first side surface 111. L0 is the distance between the projection of the end point 1111 where the bottom surface 110 located on one side of the first plane is connected to the first side surface 111 and the projection of the end point 1111' where the bottom surface 110 located on the other side of the first plane is connected to the first side surface 111. D0 is the vertical distance between the upper surface and the bottom surface of the gate part 11.

[0050] In an alternative embodiment, the upper surface of the gate portion 11 and the bottom surface 110 of the gate portion 11 are connected by a polygonal surface. That is, if MO' ≤ D0 is satisfied, the connecting surface between the endpoint 1112 where the gate portion 11 located on one side of the first plane connects to the first field plate sub-part 121 in the field plate portion 12, and the endpoint 1111 where the bottom surface 110 connects to the first side surface 111, may be a polygonal surface. Similarly, if MO' ≤ D0 is satisfied, the connecting surface between the endpoint 1112' where the gate portion 11 located on the other side of the first plane connects to the first field plate sub-part 121 in the field plate portion 12, and the endpoint 1111' where the bottom surface 110 connects to the first side surface 111, may be a polygonal surface.

[0051] In other words, the connection between the bottom surface 110 and the first side surface 111, or the connection between the first side surface 111 and the lower surface of the field plate portion 12, is a non-vertical connection, and there is a trade-off relationship between the distance between the endpoint 1111 where the bottom surface 110 is connected to the first side surface 111 and the endpoint 1112 where the gate portion 11 is connected to the field plate portion 12, thereby improving the frequency characteristics.

[0052] This type of installation can reduce parasitic capacitance and improve the bandwidth and high-frequency performance of semiconductor devices.

[0053] Figure 6 shows the configuration of a gate structure according to a second embodiment of the present invention. As shown in Figure 6, the gate portion 11 further includes a second side surface 112. The endpoint 1113, to which one end of the second side surface 112 is connected to the first side surface 111, is located on the same side of the first plane as the endpoint to which the second side surface 112 is connected to the field plate portion 12.

[0054] In one embodiment, on the plane where the bottom surface 110 is located, the projection of the endpoint 1112 where the second side surface 112 is connected to the field plate portion 12 is located on the side away from the endpoint 1111 (or the first plane) where the bottom surface 110 is connected to the first side surface 111, as opposed to the projection of the endpoint 1113 where one end of the second side surface 112 is connected to the first side surface 111. In another embodiment, on the plane where the bottom surface 110 is located, the projection of the endpoint 1113 where one end of the second side surface 112 is connected to the first side surface 111 overlaps with the projection of the endpoint 1112 where the second side surface 112 is connected to the field plate portion 12.

[0055] The connecting surface between the endpoint 1111 where the bottom surface 110 is connected to the first side surface 111 and the endpoint 1112 where the gate portion 11 is connected to the first field plate sub-portion 121 in the field plate portion 12 may be a flat surface or a curved surface. In an alternative embodiment, the endpoint 1111 where the bottom surface 110 is connected to the first side surface 111 and the endpoint 1112 where the gate portion 11 is connected to the first field plate sub-portion 121 in the field plate portion 12 are connected by a polygonal surface.

[0056] Third Example Figure 7 shows the configuration of a semiconductor device according to a third embodiment of the present invention. As shown in Figure 7, the semiconductor device includes a substrate 60, a semiconductor layer 50, a source 20, a drain 30, a passivation layer 40, and a gate structure 10. The semiconductor layer 50 is formed on one side of the substrate 60. The source 20 and drain 30 are formed on one side of the semiconductor layer 50 away from the substrate 60. The passivation layer 40 is formed on one side of the semiconductor layer 50 away from the substrate 60. The gate structure 10 is formed on one side of the passivation layer 40 away from the substrate 60. By combining this with Figure 1, it can be seen that the field plate portion 12 of the gate structure 10 is located on one side of the gate portion 11 of the gate structure 10 away from the semiconductor layer 50.

[0057] Preferably, in one embodiment of the present invention, the material of the passivation layer comprises silicon nitride and / or silicon oxynitride. The substrate may be formed from one of the materials selected from silicon, sapphire, silicon carbide, or gallium arsenide. The semiconductor layer may be formed from at least one of gallium nitride, aluminum gallium nitride, or indium gallium nitride.

[0058] Based on the above embodiment, as shown in Figure 8, the semiconductor layer 50 further includes a nucleation layer 51, a buffer layer 52, a channel layer 53, a barrier layer 54, and a cap layer (not shown) arranged sequentially in the direction away from the substrate 60. In this embodiment, the barrier layer 54 contacts the source 20 and the drain 30, respectively, to form an ohmic contact. The channel layer 53 and the barrier layer 54 form a heterojunction. A two-dimensional electron gas layer 55 is formed at the heterojunction. The bottom surface of the gate portion 11 may contact the upper surface of the barrier layer 54 away from the substrate 60, or it may be located inside the barrier layer 54.

[0059] In the area to the right of the dashed line, the positional relationship between two adjacent field plate sub-sections and the two-dimensional electron gas layer 55 is L(X-1) < 5.5*H(X-1) and LX < 5.5*HX. X is an integer greater than or equal to 2. Similarly, in the area to the left of the dashed line, the same positional relationship exists between two adjacent field plate sub-sections and the two-dimensional electron gas layer 55; therefore, the details are omitted here.

[0060] Using Figure 8 as an example, when X=2, the positional relationship between two adjacent field plate sub-sections and the two-dimensional electron gas layer 55 is L1 < 5.5*H1 and L2 < 5.5*H2. Depending on the positional relationship between the bottom surface of the gate section 11 and the barrier layer 54, the relationship between D0, L1, D1, and L2 may be appropriately adjusted to satisfy the distance requirement between the field plate section 12 and the two-dimensional electron gas layer 55.

[0061] In the portion to the right of the dashed line, in the plane where the bottom surface of the gate portion 11 is located, L(X-1) is the distance between the projection of the leading edge and the projection of the end point of the lower surface of the X-1 field plate sub-part 12(X-1) (i.e., the lower field plate sub-part), and LX is the distance between the projection of the leading edge and the projection of the end point of the lower surface of the X field plate sub-part 12X (i.e., the upper field plate sub-part). H(X-1) is the vertical distance between the lower surface of the X-1 field plate sub-part 12(X-1) and the two-dimensional electron gas layer 55. HX is the vertical distance between the lower surface of the X field plate sub-part 12X and the two-dimensional electron gas layer 55.

[0062] After L(X-1) > 5.5*H(X-1) (and LX > 5.5*HX), the length of the field plate section 12 is further increased. This provides a further mitigation effect on the electric field and increases parasitic capacitance. Because the distance between the field plate section 12 and the two-dimensional electron gas layer 55 has a significant impact on the performance of the device, the thickness of the field plate section 12 can be adjusted by adjusting the depth to which the bottom surface of the gate section 11 extends into the semiconductor layer 50, thereby controlling the ranges of D2 and D3 and adjusting the installation by the power device.

[0063] According to the gallium nitride high-frequency device formed by the semiconductor device structure of the present invention, the power and frequency of the gallium nitride high-frequency device are improved while maintaining the stability of the semiconductor device's performance, making it more suitable for application in the high-frequency 5G communication range.

[0064] In the specific embodiments described above, the endpoints are used only with respect to the cross-sectional view, but the connecting surfaces are used specifically with respect to the oblique view structure, and this does not limit the scope of protection of the present invention.

[0065] Fourth Embodiment Figure 9 is a flowchart of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. This method is for manufacturing the above-mentioned semiconductor device. Figures 10A to 10F show the configuration of an intermediate structure formed during the manufacturing process of a semiconductor device according to a fourth embodiment of the present invention. Referring to Figures 10A to 10F, this manufacturing method includes the following steps.

[0066] S110: A semiconductor layer 50 is formed on one side of the substrate 60.

[0067] S120: A passivation layer 40 is formed on one side of the semiconductor layer 50 that is separated from the substrate 60.

[0068] S130: The first photoresist is applied to the passivation layer 40 using the first photoresist 70, and the passivation layer 40 is etched to form a first layer opening hole within the passivation layer 40. In the direction perpendicular to the direction from the substrate 60 to the passivation layer 40, the opening size (also called width) of the first photoresist before etching is L1 + L1' + L0 + M0 + M0', and in the direction from the substrate 60 to the passivation layer 40, the opening size of the first photoresist after etching is L1 + L1' + L0 + M0 + M0' + M1 + M1', and in the direction from the substrate 60 to the passivation layer 40, the size (also called depth) of the first layer opening hole is D1.

[0069] Specifically, referring to Figures 10C and 10D, a first photoresist 70 is formed on one side of the passivation layer 40 away from the semiconductor layer 50, and an opening of size L1+L1′+L0+M0+M0′ is secured. A first photoresist is applied to the passivation layer 40 at the opening position. The opening size of the first photoresist after etching (i.e., the opening size of the first layer opening) is L1+L1′+L0+M0+M0′+M1+M1′. In this embodiment, in the process of etching the passivation layer 40 based on the first photoresist 70 to form the first layer opening, the passivation layer 40 is etched, and the first photoresist 70 at the edge of the first layer opening is etched simultaneously. Therefore, the opening size of the first photoresist after etching is larger than the opening size of the first photoresist before etching, and there is a certain slope on the side surface of the first layer opening. In this embodiment, the first photoresist 70 is substantially wedge-shaped before etching, and the wedge-shaped tips of the first photoresist 70 on both sides of the opening are directed toward the opening. Preferably, the inclination angle of the tips of the first photoresist 70 is different from the inclination angle of the passivation layer 40 after etching.

[0070] S140: Using the second photoresist 80, a second photoresist is applied to the passivation layer 40 based on the first layer opening, and the passivation layer 40 is etched to form a second layer opening located below the first layer opening within the passivation layer 40. In the direction perpendicular to the direction from the substrate 60 to the passivation layer 40, the opening size of the second photoresist 80 before etching is L0, and the opening size of the second photoresist 80 after etching is L0+M0+M0′. In the direction from the substrate 60 to the passivation layer 40, the size of the second layer opening is D0, and the semiconductor layer 50 is exposed at the second layer opening.

[0071] Referring to Figures 10E and 10F, a second photoresist 80 is formed on the lower surface (bottom surface) of the first layer opening, and an opening of size L0 is secured. A second photoresist is applied to the passivation layer 40 at the opening position. The opening size of the second photoresist 80 after etching is L0 + M0 + M0'. In this embodiment, in the process of forming the second layer opening by etching the passivation layer 40 based on the second photoresist 80 on the bottom surface of the first layer opening, the passivation layer 40 is etched, and the second photoresist 80 at the edge of the second layer opening is etched simultaneously. Therefore, the opening size of the second photoresist 80 after etching is larger than the opening size of the second photoresist 80 before etching, and the sides of the second layer opening also have a certain slope. In this embodiment, the second photoresist 80 is approximately wedge-shaped before etching, and the wedge-shaped tips of the second photoresist 80 on both sides of the opening are directed toward the opening. Preferably, the inclination angle of the tip of the second photoresist 80 is different from the inclination angle of the passivation layer 40 after etching.

[0072] S150: The gate structure 10 is deposited to form the gate portion 11 and the field plate portion 12. The gate portion 11 completely fills the second layer opening, and the field plate portion 12 covers the gate portion 11 to completely fill the first layer opening.

[0073] In an alternative embodiment, after forming the semiconductor layer 50, the source 20 and drain 30 are formed, and further, a passivation layer 40 covering the source 20 and drain 30 is formed on one side of the semiconductor layer 50 away from the substrate 60. In another alternative embodiment, after forming the passivation layer 40 on one side of the semiconductor layer 50 away from the substrate, the passivation layer 40 is perforated accordingly to expose the semiconductor layer 50, and the source 20 and drain 30 are formed within the perforated holes. In this embodiment, the source 20 and drain 30 are located on both sides of the gate structure 10.

[0074] Fifth Example Figure 11 is a flowchart of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. This method is for manufacturing the semiconductor device of the above embodiment. Figures 12A to 12F are diagrams showing the manufacturing process of a semiconductor device according to a fifth embodiment of the present invention. Referring to Figures 12A to 12F, this manufacturing method includes the following steps.

[0075] S210: A semiconductor layer 50 is formed on one side of the substrate 60.

[0076] S220: A passivation layer 40 is formed on one side of the semiconductor layer 50 that is separated from the substrate 60.

[0077] S230: A first photoresist is applied to the passivation layer 40 using photoresist 70, and the passivation layer 40 is etched to form a first layer opening hole within the passivation layer 40. In the direction perpendicular to the direction from the substrate 60 to the passivation layer 40, the opening size of the photoresist 70 before etching is L0, and the opening size of the photoresist 70 after etching is L0 + M0 + M0'. In the direction from the substrate 60 to the passivation layer 40, the size of the first layer opening hole is D0.

[0078] Specifically, referring to Figures 12C and 12D, a photoresist 70 is formed on one side of the passivation layer 40 that is away from the semiconductor layer 50, and an opening of size L0 is secured. A first photoresist is applied to the passivation layer 40 at the opening location. The opening size of the photoresist 70 after etching (i.e., the opening size of the first layer opening) is L0 + M0 + M0'. In this embodiment, in the process of etching the passivation layer 40 with the photoresist 70 to form the first layer opening, the passivation layer 40 is etched, and the photoresist 70 at the edge of the first layer opening is etched simultaneously. Therefore, the opening size of the photoresist 70 after etching is larger than the opening size of the photoresist 70 before etching, and there is a certain inclination on the side surface of the first layer opening. In this embodiment, before etching, the shape of the photoresist 70 near the opening is approximately wedge-shaped, and the wedge-shaped tips of the photoresist 70 on both sides of the opening are pointed towards the opening. Preferably, the inclination angle of the tip of the photoresist 70 is different from the inclination angle of the passivation layer 40 after etching.

[0079] S240: Selective etching expands the photoresist 70 after etching. The aperture size of the expanded photoresist 70 in the direction perpendicular to the direction from the substrate 60 to the passivation layer 40 is L1 + L1' + L0 + M0 + M0'.

[0080] S250: Using the expanded photoresist 70, a second photoresist is applied to the passivation layer 40 based on the first layer opening, etching the passivation layer 40 to cause the first layer opening to descend overall in the direction of the substrate 60, and forming a second layer opening located above the first layer opening within the passivation layer 40. In the direction perpendicular to the direction from the substrate 60 to the passivation layer 40, the opening size of the expanded photoresist 70 after etching is L1 + L1' + L0 + M0 + M0' + M1 + M1'. In the direction from the substrate 60 to the passivation layer 40, the size of the second layer opening is D1, and the semiconductor layer 50 is exposed at the first layer opening.

[0081] In this embodiment, in the process of etching the passivation layer 40 based on the spread photoresist 70 to form a second layer opening, the passivation layer 40 is etched, and the photoresist 70 at the edges of the second layer opening is etched simultaneously. Therefore, the opening size of the photoresist 70 after etching is larger than the opening size of the photoresist 70 before etching, and the sides of the second layer opening may also have a certain inclination. In this embodiment, before etching, the shape of the photoresist 70 near the opening is approximately wedge-shaped, and the wedge-shaped tips of the photoresist 70 on both sides of the opening face the opening. Preferably, the inclination angle of the tips of the photoresist 70 is different from the inclination angle of the passivation layer 40 after etching.

[0082] S260: The gate structure 10 is deposited to form the gate portion 11 and the field plate portion 12. The gate portion 11 completely fills the first layer opening, and the field plate portion 12 covers the gate portion 11 to completely fill the second layer opening.

[0083] In an alternative embodiment, after forming the semiconductor layer 50, the source 20 and drain 30 are formed, and further, a passivation layer 40 covering the source 20 and drain 30 is formed on one side of the semiconductor layer 50 away from the substrate 60. In another alternative embodiment, after forming the passivation layer 40 on one side of the semiconductor layer 50 away from the substrate 60, the passivation layer 40 is perforated accordingly to expose the semiconductor layer 50, and the source 20 and drain 30 are formed within the opening. In this embodiment, the source 20 and drain 30 are located on both sides of the gate structure 10.

[0084] In an alternative embodiment, the photoresist of the above embodiment may be used to manufacture an aperture of the same thickness that does not have an inclined surface.

[0085] It should be understood that the steps can be rearranged, added, or deleted using the various forms of flows shown above. For example, each step described in the present invention may be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical proposal of the present invention are achieved, and is not limited thereto.

[0086] The specific embodiments described above do not limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications, combinations, subcombinations, and substitutions may be made depending on design requirements and other factors. Modifications, equivalent substitutions, and improvements made within the spirit and intent of the present invention should all be included within the scope of protection of the present invention.

Claims

1. It is a gate structure, Including the gate section and the field plate section, The field plate portion includes at least two field plate sub-portions, Within two adjacent field plate sub-sections, the field plate sub-section further away from the gate is the upper field plate sub-section, and the field plate sub-section closer to the gate is the lower field plate sub-section. In the direction from the gate portion to the field plate portion, the gate portion and the field plate portion are divided into two parts by a first plane. In one part, in the plane where the bottom surface of the gate portion is located away from the lower field plate sub-part, the projection of the end point of the lower surface of the lower field plate sub-part is located on one side adjacent to the first plane of the projection of the tip point of the lower surface of the upper field plate sub-part, and the tip point of the lower surface of the upper field plate sub-part coincides with the endpoint where the upper surface of the lower field plate sub-part is connected to the lower surface of the upper field plate sub-part. The upper surface of one field plate sub-part is a surface away from the gate portion, the lower surface of one field plate sub-part is a surface close to the gate portion, and on the same side surface of the same field plate sub-part, one tip point is an endpoint close to the first plane of the surface of the field plate sub-part, and one end point is an endpoint away from the first plane of the surface of the field plate sub-part. In one part, the positional relationship between the two adjacent field plate sub-parts is M(X-1) < L(X-1) and M(X-1) < D(X-1), X is an integer greater than or equal to 2, In the plane where the bottom surface of the gate portion is located, M(X-1) is the distance between the projection of the leading edge of the lower surface of the upper field plate sub-part and the projection of the trailing edge of the lower surface of the lower field plate sub-part, and L(X-1) is the distance between the projection of the leading edge of the lower surface of the lower field plate sub-part and the projection of the trailing edge of the lower surface of the lower field plate sub-part. In a plane perpendicular to the plane on which the bottom surface of the gate portion is located, D(X-1) is the distance between the projection of the endpoint where the upper surface of the lower field plate sub portion connects with the lower surface of the upper field plate sub portion and the projection of the end point of the lower surface of the lower field plate sub portion.

2. In one section, the positional relationship between the two adjacent field plate sub-sections is L(X-1) < LX, X is an integer greater than or equal to 2, The gate structure according to claim 1, characterized in that, in the plane where the bottom surface of the gate portion is located, L(X-1) is the distance between the projection of the leading edge of the lower surface of the lower field plate sub-part and the projection of the end point of the lower surface of the lower field plate sub-part, and LX is the distance between the projection of the leading edge of the lower surface of the upper field plate sub-part and the projection of the end point of the lower surface of the upper field plate sub-part.

3. In one part, the gate portion includes a bottom surface that separates from the field plate portion, and a first side surface adjacent to the bottom surface. In the plane where the bottom surface of the gate portion is located, the projection of the endpoint where the gate portion is connected to the field plate portion is located on one side away from the first plane of the projection of the endpoint where the bottom surface is connected to the first side surface. In the two aforementioned parts, the distance relationship between the endpoint where the gate portion is connected to the field plate portion and the endpoint where the bottom surface is connected to the first side surface is M0 < L0 and MO' < L0. The gate structure according to claim 1, characterized in that, in the plane where the bottom surface of the gate portion is located, M0 is the distance between the projection of the endpoint where the gate portion located on one side of the first plane is connected to the field plate portion and the projection of the endpoint where the bottom surface is connected to the first side surface, M0' is the distance between the projection of the endpoint where the gate portion located on the other side of the first plane is connected to the field plate portion and the projection of the endpoint where the bottom surface is connected to the first side surface, and L0 is the distance between the projection of the endpoint where the bottom surface located on one side of the first plane is connected to the first side surface and the projection of the endpoint where the bottom surface located on the other side of the first plane is connected to the first side surface.

4. In one part, the gate portion includes a bottom surface that separates from the field plate portion, and a first side surface adjacent to the bottom surface. In the plane where the bottom surface of the gate portion is located, the projection of the endpoint where the gate portion is connected to the field plate portion is located on one side away from the first plane of the projection of the endpoint where the bottom surface is connected to the first side surface. In the two aforementioned parts, the distance relationship between the endpoint where the gate portion is connected to the field plate portion and the bottom surface of the gate portion is M0 ≤ D0 and MO' ≤ D0. The gate structure according to claim 1, characterized in that, in the plane where the bottom surface of the gate portion is located, M0 is the distance between the projection of the endpoint where the gate portion located on one side of the first plane is connected to the field plate portion and the projection of the endpoint where the bottom surface is connected to the first side surface, M0' is the distance between the projection of the endpoint where the gate portion located on the other side of the first plane is connected to the field plate portion and the projection of the endpoint where the bottom surface is connected to the first side surface, and D0 is the vertical distance between the upper surface of the gate portion adjacent to the field plate portion and the bottom surface of the gate portion.

5. In one part, the gate portion further includes a second side surface, The second side is connected at one end to the first side and at the other end to the field plate portion. The positional relationship between the endpoint where the second side surface is connected to the field plate portion and the endpoint where the first side surface is connected to the second side surface is, In the plane where the bottom surface of the gate portion is located, the projection of the endpoint where the second side surface is connected to the field plate portion is located on one side away from the first plane of the projection of the endpoint where the first side surface is connected to the second side surface, or The gate structure according to claim 3, characterized in that, in the plane where the bottom surface of the gate portion is located, the projection of the endpoint where the second side surface is connected to the field plate portion overlaps with the projection of the endpoint where the first side surface is connected to the second side surface.

6. It is a gate structure, Including the gate section and the field plate section, In the direction from the gate portion to the field plate portion, the gate portion and the field plate portion are divided into two parts by a first plane. In one part, the gate portion includes a bottom surface that separates from the field plate portion, and a first side surface adjacent to the bottom surface. In the plane where the bottom surface of the gate portion is located, the projection of the endpoint where the gate portion is connected to the field plate portion is located on one side away from the first plane of the projection of the endpoint where the bottom surface is connected to the first side surface. In the two aforementioned parts, the distance relationship between the endpoint where the gate portion is connected to the field plate portion and the endpoint where the bottom surface is connected to the first side surface is M0 < L0 and MO' < L0. In the plane where the bottom surface of the gate portion is located, M0 is the distance between the projection of the endpoint where the gate portion, located on one side of the first plane, is connected to the field plate portion and the projection of the endpoint where the bottom surface is connected to the first side surface; M0' is the distance between the projection of the endpoint where the gate portion, located on the other side of the first plane, is connected to the field plate portion and the projection of the endpoint where the bottom surface is connected to the first side surface; and L0 is the distance between the projection of the endpoint where the bottom surface, located on one side of the first plane, is connected to the first side surface and the projection of the endpoint where the bottom surface, located on the other side of the first plane, is connected to the first side surface. In one part, the distance relationship between the endpoint where the gate portion is connected to the field plate portion and the bottom surface of the gate portion is M0 ≤ D0. The gate structure is characterized in that D0 is the vertical distance between the upper surface of the gate portion that is close to the field plate portion and the bottom surface of the gate portion.

7. In one part, the gate portion further includes a second side surface, The second side is connected at one end to the first side and at the other end to the field plate portion. The positional relationship between the endpoint where the second side surface is connected to the field plate portion and the endpoint where the first side surface is connected to the second side surface is, In the plane where the bottom surface of the gate portion is located, the projection of the endpoint where the second side surface is connected to the field plate portion is located on one side away from the first plane of the projection of the endpoint where the first side surface is connected to the second side surface, or The gate structure according to claim 6, characterized in that, in the plane where the bottom surface of the gate portion is located, the projection of the endpoint where the second side surface is connected to the field plate portion overlaps with the projection of the endpoint where the first side surface is connected to the second side surface.

8. The gate structure according to claim 6, characterized in that M0 = MO'.

9. A semiconductor device, circuit board and A semiconductor layer formed on one side of the substrate, A passivation layer formed on one side of the semiconductor layer away from the substrate, A gate structure according to any one of claims 1 to 8, The gate structure is formed on one side of the passivation layer that is away from the substrate, The semiconductor device is characterized in that the field plate portion is located on one side of the gate portion that is away from the semiconductor layer.

10. The material further includes a nucleation layer, a buffer layer, a channel layer, and a barrier layer arranged sequentially in the layer direction away from the substrate, The channel layer and the barrier layer form a heterojunction. A two-dimensional electron gas layer is formed at the location of the heterojunction. The field plate portion includes at least two field plate sub-parts, The positional relationship between two adjacent field plate sub-sections and the two-dimensional electron gas layer is such that L(X-1) < 5.5*H(X-1) and LX < 5.5*HX. X is an integer greater than or equal to 2, In the direction from the gate portion to the field plate portion, the gate portion and the field plate portion are divided into two parts by a first plane. In one part, in the plane where the bottom surface of the gate portion is located, L(X-1) is the distance between the projection of the leading edge of the lower surface of the lower field plate sub-part and the projection of the trailing edge of the lower surface of the lower field plate sub-part, LX is the distance between the projection of the leading edge of the lower surface of the upper field plate sub-part and the projection of the trailing edge of the lower surface of the upper field plate sub-part, H(X-1) is the vertical distance between the lower surface of the lower field plate sub-part and the two-dimensional electron gas layer, and HX is the vertical distance between the lower surface of the upper field plate sub-part and the two-dimensional electron gas layer. Within the two adjacent field plate sub-sections, the field plate sub-section that is further away from the gate section is the upper field plate sub-section, and the field plate sub-section that is closer to the gate section is the lower field plate sub-section. In each section, the upper surface of one field plate sub-section is a surface that is away from the gate section, and the lower surface of one field plate sub-section is a surface that is close to the gate section. The semiconductor device according to claim 9, characterized in that on the same side surface of the same field plate sub-part, one tip point is an endpoint close to the first plane of the surface of the field plate sub-part, and the end point is an endpoint away from the first plane of the surface of the field plate sub-part.

11. A method for manufacturing a semiconductor device for manufacturing the semiconductor device described in claim 9, Forming a semiconductor layer on one side of the substrate, A passivation layer is formed on one side of the semiconductor layer that is away from the substrate, A first photoresist is applied to the passivation layer using a first photoresist, the passivation layer is etched to form a first layer opening hole within the passivation layer, the opening size of the first photoresist before etching is L1 + L1' + L0 + M0 + M0' in the direction perpendicular to the direction from the substrate to the passivation layer, the opening size of the first photoresist after etching is L1 + L1' + L0 + M0 + M0' + M1 + M1', and the size of the first layer opening hole in the direction from the substrate to the passivation layer is D1. Using a second photoresist, a second photoresist is applied to the passivation layer based on the first layer opening, the passivation layer is etched to form a second layer opening located below the first layer opening within the passivation layer, the opening size of the second photoresist before etching is L0 in the direction perpendicular to the direction from the substrate to the passivation layer, the opening size of the second photoresist after etching is L0 + M0 + M0', the size of the second layer opening is D0 in the direction from the substrate to the passivation layer, and the semiconductor layer is exposed at the second layer opening. This includes depositing a gate structure to form a gate portion and a field plate portion, completely filling the second layer opening hole with the gate portion, and covering the gate portion with the field plate portion to completely fill the first layer opening hole, In the direction from the gate portion to the field plate portion, the field plate portion includes at least two field plate sub-parts, and the gate portion and the field plate portion are divided into two parts by a first plane. In the two parts described above, in the plane where the bottom surface of the gate portion is located, M0 is the distance between the projection of the endpoint where the gate portion located on one side of the first plane is connected to the field plate sub portion adjacent to the gate portion and the projection of the endpoint where the bottom surface of the gate portion is connected to the first side surface of the gate portion; M0' is the distance between the projection of the endpoint where the gate portion located on the other side of the first plane is connected to the field plate sub portion adjacent to the gate portion and the projection of the endpoint where the bottom surface is connected to the first side surface; and M1 is the distance between the projection of the end point of the lower surface of the field plate sub portion located on one side of the first plane and adjacent to the gate portion and the projection of the end point of the lower surface of the field plate sub portion connected to the field plate sub portion adjacent to the gate portion. M1' is the distance between the projection of the end point of the lower surface of the field plate sub-part located on the other side of the first plane and adjacent to the gate portion, and the projection of the end point of the lower surface of the field plate sub-part connected to the field plate sub-part adjacent to the gate portion; L1 is the distance between the projection of the end point of the lower surface of the field plate sub-part located on one side of the first plane and adjacent to the gate portion, L1' is the distance between the projection of the end point of the lower surface of the field plate sub-part located on the other side of the first plane and adjacent to the gate portion, and L0 is the distance between the projection of the endpoint where the bottom surface located on one side of the first plane is connected to the first side surface, A method for manufacturing a semiconductor device, characterized in that, in each part, the upper surface of one field plate sub-part is a surface away from the gate part, the lower surface of one field plate sub-part is a surface close to the gate part, and on the same side surface of the same field plate sub-part, one tip point is an endpoint close to the first plane of the surface of the field plate sub-part, and the end point is an endpoint away from the first plane of the surface of the field plate sub-part.

12. A method for manufacturing a semiconductor device for manufacturing the semiconductor device described in claim 9, Forming a semiconductor layer on one side of the substrate, A passivation layer is formed on one side of the semiconductor layer that is away from the substrate, A first photoresist is applied to the passivation layer using a photoresist, the passivation layer is etched to form a first layer opening hole within the passivation layer, the opening size of the photoresist before etching is L0 in the direction perpendicular to the direction from the substrate to the passivation layer, the opening size of the photoresist after etching is L0 + M0 + M0', and the size of the first layer opening hole in the direction from the substrate to the passivation layer is D0. By selective etching, the photoresist after etching is spread, and in the direction perpendicular to the direction from the substrate to the passivation layer, the aperture size of the spread photoresist is L1 + L1' + L0 + M0 + M0', Using the expanded photoresist, a second photoresist is applied to the passivation layer based on the first layer opening, the passivation layer is etched to cause the first layer opening to descend overall in the direction of the substrate, a second layer opening is formed in the passivation layer above the first layer opening, the opening size of the expanded photoresist after etching is L1 + L1' + L0 + M0 + M0' + M1 + M1' in the direction perpendicular to the direction from the substrate to the passivation layer, the size of the second layer opening is D1 in the direction from the substrate to the passivation layer, and the semiconductor layer is exposed at the first layer opening. This includes depositing a gate structure to form a gate portion and a field plate portion, completely filling the first layer opening hole with the gate portion, and covering the gate portion with the field plate portion to completely fill the second layer opening hole, In the direction from the gate portion to the field plate portion, the field plate portion includes at least two field plate sub-portions, and the gate portion and the field plate portion are opened into two parts by a first plane. In the two parts described above, in the plane where the bottom surface of the gate portion is located, M0 is the distance between the projection of the endpoint where the gate portion located on one side of the first plane is connected to the field plate sub-portion adjacent to the gate portion and the projection of the endpoint where the bottom surface of the gate portion is connected to the first side surface of the gate portion; M0' is the distance between the projection of the endpoint where the gate portion located on the other side of the first plane is connected to the field plate sub-portion adjacent to the gate portion and the projection of the endpoint where the bottom surface is connected to the first side surface; and M1 is the distance between the projection of the end point of the lower surface of the field plate sub-portion located on one side of the first plane and adjacent to the gate portion and the projection of the front point of the lower surface of the field plate sub-portion connected to the field plate sub-portion adjacent to the gate portion. M1' is the distance between the projection of the end point of the lower surface of the field plate sub-part located on the other side of the first plane and adjacent to the gate portion, and the projection of the end point of the lower surface of the field plate sub-part connected to the field plate sub-part adjacent to the gate portion; L1 is the distance between the projection of the end point of the lower surface of the field plate sub-part located on one side of the first plane and adjacent to the gate portion, L1' is the distance between the projection of the end point of the lower surface of the field plate sub-part located on the other side of the first plane and adjacent to the gate portion, and L0 is the distance between the projection of the endpoint where the bottom surface located on one side of the first plane is connected to the first side surface, and the projection of the endpoint where the bottom surface located on the other side of the first plane is connected to the first side surface. A method for manufacturing a semiconductor device, characterized in that, in each part, the upper surface of one field plate sub-part is a surface away from the gate part, the lower surface of one field plate sub-part is a surface close to the gate part, and on the same side surface of the same field plate sub-part, one tip point is an endpoint close to the first plane of the surface of the field plate sub-part, and the end point is an endpoint away from the first plane of the surface of the field plate sub-part.

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