Transistor drive circuit

Abstract

To provide a transistor drive circuit capable of limiting driving force while suppressing an increase in a propagation delay time.SOLUTION: A transistor drive circuit according to an embodiment includes a driving force limiting circuit that maintains a gate potential of a driven transistor at a predetermined driving force limiting potential corresponding to a threshold voltage of the driven transistor when driving the driven transistor, and a delay time adjustment circuit that transitions the gate potential to the driving force limiting potential when the driving force limiting circuit operates.SELECTED DRAWING: Figure 2A

Description

Technical Field

[0001] This embodiment relates to a transistor drive circuit. on the road

Background Art

[0002] Conventionally, as a transistor drive circuit, a gate driver circuit for driving a power transistor is known. In the gate driver circuit, a configuration for adjusting the driving force has been adopted so as not to abruptly cause a state transition in the power transistor. That is, it was configured to increase the time for the gate capacitance of the transistor in the final stage of the gate driver circuit to transition to the threshold voltage.

[0003] Therefore, even before and after the driving force limit period, the charge flowing into the gate of the transistor in the final stage of the gate driver circuit is limited by the variable current source, so there is a problem that the time for raising the gate potential to the threshold voltage increases and the propagation delay time increases.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] Therefore, it has been desired to suppress the propagation delay time and improve the reliability of the transistor drive circuit. In view of the above problems, an object of the present invention is to provide a transistor drive circuit capable of performing driving force limitation while suppressing an increase in propagation delay time.

Means for Solving the Problems

[0006] The transistor drive circuit of the embodiment, when driving the driven transistor, sets the gate potential of the driven transistor to a predetermined driving force limiting potential corresponding to the threshold voltage of the driven transistor. Transition A driving force limiting circuit, and the gate potential when the driving force limiting circuit is operating The voltage is gradually transitioned from the driving force limiting potential to exceed the threshold voltage. It includes a delay time adjustment circuit, The delay time adjustment circuit includes a capacitor that stores a charge corresponding to the driving force limiting potential, a precharge switch that supplies charge from a power source to the capacitor or supplies charge from the capacitor to the power source prior to transitioning the gate potential to the driving force limiting potential, and a charge switch that electrically connects the capacitor to the gate of the driven transistor when transitioning the gate potential to the driving force limiting potential, and controls the period for supplying charge from the power source to the capacitor or the period for supplying charge from the capacitor to the power source based on a comparison result between the potential of the capacitor and a predetermined reference potential. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic block diagram of the transistor drive circuit of an embodiment. [Figure 2A] Figure 2A is an explanatory diagram of the first basic configuration of the embodiment. [Figure 2B] Figure 2B is an explanatory diagram of a modified example of the first basic configuration of the embodiment. [Figure 3] Figure 3 is a diagram illustrating the second basic configuration of the embodiment. [Figure 4] Figure 4 is a circuit diagram of the main components of the first embodiment. [Figure 5] Figure 5 is an explanatory diagram of an example configuration when the precharge switch is connected to the high-potential side power supply. [Figure 6] Figure 6 is an explanatory diagram of an example configuration when the precharge switch is connected to the low-potential side power supply. [Figure 7] Figure 7 is an explanatory diagram of an example configuration of a charge switch. [Figure 8] Figure 8 is an explanatory diagram of an example circuit configuration in which the precharge switch and charge switch are controlled by logic inversion using an inverter. [Figure 9] Figure 9 is an explanatory diagram of an example circuit configuration in which a non-overlap clock generation circuit generates positive logic drive control signals and negative logic drive control signals to control the precharge switch and charge switch. [Figure 10] Figure 10 is a schematic block diagram of an example configuration of a non-overlap clock generation circuit. [Figure 11] FIG. 11 is an explanatory diagram of an example of an output signal of a non-overlap clock generation circuit. [Figure 12] FIG. 12 is a circuit configuration diagram of a main part of another aspect of the first embodiment. [Figure 13A] FIG. 13A is a circuit configuration diagram of a main part of the second embodiment. [Figure 13B] FIG. 13B is a circuit configuration diagram of a main part of another aspect of the second embodiment. [Figure 14A] FIG. 14A is a circuit configuration diagram of a main part of the third embodiment. [Figure 14B] FIG. 14B is a circuit configuration diagram of a main part of another aspect of the third embodiment. [Figure 14C] FIG. 14C is a circuit configuration diagram of a main part of yet another aspect of the third embodiment. [Figure 15A] FIG. 15A is a circuit configuration diagram of a main part of the fourth embodiment. [Figure 15B] FIG. 15B is a circuit configuration diagram of a main part of another aspect of the fourth embodiment. [Figure 16] FIG. 16 is an explanatory diagram of the first modification of the embodiment. [Figure 17] FIG. 17 is an explanatory diagram of a first specific example when adjusting the time TD by the second method. [Figure 18] FIG. 18 is an explanatory diagram of a second specific example when adjusting the time TD by the second method. [Figure 19] FIG. 19 is an explanatory diagram for making the time TD variable from when the gate potential VG of the transistor to be controlled reaches 0 volts to the threshold voltage Vth. [Figure 20] FIG. 20 is an explanatory diagram of a third specific example when adjusting the time TD by the second method. [Figure 21] FIG. 21 is an explanatory diagram of a specific example when adjusting the time TD by the third method. [Figure 22] FIG. 22 is an explanatory diagram of a specific example when an element that is normally on and has a negative threshold voltage Vth is used as the controlled transistor and a MOSFET is used when the gate breakdown voltage is equal to the drain breakdown voltage. [Figure 23] Figure 23 is an explanatory diagram illustrating a specific example where a normally-on element is used as the controlled transistor, and the gate breakdown voltage is very low compared to the drain breakdown voltage. [Figure 24] Figure 24 is a schematic block diagram of the transistor drive circuit for the fourth modified example. [Figure 25] Figure 25 is a schematic block diagram of the transistor drive circuit for the fifth modified example. [Figure 26] Figure 26 is a schematic block diagram of a transistor drive circuit using a charge pump in the sixth modified example. [Figure 27] Figure 27 is a schematic block diagram of the transistor drive circuit using a charge pump in the seventh modified example. [Figure 28] Figure 28 is an explanatory diagram of the basic configuration of the fifth embodiment. [Figure 29] Figure 29 is an explanatory diagram (part 1) of the operation of the fifth embodiment. [Figure 30] Figure 30 is an explanatory diagram (part 2) of the operation of the fifth embodiment. [Figure 31] Figure 31 is an explanatory diagram of the basic configuration of the sixth embodiment. [Figure 32] Figure 32 is an explanatory diagram (part 1) of the operation of the sixth embodiment. [Figure 33] Figure 33 is an explanatory diagram (part 2) of the operation of the sixth embodiment. [Modes for carrying out the invention]

[0008] The transistor drive circuit according to the embodiment will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0009] Figure 1 is a schematic block diagram of the transistor drive circuit of an embodiment. The transistor drive circuit 10 includes a main circuit power supply VMAIN that supplies drive power, a high-potential gate drive circuit 11, a low-potential gate drive circuit 12, a high-potential switch SWH, a low-potential switch SWL, and an output terminal OUT. Here, the transistor drive circuit 10 exclusively switches the high-potential switch SWH and the low-potential switch SWL on and off, and outputs 0 volts and the voltage of the main circuit power supply VMAIN to the output terminal OUT with a desired duty cycle, thereby forming a switching circuit that outputs a desired output average voltage. In the actual circuit configuration, a predetermined low-pass filter composed of inductance and capacitance is provided at the output terminal OUT to configure the circuit to output a smoothed output average voltage.

[0010] In the above configuration, the main circuit power supply VMAIN is a power supply that can handle high voltage and high current, and is capable of supplying several watts to tens of kilowatts of power at a voltage of 100 volts to several kilovolts. The high-potential gate drive circuit 11 includes a first PWM power supply VPWMH, a first gate drive power supply VDrH, and a first gate driver IC 20. The first gate driver IC 20 is a high-side gate driver IC, and its source terminal is connected to the high-side output terminal of the first gate drive power supply VDrH, and its drain terminal is connected to the gate terminal of a power transistor that constitutes the high-side switch SWH. It also includes a P-channel MOS transistor 21, which forms a CMOS with the P-channel MOS transistor 21, and its drain terminal is connected to the gate terminal of a power transistor that constitutes the high-side switch SWH, and its source terminal is connected to the low-side output terminal of the first gate drive power supply VDrH. The input terminal is connected to the first PWM power supply VPW. The device includes a first level shift circuit 23 connected to the high-potential output terminal of MH, which shifts the voltage level and outputs it from the output terminal; a first variable amplifier 24 that variably amplifies the voltage level of the first level shift circuit 23 and outputs it to the gate terminal of the P-channel MOS transistor 21; a first delay time adjustment circuit 25 that adjusts the output delay time of the first variable amplifier 24; a first amplifier 26 that amplifies the voltage level of the first PWM power supply VPWMH and outputs it to the gate terminal of the N-channel MOS transistor 22; and a second delay time adjustment circuit 27 that adjusts the output delay time of the P-channel MOS transistor 21 or the N-channel MOS transistor 22.

[0011] The low-potential gate drive circuit 12 includes a second PWM power supply VPWML, a second gate drive power supply VDrL, and a second gate driver IC 30.

[0012] The second gate driver IC 30 is a low-side gate driver IC, and its source terminal is connected to the high-side output terminal of the second gate drive power supply VDrL, and its drain terminal is connected to the gate terminal of the power transistor that constitutes the low-side switch SWL, and it comprises a P-channel MOS transistor 31, which forms a CMOS with the P-channel MOS transistor 31, and its drain terminal is connected to the gate terminal of the power transistor that constitutes the low-side switch SWL, and its source terminal is connected to the low-side output terminal of the second gate drive power supply VDrL, and its input terminal is connected to the second PWM power supply VP The system includes a second level shift circuit 33 connected to the high-potential output terminal of the WML, which shifts the voltage level and outputs it from the output terminal; a second variable amplifier 34 that variably amplifies the voltage level of the second level shift circuit 33 and outputs it to the gate terminal of the P-channel MOS transistor 31; a third delay time adjustment circuit 35 that adjusts the output delay time of the variable amplifier 34; a second amplifier 36 that amplifies the voltage level of the second PWM power supply VPWML and outputs it to the gate terminal of the N-channel MOS transistor 32; and a fourth delay time adjustment circuit 37 that adjusts the output delay time of the P-channel MOS transistor 21 or the N-channel MOS transistor 22.

[0013] In the above configuration, the first gate drive power supply VDrH and the second gate drive power supply VDrL are so-called isolated power supplies and are configured as floating power supplies in which the low-potential side potential (VSS potential) fluctuates based on the potential of the source terminal of the high-potential side switch SWH or the low-potential side switch SWL.

[0014] Furthermore, the first PWM power supply VPWMH and the second PWM power supply VPWML are known as isolators, and they convert the input PWM signal referenced to ground into a signal referenced to the potential of the source terminal of the high-potential switch SWH or the low-potential switch SWL.

[0015] For example, the voltages of the first gate drive power supply VDrH and the second gate drive power supply VDrL are equal and set to 12 to 18 volts. Furthermore, the voltages of the first PWM power supply VPWMH and the second PWM power supply VPWML are equal and set to 5 to 18 volts.

[0016] Figure 2A is an explanatory diagram of the first basic configuration of the embodiment. In Figure 2A, the first variable amplifier 24 includes a P-channel MOS transistor 41 whose source terminal is connected to a high-potential power supply VDDC and whose drain terminal is connected to the gate terminal of a P-channel MOS transistor 21, to which the output signal VA of the first level shift circuit 23 is input; and an N-channel MOS transistor 42 whose drain terminal is connected to the gate terminal of a P-channel MOS transistor 21, whose source terminal is connected to a low-potential power supply VSSC, to which the output signal VA of the first level shift circuit 23 is input; and which has a variable driving force.

[0017] Furthermore, the first delay time adjustment circuit 25 includes a capacitor 51 with one end connected to a high-potential power supply VDDC, a precharge switch 52 with one end connected to the other end of the capacitor 51 and the other end connected to a low-potential power supply VSSD, and a charge switch 53 with one end connected to the other end of the capacitor 51 and the other end connected to the gate terminal of the P-channel MOS transistor 21.

[0018] In the above configuration, the precharge switch 52 is turned on for all or part of the period during which the output signal VA of the first level shift circuit 23 is at the "L" level. That is, it remains on until the capacitor 51 reaches a predetermined voltage.

[0019] Furthermore, the charge switch 53 remains ON for all or part of the period during which the output signal VA of the first level shift circuit 23 is at the "H" level. That is, it remains ON until the potential of the gate terminal of the P-channel MOS transistor 21 reaches a predetermined voltage (ideally, the threshold voltage of the P-channel MOS transistor 21).

[0020] Figure 2B is an explanatory diagram of a modified example of the first basic configuration of the embodiment. The modified version of the first basic configuration of the embodiment differs from the first basic configuration of the embodiment shown in Figure 2A in that it includes an N-channel MOS transistor 28 whose drain terminal is connected to the connection point between the drain terminal and output terminal OUTP of the P-channel MOS transistor 21, whose source terminal is connected to the low-potential side power supply VSSC, and whose gate terminal is connected to the gate terminal of the P-channel MOS transistor 21, and the other end of the precharge switch 52 is connected to the low-potential side power supply VSSC.

[0021] In the above configuration, the precharge switch 52 is turned on for all or part of the period during which the output signal VA of the first level shift circuit 23 is at the "L" level. That is, it remains on until the capacitor 51 reaches a predetermined voltage. In parallel with this, the N-channel MOS transistor 28 is turned on during the period when the output signal VA of the first level shift circuit 23 is at the "L" level, and the output terminal OUTP becomes the voltage of the low-potential power supply VSSC.

[0022] Furthermore, the charge switch 53 remains ON for all or part of the period during which the output signal VA of the first level shift circuit 23 is at the "H" level. That is, it remains ON until the potential of the gate terminal of the P-channel MOS transistor 21 reaches a predetermined voltage (ideally, the threshold voltage of the P-channel MOS transistor 21). In parallel with this, the N-channel MOS transistor 28 is turned off during the period when the output signal VA of the first level shift circuit 23 is at the "H" level, and the output terminal OUTP becomes the voltage of the high-potential power supply VDDC.

[0023] Next, we will explain the operation of the first basic configuration shown in Figure 2A. To transition the P-channel MOS transistor 21 from the off state (open state) to the on state (closed state), first, the output signal VA of the first level shift circuit 23 is set to the "H" level.

[0024] As a result, the P-channel MOS transistor 41 begins to transition to the off state (open state), and the N-channel MOS transistor 42 begins to transition to the on state (closed state). In this case, because the driving force of the N-channel MOS transistor 42 is limited, the gate potential of the P-channel MOS transistor 21 gradually transitions to the "L" level.

[0025] Therefore, the P-channel MOS transistor 21 will not abruptly transition to the ON state (closed state). Consequently, the subsequent power transistor will not abruptly transition to the ON state (closed state).

[0026] In parallel with the above operation, the charge switch 53 turns ON, and the charge stored in capacitor 51 is supplied to the gate terminal of P-channel MOS transistor 21. The potential of the gate terminal of P-channel MOS transistor 21 drops sharply, and due to the ratio of the capacitance of capacitor 51 to the capacitance of the gate terminal (gate capacitance), it naturally reaches a potential near the threshold voltage Vth of P-channel MOS transistor 21.

[0027] Next, when the output signal VA of the first level shift circuit 23 becomes "L" level, the P-channel MOS transistor 41 begins to transition to the ON state (closed state), and the N-channel MOS transistor 42 begins to transition to the OFF state (open state).

[0028] In parallel with this, the precharge switch 52 is turned ON, and the capacitor 51 is discharged by the high-potential power supply VDDC to the potential of the low-potential VSSD. Then, once the time required for the capacitor 51 to discharge has elapsed, the pre-charge switch 52 turns off.

[0029] Therefore, the period during which the gate potential VG of the P-channel MOS transistor 21 moves from 0 volts to a potential near the threshold voltage Vth is the high-speed drive period, and the period during which the driving force is to be limited is the period during which the driving force of the P-channel MOS transistor 21 is to be limited. )Therefore, the driving force can be controlled using a current source without the need for feedback control.

[0030] Next, we will explain the operation of a modified example of the first basic configuration shown in Figure 2B. To transition the P-channel MOS transistor 21 from the off state (open state) to the on state (closed state), first, the output signal VA of the first level shift circuit 23 is set to the "H" level.

[0031] As a result, the P-channel MOS transistor 41 begins to transition to the off state (open state), and the N-channel MOS transistor 42 begins to transition to the on state (closed state). In this case, because the driving force of the N-channel MOS transistor 42 is limited, the gate potential of the P-channel MOS transistor 21 gradually transitions to the "L" level. In parallel with this, the gate potential of the P-channel MOS transistor also gradually transitions to the "L" level.

[0032] Therefore, the P-channel MOS transistor 21 does not abruptly transition to the ON state (closed state), and the N-channel MOS transistor 28 does not abruptly transition to the OFF state. Consequently, the subsequent power transistors do not abruptly transition to the ON state (closed state).

[0033] In parallel with the above operation, the charge switch 53 turns ON, and the charge stored in the capacitor 51 is supplied to the gate terminal of the P-channel MOS transistor 21 and the gate terminal of the N-channel MOS transistor 28.

[0034] As a result, the potential at the gate terminal of the P-channel MOS transistor 21 drops sharply, and due to the ratio of the capacitance of capacitor 51 to the capacitance of the gate terminal (gate capacitance), the potential naturally becomes close to the threshold voltage Vth of the P-channel MOS transistor 21. Similarly, the potential at the gate terminal of the N-channel MOS transistor drops sharply, and due to the ratio of the capacitance of capacitor 51 to the capacitance of the gate terminal (gate capacitance), it naturally becomes a potential near the threshold voltage Vth of the N-channel MOS transistor 28.

[0035] Next, when the output signal VA of the first level shift circuit 23 becomes "L" level, the P-channel MOS transistor 41 begins to transition to the ON state (closed state), and the N-channel MOS transistor 42 begins to transition to the OFF state (open state).

[0036] In parallel with this, the precharge switch 52 is turned ON, and the capacitor 51 is discharged by the high-potential power supply VDDC to the potential of the low-potential VSSC. Then, once the time required for the capacitor 51 to discharge has elapsed, the pre-charge switch 52 turns off. Furthermore, since the P-channel MOS transistor 41 has no limit on driving force, the gate potential of the N-channel MOS transistor 28 immediately exceeds the threshold voltage Vth, and the level of the output terminal OUTP becomes the potential level of the low-potential power supply VSSC.

[0037] Therefore, even with the modified version of the first basic configuration shown in Figure 2B, the period from when the gate potential VG of the P-channel MOS transistor 21 is 0 volts to when it is near the threshold voltage Vth becomes a high-speed drive, and the drive force can be controlled by the current source without feedback control during the period when the drive force of the P-channel MOS transistor 21 is to be limited.

[0038] Figure 3 is a diagram illustrating the second basic configuration of the embodiment. In Figure 3, the first variable amplifier 24 includes a P-channel MOS transistor 61 with a variable driving force, the source terminal of which is connected to the high-potential power supply VDDA and the drain terminal of which is connected to the gate terminal of an N-channel MOS transistor 22, and the output signal VB of the first PWM power supply VPWMH is input to the gate terminal, and an N-channel MOS transistor 62 with a drain terminal of which is connected to the gate terminal of an N-channel MOS transistor 22 and the source terminal of which is connected to the low-potential power supply VSSA, and the output signal VB of the first PWM power supply VPWMH is input to the gate terminal.

[0039] Furthermore, the first delay time adjustment circuit 25 includes a capacitor 71 with one end connected to a low-potential power supply VSSA, a precharge switch 72 with one end connected to the other end of the capacitor 71 and the other end connected to a high-potential power supply VDDB, and a charge switch 73 with one end connected to the other end of the capacitor 71 and the other end connected to the gate terminal of the N-channel MOS transistor 22.

[0040] In the above configuration, the precharge switch 72 is turned on for all or part of the period during which the output signal VB of the first PWM power supply VPWMH is at the "H" level. That is, it remains on until the capacitor 51 reaches a predetermined voltage.

[0041] Furthermore, the charge switch 73 remains ON for all or part of the period during which the output signal VB of the first PWM power supply VPWMH is at the "L" level. That is, it remains ON until the potential of the gate terminal of the N-channel MOS transistor 22 reaches a predetermined voltage (ideally, the threshold voltage of the N-channel MOS transistor 22).

[0042] Next, we will explain the operation of the second basic configuration. To transition the N-channel MOS transistor 22 from the off state (open state) to the on state (closed state), first, the output signal VB of the first PWM power supply VPWMH is set to the "L" level.

[0043] As a result, the N-channel MOS transistor 62 begins to transition to the off state (open state), and the P-channel MOS transistor 61 begins to transition to the on state (closed state). In this case, because the driving force of the P-channel MOS transistor 61 is limited, the gate potential of the N-channel MOS transistor 22 gradually transitions to the "H" level.

[0044] Therefore, the N-channel MOS transistor 22 will not abruptly transition to the ON state (closed state). Consequently, the subsequent power transistor will not abruptly transition to the ON state (closed state).

[0045] In parallel with the above operation, the charge switch 73 turns ON, and the charge stored in capacitor 71 is supplied to the gate terminal of N-channel MOS transistor 22. The potential of the gate terminal of N-channel MOS transistor 22 rises rapidly, and due to the ratio of the capacitance of capacitor 71 to the capacitance of the gate terminal (gate capacitance), the potential naturally becomes close to the threshold voltage Vth of N-channel MOS transistor 22.

[0046] Next, when the output signal VB of the first PWM power supply VPWMH reaches the "H" level, the P-channel MOS transistor 61 begins to transition to the off state (open state), and the N-channel MOS transistor 62 begins to transition to the on state (closed state).

[0047] Simultaneously, since the output signal VB is at the "H" level, the precharge switch 72 is turned ON, and the capacitor 71 is charged by the high-potential power supply VDDC to the potential of the high-potential power supply VDDB. Once the time required for the capacitor 71 to fully charge has elapsed, the precharge switch 72 is turned OFF.

[0048] Therefore, the period during which the gate potential VG of the N-channel MOS transistor 22 moves from 0 volts to a potential near the threshold voltage Vth is high-speed drive, and the drive force can be controlled by the current source without feedback control during the period during which the drive force of the N-channel MOS transistor 22 needs to be limited.

[0049] Next, a more specific embodiment will be described. In the following explanation, for ease of understanding, an embodiment corresponding to the second basic configuration described above will be described. However, in actual circuits, the first basic configuration, in which the driven object is a P-channel MOS transistor and the carriers involved in the charge transfer described above are holes, is technically more effective.

[0050] [1] First Embodiment Figure 4 is a circuit diagram of the main components of the first embodiment. In Figure 4, the same reference numerals are used for parts that are the same as those in the second basic configuration diagram in Figure 3, and their detailed explanations are provided by referring to Figure 3. The difference between the configuration of the first embodiment and the second basic configuration is that, instead of the variable-drive P-channel MOS transistor 61, it includes a first P-channel MOS transistor 81 that functions as a variable current source to which a control signal Vvar is input to the gate terminal and which can supply a current corresponding to the control signal Vvar, and a second P-channel MOS transistor 82 connected in series with the first P-channel MOS transistor 81.

[0051] First, before describing the first embodiment, we will explain the specific configurations of the pre-charge switch 72 and the charge switch 73. The configuration of the precharge switch 72 differs depending on whether it is connected to the high-potential power supply or the low-potential power supply.

[0052] Figure 5 is an explanatory diagram of an example configuration when the precharge switch is connected to the high-potential side power supply. When the precharge switch 72 is connected to a high-potential power supply, it is configured as shown in Figure 5, comprising, for example, an inverter 72A to which a drive control signal (in this example, the output signal VB of the first PWM power supply VPWMH) is connected as an input terminal, and a P-channel MOS transistor 72B whose gate terminal is connected as an output terminal of the inverter.

[0053] Figure 6 is an explanatory diagram of an example configuration when the precharge switch is connected to the low-potential side power supply.

[0054] When the precharge switch 72 is connected to a low-potential power supply, it is configured, as shown in Figure 6, to include, for example, an N-channel MOS transistor 72C to which a drive control signal is input at its gate terminal.

[0055] The above configuration is such that the precharge switch 72 is ON when the drive control signal is at the "H" level, and OFF when the drive control signal is at the "L" level.

[0056] On the other hand, since the charge switch 73 operates in a floating state, it is generally configured as a complementary switch.

[0057] Figure 7 is an explanatory diagram of an example configuration of a charge switch. As shown in Figure 7, the charge switch 73 is configured to include, for example, an inverter 73A to which a drive control signal (in this example, the logic inverted signal of the output signal VB of the first PWM power supply VPWMH) is connected to the input terminal, a P-channel MOS transistor 73B whose gate terminal is connected to the output terminal of inverter 73A, and an N-channel MOS transistor 73C to which the drive control signal is input to the gate terminal, whose source terminal is connected to the drain terminal of the P-channel MOS transistor 73B, and whose drain terminal is connected to the source terminal of the P-channel MOS transistor 73B.

[0058] The above configuration is such that the charge switch 73 is ON when the drive control signal is at the "H" level, and OFF when the drive control signal is at the "L" level.

[0059] Here, we will explain the control of the pre-charge switch 72 and the charge switch 73. In this embodiment, the pre-charge switch 72 and the charge switch 73 are ideally switched on and off exclusively so that they do not become ON at the same time.

[0060] Therefore, one possible method is to simply invert the drive control signal (in this example, the output signal VB of the first PWM power supply VPWMH) using an inverter to control the precharge switch 72 and the charge switch 73.

[0061] Figure 8 is an explanatory diagram of an example circuit configuration in which the precharge switch and charge switch are controlled by logic inversion using an inverter. In Figure 8, parts similar to those in the first embodiment of Figure 4 are denoted by the same reference numerals, and their detailed descriptions are provided by reference to Figure 4.

[0062] In the example shown in Figure 8, the output signal VB of the first PWM power supply VPWMH is input as the drive control signal for the precharge switch 72. Furthermore, the output signal VB of the first PWM power supply VPWMH is inverted via the inverter 74 and input as the drive control signal for the charge switch 73.

[0063] While this configuration simplifies the circuit design, depending on the configuration of the precharge switch 72 and the charge switch 73, an overlap may occur where the precharge switch 72 and the charge switch 73 are simultaneously on (closed), potentially causing a malfunction. Therefore, it is not suitable for applications requiring high reliability.

[0064] A second method involves using a so-called non-overlap clock generation circuit to generate positive logic drive control signals and negative logic drive control signals based on a drive control signal (in this example, the output signal VB of the first PWM power supply VPWMH) to control the precharge switch 72 and the charge switch 73.

[0065] Figure 9 is an explanatory diagram of an example circuit configuration in which a non-overlap clock generation circuit generates positive logic drive control signals and negative logic drive control signals to control the precharge switch and charge switch. In Figure 9, parts similar to those in the first embodiment of Figure 4 are denoted by the same reference numerals, and their detailed descriptions are provided by reference to the Figure 4 description.

[0066] In the example shown in Figure 9, the output signal VB of the first PWM power supply VPWMH is input as the input to the non-overlap clock generation circuit.

[0067] Figure 10 is a schematic block diagram of an example configuration of a non-overlap clock generation circuit. The non-overlap clock generation circuit 75 includes a first NOR circuit 75A which receives an input clock signal φ (rectangular pulse signal) at one input terminal and a second delayed clock signal dφ2 at the other input terminal, and outputs a first clock signal φ1 from the output terminal by taking the negation of the logical OR of the input clock signal φ and the second delayed clock signal dφ2; a first delay circuit 75B which receives the first clock signal φ1 at the input terminal, delays the first clock signal φ1 for a predetermined time, and outputs a first delayed clock signal dφ1 from the output terminal; and the input clock signal φ is input The device includes an inverter 75C that receives input to a terminal and inverts the input clock signal φ to output an inverted input clock signal / φ; a second NOR circuit 75D that receives a first delayed clock signal dφ1 to one input terminal and an inverted input clock signal / φ to the other input terminal, and outputs a second clock signal φ2 from the output terminal by taking the negation of the logical OR of the first delayed clock signal dφ1 and the inverted input clock signal / φ; and a second delay circuit 75E that delays the second clock signal φ2 for a predetermined time and outputs a second delayed clock signal dφ2 from the output terminal.

[0068] In the above configuration, the phase of the input clock signal φ, the phase of the second clock signal φ2, the phase of the inverted input clock signal / φ, and the phase of the first clock signal φ1 are all in the same phase.

[0069] Figure 11 is an explanatory diagram illustrating an example of the output signal of a non-overlap clock generation circuit. As shown in Figure 11, the first clock signal φ1 and the second clock signal φ2 are set to the "H" level without overlapping every 1 / 2 period (=T / 2).

[0070] Although this configuration complicates the circuit, it allows for reliable operation because it prevents overlap between the pre-charge switch 72 and the charge switch 73, regardless of their configuration, preventing them from being simultaneously on (closed).

[0071] Next, the operation of the first embodiment will be described. When the output signal VB of the first PWM power supply VPWMH reaches the "H" level, the precharge switch 72 turns ON, and the capacitor 71 is charged by the high-potential power supply VDDA to the potential of the high-potential power supply VDDA (or a desired potential).

[0072] Then, once the time required for capacitor 71 to fully charge has elapsed, the pre-charge switch 72 turns off. At this time, the N-channel MOS transistor 62 is in the ON state (closed state) because an "H" level is applied to its gate terminal. Consequently, the gate terminal of the N-channel MOS transistor 22 is at an "L" level, and the N-channel MOS transistor 22 is in the OFF state (open state).

[0073] Next, in order to transition the N-channel MOS transistor 22 from the off state (open state) to the on state (closed state), the output signal VB of the first PWM power supply VPWMH is set to the "L" level.

[0074] As a result, the second P-channel MOS transistor 82 begins to transition to the ON state (closed / open state), and the N-channel MOS transistor 62 begins to transition to the OFF state (open state).

[0075] In this case, a first P-channel MOS transistor 81, which functions as a variable current source, is provided between the P-channel MOS transistor 82 and the high-potential power supply VDDA. Charge movement is restricted, meaning that the first P-channel MOS transistor 81 and the second P-channel MOS transistor 83 effectively function similarly to a P-channel MOS transistor 61 with variable driving force, and the driving force is restricted, causing the gate potential of the N-channel MOS transistor 22 to gradually transition to the "H" level.

[0076] Therefore, the N-channel MOS transistor 22 does not abruptly transition to the ON state (closed state). Consequently, the subsequent power transistor does not abruptly transition to the ON state (closed state), and no through-current flows, so power consumption does not become unnecessarily high.

[0077] Then, as the output signal VB of the first PWM power supply VPWMH becomes "L" level, the N-channel MOS transistor 62 begins to transition to the off state (open state) in parallel with the above operation.

[0078] Furthermore, the charge switch 73 turns ON, and the charge stored in capacitor 71 moves to the gate terminal of N-channel MOS transistor 22. The potential at the gate terminal of N-channel MOS transistor 22 rises rapidly, and due to the ratio of the capacitance of capacitor 71 to the capacitance of the gate terminal (gate capacitance), it naturally reaches a potential near the threshold voltage Vth of N-channel MOS transistor 22.

[0079] Therefore, while shortening the period during which the gate potential VG of the N-channel MOS transistor 22 moves from 0 volts to a potential near the threshold voltage Vth, the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 22 is to be limited).

[0080] As a result of these findings, according to this first embodiment, it is possible to shorten the period during which the gate potential VG of the N-channel MOS transistor 22, which is the target of the drive, rises from 0 volts to a voltage near the threshold voltage Vth, while simultaneously limiting the driving force of the N-channel MOS transistor thereafter.

[0081] [1.1] Other embodiments of the first embodiment Figure 12 is a circuit diagram of the main components of another embodiment of the first embodiment. In Figure 12, the same reference numerals are used for parts that are the same as those in the first embodiment in Figure 4, and their detailed descriptions are provided by reference to the Figure 4 description. Another aspect of the first embodiment shown in Figure 12 differs from the first embodiment shown in Figure 4 in that, instead of the charge switch 73, it includes a charge switch 73A, one end of which is connected to the other end (high potential side) of the capacitor 71, and the other end of which is connected to the connection point between the drain terminal of the first P-channel MOS transistor 81 and the source terminal of the second P-channel MOS transistor 82.

[0082] Next, the operation of other embodiments of the first embodiment will be described. In this case, the operation and effects of the first level shift circuit 23 until the output signal VA becomes "L" level are the same as in the first embodiment, so the operation after the output signal VA becomes "L" level will be described.

[0083] Then, as the output signal VA of the first level shift circuit 23 becomes "L" level, the N-channel MOS transistor 62 begins to transition to the off state (open state) in parallel with the above operation.

[0084] Furthermore, the charge switch 73A is turned ON, and the charge stored in capacitor 71 moves to the gate terminal of N-channel MOS transistor 22 via the source and drain terminals of the second P-channel MOS transistor 82. The potential of the gate terminal of N-channel MOS transistor 22 rises rapidly and, due to the ratio of the capacitance of capacitor 71 to the capacitance of the gate terminal (gate capacitance), naturally reaches a potential near the threshold voltage Vth of N-channel MOS transistor 22.

[0085] Therefore, while shortening the period during which the gate potential VG of the N-channel MOS transistor 22 is at a potential near 0 volts to the threshold voltage Vth, the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 22 is to be limited).

[0086] As described above, other aspects of this first embodiment can be obtained to achieve the same effects as those of the first embodiment.

[0087] [2] Second embodiment Figure 13A is a circuit diagram of the main components of the second embodiment. In Figure 13A, the same reference numerals are used for parts that are the same as those in the second basic configuration diagram in Figure 3, and their detailed explanations are provided by referring to Figure 3.

[0088] The configuration of the second embodiment differs from the second basic configuration in that, instead of the variable-drive P-channel MOS transistor 61, it includes a first P-channel MOS transistor 85 with a constant drive force, a second P-channel MOS transistor 86 whose source terminal is connected to the drain terminal of the first P-channel MOS transistor 85 and which functions as a variable current source, and a third P-channel MOS transistor 87 whose source terminal is connected to the drain terminal of the second P-channel MOS transistor 86, whose drain terminal is connected to the drain terminal of the N-channel MOS transistor 62, and whose gate terminal is connected to the low-potential side power supply VSSA.

[0089] In this case, the third P-channel MOS transistor 87 is provided to improve reliability by increasing the drain breakdown voltage, and is not necessarily required.

[0090] Next, the operation of the second embodiment will be described. When the output signal VB of the first PWM power supply VPWMH reaches the "H" level, the precharge switch 72 turns ON, and the capacitor 71 is charged by the high-potential power supply VDDA to the potential of the high-potential power supply VDDA (or a desired potential).

[0091] Then, once the time required for capacitor 71 to fully charge has elapsed, the pre-charge switch 72 turns off. At this time, the N-channel MOS transistor 62 is in the ON state (closed state) because an "H" level is applied to its gate terminal. Consequently, the gate terminal of the N-channel MOS transistor 22 is at an "L" level, and the N-channel MOS transistor 22 is in the OFF state (open state).

[0092] Next, in order to transition the N-channel MOS transistor 22 from the off state (open state) to the on state (closed state), the output signal VB of the first PWM power supply VPWMH is set to the "L" level. As a result, the first P-channel MOS transistor 85 begins to transition to the ON state (closed state), and the N-channel MOS transistor 62 begins to transition to the OFF state (open state).

[0093] In this case, a second P-channel MOS transistor 86, which functions as a variable current source, is provided between the first P-channel MOS transistor 85 and the third P-channel MOS transistor 87. This restricts charge movement, meaning that the first P-channel MOS transistor 85 and the second P-channel MOS transistor 86 effectively function similarly to a P-channel MOS transistor 61 with variable driving force. With the driving force restricted, the gate potential of the N-channel MOS transistor 22 gradually transitions to the "H" level.

[0094] Therefore, the N-channel MOS transistor 22 does not transition abruptly to the ON state (closed state). Consequently, the subsequent power transistor does not transition abruptly, and no through-current flows, so power consumption does not become unnecessarily high.

[0095] Then, as the output signal VB of the first PWM power supply VPWMH becomes "L" level, the N-channel MOS transistor 62 begins to transition to the off state (open state) in parallel with the above operation.

[0096] Furthermore, the charge switch 73 turns ON, and the charge stored in capacitor 71 moves to the gate terminal of N-channel MOS transistor 22. The potential at the gate terminal of N-channel MOS transistor 22 rises rapidly, and due to the ratio of the capacitance of capacitor 71 to the capacitance of the gate terminal (gate capacitance), it naturally reaches a potential near the threshold voltage Vth of N-channel MOS transistor 22.

[0097] Therefore, while shortening the period during which the gate potential VG of the N-channel MOS transistor 22 moves from 0 volts to a potential near the threshold voltage Vth, the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 22 is to be limited). As a result, according to this second embodiment, in addition to the effects of the first embodiment, the drain pressure resistance can be improved and reliability can be enhanced.

[0098] [2.1] Other aspects of the second embodiment Figure 13B is a diagram showing the main circuit configuration of another embodiment of the second embodiment. In Figure 13B, the same reference numerals are used for parts that are the same as those in the second embodiment of Figure 13A, and their detailed descriptions are provided by reference to Figure 13B. Another aspect of the second embodiment shown in Figure 13B differs from the second embodiment shown in Figure 13A in that, instead of the charge switch 73, one end is connected to the other end (high potential side) of the capacitor 71, and the other end is The device is equipped with a charge switch 73A connected to the connection point between the drain terminal of the second P-channel MOS transistor 86 and the source terminal of the third P-channel MOS transistor 87.

[0099] Next, the operation of other embodiments of the second embodiment will be described. In this case, the operation and effects until the output signal VB of the first PWM power supply VVPWMH reaches the "L" level are the same as in the second embodiment. Therefore, the operation after the output signal VA of the first PWM power supply VVPWMH reaches the "L" level will be described.

[0100] Then, as the output signal VB of the first PWM power supply VPWMH becomes "L" level, the N-channel MOS transistor 62 begins to transition to the off state (open state) in parallel with the above operation.

[0101] Furthermore, the charge switch 73A turns ON, and the charge stored in capacitor 71 moves to the gate terminal of N-channel MOS transistor 22 via the source and drain terminals of the third P-channel MOS transistor 87. The potential of the gate terminal of N-channel MOS transistor 22 rises rapidly and, due to the ratio of the capacitance of capacitor 71 to the capacitance of the gate terminal (gate capacitance), naturally reaches a potential near the threshold voltage Vth of N-channel MOS transistor 22.

[0102] Therefore, while shortening the period during which the gate potential VG of the N-channel MOS transistor 22 is at a potential near 0 volts to the threshold voltage Vth, the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 22 is to be limited).

[0103] As described above, according to other aspects of this second embodiment, in addition to the effects of the first embodiment, similar to the effects of the second embodiment, reliability can be improved by improving the drain withstand pressure.

[0104] [3] Third embodiment Figure 14A is a diagram showing the main circuit configuration of the third embodiment. In Figure 14A, the same reference numerals are used for parts that are the same as those in the second basic configuration diagram in Figure 3, and their detailed explanations are provided by referring to Figure 3. The configuration of the third embodiment differs from the second basic configuration in that, instead of the variable-drive P-channel MOS transistor 61, it includes a first P-channel MOS transistor 91 that functions as a variable current source, a second P-channel MOS transistor 92 connected in series with the first P-channel MOS transistor 91, and a third P-channel MOS transistor 93 connected in series with the second P-channel MOS transistor 92, with its source terminal connected to the drain terminal of the N-channel MOS transistor 62 and its gate terminal connected to the low-potential power supply VSSA.

[0105] In this case, the third P-channel MOS transistor 93 is provided to improve reliability by increasing the drain breakdown voltage, and is not necessarily required.

[0106] Next, the operation of the third embodiment will be described. When the output signal VB of the first PWM power supply VPWMH reaches the "H" level, the precharge switch 72 turns ON, and the capacitor 71 is charged by the high-potential power supply VDDA to the potential of the high-potential power supply VDDA (or a desired potential).

[0107] Then, once the time required for capacitor 71 to fully charge has elapsed, the pre-charge switch 72 turns off.

[0108] At this time, the N-channel MOS transistor 62 is in the ON state (closed state) because an "H" level is applied to its gate terminal. Consequently, the gate terminal of the N-channel MOS transistor 22 is at an "L" level, and the N-channel MOS transistor 22 is in the OFF state (open state).

[0109] Next, in order to transition the N-channel MOS transistor 22 from the off state (open state) to the on state (closed state), the output signal VB of the first PWM power supply VPWMH is set to the "L" level. As a result, the second P-channel MOS transistor 92 begins to transition to the ON state (closed / open state), and the N-channel MOS transistor 62 begins to transition to the OFF state (open state).

[0110] In this case, a first P-channel MOS transistor 91, which functions as a variable current source, is provided between the high-potential power supply VDDA and the second P-channel MOS transistor 92, thereby restricting charge movement.

[0111] In other words, the first P-channel MOS transistor 91 and the second P-channel MOS transistor 92 effectively function similarly to a P-channel MOS transistor 61 with variable driving force, and with the driving force limited, the gate potential of the N-channel MOS transistor 22 gradually transitions to the "H" level.

[0112] As a result, the N-channel MOS transistor 22 does not transition abruptly to the ON state (closed state). Consequently, the power transistors downstream of the N-channel MOS transistor 22 do not transition abruptly, the two power transistors constituting the upper arm and lower arm do not turn ON (close) simultaneously, and no through-current flows, thus preventing unnecessary increases in power consumption.

[0113] Then, as the output signal VB of the first PWM power supply VPWMH becomes "L" level, the N-channel MOS transistor 62 begins to transition to the off state (open state) in parallel with the above operation.

[0114] Furthermore, the charge switch 73 turns ON, and the charge stored in capacitor 71 moves to the gate terminal of N-channel MOS transistor 22. The potential at the gate terminal of N-channel MOS transistor 22 rises rapidly, and due to the ratio of the capacitance of capacitor 71 to the capacitance of the gate terminal (gate capacitance), it naturally reaches a potential near the threshold voltage Vth of N-channel MOS transistor 22.

[0115] Therefore, while shortening the period during which the gate potential VG of the N-channel MOS transistor 22 is at a potential near 0 volts to the threshold voltage Vth, the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 22 is to be limited). As described above, the third embodiment provides the same effects as the second embodiment. [3.1] Other aspects of the third embodiment Figure 14B is a diagram showing the main circuit configuration of another embodiment of the third embodiment. In Figure 14B, the same reference numerals are used for parts that are the same as those in the third embodiment of Figure 14A, and their detailed descriptions are provided by reference to Figure 14B. Another aspect of the third embodiment shown in Figure 14B differs from the third embodiment shown in Figure 14A in that, instead of the charge switch 73, it is equipped with a charge switch 73B, one end of which is connected to the other end (high potential side) of the capacitor 71, and the other end of which is connected to the connection point between the drain terminal of the second P-channel MOS transistor 92 and the source terminal of the third P-channel MOS transistor 93.

[0116] Next, the operation of other embodiments of the third embodiment will be described. In this case, the operation and effects until the output signal VB of the first PWM power supply VVPWMH reaches the "L" level are the same as in the third embodiment. Therefore, the operation after the output signal VB of the first PWM power supply VVPWMH reaches the "L" level will be described.

[0117] Then, as the output signal VB of the first PWM power supply VPWMH becomes "L" level, the N-channel MOS transistor 62 begins to transition to the off state (open state) in parallel with the above operation.

[0118] Furthermore, the charge switch 73B turns ON, and the charge stored in capacitor 71 moves to the gate terminal of N-channel MOS transistor 22 via the source and drain terminals of the third P-channel MOS transistor 93. The potential of the gate terminal of N-channel MOS transistor 22 rises rapidly and, due to the ratio of the capacitance of capacitor 71 to the capacitance of the gate terminal (gate capacitance), naturally reaches a potential near the threshold voltage Vth of N-channel MOS transistor 22.

[0119] Therefore, while shortening the period during which the gate potential VG of the N-channel MOS transistor 22 is at a potential near 0 volts to the threshold voltage Vth, the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 22 is to be limited). As described above, according to other aspects of this third embodiment, the same effects as those of the second embodiment can be obtained as with the third embodiment.

[0120] [3.2] Further aspects of the third embodiment Figure 14C is a diagram showing the main circuit configuration of yet another embodiment of the third embodiment. In Figure 14C, the same reference numerals are used for parts that are the same as those in the third embodiment of Figure 14A, and their detailed descriptions are provided by reference to Figure 14C. Another aspect of the third embodiment shown in Figure 14C differs from the third embodiment shown in Figure 14A in that it includes a charge switch 73C instead of the charge switch 73, with one end connected to the other end (high potential side) of the capacitor 71 and the other end connected to the connection point between the drain terminal of the first P-channel MOS transistor 91 and the source terminal of the second P-channel MOS transistor 92. In this case, the operation and effects until the output signal VB of the first PWM power supply VVPWMH reaches the "L" level are the same as in the third embodiment. Therefore, the operation after the output signal VB of the first PWM power supply VVPWMH reaches the "L" level will be described.

[0121] As the output signal VB of the first PWM power supply VPWMH becomes "L" level, the N-channel MOS transistor 62 begins to transition to the off state (open state) in parallel with the above operation.

[0122] Furthermore, the charge switch 73C is turned ON, and the charge stored in capacitor 71 moves to the gate terminal of N-channel MOS transistor 22 via the source and drain terminals of the second P-channel MOS transistor 92 and the source and drain terminals of the third P-channel MOS transistor 93. The potential of the gate terminal of N-channel MOS transistor 22 rises rapidly and, due to the ratio of the capacitance of capacitor 71 to the capacitance of the gate terminal (gate capacitance), naturally reaches a potential near the threshold voltage Vth of N-channel MOS transistor 22.

[0123] Therefore, while shortening the period during which the gate potential VG of the N-channel MOS transistor 22 is at a potential near 0 volts to the threshold voltage Vth, the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 22 is to be limited). As described above, according to yet another aspect of this third embodiment, the same effects as those of the second embodiment can be obtained as with the third embodiment.

[0124] [4] Fourth Embodiment Figure 15A is a diagram showing the main circuit configuration of the fourth embodiment. In Figure 15A, the same reference numerals are used for parts that are the same as those in the second basic configuration diagram in Figure 3, and their detailed explanations are to be found therein.

[0125] The fourth embodiment differs from the second basic configuration in that, instead of the variable-drive P-channel MOS transistor 61, it includes a first P-channel MOS transistor 95 that functions as a switchable variable current source, with either a high-potential power supply VDDA or a low-potential power supply VSSA switchably connected to its gate terminal; a second P-channel MOS transistor 96 that functions as a switchable variable current source, with either a high-potential power supply VDDA or a low-potential power supply VSSA switchably connected to its gate terminal; and a third P-channel MOS transistor 97 whose source terminal is connected to the drain terminals of the first P-channel MOS transistor 95 and the drain terminal of the second P-channel MOS transistor 96, whose drain terminal is connected to the drain terminal of the N-channel MOS transistor 62, and whose gate terminal is input to the output signal VB of the first PWM power supply VPWMH.

[0126] In the above explanation, a second P-channel MOS transistor 96 was provided in parallel with the first P-channel MOS transistor 95, which functions as a switchable variable current source. However, it is also possible to use a configuration in which three or more P-channel MOS transistors (at least one of which functions as a variable current source) are connected in parallel. This configuration allows for limiting charge transfer in more stages and enables more precise control of the driving force limit.

[0127] Next, the operation of the fourth embodiment will be described. In this case, when the output signal VB of the first PWM power supply VPWMH reaches the "H" level, the precharge switch 72 turns ON, and the capacitor 71 is charged by the high-potential power supply VDDA to the potential of the high-potential power supply VDDA (or a desired potential). Then, once the time required for capacitor 71 to fully charge has elapsed, the pre-charge switch 72 turns off.

[0128] At this time, the N-channel MOS transistor 62 is in the ON state (closed state) because an "H" level is applied to its gate terminal. Consequently, the gate terminal of the N-channel MOS transistor 22 is at an "L" level, and the N-channel MOS transistor 22 is in the OFF state (open state).

[0129] Next, in order to transition the N-channel MOS transistor 22 from the off state (open state) to the on state (closed state), the output signal VB of the first PWM power supply VPWMH is set to the "L" level. As a result, the second P-channel MOS transistor 96 begins to transition to the ON state (closed state), and the N-channel MOS transistor 62 begins to transition to the OFF state (open state).

[0130] In this case, a first P-channel MOS transistor 95 and a second P-channel MOS transistor 96, which function as switchable variable current sources, are provided between the high-potential power supply VDDA and the third P-channel MOS transistor 97. When the high-potential power supply VDDA is connected to the gate terminal of either the first P-channel MOS transistor 95 or the second P-channel MOS transistor 96, and the gate terminal is at the "H" level, the P-channel MOS transistor is in an off state (open state). Therefore, the movement of charge is restricted compared to the normal operating state in which both the first P-channel MOS transistor 95 and the second P-channel MOS transistor 96 are in an on state (closed state).

[0131] In other words, either the first P-channel MOS transistor 95 or the second P-channel MOS transistor 92, along with the third P-channel MOS transistor 97, effectively function in the same way as the P-channel MOS transistor 61 with variable driving force. As a result, the driving force is limited, and the gate potential of the N-channel MOS transistor 22 gradually transitions to the "H" level.

[0132] As a result, the N-channel MOS transistor 22 does not transition abruptly to the ON state (closed state). Consequently, the power transistors downstream of the N-channel MOS transistor 22 do not transition abruptly, the two power transistors constituting the upper arm and lower arm do not turn ON (close) simultaneously, and no through-current flows, thus preventing unnecessary increases in power consumption.

[0133] Then, as the output signal VB of the first PWM power supply VPWMH becomes "L" level, the N-channel MOS transistor 62 begins to transition to the off state (open state) in parallel with the above operation.

[0134] Furthermore, the charge switch 73 turns ON, and the charge stored in capacitor 71 moves to the gate terminal of N-channel MOS transistor 22. The potential at the gate terminal of N-channel MOS transistor 22 rises rapidly, and due to the ratio of the capacitance of capacitor 71 to the capacitance of the gate terminal (gate capacitance), it naturally reaches a potential near the threshold voltage Vth of N-channel MOS transistor 22.

[0135] Therefore, while shortening the period during which the gate potential VG of the N-channel MOS transistor 22 moves from 0 volts to a potential near the threshold voltage Vth, the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 22 is to be limited). As described above, the same effects as those of the first embodiment can be obtained with this fourth embodiment.

[0136] [4.1] Other aspects of the fourth embodiment Figure 15B is a diagram showing the main circuit configuration of another embodiment of the fourth embodiment. In Figure 15B, the same reference numerals are used for parts that are the same as those in the fourth embodiment of Figure 15A, and their detailed descriptions are provided by reference to Figure 15B. Another aspect of the fourth embodiment shown in Figure 15B differs from the fourth embodiment shown in Figure 15A in that it includes a charge switch 73D instead of the charge switch 73, with one end connected to the other end (high potential side) of the capacitor 71 and the other end connected to the connection point between the drain terminal of the second P-channel MOS transistor 96 and the source terminal of the third P-channel MOS transistor 97.

[0137] Next, the operation of other embodiments of the fourth embodiment will be described. In this case, the operation and effects until the output signal VB of the first PWM power supply VVPWMH reaches the "L" level are the same as in the fourth embodiment. Therefore, the operation after the output signal VB of the first PWM power supply VVPWMH reaches the "L" level will be described.

[0138] As the output signal VB of the first PWM power supply VPWMH becomes "L" level, the N-channel MOS transistor 62 begins to transition to the off state (open state) in parallel with the above operation.

[0139] Furthermore, the charge switch 73D turns ON, and the charge stored in capacitor 71 moves to the gate terminal of N-channel MOS transistor 22 via the source and drain terminals of the third P-channel MOS transistor 97. The potential of the gate terminal of N-channel MOS transistor 22 rises rapidly and, due to the ratio of the capacitance of capacitor 71 to the capacitance of the gate terminal (gate capacitance), naturally reaches a potential near the threshold voltage Vth of N-channel MOS transistor 22.

[0140] Therefore, while shortening the period during which the gate potential VG of the N-channel MOS transistor 22 moves from 0 volts to a potential near the threshold voltage Vth, the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 22 is to be limited). Therefore, other aspects of this fourth embodiment can also be used to obtain the same effects as those of the first embodiment.

[0141] [5] Modified versions of the first to fourth embodiments [5.1] First variation In the above explanation, the time TD for the gate potential VG of the controlled transistor to change from 0 volts to the threshold voltage Vth was not adjusted. However, this first modification involves adjusting the time TD.

[0142] Figure 16 is an explanatory diagram of a first modified example of the embodiment. One method for varying the time TD (the time it takes for the gate potential VG of the controlled transistor to change from 0 volts to the threshold voltage Vth) is to adjust the charge Q charged to the capacitor. For example, the following three methods are possible.

[0143] One possible approach is to configure the power supply connected to the capacitor 71 to be pre-charged via a pre-charge switch 72 as a variable voltage source. With this configuration, the time TD can be shortened by raising the voltage of the variable voltage source as high as possible.

[0144] Another possible approach is to configure the capacitor 71 to be pre-charged as a variable capacitance capacitor. With this configuration, the time TD can be shortened by increasing the capacitance of the variable capacitance capacitor as much as possible.

[0145] Note that Figure 16 combines both the first and second methods, but the same effect can be obtained using either method alone. Furthermore, a third method involves making the current capacity (charge transfer capacity) of the precharge switch or charge switch variable, and increasing the current capacity to further shorten the time TD.

[0146] Figure 17 is an explanatory diagram of the first specific example of adjusting time TD using the second method. As shown in Figure 17, the output signal VB of the first PWM power supply VPWMH is input to one input terminal, and the enable signal Enx(x=1,2,…) of one of the corresponding capacitors is input to the other input terminal. An AND circuit Ax(x=1,2,…) is provided that turns on the corresponding precharge switch 72x(x=1,2,…) when an "H" level output signal and an "H" level enable signal are input, and connects the corresponding capacitor Cx(x=1,2,…) to the high-potential side power supply VDDB. As a result, by changing the combined capacitance of the capacitors simultaneously connected to the high-potential power supply VDDB, multiple fixed-capacitance capacitors are made to function as variable-capacitance capacitors. In other words, the larger the capacitance of the variable capacitor, the shorter the time TD can be. In this case, pre-charge switches 72-x (x=1,2,…) and charge switches 73-x (x=1,2,…) are provided in correspondence with each capacitor Cx (x=1,2,…).

[0147] Figure 18 is an explanatory diagram of a second specific example of adjusting time TD using the second method. As shown in Figure 18, this second specific example includes a comparator 151 that compares the charge voltage of capacitor 71 with a reference voltage VREF and outputs a comparison result signal, and an AND circuit 152 that receives the output signal VA of the first level shift circuit 23 as input to one input terminal and the comparison result signal of comparator 151 as input to the other input terminal and takes the logical AND of the two. Based on the output result of the AND circuit 152, if the voltage of capacitor 71 exceeds the set reference voltage VREF, the precharge switch 72 is turned off, effectively making the capacitance of the capacitor correspond to the reference voltage VREF, and the capacitance of the capacitor is effectively made variable by changing the reference voltage VREF.

[0148] Figure 19 is an explanatory diagram for varying the time TD (time taken for the gate potential VG of the controlled transistor to change from 0 volts to the threshold voltage Vth). In other words, the larger the effective capacitance of capacitor C1, the shorter the time TD can be, as shown in Figure 19.

[0149] More specifically, according to this second specific example, compared to the case of a waveform WL similar to the conventional example where the driving force is small, the time TD can be shortened as shown in waveform W. Furthermore, compared to the case of a waveform WH with a larger driving force, the driving force can be reliably suppressed, thereby suppressing the operation of the controlled transistors in the subsequent stage, and preventing an increase in power consumption and a decrease in reliability.

[0150] Figure 20 is an explanatory diagram of a third specific example of adjusting time TD using the second method. As shown in Figure 20, in this third specific example, instead of the AND circuit 152 that controls the precharge switch in the second specific example, a timer 155 that controls the precharge switch is provided. The output signal VB of the first PWM power supply VPWMH is input to the input terminal of the timer 155, and the rising edge of the output signal VB is detected to turn on the precharge switch 72.

[0151] Then, if the output signal VB of the first PWM power supply VPWMH remains at the "H" level for a set period of time, or if the output signal VB becomes "L" level, the precharge switch 72 is turned off, effectively allowing capacitor C1 to function as a variable capacitance capacitor.

[0152] In this third specific example, as shown in Figure 19 in the second specific example, the time TD can be shortened compared to the case of waveform WL, which is similar to the conventional example with a small driving force, as shown in waveform W. Furthermore, compared to the case of a waveform WH with a larger driving force, the driving force can be reliably suppressed, thereby suppressing the operation of the controlled transistors in the subsequent stage, and preventing an increase in power consumption and a decrease in reliability.

[0153] Figure 21 is an explanatory diagram illustrating a specific example of adjusting time TD using the third method. As shown in Figure 21, by replacing the precharge switch 72 with a variable current capacity precharge switch 72X, or replacing the charge switch 73 with a variable current capacity charge switch 73X, the effective precharge voltage or charge voltage can be varied, thereby making the time TD variable.

[0154] In the case of a specific example of adjusting time TD using the third method, as shown in Figure 19 in the second specific example, time TD can be shortened compared to the case of waveform WL, which is similar to the conventional example with a small driving force, as shown in waveform W. Furthermore, compared to the case of a waveform WH with a larger driving force, the driving force can be reliably suppressed, thereby suppressing the operation of the controlled transistors in the subsequent stage, and preventing an increase in power consumption and a decrease in reliability.

[0155] [5.2] Second variation The above explanation described the case where the controlled transistor is a normally-off element, but this second modification describes the case where the controlled transistor, which is the output transistor, is a normally-on element.

[0156] Figure 22 is an explanatory diagram illustrating a specific example where a normally-on element with a negative threshold voltage Vth is used as the controlled transistor, and a MOSFET is used in which the gate breakdown voltage is equal to the drain breakdown voltage.

[0157] In the example in Figure 22, a normally-on N-channel MOS transistor 22A is used instead of the N-channel MOS transistor 22. In this case, the drain terminal of the P-channel MOS transistor 61 is connected to the high-potential power supply VDDA, the drain terminal is connected to the gate terminal of the N-channel MOS transistor 22A, and the output signal VB of the first PWM power supply VPWMH is input to the gate terminal. The P-channel MOS transistor 61, whose drain terminal is connected to the gate terminal of the N-channel MOS transistor 22A, the source terminal is connected to the low-potential power supply VSSA, and the output signal VB of the first PWM power supply VPWMH is input to the gate terminal, is assumed to be a transistor whose gate breakdown voltage is equal to the drain breakdown voltage.

[0158] Furthermore, the drain terminal of the low-voltage N-channel MOS transistor 101 is connected to the source terminal of the N-channel MOS transistor 22A. Furthermore, a drive power supply V, which supplies drive power based on the high-potential side power supply VDDA, is connected to the source terminal of the low-voltage N-channel MOS transistor 101. In this case, the low-potential power supply VSSA is set to a negative voltage, and the potential of the second high-potential power supply VDDB is set to a potential higher than the threshold voltage Vth (<0V) of the N-channel MOS transistor 22A.

[0159] Now, let's explain the operation of the second modified example. When the output signal VB of the first PWM power supply VPWMH reaches the "H" level, the precharge switch 72 turns ON, and the capacitor 71 is charged by the second high-potential power supply VDDB to the potential of the high-potential power supply VDDB (or a desired potential).

[0160] Then, once the time required for capacitor 71 to fully charge has elapsed, the pre-charge switch 72 turns off. At this time, the N-channel MOS transistor 62 is in the ON state (closed state) because an "H" level is applied to its gate terminal. Consequently, the gate terminal of the N-channel MOS transistor 22A is at an "L" level (=VSSA), and the N-channel MOS transistor 22A is in the OFF state (open state).

[0161] Next, in order to transition the N-channel MOS transistor 22A from the off state (open state) to the on state (closed state), the output signal VB of the first PWM power supply VPWMH is set to the "L" level.

[0162] As a result, the second P-channel MOS transistor 92 begins to transition to the ON state (closed / open state), and the N-channel MOS transistor 62 begins to transition to the OFF state (open state). Furthermore, the P-channel MOS transistor 61 begins to transition to the ON state.

[0163] In this case, the P-channel MOS transistor 61 functions as a variable current source, and charge movement is restricted. As a result, the driving force is limited, and the gate potential of the N-channel MOS transistor 22A gradually transitions to the "H" level.

[0164] As a result, the N-channel MOS transistor 22A does not transition abruptly to the ON state (closed state). Consequently, the power transistors downstream of the N-channel MOS transistor 22A do not transition abruptly, the two power transistors constituting the upper and lower arms do not turn ON (close) simultaneously, and no through-current flows, thus preventing unnecessary increases in power consumption.

[0165] Then, as the output signal VB of the first PWM power supply VPWMH becomes "L" level, the N-channel MOS transistor 62 begins to transition to the off state (open state) in parallel with the above operation.

[0166] Furthermore, the charge switch 73 is turned ON, and the charge stored in capacitor 71 moves to the gate terminal of N-channel MOS transistor 22A. The potential at the gate terminal of N-channel MOS transistor 22A rises rapidly and, due to the ratio of the capacitance of capacitor 71 to the capacitance of the gate terminal (gate capacitance), naturally reaches a potential near the threshold voltage Vth of N-channel MOS transistor 22A.

[0167] Therefore, the period until the gate potential VG of the N-channel MOS transistor 22A reaches a potential near the threshold voltage Vth, which is higher than the potential of the low-potential side power supply VSSA, is shortened, while the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 22A is to be limited). Then, once the driving force limiting period has elapsed, the N-channel MOS transistor 22A switches to the ON state, current flows from the drain terminal of the low-voltage N-channel MOS transistor 101 to the source terminal, and the potential of the output terminal OUT becomes "L". Therefore, the same effects as those of the first embodiment can be obtained with this second modified example.

[0168] [5.3] Third variation In the second modification described above, a normally-on element with a negative threshold voltage Vth was used as the controlled transistor, and a MOSFET with a gate breakdown voltage equal to the drain breakdown voltage was used. However, in this third modification, a normally-on element with a negative threshold voltage Vth was used as the controlled transistor, and the gate breakdown voltage is very low compared to the drain breakdown voltage.

[0169] Figure 23 is an explanatory diagram illustrating a specific example where a normally-on element is used as the controlled transistor, and the gate breakdown voltage is very low compared to the drain breakdown voltage. In Figure 23, the same reference numerals shall be used for parts that are the same as those in the second modified example of Figure 22.

[0170] In this case, the variable-force P-channel MOS transistor 61 has its source terminal connected to a high-potential power supply VDDA and its drain terminal connected to the gate terminal of the N-channel MOS transistor 22A. Instead of the output signal VA of the first level shift circuit 23, a high-potential power supply PWMH is connected to the gate terminal of the variable-force P-channel MOS transistor 61 to apply a potential equivalent to the breakdown voltage (gate breakdown voltage) of the gate terminal of the N-channel MOS transistor 22A.

[0171] Similarly, the drain terminal of the N-channel MOS transistor 62 is connected to the gate terminal of the N-channel MOS transistor 22A, the source terminal is connected to the low-potential power supply VSSA, and the gate terminal is connected to the low-potential power supply PWML, which applies a potential equivalent to the withstand voltage (gate breakdown voltage) of the gate terminal of the N-channel MOS transistor 22A, instead of the output signal VB of the first PWM power supply VPWMH.

[0172] The operation of this third modified example is the same as the second modified example, except that when transitioning the N-channel MOS transistor 22A to the ON state, a potential equivalent to the breakdown voltage (gate breakdown voltage) of the gate terminal of the N-channel MOS transistor 22A (= potential of the high-potential-side power supply VDDA - potential of the high-potential-side power supply PWMH) is applied as the gate potential via the P-channel MOS transistor 61 by the high-potential-side power supply PWMH, and when transitioning the N-channel MOS transistor 22A to the OFF state, a potential equivalent to the breakdown voltage (gate breakdown voltage) of the gate terminal of the N-channel MOS transistor 22A (= potential of the low-potential-side power supply VSSA + potential of the low-potential-side power supply PWML) is applied as the gate potential via the N-channel MOS transistor 62 by the low-potential-side power supply PWML. Therefore, the same effects as those of the first embodiment can be obtained with this third modified example.

[0173] [5.4] Fourth variation Figure 24 is a schematic block diagram of the transistor drive circuit for the fourth modified example. In Figure 24, the same reference numerals are used for parts that are the same as those in Figure 1. The difference between the transistor drive circuit 10A and the transistor drive circuit in Figure 1 is that, similar to the second and third modified examples described above, a high-potential-side switch SWH (=output transistor) configured as a normally-on element is provided between the output terminal OUT and a high-potential-side low-voltage N-channel MOS transistor LVH. In order to apply a potential corresponding to the gate breakdown voltage of the high-potential-side switch SWH to the gate terminal of the high-potential-side low-voltage N-channel MOS transistor LVH, a high-potential-side power supply VLVH generates a predetermined potential from the potential of the high-potential-side power supply VH, and the high-potential-side low-voltage N-channel MOS transistor receives power from the high-potential-side power supply VLVH. The device includes a drive amplifier 105 for driving the LVH, and a low-potential side low-voltage N-channel MOS transistor LVL is provided between the low-potential side switch SWL (=output transistor), which is configured as a normally-on element, and the output terminal OUT. In order to apply a potential corresponding to the gate breakdown voltage of the low-potential side switch SWL to the gate terminal of the low-potential side low-voltage N-channel MOS transistor LVL, the device includes a low-potential side power supply VLVL that generates a predetermined potential from the potential of the low-potential side power supply VL, and a drive amplifier 106 that drives the low-potential side low-voltage N-channel MOS transistor LVL by receiving power from the low-potential side power supply VLVL.

[0174] The operation is the same as in the second and third modified examples. Therefore, according to this fourth modification, even when a high-potential switch SWH and a low-potential switch SWL configured as normally-on elements are used as output transistors, the same effects as those of the first embodiment can be obtained.

[0175] [5.5] Fifth Variation In each of the above embodiments and modifications, the delay time adjustment circuit was used to control the potential of the gate terminal of the output transistor. However, the same problem may occur in the controlled transistor located downstream of the output transistor.

[0176] Therefore, this fifth modified example includes a second delay time adjustment circuit to control the potential of the gate terminal of the subsequent controlled transistor, in addition to controlling the potential of the gate terminal of the output transistor.

[0177] Figure 25 is a schematic block diagram of the transistor drive circuit for the fifth modified example. In Figure 25, the transistor drive circuit 10B includes a P-channel MOS transistor 111 as an output transistor, a P-channel MOS transistor 112 whose source terminal is connected to a high-potential power supply VDDC and whose drain terminal is connected to the gate terminal of the P-channel MOS transistor 111, with the output signal VA of the first level shift circuit 23 input to its gate terminal, a variable-drive N-channel MOS transistor 113 whose drain terminal is connected to the gate terminal of the P-channel MOS transistor 111 and whose source terminal is connected to a low-potential power supply VSSC, with the output signal VA of the first level shift circuit 23 input to its gate terminal, and a first delay time adjustment circuit 114.

[0178] Here, the first delay time adjustment circuit 114 includes a capacitor 121 with one end connected to a high-potential power supply VDDC, a first precharge switch 122 with one end connected to the other end of the capacitor 121 and the other end connected to a low-potential power supply VSSC, to which an inverted output signal / VA, which is the inverted signal of the output signal VA of the first level shift circuit 23, is input as a control signal, a first charge switch 123 with one end connected to the other end of the capacitor 121 and the other end connected to the gate terminal of a P-channel MOS transistor 111, to which the output signal VA of the first level shift circuit 23 is input as a control signal, and an inverter 124 with the output signal VA of the first level shift circuit 23 input to its input terminal, inverting the output signal VA and outputting it as an inverted output signal / VA.

[0179] Furthermore, the transistor drive circuit 10B includes an N-channel MOS transistor 131 as an output transistor, a P-channel MOS transistor 132 whose source terminal is connected to a high-potential power supply VDDA and whose drain terminal is connected to the gate terminal of the N-channel MOS transistor 131, with the output signal VB of the first PWM power supply VPWMH input to its gate terminal, an N-channel MOS transistor 133 whose drain terminal is connected to the gate terminal of the N-channel MOS transistor 131 and whose source terminal is connected to a low-potential power supply VSSA, with the output signal VB of the first PWM power supply VPWMH input to its gate terminal, and a second delay time adjustment circuit 134.

[0180] Here, the second delay time adjustment circuit 134 includes a capacitor 141 with one end connected to the low-potential power supply VSSA, a second precharge switch 142 with one end connected to the other end of the capacitor 141 and the other end connected to the high-potential power supply VDDC, to which the inverted output signal / VA is input as a control signal, and a second charge switch 143 with one end connected to the other end of the capacitor 141 and the other end connected to, for example, the gate terminal of a subsequent controlled transistor, an N-channel MOS transistor 145, to which the output signal VA of the first level shift circuit 23 is input as a control signal.

[0181] Next, we will explain the operation of the fifth modified example. When the output signal VA of the first level shift circuit 23 becomes "L" level, the inverter 124 inverts the output signal VA and outputs the inverted output signal / VA = "H" level to the first precharge switch 122 and the second precharge switch 142.

[0182] As a result, the first precharge switch 122 turns ON, and the capacitor 121 is charged by the low-potential power supply VSSC to the potential of the low-potential power supply VSSC (or a desired potential).

[0183] Then, once the capacitor 121 has finished charging, the first precharge switch 122 turns off. Furthermore, the second precharge switch 142 is turned ON, and the capacitor 141 is charged by the high-potential power supply VDDA to the potential of the high-potential power supply VDDA (or a desired potential).

[0184] Then, once the capacitor 141 has finished charging, the second precharge switch 142 turns off.

[0185] At this time, the gate terminal of the P-channel MOS transistor 132 is in the ON state (closed state) because an "L" level is applied, the gate terminal of the N-channel MOS transistor 133 is in the OFF state (open state) because an "L" level is applied, and the N-channel MOS transistor 131, which acts as an output transistor, is in the ON state. As a result, the subsequent controlled transistor, the N-channel MOS transistor 145, is in the off state (open state).

[0186] Next, in order to transition the P-channel MOS transistor 111 from the off state (open state) to the on state (closed state), and consequently transition the subsequent controlled transistor, the N-channel MOS transistor 145, from the off state (open state) to the on state (closed state), the output signal VA of the first level shift circuit 23 is set to "H" level, and at the same time, the output signal VB of the first PWM power supply VPWMH is set to "H" level.

[0187] As a result, the P-channel MOS transistor 112 begins to transition to the off state (open state), and the N-channel MOS transistor 113 begins to transition to the on state (closed state). At this time, the inverted output signal / VA, which is the output signal of the inverter 124, becomes "L" level, and the first precharge switch 122 and the second precharge switch 142 are turned off.

[0188] On the other hand, since the output signal VA of the first level shift circuit 23 is at the "H" level, the first charge switch 123 and the second charge switch 143 are turned ON.

[0189] In this case, an N-channel MOS transistor 113, which functions as a variable current source, is provided between the low-potential power supply VSSC and the gate terminal of the P-channel MOS transistor 111, thereby restricting charge movement. As a result, the driving force is limited, and the gate potential of the P-channel MOS transistor 111 gradually transitions to the "L" level.

[0190] As a result, the P-channel MOS transistor 111 does not transition abruptly to the ON state (closed state). Consequently, the controlled transistor (power transistor) 145 downstream of the P-channel MOS transistor 111 does not transition abruptly, the two power transistors constituting the upper arm and lower arm do not turn ON (close) simultaneously, and no through-current flows, thus preventing unnecessary increases in power consumption.

[0191] Furthermore, the first charge switch 123 turns ON, and the charge at the gate terminal of the P-channel MOS transistor 111 is discharged to the capacitor 121 and moved. The potential at the gate terminal of the P-channel MOS transistor 111 drops sharply, and due to the ratio of the capacitance of the capacitor 121 to the capacitance of the gate terminal (gate capacitance), it naturally becomes a potential near the threshold voltage Vth of the P-channel MOS transistor 111.

[0192] Therefore, the period during which the gate potential VG of the P-channel MOS transistor 111 reaches a potential near the threshold voltage Vth from the high-potential power supply VDDC is shortened, and the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the P-channel MOS transistor 111 is to be limited).

[0193] Similarly, since the output signal VA of the first level shift circuit 23 is at the "H" level, the second charge switch 143 is turned ON, the charge of capacitor 141 moves to the gate terminal of N-channel MOS transistor 145, and the potential of the gate terminal of N-channel MOS transistor 145 rises rapidly. Due to the ratio of the capacitance of capacitor 141 to the capacitance of the gate terminal (gate capacitance), the potential naturally becomes close to the threshold voltage Vth of N-channel MOS transistor 151.

[0194] Therefore, the period during which the gate potential VG of the N-channel MOS transistor 145 reaches a potential near the threshold voltage Vth from the low-potential power supply VSSA is shortened, while the driving force can be controlled by a variable current source without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 151 is to be limited).

[0195] Therefore, the period during which the gate potential VG of the N-channel MOS transistor 151 rises from the voltage of the low-potential power supply VSSA to near the threshold voltage Vth is shortened, while driving force control can be performed without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 151 is limited and the operation of subsequent transistors is to be suppressed). Therefore, this fifth modification also provides the same effects as the first embodiment, not only for the output transistor but also for the subsequent controlled transistor.

[0196] [5.6] Sixth variation In the above embodiments and modifications, the case in which a precharge switch and a charge switch are used as the delay time adjustment circuit was described. However, this sixth modification describes a case in which a charge pump is used instead of a precharge switch and a charge switch.

[0197] Figure 26 is a schematic block diagram of a transistor drive circuit using a charge pump in the sixth modified example. In Figure 26, the same reference numerals are used for parts that are the same as those in the second basic configuration diagram of the embodiment shown in Figure 3.

[0198] In Figure 26, the first variable amplifier 24 includes a P-channel MOS transistor 61 with a variable driving force, the source terminal of which is connected to a high-potential power supply VDDA and the drain terminal of which is connected to the gate terminal of an N-channel MOS transistor 22, and the output signal VB of the first PWM power supply VPWMH is input to the gate terminal, and an N-channel MOS transistor 62 with a drain terminal of which is connected to the gate terminal of an N-channel MOS transistor 22 and the source terminal of which is connected to a low-potential power supply VSSA, and the output signal VB of the first PWM power supply VPWMH is input to the gate terminal.

[0199] Furthermore, the delay time adjustment circuit 161 is configured as a charge pump circuit and includes an inverter 171 to which an intermediate potential power supply VDDE (< high potential power supply VDDA) is connected as the high potential power supply, a low potential power supply VSSE is connected, the output signal VC of the third level shift circuit 175 is input to the input terminal, and the inverter 171 inverts the output signal VC to output an inverted output signal / VC, a capacitor 172 to which the output terminal of the inverter 171 is connected at one end, a precharge diode 173 to which the anode terminal is connected to the intermediate potential power supply VDDE and the cathode terminal is connected to the other end of the capacitor 172, and a charge diode 174 to which the anode terminal is connected to the cathode terminal of the precharge diode 173 and the cathode terminal is connected to the gate terminal of the N channel MOS transistor 22.

[0200] Next, we will explain the operation of the sixth modified example. First, set the output signal VB of the first PWM power supply VPWMH to the "H" level. As a result, the P-channel MOS transistor 61 begins to transition to the off state (open state), and the N-channel MOS transistor 62 begins to transition to the on state (closed state).

[0201] In parallel with the above operation, the inverter 171 inverts the output signal VC and outputs an inverted output signal / VC.

[0202] At this time, the potential of the output terminal of inverter 171 becomes the potential of the low-potential power supply VSSE, so the capacitor 172 is charged to the potential of the intermediate-potential power supply VDDE via the pre-charge diode 173. Then, when the potential of capacitor 172 becomes equal to the potential of the intermediate potential power supply VDDE, the pre-charging process ends.

[0203] Next, when the output signal VB of the first PWM power supply VPWMH becomes "L" level, the P-channel MOS transistor 61 begins to transition to the ON state (closed state), and the N-channel MOS transistor 62 begins to transition to the OFF state (open state). In this case, since the driving force of the P-channel MOS transistor 61 is limited, the gate potential of the N-channel MOS transistor 22 gradually transitions to the "H" level.

[0204] Therefore, the N-channel MOS transistor 22 will not abruptly transition to the ON state (closed state). Consequently, the subsequent power transistor will not abruptly transition either.

[0205] At this time, the potential of the output terminal of inverter 171 is approximately equal to the potential of the intermediate potential power supply VDDE. On the other hand, the potential at the other end of capacitor 172 is approximately equal to the potential obtained by adding a voltage equal to the difference between the potential of the intermediate potential power supply VDDE and the potential of the low-potential side power supply VSSA to the intermediate potential power supply VDDE. In other words, the potential at the other end of capacitor 172 ≈ VDDE + (VDDE - VSSA). Therefore, the charge stored in capacitor 172 is supplied to the gate terminal of N-channel MOS transistor 22, causing the potential at the gate terminal of N-channel MOS transistor 22 to rise rapidly. Due to the ratio of the capacitance of capacitor 172 to the capacitance of the gate terminal of N-channel MOS transistor 22 (gate capacitance), the potential naturally approaches the threshold voltage Vth of N-channel MOS transistor 22.

[0206] Therefore, the period during which the gate potential VG of the N-channel MOS transistor 22 moves from the potential of the low-potential side power supply VSSA to a potential near the threshold voltage Vth results in high-speed drive, and the drive force can be controlled by the current source without feedback control during the period during which the drive force of the N-channel MOS transistor 22 needs to be limited.

[0207] In other words, according to this sixth modified example, the same effects as those of the first embodiment can be obtained.

[0208] [5.7] Seventh variation This seventh modification, like the sixth modification, involves using a charge pump instead of a precharge switch and a charge switch.

[0209] Figure 27 is a schematic block diagram of the transistor drive circuit using a charge pump in the seventh modified example. In Figure 27, the same reference numerals shall be used for parts that are the same as those in the sixth modified example of Figure 25.

[0210] In Figure 27, the delay time adjustment circuit 162 is configured as a charge pump circuit, and has a low-potential power supply VSSA connected as a high-potential power supply, a low-potential power supply VSSE (< low-potential power supply VSSA) connected as a low-potential power supply, an inverter 171 to which the output signal VC of the third level shift circuit 175 is input and which inverts the output signal VC to output an inverted output signal / VC, a capacitor 172 to which the output terminal of the inverter 171 is connected at one end, a pre-charge diode 181 to which the anode terminal is connected to the intermediate-potential power supply VDDE and the cathode terminal is connected to the other end of the capacitor 172, and a charge diode 182 to which the anode terminal is connected to the cathode terminal of the pre-charge diode 173 and the cathode terminal is connected to the gate terminal of the N-channel MOS transistor 22.

[0211] Next, we will explain the operation of the seventh modified example. First, set the output signal VB of the first PWM power supply VPWMH to the "H" level. As a result, the P-channel MOS transistor 61 begins to transition to the off state (open state), and the N-channel MOS transistor 62 begins to transition to the on state (closed state).

[0212] In parallel with the above operation, the inverter 171 inverts the output signal VC and outputs an inverted output signal / VC. At this time, the potential of the output terminal of inverter 171 becomes the potential of the low-potential power supply VSSE, so the capacitor 172 is charged to the potential of the low-potential power supply VSSA, which acts as the high-potential power supply, via the pre-charge diode 181.

[0213] Then, when the potential of capacitor 172 becomes equal to the potential of the low-potential power supply VSSA, the pre-charging process ends.

[0214] Next, when the output signal VB of the first PWM power supply VPWMH becomes "L" level, the P-channel MOS transistor 61 begins to transition to the ON state (closed state), and the N-channel MOS transistor 62 begins to transition to the OFF state (open state). In this case, since the driving force of the P-channel MOS transistor 61 is limited, the gate potential of the N-channel MOS transistor 22 gradually transitions to the "H" level.

[0215] Therefore, the N-channel MOS transistor 22 will not abruptly transition to the ON state (closed state). Consequently, the subsequent power transistor will not abruptly transition either.

[0216] At this time, the potential at the other end of capacitor 172 is approximately equal to the potential of the low-potential power supply VSSA plus a voltage equal to the difference between the potential of the low-potential power supply VSSA and the potential of the low-potential power supply VSSE. In other words, the potential at the other end of capacitor 172 is approximately VSSA + (VSSA - VSSE). Therefore, the potential of the gate terminal of the N-channel MOS transistor 22 rises instantaneously and naturally reaches a potential near the threshold voltage Vth of the N-channel MOS transistor 22 according to the ratio between the capacitance of the capacitor 172 and the capacitance of the gate terminal of the N-channel MOS transistor 22 (gate capacitance).

[0217] Therefore, the period during which the gate potential VG of the N-channel MOS transistor 22 changes from the potential of the low-potential-side power supply VSSA to a potential near the threshold voltage Vth is a high-speed driving period, and for the driving force limiting period during which the driving force is to be limited (for the period during which the driving force of the N-channel MOS transistor 22 is to be limited, the driving force can be controlled by a current source without performing feedback control).

[0218] That is, according to this 7th modification example as well, the same effects as those of the first embodiment can be obtained.

[0219] [6] Fifth Embodiment In the driving force limiting circuit of the gate driver of each of the above embodiments, it was effective for speeding up the final stage of the driver to charge at high speed up to the voltage determined by the capacitance ratio and reduce the propagation delay. However, when the load capacitance (load gate capacitance) to be driven is large, it is necessary to use a large capacitance. For example, the gate capacitance of a power device is about 10 nF. In such a case, a method of using an external capacitance can be considered, but it is desirable to reduce the number of external components and suppress the parasitic inductance of the external capacitance, and it is desired to be composed of components that can be built in.

[0220] Therefore, in this fifth embodiment, instead of using a large external capacitance, a configuration is adopted in which the discharge power of a built-in capacitance is amplified by a current mirror circuit.

[0221] FIG. 28 is a diagram for explaining the basic configuration of the fifth embodiment. In FIG. 28, the same parts as those in FIG. 3 are denoted by the same reference numerals. In FIG. 28, the first variable amplifier 24 includes a P-channel MOS transistor 61 with a source terminal connected to the high-potential-side power supply VDDA, a drain terminal connected to the gate terminal of the N-channel MOS transistor 22, and an output signal VB of the first PWM power supply VPWMH input to the gate terminal, and an N-channel MOS transistor 62 with a drain terminal connected to the gate terminal of the N-channel MOS transistor 22, a source terminal connected to the low-potential-side power supply VSSA, and the output signal VB of the first PWM power supply VPWMH input to the gate terminal.

[0222] In FIG. 28, the delay time adjustment circuit 191 includes a capacitor 192 with one end connected to the high-potential-side power supply VDDA, a precharge switch 193 with one end connected to the other end of the capacitor 192 and the other end connected to the low-potential-side power supply VSSA, a charge switch 194 with one end connected to the other end of the capacitor 192, and a current mirror circuit 195.

[0223] In the above configuration, the current mirror circuit 195 includes a P-channel MOS transistor 195A with a source terminal connected to the high-potential-side power supply VDDA, a drain terminal connected to the other end of the charge switch 194, and a gate terminal connected to the drain terminal, a P-channel MOS transistor 195B with a source terminal connected to the high-potential-side power supply VDDA, a drain terminal connected to the gate terminal of the N-channel MOS transistor 22, and a gate terminal connected to the gate terminal of the P-channel MOS transistor 195A, and a switch 195C with one end connected to the high-potential-side power supply VDDA and the other end connected to the gate terminals of the P-channel MOS transistor 195A and the P-channel MOS transistor 195B.

[0224] In this case, the P-channel MOS transistor 195B is shown as a single MOS transistor. However, the P-channel MOS transistor 195B can also be configured by connecting m (where m is an integer greater than or equal to 2) P-channel MOS transistors in parallel, or by setting the gate area of ​​the P-channel MOS transistor 195B to m times the gate area of ​​the P-channel MOS transistor 195A, thereby allowing a current m times the current flowing between the source and drain terminals of the P-channel MOS transistor 195A to flow. Note that m is the Miller ratio of the current mirror and can take values ​​other than integers.

[0225] In the above configuration, the precharge switch 193 is turned on for all or part of the period during which the output signal VB of the first PWM power supply VPWMH is at the "H" level. That is, it remains on until the capacitor 192 reaches a predetermined voltage.

[0226] Furthermore, the charge switch 194 remains ON for all or part of the period during which the output signal VB of the first PWM power supply VPWMH is at the "L" level. That is, it remains ON until the potential of the gate terminal of the N-channel MOS transistor 22 reaches a predetermined voltage (ideally, the threshold voltage of the N-channel MOS transistor 22).

[0227] Next, the operation of the fifth embodiment will be described. Figure 29 is an explanatory diagram (part 1) of the operation of the fifth embodiment. To transition the N-channel MOS transistor 22 from the off state (open state) to the on state (closed state), first, the output signal VB of the first PWM power supply VPWMH is set to the "H" level.

[0228] As a result, the P-channel MOS transistor 61 begins to transition to the off state (open state), and the N-channel MOS transistor 62 begins to transition to the on state (closed state).

[0229] In parallel with the above operation, since the output signal VB is at the "H" level, the precharge switch 193 is turned ON, and a charging current flows through the capacitor 192 from the high-potential power supply VDDA, as shown by the arrow in Figure 28. As a result, the capacitor 192 is charged to the potential of the high-potential power supply VDDA.

[0230] In this state, the switch 195C of the current mirror circuit 195 is turned ON, so the potential between the source terminal and gate terminal of the P-channel MOS transistors 195A and 195B becomes the same, and therefore the current mirror circuit does not function.

[0231] Then, once the time required for capacitor 192 to fully charge has elapsed, the precharge switch 193 turns off.

[0232] Figure 30 is an explanatory diagram (part 2) of the operation of the fifth embodiment. Next, when the output signal VB of the first PWM power supply VPWMH becomes "L" level, the P-channel MOS transistor 61 begins to transition to the ON state (closed state), and the N-channel MOS transistor 62 begins to transition to the OFF state (open state). In this case, since the driving force of the P-channel MOS transistor 61 is limited, the gate potential of the N-channel MOS transistor 22 gradually transitions to the "H" level.

[0233] Therefore, the N-channel MOS transistor 22 will not abruptly transition to the ON state (closed state). Consequently, the subsequent power transistor will not abruptly transition either.

[0234] Simultaneously, the switch 195C of the current mirror circuit 195 is turned off, and the charge switch 194 is turned on. As a result, the charge stored in capacitor 192 flows between the source and drain terminals of the P-channel MOS transistor 195A that constitutes the current mirror circuit 195, thereby performing current mirror operation.

[0235] In other words, a current m times greater than the current between the source and drain terminals of the P-channel MOS transistor 195A flows between the source and drain terminals of the P-channel MOS transistor 195B, which constitutes the current mirror circuit 195. As a result, the potential of the gate terminal of the N-channel MOS transistor 22 instantly rises to a potential near the threshold voltage Vth of the N-channel MOS transistor 22.

[0236] Therefore, the period during which the gate potential VG of the N-channel MOS transistor 22 moves from 0 volts to a potential near the threshold voltage Vth is high-speed drive, and the drive force can be controlled without feedback control during the drive force limiting period (the period during which the drive force of the N-channel MOS transistor 22 is to be limited).

[0237] [7] Sixth Embodiment Figure 31 is an explanatory diagram of the basic configuration of the sixth embodiment. In Figure 31, the same reference numerals are used for parts that are the same as those in Figure 3.

[0238] In Figure 31, the first variable amplifier 24 includes a P-channel MOS transistor 61 whose source terminal is connected to a high-potential power supply VDDA and whose driving force is variable; a P-channel (LD) MOS transistor 201 whose source terminal is connected to the drain terminal of the P-channel MOS transistor 61, whose drain terminal is connected to the gate terminal of an N-channel MOS transistor 22, and whose gate terminal is input to the output signal VB of the first PWM power supply VPWMH; and an N-channel (LD) MOS transistor 62 whose drain terminal is connected to the drain terminal of the P-channel (LD) MOS transistor 201, whose source terminal is connected to a low-potential power supply VSSA, and whose gate terminal is connected to the gate terminal of the P-channel (LD) MOS transistor 201.

[0239] In FIG. 31, the delay time adjustment circuit 200 includes a P-channel MOS transistor 202 having a source terminal connected to the high-potential-side power supply VDDA and a gate terminal to which an output signal VB of the first PWM power supply VPWMH is input, and an N-channel MOS transistor 203 having a drain terminal connected to the drain terminal of the P-channel MOS transistor 202, a source terminal connected to the low-potential-side power supply VSSA, and a gate terminal connected to the gate terminal of the P-channel MOS transistor 202, and a capacitor 204 having one end connected to the connection point between the drain terminal of the P-channel MOS transistor 201 and the drain terminal of the N-channel MOS transistor 62 and the other end connected to the connection point between the drain terminal of the P-channel MOS transistor 202 and the drain terminal of the N-channel MOS transistor 203.

[0240] In the above configuration, when the P-channel MOS transistor 202 and the N-channel MOS transistor 203 cooperate to transition the N-channel MOS transistor 22 from the off state (open state) to the on state (closed state) during turn-on, they constitute a charging path for the capacitor 204.

[0241] Also, the P-channel MOS transistor 202 and the N-channel MOS transistor 203 function as an inverter circuit and, when they cooperate to transition the N-channel MOS transistor 22 from the on state (closed state) to the off state (open state) during turn-off, they constitute a discharging path for the capacitor 204.

[0242] Next, the operation of the sixth embodiment will be described. FIG. 32 is an operation explanatory diagram (part 1) of the sixth embodiment. When transitioning the N-channel MOS transistor 22 from the off state (open state) to the on state (closed state), first, the output signal VB of the first PWM power supply VPWMH is set to the “L” level.

[0243] As a result, the P-channel (LD) MOS transistor 201 transitions to the ON state (closed state), and the N-channel MOS transistor 62 transitions to the OFF state (open state). In this case, since the driving force of the P-channel MOS transistor 61 is limited, the gate potential of the N-channel MOS transistor 22 gradually transitions to the "H" level.

[0244] In parallel with this, the P-channel MOS transistor 202 transitions to the ON state, and the N-channel MOS transistor 203 transitions to the OFF state. Therefore, the P-channel MOS transistor 202 constitutes a charging path to the capacitor 204, and the capacitor 204 is gradually charged.

[0245] Therefore, the N-channel MOS transistor 22 will not abruptly transition to the ON state (closed state). Consequently, the subsequent power transistor will not abruptly transition either.

[0246] Subsequently, when the capacitor 204 is fully charged and reaches a potential near the high-potential power supply VDDA, the N-channel MOS transistor 22 turns ON (closed).

[0247] Figure 33 is an explanatory diagram (part 2) of the operation of the sixth embodiment. To transition the N-channel MOS transistor 22 from the ON state (closed state) to the OFF state (open state), first, the output signal VB of the first PWM power supply VPWMH is set to the "H" level.

[0248] As a result, the P-channel (LD) MOS transistor 201 transitions to the off state (open state), and the N-channel MOS transistor 62 transitions to the on state (closed state). In parallel with this, the P-channel MOS transistor 202 transitions to the off state, and the N-channel MOS transistor 203 transitions to the on state. Therefore, the N-channel MOS transistor 203 constitutes a discharge path to the capacitor 204, and the capacitor 204 is discharged rapidly.

[0249] Therefore, the N-channel MOS transistor 22 quickly transitions to the off state (closed state). Consequently, the subsequent power transistor can also be quickly transitioned. Subsequently, as discharge progresses in capacitor 204, the N-channel MOS transistor 22 enters the off state (closed state).

[0250] As described above, according to the sixth embodiment, the period during which the gate potential VG of the N-channel MOS transistor 22 moves from 0 volts to a potential near the threshold voltage Vth is driven at high speed while reducing the operating delay, and driving force control can be performed without feedback control during the driving force limiting period (the period during which the driving force of the N-channel MOS transistor 22 is to be limited).

[0251] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0252] 10, 10A, 10B Transistor Drive Circuit 11. High-potential side gate drive circuit 12 Low-voltage side gate drive circuit 20. First Gate Driver IC 21 P-channel MOS transistors 22 N-channel MOS transistors 22A N-channel MOS transistor (normally on) 23. First Level Shift Circuit 24. First Variable Amplifier 25. First Delay Time Adjustment Circuit 26. First Amplifier 27. Second Delay Time Adjustment Circuit 30 Second Gate Driver IC 31 P-channel MOS transistors 32 N-channel MOS transistors 33. Second Level Shift Circuit 34. Second Variable Amplifier 35 Third Delay Time Adjustment Circuit 36. Second Amplifier 37. Fourth Delay Time Adjustment Circuit 41 P-channel MOS transistors 42 N-channel MOS transistors 51 Capacitors 52 Precharge switch 53 Charge switch 61 Capacitors 61 P-channel MOS transistors 62 N-channel MOS transistors 71 Capacitors 72, 72X Precharge Switch 72A Inverter 72B P-channel MOS transistor 72C N-channel MOS transistor 73, 73X Charge Switch 73A Inverter 73B P-channel MOS transistor 73C N-channel MOS transistor 74 Inverter 75 Non-overlap clock generation circuit 75A First NOR Circuit 75B First Delay Circuit 75C Inverter 75D Second NOR Circuit 75E Second Delay Circuit 81. First P-channel MOS transistor 82. Second P-channel MOS transistor 83. Second P-channel MOS transistor 85. First P-channel MOS transistor 86. Second P-channel MOS transistor 87. Third P-channel MOS transistor 91. First P-channel MOS transistor 92 Second P-channel MOS transistor 93 Third P-channel MOS transistor 95. First P-channel MOS transistor 96. Second P-channel MOS transistor 97 Third P-channel MOS transistor 101 Low-voltage N-channel MOS transistor 105, 106 drive amplifier 111 P-channel MOS transistors 112 P-channel MOS transistors 113 N-channel MOS transistors 114 First Delay Time Adjustment Circuit 121 Capacitor 122 First precharge switch 123 First Charge Switch 124 Inverter 131 N-channel MOS transistors 132 P-channel MOS transistors 133 N-channel MOS transistors 134 Second Delay Time Adjustment Circuit 141 Capacitors 142 Second precharge switch 143 Second charge switch 145 N-channel MOS transistors 151 Comparator 152 AND gate 155 timer 161, 162 Delay Time Adjustment Circuit 171 Inverter 172 Capacitors 173, 181 Precharge diodes 174, 182 Charge diodes C1, C2 Capacitors dφ1 First delayed clock signal dφ2 Second delayed clock signal En1, En2, Enable signal LVH (Low Voltage N-Channel MOS Transistor) LVL Low-Voltage N-Channel MOS Transistor OUT, OUTN output terminals PWMH High potential side power supply PWML Low potential side power supply SWH High-potential switch SWL (Small Voltage Switch) TD Time V drive power supply VA output signal Vth threshold voltage Vvar control signal φ1 First clock signal φ2 Second clock signal

Claims

1. A driving force limiting circuit that, when a driven transistor is driven, transitions the gate potential of the driven transistor to a predetermined driving force limiting potential corresponding to the threshold voltage of the driven transistor, The system includes a delay time adjustment circuit that, when the drive force limiting circuit is operating, gradually transitions the gate potential from the drive force limiting potential to exceed the threshold voltage, The aforementioned delay time adjustment circuit includes a capacitor that stores a charge corresponding to the driving force limiting potential, Prior to transitioning the gate potential to the driving force limiting potential, a precharge switch supplies charge from the power supply to the capacitor, or supplies charge from the capacitor to the power supply. When the gate potential is transitioned to the driving force limiting potential, a charge switch is used to electrically connect the capacitor to the gate of the driven transistor, Equipped with Based on the comparison result between the potential of the capacitor and a predetermined reference potential, the period for supplying charge from the power supply to the capacitor, or the period for supplying charge from the capacitor to the power supply, is controlled. Transistor drive circuit.

2. A driving force limiting circuit that, when a driven transistor is driven, transitions the gate potential of the driven transistor to a predetermined driving force limiting potential corresponding to the threshold voltage of the driven transistor, The system includes a delay time adjustment circuit that, when the drive force limiting circuit is operating, gradually transitions the gate potential from the drive force limiting potential to exceed the threshold voltage, The aforementioned delay time adjustment circuit includes a capacitor that stores a charge corresponding to the driving force limiting potential, Prior to transitioning the gate potential to the driving force limiting potential, a precharge pump circuit transfers charge from the power supply to the capacitor, or transfers charge from the capacitor to the power supply. Equipped with Based on the comparison result between the potential of the capacitor and a predetermined reference potential, the period for supplying charge from the power supply to the capacitor, or the period for supplying charge from the capacitor to the power supply, is controlled. Transistor drive circuit.

3. A variable capacitance capacitor is used as the aforementioned capacitor. A transistor drive circuit according to claim 1 or claim 2.

4. The capacitor is configured to function as a variable capacitance capacitor by selecting one or more capacitors from a plurality of capacitors connected in parallel. A transistor drive circuit according to claim 1 or claim 2.

5. Based on the comparison result between the potential of the capacitor and a predetermined reference potential, the period for supplying charge from the power supply to the capacitor, or the period for supplying charge from the capacitor to the power supply, is controlled. A transistor drive circuit according to claim 1 or claim 2.

6. The system includes a timer that sets the time for supplying charge from the power supply to the capacitor, or the time for supplying charge from the capacitor to the power supply, thereby causing the capacitor to function as a variable capacitance capacitor. A transistor drive circuit according to claim 1 or claim 2.

7. The aforementioned driving force limiting circuit is configured as a MOS transistor with variable driving force. A transistor drive circuit according to claim 1 or claim 2.

8. The aforementioned driving force limiting circuit includes a first MOS transistor with variable driving force, A second MOS transistor with a constant driving force is connected in series with the first MOS transistor, It is configured to include, A transistor drive circuit according to claim 1 or claim 2.

9. As the precharge switch, a switch with variable current capacity is used. The transistor drive circuit according to claim 1.

10. The control circuits for the pre-charge switch and the charge switch use an inverter. The transistor drive circuit according to claim 1.

11. A non-overlap clock generation circuit is used as the control circuit for the pre-charge switch and the charge switch. The transistor drive circuit according to claim 1.

12. The aforementioned delay time adjustment circuit includes a capacitor that stores a charge corresponding to the driving force limiting potential, Prior to transitioning the gate potential to the driving force limiting potential, a precharge switch supplies charge from the power supply to the capacitor, or supplies charge from the capacitor to the power supply. A current mirror circuit receives the current from the capacitor as a reference current and electrically outputs an output current m (where m is any number greater than 1) times the reference current to the gate of the driven transistor. A charge switch that supplies the current from the capacitor as the reference current to the current mirror circuit when transitioning the gate potential to the driving force limiting potential, A transistor drive circuit according to claim 1 or claim 2, comprising:

13. The aforementioned delay time adjustment circuit includes a capacitor that stores a charge corresponding to the driving force limiting potential, Prior to transitioning the gate potential to the driving force limiting potential, an inverter circuit supplies charge from the power supply to the capacitor, or supplies charge from the capacitor to the power supply. A transistor drive circuit according to claim 1 or claim 2, comprising:

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