Semiconductor equipment

Abstract

To provide a semiconductor device with reduced leakage current, especially useful for a power device.SOLUTION: A semiconductor device has at least an n+ type semiconductor layer, an n-type semiconductor layer disposed on the n+ type semiconductor layer, a high resistivity layer at least partially embedded in the n-type semiconductor layer, and a Schottky electrode forming a Schottky junction with the n-type semiconductor layer, and the n+ type semiconductor layer and the n-type semiconductor layer each contain a crystalline oxide semiconductor as a major component, and the edge of the Schottky electrode is located on the high resistance layer, and the depth d (μm) of the portion of the high resistance layer that is embedded in the n-type semiconductor layer satisfies d≥1.4.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a semiconductor device useful as a power device or the like. [Background technology]

[0002] Gallium oxide (Ga2O3) is a transparent semiconductor with a broad band gap of 4.8-5.3 eV at room temperature and absorbs almost no visible or ultraviolet light. Therefore, it is a promising material for use in optoelectronic devices and transparent electronics, particularly those operating in the deep ultraviolet region. In recent years, photodetectors, light-emitting diodes (LEDs), and transistors based on gallium oxide (Ga2O3) have been developed (see Non-Patent Document 1). According to Patent Document 3, the band gap of gallium oxide can be controlled by forming a mixed crystal with indium or aluminum, either individually or in combination, forming an extremely attractive material system as an InAlGaO-based semiconductor. Here, an InAlGaO-based semiconductor refers to In X Al Y Ga Z It exhibits the O3 property (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5~2.5) and can be viewed as part of the same material system containing gallium oxide.

[0003] Furthermore, gallium oxide (Ga2O3) has five crystal structures: α, β, γ, σ, and ε, and generally the most stable structure is β-Ga2O3. However, since β-Ga2O3 is a β-gallia structure, it differs from the crystal systems generally used in electronic materials, and is not necessarily suitable for use in semiconductor devices. In addition, the growth of β-Ga2O3 thin films requires high substrate temperatures and high vacuum levels, which increases manufacturing costs. Also, as described in Non-Patent Literature 2, β-Ga2O3 is suitable for high concentrations (e.g., 1 × 10⁻⁶). 19 / cm 3 Even the dopants (Si) mentioned above could not be used as donors unless they were annealed at high temperatures of 800°C to 1100°C after ion implantation. On the other hand, α-Ga2O3 has the same crystal structure as the already widely used sapphire substrate, making it suitable for use in optoelectronic devices. Furthermore, because it has a wider band gap than β-Ga2O3, it is particularly useful for power devices. For this reason, semiconductor devices using α-Ga2O3 as a semiconductor are eagerly awaited.

[0004] Patent Document 1 discloses a Schottky barrier diode comprising a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide provided on the semiconductor substrate, an anode electrode that makes Schottky contact with the drift layer, and a cathode electrode that makes ohmic contact with the semiconductor substrate, wherein the drift layer has an outer periphery trench provided at a position surrounding the anode electrode in a plan view. Patent Document 2 discloses a crystal stacking structure comprising a Ga2O3-based high-resistance crystal layer containing Mg and ion implantation damage and having a thickness of 750 nm or less, and an impurity concentration gradient layer below the Ga2O3-based high-resistance crystal layer having a thickness of 100 nm or more, in which the concentration of Mg is lower than that of the Ga2O3-based high-resistance crystal layer and the concentration of Mg is gradient in the depth direction. However, the semiconductor devices described in Patent Documents 1 and 2 suffer from leakage current problems near the Schottky electrode ends or at the interface between the Schottky electrode and the high-resistance crystal layer, and have not been able to produce a semiconductor device that is practically satisfactory. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2019-050290 [Patent Document 2] Patent No. 6344718 [Patent Document 3] International Publication No. 2014 / 050793 [Non-patent literature]

[0006] [Non-Patent Document 1] Jun Liang Zhao et al, “UV and Visible Electroluminescence From a Sn:Ga2O3 / n+-Si Heterojunction by Metal-Organic Chemical Vapor Deposition”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO.5 MAY 2011 [Non-Patent Document 2] Kohei Sasaki et al, “Si-Ion Implantation Doping in β-Ga2O3 and Its Application to Fabrication of Low-Resistance Ohmic Contacts”, Applied Physics Express 6 (2013) 086502 [Summary of the Invention] [Problems to be Solved by the Invention]

[0007] An object of the present invention is to provide a semiconductor device with suppressed leakage current. [Means for Solving the Problems]

[0008] As a result of intensive studies to achieve the above object, the inventors have found that a semiconductor device comprising at least an n+-type semiconductor layer, an n-type semiconductor layer disposed on the n+-type semiconductor layer, a high-resistance layer at least partially embedded in the n-type semiconductor layer, and a Schottky electrode forming a Schottky junction with the n-type semiconductor layer, wherein the n+-type semiconductor layer and the n-type semiconductor layer each contain a crystalline oxide semiconductor as a main component, an end portion of the Schottky electrode is located on the high-resistance layer, and a depth d (μm) of a portion of the high-resistance layer embedded in the n-type semiconductor layer satisfies d≧1.4 μm, can reduce leakage current, and have found that the semiconductor device thus obtained can solve the above-described conventional problems. After obtaining the above findings, the inventors of the present invention further conducted extensive studies and ultimately completed the present invention.

[0009] That is, the present invention relates to the following inventions. [1] A semiconductor device comprising at least an n+-type semiconductor layer, an n−-type semiconductor layer disposed on the n+-type semiconductor layer, a high-resistance layer at least partially embedded in the n−-type semiconductor layer, and a Schottky electrode forming a Schottky junction with the n−-type semiconductor layer, where the n+-type semiconductor layer and the n−-type semiconductor layer each contain a crystalline oxide semiconductor as a main component, an end portion of the Schottky electrode is located on the high-resistance layer, and a depth d (μm) of a portion of the high-resistance layer embedded in the n−-type semiconductor layer satisfies d≧1.4. [2] The semiconductor device according to [1], where the depth d satisfies d>1.5. [3] When a rated voltage is applied to the semiconductor device, with a depletion layer width extending from the Schottky junction being W1 (μm) and a depletion layer width extending from the lower end of the high-resistance layer being W2 (μm), the semiconductor device according to [1] or [2], where the depth d, the depletion layer width W1, and the depletion layer width W2 satisfy the relational expression (W2 + d)−W1≧−1.0. [4] The semiconductor device according to any one of [1] to [3], where the crystalline oxide semiconductor contains one or more metals selected from aluminum, indium, and gallium. [5] The semiconductor device according to any one of [1] to [4], where the crystalline oxide semiconductor contains at least gallium. [6] The semiconductor device according to any one of [1] to [5], where the crystalline oxide semiconductor has a corundum structure or a β-gallium structure. [7] The semiconductor device according to any one of [1] to [6], where a distance between a bottom surface of the high-resistance layer and an upper surface of the n+-type semiconductor layer is 1.0 μm or less. [8] The semiconductor device according to any one of [1] to [7], wherein the bottom surface of the high-resistance layer is at the same height as the interface between the n+-type semiconductor layer and the n--type semiconductor layer, or is located below the interface between the n+-type semiconductor layer and the n--type semiconductor layer. [9] The semiconductor device according to any one of [1] to [8], wherein the high-resistance layer comprises SiO2.

[10] The semiconductor device according to any one of [1] to [9], further comprising an insulating layer formed on the n-type semiconductor layer, wherein the end of the Schottky electrode is located on the insulating layer.

[11] A semiconductor device according to any of [1] to

[10] above, wherein the depletion layer width W1 extending from the Schottky junction when a rated voltage is applied to the semiconductor device is defined by the following formula.

number

[12] The semiconductor device according to

[11] , wherein the depletion layer width W2 extending from the lower end of the high-resistance layer when a rated voltage is applied to the semiconductor device is defined by the following formula.

number

[13] The semiconductor device according to any one of [1] to

[12] , further comprising a passivation film covering the outer end of the Schottky electrode and at least a portion of the surface of the n-semiconductor layer.

[14] A semiconductor device according to any of [1] to

[13] above, which is a diode.

[15] A semiconductor device described in any of [1] to

[14] above, which is a power device.

[16] A power conversion device using a semiconductor device described in any of [1] to

[15] above.

[17] A control system using a semiconductor device described in any of [1] to

[15] above. [Effects of the Invention]

[0010] According to the present invention, leakage current of a semiconductor device can be suppressed. [Brief explanation of the drawing]

[0011] [Figure 1] This figure schematically shows a Schottky barrier diode (SBD) according to an embodiment of the present invention. [Figure 2] This figure schematically illustrates a preferred manufacturing process for a Schottky barrier diode (SBD) according to an embodiment of the present invention. [Figure 3] This figure schematically shows a Schottky barrier diode (SBD) according to an embodiment of the present invention. [Figure 4] This is a diagram showing the configuration of a mist CVD apparatus used in this embodiment of the present invention. [Figure 5] This figure shows the simulation results in the examples and comparative examples. [Figure 6] This figure shows the simulation results in the examples and comparative examples. [Figure 7] This is a block diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention. [Figure 8] This is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention. [Figure 9] This is a block diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention. [Figure 10] This is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention. [Figure 11]This figure schematically shows a Schottky barrier diode (SBD) according to an embodiment of the present invention. [Figure 12] This figure shows the results of cross-sectional scanning electron microscopy (SEM) observations in the examples. [Figure 13] This figure shows the results of cross-sectional scanning electron microscopy (SEM) observations in the comparative example. [Figure 14] This figure shows the results of IV measurements in the examples and comparative examples. [Figure 15] This figure shows the results of the IV measurement in the example. [Figure 16] This figure shows the calculated relationship between the embedding depth in the n-type semiconductor layer of the high-resistance layer and the maximum electric field strength within the high-resistance layer. [Figure 17] This figure schematically shows a Schottky barrier diode (SBD) according to another embodiment of the present invention. [Figure 18] This figure shows the results of IV measurements in the examples. The vertical and horizontal axes represent arbitrary units. [Modes for carrying out the invention]

[0012] The semiconductor device of the present invention comprises at least an n+ type semiconductor layer, an n- type semiconductor layer disposed on the n+ type semiconductor layer, a high-resistance layer in which at least a portion is embedded in the n- type semiconductor layer, and a Schottky electrode that forms a Schottky junction with the n- type semiconductor layer, wherein the n+ type semiconductor layer and the n- type semiconductor layer each contain a crystalline oxide semiconductor as the main component, the end of the Schottky electrode is located on the high-resistance layer, and the depth d (μm) of the portion of the high-resistance layer embedded in the n- type semiconductor layer satisfies d ≥ 1.4 μm. In the present invention, it is preferable that the depth d satisfies d > 1.5 μm, and more preferably that d ≥ 2.0. Furthermore, in embodiments of the present invention, when a rated voltage is applied to the semiconductor device, it is preferable that the depth d, the depletion layer width W1, and the depletion layer width W2 satisfy the relationship (W2+d)-W1≧-1, where W1 (μm) is the depletion layer width extending from the Schottky junction and W2 (μm) is the depletion layer width extending from the lower end of the high-resistance layer.

[0013] The n+-type semiconductor layer is not particularly limited as long as it has a carrier density higher than that of the n−-type semiconductor layer and contains a crystalline oxide semiconductor as a main component. Examples of the crystalline oxide semiconductor include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In an embodiment of the present invention, the crystalline oxide semiconductor preferably contains at least one metal selected from aluminum, indium, and gallium, more preferably contains at least gallium, and most preferably is α-Ga2O3 or a mixed crystal thereof. According to an embodiment of the present invention, even when a semiconductor having a large bandgap such as gallium oxide or a mixed crystal thereof is used, the leakage current can be favorably reduced. The crystal structure of the crystalline oxide semiconductor is not particularly limited as long as it does not inhibit the object of the present invention. Examples of the crystal structure of the crystalline oxide semiconductor include a corundum structure, a β-gallia structure, a hexagonal crystal structure (e.g., an ε-type structure, etc.), an orthorhombic crystal structure (e.g., a κ-type structure, etc.), a cubic crystal structure, or a tetragonal crystal structure. In an embodiment of the present invention, the crystalline oxide semiconductor preferably has a corundum structure, a β-gallia structure, or a hexagonal crystal structure (e.g., an ε-type structure, etc.), and more preferably has a corundum structure. Note that the “main component” means that the crystalline oxide semiconductor is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, still more preferably 90% or more, and may be 100% with respect to all components of the n+-type semiconductor layer. Also, the thickness of the n+-type semiconductor layer is not particularly limited and may be 1 μm or less or 1 μm or more. In an embodiment of the present invention, the thickness of the n+-type semiconductor layer is preferably 1 μm or more, and more preferably 3 μm or more. The area of the semiconductor film in plan view is not particularly limited, and may be 1 mm 2 or more, or may be 1 mm 2 or less, but is preferably 10 mm 2 to 300 cm 2 and more preferably 100 mm 2 to 100 cm 2It is more preferable that this is the case. Furthermore, the +-type semiconductor layer is usually a single crystal, but it may also be polycrystalline. The carrier density of the semiconductor layer can be appropriately set by adjusting the doping amount.

[0014] The n+ type semiconductor layer preferably contains a dopant. The dopant is not particularly limited and may be a known dopant. In embodiments of the present invention, particularly when the semiconductor layer is mainly composed of a crystalline oxide semiconductor containing gallium, preferred examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium. In embodiments of the present invention, the n-type dopant is preferably Sn, Ge, or Si. The dopant content is preferably 0.00001 atomic% or more, more preferably 0.00001 atomic% to 20 atomic% in the composition of the semiconductor layer, and most preferably 0.00001 atomic% to 10 atomic%. More specifically, the dopant concentration is usually about 1 × 10⁻⁶ 16 / cm 3 ~1 × 10 22 / cm 3 This may also be the case. In this embodiment of the present invention, the dopant is approximately 1 × 10⁻⁶ 20 / cm 3 It may be included at the above high concentration. In this embodiment of the present invention, 1 × 10 17 / cm 3 It is preferable to include the carrier at the above concentrations.

[0015] The n-type semiconductor layer is not particularly limited as long as it has a lower carrier density than the n+-type semiconductor layer and contains a crystalline oxide semiconductor as its main component. Examples of the crystalline oxide semiconductor include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In embodiments of the present invention, the crystalline oxide semiconductor preferably contains at least one metal selected from aluminum, indium, and gallium, more preferably contains at least gallium, and most preferably is α-Ga2O3 or a mixed crystal thereof. In embodiments of the present invention, the crystalline oxide semiconductor that is the main component of the n+-type semiconductor layer and the crystalline oxide semiconductor that is the main component of the n-type semiconductor layer may be the same or different. The crystal structure of the crystalline oxide semiconductor is also not particularly limited as long as it does not hinder the objectives of the present invention. Examples of the crystal structure of the crystalline oxide semiconductor include a corundum structure, a β-gallia structure, a hexagonal structure (e.g., an ε-type structure), an orthorhombic structure (e.g., a κ-type structure), a cubic structure, or a tetragonal structure. In the embodiments of the present invention, it is preferable that the crystalline oxide semiconductor has a corundum structure, a β-gallia structure, or a hexagonal structure (e.g., an ε-type structure), and it is more preferable that it has a corundum structure. The term "main component" means that the crystalline oxide semiconductor is preferably present in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more, of the total components of the n-type semiconductor layer, and may be 100%. The thickness of the n-type semiconductor layer is not particularly limited and may be 1 μm or less, or 1 μm or more, but in the embodiments of the present invention, it is preferably 3 μm or more. The area of ​​the semiconductor film in plan view is not particularly limited, but may be 1 mm 2 More than that is also fine, or 1mm 2 The following is also acceptable, but 10mm 2 ~300cm 2 Preferably, 100 mm 2 ~100cm 2It is more preferable that this is the case. Furthermore, the semiconductor layer is usually a single crystal, but it may also be polycrystalline. The carrier density of the semiconductor layer can be appropriately set by adjusting the doping amount.

[0016] The n-type semiconductor layer may contain a dopant. The dopant is not particularly limited and may be a known dopant. In embodiments of the present invention, in particular when the semiconductor layer is mainly composed of a crystalline oxide semiconductor containing gallium, suitable examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium. In embodiments of the present invention, the n-type dopant is preferably Sn, Ge, or Si. The dopant content is preferably 0.00001 atomic% or more, more preferably 0.00001 atomic% to 20 atomic%, and most preferably 0.00001 atomic% to 10 atomic% in the composition of the semiconductor layer. More specifically, the dopant concentration is usually about 1 × 10⁻⁶ 16 / cm 3 ~1 × 10 22 / cm 3 Alternatively, the concentration of the dopant may be set to, for example, approximately 1 × 10⁻⁶. 17 / cm 3 The following low concentrations may also be used.

[0017] The aforementioned high-resistance layer is typically 1.0 × 10 6 It has a resistance of Ω·cm or more. In this embodiment of the present invention, the resistance of the high-resistance layer is 1.0 × 10 10 Preferably, the resistance is Ω·cm or greater, and the resistance of the high-resistance layer is 1.0 × 10⁻⁶ 12 It is more preferable that the resistance is Ω·cm or greater. The resistance can be measured by forming measuring electrodes on the high-resistance layer and passing a current through them. There is no particular upper limit to the resistance. The upper limit of the resistance is preferably 1.0 × 10⁻⁶. 15 It is Ω·cm, and more preferably 1.0 × 10⁻⁶. 14The resistance is Ω·cm. The constituent material of the high-resistance layer is not particularly limited as long as it does not hinder the objective of the present invention. In embodiments of the present invention, it is preferable that the high-resistance layer is an insulating layer. In this case, examples of the constituent material of the high-resistance layer include SiO2, phosphorus-doped SiO2 (PSG), boron-doped SiO2, phosphorus-boron-doped SiO2 (BPSG), etc. Examples of means for forming the high-resistance layer include CVD method, atmospheric pressure CVD method, plasma CVD method, mist CVD method, etc. In embodiments of the present invention, it is preferable that the means for forming the high-resistance layer is mist CVD method or atmospheric pressure CVD method. In embodiments of the present invention, it is also preferable that the main component of the high-resistance layer is the crystalline oxide semiconductor. When the main component of the high-resistance layer is the crystalline oxide semiconductor, it is also preferable that the high-resistance layer contains a p-type dopant. Examples of the p-type dopant include magnesium, calcium, zinc, etc.

[0018] The high-resistance layer satisfies d≧1.4, where d(μm) is the depth of the portion of the high-resistance layer embedded in the n-type semiconductor layer. In the embodiment of the present invention, it is preferable that the depth d(μm) satisfies d>1.5, and more preferably that d≧2.0. Furthermore, in the embodiments of the present invention, when a rated voltage is applied to the semiconductor device, it is more preferable that the depletion layer width extending from the Schottky junction is W1 (μm) and the depletion layer width extending from the lower end of the high-resistance layer is W2 (μm), and that the depth d, the depletion layer width W1, and the depletion layer width W2 satisfy the relationship (W2+d)-W1≧-1. By adopting such a preferred configuration, electric field concentration can be reduced more effectively. In addition, as described above, the semiconductor device can be made smaller by configuring the bottom surface of the high-resistance layer to be at the same height as the interface between the n+-type semiconductor layer and the n--type semiconductor layer, or below the interface between the n+-type semiconductor layer and the n--type semiconductor layer. In addition, in the embodiments of the present invention, the bottom surface of the high-resistance layer may be at the same height as the interface between the n+-type semiconductor layer and the n--type semiconductor layer, or it may be located below the interface between the n+-type semiconductor layer and the n--type semiconductor layer. By adopting such a preferred configuration, the semiconductor device can be made to have reduced leakage current.

[0019] Furthermore, in the embodiments of the present invention, it is preferable that the depletion layer width W1 extending from the Schottky junction when a rated voltage is applied to the semiconductor device is defined by the following formula (1).

[0020]

number

[0021] In embodiments of the present invention, it is preferable that the depletion layer width W2 extending from the lower end of the high-resistance layer when a rated voltage is applied to the semiconductor device is defined by the following formula (2).

[0022]

number

[0023] The n+-type semiconductor layer and the n--type semiconductor layer (hereinafter also simply referred to as "semiconductor layer" or "semiconductor film") may be formed using known means. Examples of means for forming the semiconductor layer include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulse growth, or ALD. In embodiments of the present invention, the means for forming the semiconductor layer is preferably MOCVD, mist CVD, mist epitaxy, or HVPE, and preferably mist CVD or mist epitaxy. In the aforementioned mist CVD method or mist epitaxy method, for example, using the mist CVD apparatus shown in Figure 4, the raw material solution is atomized (atomization step), the droplets are suspended, the atomized droplets are transported to the substrate using a carrier gas after atomization (transportation step), and then the atomized droplets are subjected to a thermal reaction near the substrate to deposit a semiconductor film mainly composed of a crystalline oxide semiconductor on the substrate (film formation step), thereby forming the semiconductor layer.

[0024] (Atomization process) The atomization step atomizes the raw material solution. The atomization means for the raw material solution is not particularly limited as long as it can atomize the raw material solution, and any known means may be used. However, in the embodiments of the present invention, an atomization means using ultrasound is preferred. The atomized droplets obtained using ultrasound are preferred because they have zero initial velocity and float in the air. For example, they are mist that can be transported as a gas while floating in space, rather than being sprayed like a spray, so there is no damage due to collision energy, making them very suitable. The droplet size is not particularly limited and may be several millimeters in size, but is preferably 50 μm or less, and more preferably 100 nm to 10 μm.

[0025] (Raw material solution) The raw material solution is not particularly limited as long as it contains raw materials that can be atomized or dropletized and that can form a semiconductor film, and may be inorganic or organic materials. In embodiments of the present invention, the raw materials are preferably metals or metal compounds, and more preferably contain one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium.

[0026] In embodiments of the present invention, the raw material solution can preferably be a solution in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or a salt. Examples of complexes include acetylacetonate complexes, carbonyl complexes, ammine complexes, and hydride complexes. Examples of salts include organometallic salts (e.g., metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphorylate salts, and metal halide salts (e.g., metal chloride salts, metal bromide salts, metal iodide salts, etc.).

[0027] Furthermore, it is preferable to mix additives such as hydrohalic acid and oxidizing agents into the raw material solution. Examples of hydrohalic acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid, but hydrobromic acid or hydroiodic acid are preferred because they can more efficiently suppress the generation of abnormal particles. Examples of oxidizing agents include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), and benzoyl peroxide (C6H5CO)2O2, as well as organic peroxides such as hypochlorous acid (HClO), perchloric acid, nitric acid, ozonated water, peracetic acid, and nitrobenzene.

[0028] The raw material solution may contain a dopant. By including a dopant in the raw material solution, doping can be performed effectively. The dopant is not particularly limited as long as it does not hinder the objectives of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants such as Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P. The dopant content can be appropriately determined by using a calibration curve that shows the relationship between the concentration of the dopant in the raw material and the desired carrier density.

[0029] The solvent of the raw material solution is not particularly limited and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the embodiments of the present invention, it is preferable that the solvent contains water, and more preferably that it is water or a mixed solvent of water and alcohol.

[0030] (Conveying process) In the transport process, the atomized droplets are transported into the film-forming chamber using a carrier gas. The carrier gas is not particularly limited as long as it does not hinder the objective of the present invention, and suitable examples include inert gases such as oxygen, ozone, nitrogen, and argon, or reducing gases such as hydrogen gas and foaming gas. There may be one type of carrier gas, or there may be two or more types, and a dilution gas with a reduced flow rate (e.g., a 10-fold dilution gas) may be used as a second carrier gas. There may also be two or more locations for supplying the carrier gas, not just one. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, and more preferably 1 to 10 L / min. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L / min, and more preferably 0.1 to 1 L / min.

[0031] (Film forming process) In the film formation process, the semiconductor film is formed on the substrate by thermally reacting the atomized droplets near the substrate. The thermal reaction only needs to involve the reaction of the atomized droplets with heat, and the reaction conditions are not particularly limited as long as they do not hinder the objective of the present invention. In this process, the thermal reaction is usually carried out at a temperature above the evaporation temperature of the solvent, but a temperature that is not too high (e.g., 1000°C) or lower is preferred, 650°C or lower is more preferred, and 300°C to 650°C is most preferred. The thermal reaction may be carried out under any of the following conditions, as long as it does not hinder the objective of the present invention: under vacuum, under a non-oxygen atmosphere (e.g., under an inert gas atmosphere), under a reducing gas atmosphere, or under an oxygen atmosphere, but it is preferred to carry it out under an inert gas atmosphere or an oxygen atmosphere. It may also be carried out under any of the following conditions: under atmospheric pressure, under pressurized pressure, or under reduced pressure, but in the embodiments of the present invention, it is preferred to carry it out under atmospheric pressure. The film thickness can be set by adjusting the film formation time.

[0032] (Base) The substrate is not particularly limited as long as it can support the semiconductor film. The material of the substrate is also not particularly limited as long as it does not hinder the objective of the present invention, and may be a known substrate, an organic compound or an inorganic compound. The shape of the substrate may be any shape and is effective for any shape, such as a plate shape such as a flat plate or disc, a fibrous shape, a rod shape, a cylindrical shape, a prismatic shape, a tubular shape, a spiral shape, a spherical shape, a ring shape, etc., but in the embodiments of the present invention, a substrate is preferred. The thickness of the substrate is not particularly limited in the embodiments of the present invention.

[0033] The substrate is plate-shaped and is not particularly limited as long as it serves as a support for the semiconductor film. It may be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate, but it is preferable that the substrate is an insulating substrate, and it is also preferable that the substrate has a metal film on its surface. Examples of the substrate include a base substrate mainly composed of a substrate material having a corundum structure, a base substrate mainly composed of a substrate material having a β-gallia structure, and a base substrate mainly composed of a substrate material having a hexagonal crystal structure. Here, "main component" means that the substrate material having the specific crystal structure is preferably present in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the substrate material, and may be 100%.

[0034] The substrate material is not particularly limited and may be a known material, as long as it does not hinder the objectives of the present invention. Examples of substrate materials having the corundum structure include, for example, α-Al2O3 (sapphire substrate) or α-Ga2O3, with a-plane sapphire substrates, m-plane sapphire substrates, r-plane sapphire substrates, c-plane sapphire substrates, and α-type gallium oxide substrates (a-plane, m-plane, or r-plane) being more preferred examples. Examples of underlayment substrates mainly composed of substrate materials having a β-gallia structure include β-Ga2O3 substrates, or mixed crystal substrates containing Ga2O3 and Al2O3, where Al2O3 is more than 0 wt% and 60 wt% or less. Examples of underlayment substrates mainly composed of substrate materials having a hexagonal structure include SiC substrates, ZnO substrates, and GaN substrates.

[0035] In embodiments of the present invention, an annealing treatment may be performed after the film formation step. The annealing treatment temperature is not particularly limited as long as it does not hinder the objective of the present invention, and is usually 300°C to 650°C, preferably 350°C to 550°C. The annealing treatment time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. The annealing treatment may be performed under any atmosphere as long as it does not hinder the objective of the present invention. It may be under a non-oxygen atmosphere or an oxygen atmosphere. Examples of non-oxygen atmospheres include an inert gas atmosphere (e.g., a nitrogen atmosphere) or a reducing gas atmosphere, but in embodiments of the present invention, an inert gas atmosphere is preferred, and a nitrogen atmosphere is more preferred.

[0036] Furthermore, in embodiments of the present invention, the semiconductor film may be provided directly on the substrate, or it may be provided via other layers such as a stress relaxation layer (e.g., a buffer layer, an ELO layer, etc.) or a delamination sacrificial layer. The means for forming each layer are not particularly limited and may be known means, but in embodiments of the present invention, the mist CVD method is preferred.

[0037] In embodiments of the present invention, the semiconductor film may be used as the semiconductor layer in a semiconductor device after being peeled off from the substrate or the like by known means, or it may be used as the semiconductor layer in a semiconductor device as is.

[0038] The Schottky electrode is not particularly limited as long as it is capable of forming a Schottky junction with the n-type semiconductor layer. The constituent material of the Schottky electrode may be a conductive inorganic material or a conductive organic material. In embodiments of the present invention, it is preferable that the constituent material of the Schottky electrode is a metal. Preferably, the metal is at least one metal selected from groups 4 to 10 of the periodic table. Examples of metals from group 4 of the periodic table include titanium (Ti), zirconium (Zr), and hafnium (Hf). Examples of metals from group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of metals from group 6 of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of metals from group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals in Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals in Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals in Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt). The thickness of the Schottky electrode is not particularly limited, but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm. In embodiments of the present invention, the Schottky electrode may include a first electrode layer provided on the n-type semiconductor layer and a second electrode layer provided on the first electrode layer. In embodiments of the present invention, it is preferable that the thickness of the first electrode layer is thinner than the thickness of the second electrode layer. In embodiments of the present invention, it is also preferable that the work function of the first electrode layer is greater than the work function of the second electrode layer. By adopting such a preferred configuration for the first electrode layer, it is possible to obtain a semiconductor device with superior Schottky characteristics, as well as to better exhibit the effect of improving reverse breakdown voltage. Furthermore, in the embodiment of the present invention, the Schottky electrode may be a single layer or may be composed of two or more metal layers.

[0039] The means for forming the Schottky electrode is not particularly limited and may be a known method. Specific examples of the means for forming the Schottky electrode include dry methods and wet methods. Examples of dry methods include sputtering, vacuum deposition, and CVD. Examples of wet methods include screen printing and die coating.

[0040] In embodiments of the present invention, it is also preferable that the semiconductor device further has an insulating layer formed on the n-type semiconductor layer, and that the end of the Schottky electrode is located on the insulating layer. The constituent material of the insulating layer is not particularly limited as long as it does not hinder the objective of the present invention, and may be a known material. Examples of the insulating layer include an SiO2 film, a phosphorus-doped SiO2 film (PSG film), a boron-doped SiO2 film, a phosphorus-boron-doped SiO2 film (BPSG film), and the like. Examples of means for forming the insulating layer include CVD, atmospheric pressure CVD, plasma CVD, and mist CVD. In embodiments of the present invention, it is preferable that the means for forming the insulating layer is mist CVD or atmospheric pressure CVD. Furthermore, in embodiments of the present invention, it is also preferable that the semiconductor device has a passivation film formed that covers the outer end of the Schottky electrode and at least a part of the surface of the n-type semiconductor layer. By adopting such a preferred configuration, the leakage current of the semiconductor device can be suppressed more effectively. The constituent material and forming means of the passivation film may be the same as those of the insulating layer.

[0041] The semiconductor device of the present invention is useful for various semiconductor elements, and is particularly useful for power devices. Semiconductor elements can be classified into horizontal elements (horizontal devices) in which electrodes are formed on one side of the semiconductor layer and current flows in the direction of the thickness of the semiconductor layer and in the in-plane direction of the film plane, and vertical elements (vertical devices) in which electrodes are formed on both the front and back sides of the semiconductor layer and current flows in the direction of the thickness of the semiconductor layer. In the embodiments of the present invention, the semiconductor element can be suitably used as both a horizontal and a vertical device, but its use as a vertical device is particularly preferred. Examples of the semiconductor element include Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSs), metal-semiconductor field-effect transistors (MESFETs), metal-insulating semiconductor field-effect transistors (MISFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), high electron-mobility transistors (HEMTs), and light-emitting diodes. In the embodiments of the present invention, the semiconductor device is preferably a diode, and more preferably a Schottky barrier diode (SBD).

[0042] The following describes preferred examples of the semiconductor device with reference to the drawings, but the present invention is not limited to these embodiments. In the semiconductor device illustrated below, other layers (e.g., insulating layers, semi-insulating layers, conductive layers, semiconductor layers, buffer layers, or other intermediate layers) may be included, as long as they do not hinder the objective of the present invention, and buffer layers may also be omitted as appropriate.

[0043] Figure 1 shows the main components of a Schottky barrier diode (SBD), which is one of the preferred embodiments of the present invention. The SBD in Figure 1 comprises an ohmic electrode 102, an n+ type semiconductor layer 101b, an n- type semiconductor layer 101a, a high-resistance layer 106, and a Schottky electrode 103. In the semiconductor device shown in Figure 1, the depth d (μm) of the portion of the high-resistance layer 106 embedded in the n-type semiconductor layer 101a is 1.4 or more. This configuration allows for a good reduction in the leakage current of the semiconductor device. In this embodiment of the present invention, it is also preferable that at least a portion of the inner side surface of the high-resistance layer 106 has a tapered shape such that the area of ​​the high-resistance layer 106 increases when viewed in plan from the Schottky electrode 103 side toward the ohmic electrode 102 side. This preferred structure allows for a better reduction in electric field concentration on the surface. Examples of constituent materials for the Schottky electrode and / or ohmic electrode include the metals exemplified as constituent materials for the Schottky electrode. The means for forming each layer in Figure 1 are not particularly limited and may be known means, as long as they do not hinder the objectives of the present invention. Examples include means of forming a film by vacuum deposition, CVD, sputtering, or various coating techniques followed by patterning by photolithography, or means of directly patterning using printing technology. Figure 16 shows the calculated relationship between the embedding depth d (μm) of the high-resistance layer and the maximum electric field strength (V / cm) within the high-resistance layer when a rated voltage of 600V is applied to the semiconductor device shown in Figure 1. In Figure 16, the calculation results are shown when SiO2 is used as the high-resistance layer and an α-Ga2O3 layer is used as the n-type semiconductor layer. As is clear from Figure 16, by setting the embedding depth d of the high-resistance layer within the n-type semiconductor layer to 1.4 μm or more, a semiconductor device with excellent dielectric strength, at least 600V or more, can be obtained in relation to the dielectric breakdown field of the high-resistance layer.

[0044] To verify the effects of the embodiment of the present invention, a simulation was performed simulating the semiconductor device shown in Figure 1. The simulation was performed assuming the use of α-Ga2O3 as the n+-type semiconductor layer and n--type semiconductor layer, and SiO2 as the high-resistance layer. Figure 5 shows the simulation results of the potential distribution (reverse voltage: 600V) (equipotential lines are shown in red. The spacing is 60V) for the case where the depth d of the portion of the high-resistance layer embedded in the n-type semiconductor layer is 1.5 μm, 2.0 μm, 2.5 μm, and 3.0 μm. Figure 6 shows the simulation results of the current density for the case where the depth d is 1.5 μm, 2.0 μm, 2.5 μm, and 3.0 μm. As is clear from Figures 5 and 6, it can be seen that the current density between the Schottky electrode and the edge of the high-resistance layer is significantly reduced when the depth d (μm) satisfies d > 1.5. Furthermore, it can be seen that an even better reduction in leakage current can be obtained when the depth d satisfies d ≥ 2.0 and d ≥ 2.5. Furthermore, Figure 5 also shows the values ​​of the relationship formula "(W2+d)-W1" between depth d, depletion layer width W1, and depletion layer width W2 for depths d of 1.5 μm, 2.0 μm, 2.5 μm, and 3.0 μm, respectively. As is clear from Figures 5 and 6, the leakage current can be reduced most effectively when depth d, depletion layer width W1, and depletion layer width W2 satisfy the relationship formula (W2+d)-W1>-1.0.

[0045] Table 1 shows the results of calculating and comparing the defect current generated due to defects at the interface between the side surface of the high-resistance layer and the side surface of the n-type semiconductor layer when gallium oxide is used as the n-type semiconductor layer and when SiC or GaN is used as the n-type semiconductor layer. It was assumed that the current generated due to defects in the depletion layer on the side surface is proportional to the intrinsic carrier density, and was calculated from the ratio of intrinsic carrier densities considering the band gap of each material. Note that each value in Table 1 represents the magnitude of the defect current when the magnitude of the defect current in the case of 4H-SiC is set to 1. As is clear from Table 1, it was found that when gallium oxide is used as the n-type semiconductor layer, the defect current generated due to defects at the interface between the side surface of the high-resistance layer and the side surface of the n-type semiconductor layer is significantly reduced compared to when SiC or GaN is used as the n-type semiconductor layer. In other words, it can be seen that the structure in which a high-resistance layer is embedded in an n-type semiconductor layer, as shown in Figure 1, is particularly suitable for semiconductor devices using gallium oxide. Furthermore, it was found that when α-Ga2O3 is used as the n-type semiconductor layer, the leakage current generated due to defects at the interface is further reduced compared to when β-Ga2O3 is used.

[0046] [Table 1] *This shows the magnitude of the defect current when the magnitude of the defect current in the case of 4H-SiC is set to 1.

[0047] The present invention will be described in more detail below using a preferred example of manufacturing the semiconductor device shown in Figure 1.

[0048] Figure 2(a) shows a laminate in which an n+-type semiconductor layer 101b and an n--type semiconductor layer 101a are formed in that order on an ohmic electrode 102, and a trench is formed in the n--type semiconductor layer 101a. The trench is formed using a known etching method or the like. Here, when forming the trench, the trench is formed so that the distance between the bottom surface of the trench and the top surface of the n+-type semiconductor layer 101b is less than 1.5 μm. Next, a high-resistance layer 106 is formed on the laminate of Figure 2(a) to obtain the laminate of Figure 2(b). Here, after forming the high-resistance layer 106, the surface of the n--type semiconductor layer and / or the high-resistance layer 106 may be polished using CMP or the like. Examples of methods for forming the high-resistance layer 106 include sputtering, vacuum deposition, coating, CVD, atmospheric pressure CVD, plasma CVD, and mist CVD. Next, Schottky electrodes 103 are formed on the laminate shown in Figure 2(b) using the dry method or the wet method and photolithography method to obtain the laminate shown in Figure 2(c). In the semiconductor device obtained in this manner, the depth d (μm) of the portion of the high-resistance layer 106 embedded in the n-type semiconductor layer 101b satisfies d ≥ 1.4. With this configuration, the leakage current of the semiconductor device can be reduced effectively.

[0049] Figure 3 shows the main part of a Schottky barrier diode (SBD), which is another preferred embodiment of the present invention. The SBD in Figure 3 differs from the SBD in Figure 1 in that it further has an insulating layer 104, and the ends of the Schottky electrodes 103 are located on the insulating layer 104. This configuration makes it possible to improve the breakdown voltage characteristics of the semiconductor device. The means for forming each layer in Figure 3 are not particularly limited as long as they do not hinder the objective of the present invention, and may be known means. For example, means of forming a film by vacuum deposition, CVD, sputtering, various coating techniques followed by patterning by photolithography, or means of directly patterning using printing technology.

[0050] Figure 4 shows the main part of a Schottky barrier diode (SBD), which is another preferred embodiment of the present invention. The SBD in Figure 4 differs from the SBD in Figure 1 in that the high-resistance layer 106 has a first region 106a located inside the semiconductor device and a second region 106b located outside the semiconductor device, the distance between the bottom surface of the first region 106a and the n+ type semiconductor layer 101b is less than 1.5 μm (this distance is depicted as zero in Figure 4), and the bottom surface of the second region 106b is located above the bottom surface of the first region. The means for forming each layer in Figure 4 are not particularly limited and may be known means as long as they do not hinder the objectives of the present invention. For example, means of forming a film by vacuum deposition, CVD, sputtering, various coating techniques followed by patterning by photolithography, or means of directly patterning using printing techniques.

[0051] Figure 11 shows the main part of a Schottky barrier diode (SBD), which is another preferred embodiment of the present invention. The SBD in Figure 11 differs from the SBD in Figure 1 in that a high-resistance layer 107 is formed between the high-resistance layer 106 and the n-type semiconductor layer 101a. In the SBD of Figure 11, the high-resistance layer 106 is, for example, a high-resistance layer obtained by impurity doping of an oxide semiconductor. This oxide semiconductor is an epitaxial film formed based on the crystal structure of the n-layer semiconductor 101a. By adopting such a configuration, defects that tend to occur at the interface between the high-resistance layer and the n-semiconductor layer can be reduced, enabling further high voltage resistance of the semiconductor device. The means for forming each layer other than the high-resistance layer 107 in Figure 11 are not particularly limited as long as they do not hinder the objective of the present invention, and may be known means. For example, means of forming a film by vacuum deposition, CVD, sputtering, various coating techniques followed by patterning by photolithography, or means of directly patterning using printing technology. Figure 17 also shows the main part of a Schottky barrier diode (SBD), which is another preferred embodiment of the present invention. The SBD in Figure 17 differs from the SBD in Figure 1 in that it comprises a passivation film 108 that covers at least a portion of the surface of the n-type semiconductor layer 101a and the outer edge of the Schottky electrode 103. This preferred configuration further reduces the leakage current when a reverse voltage is applied. In this embodiment of the present invention, it is preferable that, in a plan view, the passivation film 108 covers at least a portion of the high-resistance layer 106, and more preferably covers the outer edge of the high-resistance layer 106. Furthermore, in this embodiment of the present invention, it is more preferable that, in a plan view, the passivation film 108 covers the surface of the semiconductor layer 101a all the way to the outer edge.

[0052] The semiconductor device is particularly useful for power devices. Examples of the semiconductor device include diodes (e.g., PN diodes, Schottky barrier diodes, junction barrier Schottky diodes, etc.) or transistors (e.g., MOSFETs, MESFETs, etc.).

[0053] The semiconductor device according to the above-described embodiment of the present invention can be applied to power conversion devices such as inverters and converters in order to perform the functions described above. More specifically, it can be applied as a diode built into an inverter or converter, or as a switching element such as a thyristor, power transistor, IGBT (Insulated Gate Bipolar Transistor), or MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Figure 7 is a block diagram showing an example of a control system using the semiconductor device according to the embodiment of the present invention, and Figure 8 is a circuit diagram of the same control system, which is a control system particularly suitable for installation in electric vehicles.

[0054] As shown in Figure 7, the control system 500 includes a battery (power source) 501, a boost converter 502, a buck converter 503, an inverter 504, a motor (driven object) 505, and a drive control unit 506, all of which are mounted on an electric vehicle. The battery 501 is a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and stores power through charging at a power supply station or regenerative energy during deceleration, and can output a DC voltage necessary for the operation of the electric vehicle's drive system and electrical system. The boost converter 502 is a voltage converter equipped with a chopper circuit, for example, and can boost a DC voltage of, for example, 200V supplied from the battery 501 to, for example, 650V by the switching operation of the chopper circuit, and output it to the drive system such as a motor. Similarly, the step-down converter 503 is a voltage conversion device equipped with a chopper circuit, but it can step down a DC voltage of, for example, 200V supplied from the battery 501 to, for example, about 12V, and output it to the electrical system, including power windows, power steering, or on-board electrical equipment.

[0055] The inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by switching operation and outputs it to the motor 505. The motor 505 is a three-phase AC motor that constitutes the traction system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from the inverter 504. This rotational driving force is transmitted to the wheels of the electric vehicle via a transmission (not shown) and the like.

[0056] Meanwhile, various sensors (not shown) are used to measure actual values ​​such as wheel rotation speed, torque, and accelerator pedal depression (accelerator amount) from the electric vehicle while it is in motion, and these measurement signals are input to the drive control unit 506. At the same time, the output voltage value of the inverter 504 is also input to the drive control unit 506. The drive control unit 506 functions as a controller equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as memory. It generates control signals using the input measurement signals and outputs them as feedback signals to the inverter 504, thereby controlling the switching operation of the switching elements. As a result, the AC voltage supplied by the inverter 504 to the motor 505 is corrected instantaneously, enabling accurate operation control of the electric vehicle and realizing safe and comfortable operation of the electric vehicle. It is also possible to control the output voltage to the inverter 504 by supplying the feedback signal from the drive control unit 506 to the boost converter 502.

[0057] Figure 8 shows the circuit configuration excluding the step-down converter 503 in Figure 7, i.e., the configuration for driving the motor 505. As shown in the figure, the semiconductor device of the present invention is used for switching control by being employed, for example, as a Schottky barrier diode in the step-up converter 502 and the inverter 504. In the step-up converter 502, it is incorporated into a chopper circuit to perform chopper control, and in the inverter 504, it is incorporated into a switching circuit including an IGBT to perform switching control. In addition, current stabilization is achieved by interposing an inductor (such as a coil) at the output of the battery 501, and voltage stabilization is achieved by interposing capacitors (such as electrolytic capacitors) between the battery 501, the step-up converter 502, and the inverter 504.

[0058] Furthermore, as shown by the dotted line in Figure 8, the drive control unit 506 is equipped with a calculation unit 507 consisting of a CPU (Central Processing Unit) and a storage unit 508 consisting of non-volatile memory. Signals input to the drive control unit 506 are provided to the calculation unit 507, which performs the necessary calculations to generate feedback signals for each semiconductor element. The storage unit 508 temporarily holds the calculation results from the calculation unit 507 and stores physical constants and functions necessary for drive control in the form of a table, outputting them to the calculation unit 507 as appropriate. The calculation unit 507 and the storage unit 508 can employ known configurations, and their processing capabilities can be arbitrarily selected.

[0059] As shown in Figures 7 and 8, in the control system 500, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the switching operation of the boost converter 502, buck converter 503, and inverter 504. By using gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3), as the material for these semiconductor elements, the switching characteristics are significantly improved. Furthermore, by applying the semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be achieved. In other words, the boost converter 502, buck converter 503, and inverter 504 can each be expected to benefit from the effects of the present invention, and the effects of the present invention can be expected in any one of these, any combination of two or more, or in any configuration including the drive control unit 506. Furthermore, the control system 500 described above can be applied not only to the control system of an electric vehicle using the semiconductor device of the present invention, but also to control systems for a wide range of applications, such as boosting or stepping down power from a DC power source, or converting DC to AC power. It is also possible to use a power source such as a solar cell as the battery.

[0060] Figure 9 is a block diagram showing another example of a control system employing a semiconductor device according to an embodiment of the present invention, and Figure 10 is a circuit diagram of the same control system. This control system is suitable for installation in infrastructure equipment and home appliances that operate on power from an AC power source.

[0061] As shown in Figure 9, the control system 600 receives power supplied from an external source, such as a three-phase AC power supply (power source) 601, and includes an AC / DC converter 602, an inverter 604, a motor (to be driven) 605, and a drive control unit 606, which can be mounted on various devices (described later). The three-phase AC power supply 601 is, for example, a power generation facility of a power company (thermal power plant, hydroelectric power plant, geothermal power plant, nuclear power plant, etc.), and its output is supplied as AC voltage after being stepped down via a substation. Alternatively, it may be installed in a building or nearby facility in the form of a private generator, for example, and supplied via power cables. The AC / DC converter 602 is a voltage converter that converts AC voltage to DC voltage, converting the 100V or 200V AC voltage supplied from the three-phase AC power supply 601 into a predetermined DC voltage. Specifically, the voltage conversion converts it to a commonly used desired DC voltage such as 3.3V, 5V, or 12V. If the to be driven is a motor, the conversion to 12V is performed. It is also possible to use a single-phase AC power supply instead of a three-phase AC power supply, and in that case, a similar system configuration can be achieved by using an AC / DC converter with a single-phase input.

[0062] The inverter 604 converts the DC voltage supplied from the AC / DC converter 602 into a three-phase AC voltage by switching operation and outputs it to the motor 605. The form of the motor 604 varies depending on the controlled object, but if the controlled object is a train, it drives the wheels; if it is factory equipment, it drives pumps and various power sources; and if it is home appliances, it drives compressors, etc. It is a three-phase AC motor that is rotationally driven by the three-phase AC voltage output from the inverter 604 and transmits that rotational driving force to the driven object (not shown).

[0063] In addition, many home appliances, for example, can be driven directly using the DC voltage output from the AC / DC converter 602 (e.g., personal computers, LED lighting equipment, video equipment, audio equipment, etc.). In such cases, the inverter 604 is not required for the control system 600, and the DC voltage is supplied to the driven object from the AC / DC converter 602, as shown in Figure 9. In this case, for example, a 3.3V DC voltage is supplied to personal computers, and a 5V DC voltage is supplied to LED lighting equipment, etc.

[0064] Meanwhile, various sensors (not shown) are used to measure actual values ​​such as the rotational speed and torque of the driven object, as well as the temperature and flow rate of the surrounding environment of the driven object. These measurement signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measurement signals, the drive control unit 606 provides a feedback signal to the inverter 604, controlling the switching operation of the switching element. This instantly corrects the AC voltage supplied by the inverter 604 to the motor 605, enabling accurate operation control of the driven object and achieving stable operation of the driven object. Furthermore, as described above, if the driven object can be driven with a DC voltage, it is also possible to use feedback control of the AC / DC converter 602 instead of feedback to the inverter.

[0065] Figure 10 shows the circuit configuration of Figure 9. As shown in the figure, the semiconductor device of the present invention is used for switching control by being employed, for example, as a Schottky barrier diode in the AC / DC converter 602 and inverter 604. The AC / DC converter 602 uses, for example, a Schottky barrier diode configured in a bridge circuit, and performs DC conversion by converting the negative voltage component of the input voltage to a positive voltage and rectifying it. The inverter 604 is incorporated into the switching circuit of the IGBT to perform switching control. Voltage stabilization is achieved by interposing a capacitor (such as an electrolytic capacitor) between the AC / DC converter 602 and the inverter 604.

[0066] Furthermore, as shown by the dotted line in Figure 10, the drive control unit 606 is equipped with a calculation unit 607 consisting of a CPU and a storage unit 608 consisting of non-volatile memory. Signals input to the drive control unit 606 are provided to the calculation unit 607, which performs the necessary calculations to generate feedback signals for each semiconductor element. The storage unit 608 temporarily holds the calculation results from the calculation unit 607 and stores physical constants and functions necessary for drive control in the form of a table, outputting them to the calculation unit 607 as appropriate. The calculation unit 607 and the storage unit 608 can employ known configurations, and their processing capabilities can be arbitrarily selected.

[0067] In such a control system 600, as with the control system 500 shown in Figures 7 and 8, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the rectification and switching operations of the AC / DC converter 602 and inverter 604. By using gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3), as the material for these semiconductor elements, the switching characteristics are improved. Furthermore, by applying the semiconductor film and semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be achieved. In other words, the effects of the present invention can be expected for each of the AC / DC converter 602 and inverter 604, and the effects of the present invention can be expected for any one of them, a combination thereof, or a configuration including the drive control unit 606.

[0068] Although Figures 9 and 10 illustrate the motor 605 as the target to be driven, the target to be driven is not necessarily limited to mechanically operating devices, and can be many devices that require AC voltage. The control system 600 is applicable as long as it drives the target to be driven by inputting power from an AC power source, and can be installed for drive control of infrastructure equipment (e.g., power equipment in buildings and factories, communication equipment, traffic control equipment, water and wastewater treatment equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (e.g., refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.). [Examples]

[0069] (Example 1) Following the manufacturing method described above, a Schottky barrier diode (SBD) with a structure similar to that shown in Figure 1 was fabricated, and an IV measurement was performed. The depth of the portion of the high-resistance layer embedded in the n-type semiconductor layer was set to 1.7 μm. Figure 12 shows the results of observing the cross-section of the obtained semiconductor device. The IV measurement results showed that the breakdown voltage of the obtained semiconductor device was 850 V. It was found that, according to the embodiment of the present invention, a high-voltage semiconductor device can be obtained because the leakage current is reduced. The results of the IV measurement are shown in Figure 14.

[0070] (Comparative Example 1) An SBD was fabricated in the same manner as in Example 1, except that the depth of the portion of the high-resistance layer embedded in the n-type semiconductor layer was set to 1.1 μm. The results of observing the cross-section of the obtained semiconductor device are shown in Figure 13. The breakdown voltage of the obtained semiconductor device was 385 V as a result of IV measurement. The results of the IV measurement are shown in Figure 14.

[0071] (Example 2) A semiconductor device was fabricated in the same manner as in Example 1, except that the high-resistance layer was formed such that the depth of the portion embedded in the n-type semiconductor layer was 2.0 μm or more. IV measurements were performed on the obtained semiconductor device in the same manner as in Example 1. The results of the IV measurements are shown in Figure 15. As is clear from Figure 15, it was found that the leakage current was further reduced compared to Example 1.

[0072] (Example 3) As shown in Figure 17, a semiconductor device was fabricated in accordance with Example 1, except that a passivation film was formed in addition to the high-resistance layer. For comparison, a device with a high-resistance layer was also fabricated. Figure 18(a) shows the IV measurement results with the passivation film, and Figure 18(b) shows the IV measurement results without the passivation film (high-resistance layer only). As is clear from Figure 18, the leakage current can be further reduced by using a passivation film in combination with the high-resistance layer. [Industrial applicability]

[0073] The semiconductor device of the present invention can be used in a wide range of fields, including semiconductors (e.g., compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic equipment, and industrial materials, but is particularly useful as a power device. [Explanation of Symbols]

[0074] 1. Film deposition apparatus (mist CVD apparatus) 2a Carrier gas source 2b Carrier gas (dilution) source 3a Flow control valve 3b Flow control valve 4. Mist source 4a Raw material solution 4b Raw material fine particles 5 containers 5a water 6. Ultrasonic transducer 7 Deposition chamber 8. Hot plate 9 Supply pipe 10 circuit boards 101 Semiconductor layer 101a n-type semiconductor layer 101b n+ type semiconductor layer 102 Ohmic Electrode 103 Schottky electrode 104 Insulator layer 106 High resistance layer 106a First area 106b Second area 107 High resistance layer 500 Control Systems 501 Battery (Power Supply) 502 Boost Converter 503 Step-Down Converter 504 Inverter 505 Motor (Driven object) 506 Drive Control Unit 507 Arithmetic section 508 Storage section 600 Control System 601 Three-phase AC power supply (power supply) 602 AC / DC Converter 604 Inverter 605 Motor (Driven object) 606 Drive Control Unit 607 Arithmetic section 608 Storage section

Claims

1. A semiconductor device comprising at least an n+ type semiconductor layer, an n- type semiconductor layer disposed on the n+ type semiconductor layer, a high-resistance layer in which at least a portion is embedded in the n- type semiconductor layer, and a Schottky electrode that forms a Schottky junction with the n- type semiconductor layer, A semiconductor device characterized in that the n+-type semiconductor layer and the n--type semiconductor layer each contain a crystalline oxide semiconductor as the main component, the crystalline oxide semiconductor of the n--type semiconductor layer contains gallium and has a corundum structure or a β-gallia structure, the high-resistance layer has a resistance of 1.0 × 10⁶ Ω·cm or more, the end of the Schottky electrode is located on the high-resistance layer, and for the portion of the high-resistance layer embedded in the n--type semiconductor layer, the depth d (μm) of the Schottky electrode with respect to the end located on the high-resistance layer satisfies d ≥ 1.

5.

2. The semiconductor device according to claim 1, wherein the depth d satisfies d > 1.

5.

3. The semiconductor device according to claim 1 or 2, wherein when a rated voltage is applied to the semiconductor device, the depletion layer width extending from the Schottky junction is W1 (μm), and the depletion layer width extending from the lower end of the high-resistance layer is W2 (μm), and the depth d, the depletion layer width W1, and the depletion layer width W2 satisfy the relationship (W2 + d) - W1 ≥ -1.

0.

4. The semiconductor device according to claim 1 or 2, wherein the distance between the bottom surface of the high-resistance layer and the top surface of the n+-type semiconductor layer is 1.0 μm or less.

5. The semiconductor device according to claim 1 or 2, wherein the bottom surface of the high-resistance layer is at the same height as the interface between the n+-type semiconductor layer and the n--type semiconductor layer, or is located below the interface between the n+-type semiconductor layer and the n--type semiconductor layer.

6. The high-resistance layer is SiO ２ A semiconductor device according to claim 1 or 2, including the following:

7. Furthermore, the semiconductor device according to claim 1 or 2, wherein it has an insulating layer formed on the n-type semiconductor layer, and the end of the Schottky electrode is located on the insulating layer.

8. The semiconductor device according to claim 1 or 2, wherein the depletion layer width W1 extending from the Schottky junction when a rated voltage is applied to the semiconductor device is defined by the following formula. [Math 1] [In the formula, ε １ is the dielectric constant (F / cm) of the n-type semiconductor layer, V is the rated current (V), q is the elementary charge (C), and Nd is the donor density (cm) of the n-type semiconductor layer. －３ These represent the following:

9. The semiconductor device according to claim 8, wherein the depletion layer width W2 extending from the lower end of the high-resistance layer when a rated voltage is applied to the semiconductor device is defined by the following formula. [Math 2] [In the formula, ε １ The dielectric constant (F / cm) of the n-type semiconductor layer is ε. ２ is the dielectric constant of the high-resistance layer (F / cm), d is the depth (cm) of the portion of the high-resistance layer embedded in the n-type semiconductor layer, V is the rated voltage (V), q is the elementary charge (C), and W1 is the depletion layer width (cm) extending from the Schottky junction when the rated voltage is applied.

10. The semiconductor device according to claim 1 or 2, further comprising a passivation film covering the outer end of the Schottky electrode and at least a portion of the surface of the n-semiconductor layer.

11. A semiconductor device according to claim 1 or 2, which is a diode.

12. A semiconductor device according to claim 1 or 2, which is a power device.

13. A power conversion device using the semiconductor device described in claim 1 or 2.

14. A control system using a semiconductor device according to claim 1 or 2.

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