Waveguide

Abstract

This waveguide comprises: three or more conductor layers that are stacked; two or more dielectric layers that are stacked, each being formed between two conductor layers adjacent to each other among the three or more conductor layers; and a first via group and a second via group each including one or more vias disposed in at least one dielectric layer among the two or more dielectric layers. The first via group and the second via group are arrayed in parallel. Among the vias included in the first via group and the second via group, the vias disposed in at least one of the two or more dielectric layers differ in position on the plane of the dielectric layer from the vias disposed in the remaining dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to a waveguide.

Background Art

[0002] As a method of forming a waveguide on a dielectric substrate, there is an example of forming a waveguide by providing conductors above and below the dielectric and providing a number of vias for electrically connecting these conductors. Such waveguides may be called post-wall waveguides, SIW (Substrate Integrated Waveguide), etc. The basic configuration of these waveguides uses a single layer of dielectric substrate, but there are also examples of forming a waveguide on such a multi-layer dielectric substrate using a multi-layer dielectric substrate (see, for example, Patent Document 1).

[0003] In the configuration of forming a post-wall waveguide on a multi-layer dielectric substrate, which is an existing technology, the posts of a plurality of layers are formed at the same location when viewed from the axial direction perpendicular to the substrate. When using through-holes as these posts, they penetrate all layers of the multi-layer substrate, making it difficult to form other circuits in the upper and lower layers of the post-wall waveguide, and losing the advantage of forming dielectric layers above and below the post-wall waveguide.

[0004] When forming posts using laser vias, it is conceivable to configure the post-wall waveguide 20 shown in FIGS. 2A to 2D using stacked vias shown in FIG. 1A, which has a configuration where vias are stacked directly above each other. Hereinafter, those with vias stacked directly above all layers will be called full-stack vias, and the post-wall waveguide using full-stack vias may be called a post-wall waveguide with a full-stack configuration, a full-stack post-wall waveguide, etc. However, the shape of the vias is not limited to the shapes shown in FIGS. 1A and 1B, and in the description of the post-wall waveguide in this specification, the vias are described as having a cylindrical shape.

[0005] Figure 2A is a perspective view of a fully stacked post-wall waveguide 20 containing two sets (two rows) of vias parallel to the Y-axis. Figure 2B is a cross-sectional view of the a23-a24 plane of the fully stacked post-wall waveguide 20 as seen from the Y-axis direction. Figure 2C is a cross-sectional view of the c21-c22 plane, the c23-c24 plane, and the c25-c26 plane of the fully stacked post-wall waveguide 20 as seen from the Z-axis direction (vertical direction, stacking direction). Figure 2D is a cross-sectional view of a portion of the a21-a22 plane of the fully stacked post-wall waveguide 20 as seen from the X-axis direction.

[0006] For example, as shown in Figure 2D, a fully stacked post-wall waveguide 20 includes four stacked dielectric layers 2-1-1 to 2-1-4, five stacked conductor layers 2-2-1 to 2-2-5, and two sets of vias 2-3-1-k to 2-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in the example shown in Figures 2A to 2D, N = 14). Vias 2-3-1-1 to 2-3-1-N are equally spaced in a plane perpendicular to the Z-axis, and similarly, vias 2-3-2-1 to 2-3-2-N, vias 2-3-3-1 to 2-3-3-N, and vias 2-3-4-1 to 2-3-4-N. Each dielectric layer is formed between two adjacent conductor layers in the Z-axis direction, provided that each dielectric layer is in contact with an adjacent dielectric layer if there is no conductor in the conductor layer. Note that one set of the two sets of vias 2-3-1-k ~ 2-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2)) corresponds to via group A shown in Figure 2C, and the other set corresponds to via group B shown in Figure 2C, which is the via group on the a21-a22 plane shown in Figure 2D.

[0007] As shown in Figures 2C and 2D, the waveguide 20 is composed of the lowest conductor layer 2-2-1 and the uppermost conductor layer 2-2-5 in the central part, and via group A and via group B. As shown in Figure 2C, when a high-frequency electromagnetic wave is input from IO1, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO2, and when an electromagnetic wave is input from IO2, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO1. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2008-193663 [Overview of the project]

[0009] However, fully stacking vias (stacking vias directly on top of each other in all layers) carries the risk of failure due to thermal expansion, which can lead to reduced reliability and lower yield during waveguide manufacturing.

[0010] Non-limiting embodiments of this disclosure contribute to providing waveguides that can reduce the risk of failure due to thermal expansion associated with full stacking of vias, thereby suppressing reduced reliability and yield during manufacturing.

[0011] A waveguide according to one embodiment of the present disclosure comprises three or more stacked conductor layers, two or more stacked dielectric layers formed between two adjacent conductor layers among the three or more conductor layers, and a first via group and a second via group, each including one or more vias disposed inside at least one of the dielectric layers among the two or more dielectric layers, wherein the first via group and the second via group are arranged in parallel, and among the vias included in the first via group and the second via group, the vias disposed in at least one of the two or more dielectric layers are positioned differently on the dielectric layer plane from the vias disposed in the remaining dielectric layers.

[0012] According to one embodiment of the present disclosure, the vias constituting the waveguide do not overlap all of the dielectric layers constituting the waveguide when viewed from the stacking direction. As a result, the vias are not fully stacked, which reduces the risk of damage due to thermal expansion associated with fully stacking the vias, thereby suppressing a decrease in reliability and a deterioration in yield.

[0013] Further advantages and effects of one embodiment of this disclosure will be made apparent from the specification and drawings. Such advantages and / or effects are provided by several embodiments and features described in the specification and drawings, but not all of them are necessarily provided in order to obtain one or more identical features. [Brief explanation of the drawing]

[0014] [Figure 1A] Diagram showing the configuration of stack vias [Figure 1B] Diagram showing the configuration of staggered vias. [Figure 2A] Perspective view of a post-wall waveguide using full-stack vias. [Figure 2B] Cross-sectional view of a post-wall waveguide using full-stack vias, viewed from the Y-axis direction. [Figure 2C] Cross-sectional view of a post-wall waveguide using full-stack vias, viewed from the Z-axis direction. [Figure 2D] Partial cross-sectional view of a post-wall waveguide using full-stack vias, viewed from the X-axis direction. [Figure 3A] A perspective view showing an example of a post-wall waveguide according to Embodiment 1 of this disclosure. [Figure 3B] A cross-sectional view from the Y-axis direction showing an example of a post-wall waveguide according to Embodiment 1 of this disclosure. [Figure 3C] A cross-sectional view from the Z-axis direction showing an example of a post-wall waveguide according to Embodiment 1 of this disclosure. [Figure 3D] A partial cross-sectional view from the X-axis direction showing an example of a post-wall waveguide according to Embodiment 1 of this disclosure. [Figure 4A] A perspective view showing an example of a post-wall waveguide according to Embodiment 2 of this disclosure. [Figure 4B] A cross-sectional view from the Y-axis direction showing an example of a post-wall waveguide according to Embodiment 2 of this disclosure. [Figure 4C] A cross-sectional view from the Z-axis direction showing an example of a post-wall waveguide according to Embodiment 2 of this disclosure. [Figure 4D] A partial cross-sectional view from the X-axis direction showing an example of a post-wall waveguide according to Embodiment 2 of this disclosure. [Figure 5A] Perspective view showing an example of a post-wall waveguide according to Embodiment 3 of the present disclosure [Figure 5B] Cross-sectional view taken from the Y-axis direction showing an example of a post-wall waveguide according to Embodiment 3 of the present disclosure [Figure 5C] Cross-sectional view taken from the Z-axis direction showing an example of a post-wall waveguide according to Embodiment 3 of the present disclosure [Figure 5D] Partial cross-sectional view taken from the X-axis direction showing an example of a post-wall waveguide according to Embodiment 3 of the present disclosure [Figure 6] Figure showing an example of simulation results of losses of a post-wall waveguide using full-stack vias and post-wall waveguides according to Embodiments 1 to 3 of the present disclosure [Figure 7A] Perspective view showing an example of a post-wall waveguide according to Embodiment 4 of the present disclosure [Figure 7B] Cross-sectional view taken from the Y-axis direction showing an example of a post-wall waveguide according to Embodiment 4 of the present disclosure [Figure 7C] Cross-sectional view taken from the Z-axis direction showing an example of a post-wall waveguide according to Embodiment 4 of the present disclosure [Figure 7D] Partial cross-sectional view taken from the X-axis direction showing an example of a post-wall waveguide according to Embodiment 4 of the present disclosure [Figure 8A] Perspective view showing an example of a post-wall waveguide according to Embodiment 5 of the present disclosure [Figure 8B] Cross-sectional view taken from the Y-axis direction showing an example of a post-wall waveguide according to Embodiment 5 of the present disclosure [Figure 8C] Cross-sectional view taken from the Z-axis direction showing an example of a post-wall waveguide according to Embodiment 5 of the present disclosure [Figure 8D] Partial cross-sectional view taken from the X-axis direction showing an example of a post-wall waveguide according to Embodiment 5 of the present disclosure [Figure 9A] Perspective view showing an example of a post-wall waveguide according to Embodiment 6 of the present disclosure [Figure 9B] Cross-sectional view taken from the Y-axis direction showing an example of a post-wall waveguide according to Embodiment 6 of the present disclosure [Figure 9C]A cross-sectional view from the Z-axis direction showing an example of a post-wall waveguide according to Embodiment 6 of this disclosure. [Figure 9D] A partial cross-sectional view from the X-axis direction showing an example of a post-wall waveguide according to Embodiment 6 of this disclosure. [Figure 10] This figure shows an example of simulation results for the loss of a post-wall waveguide using full-stack vias and post-wall waveguides according to embodiments 4 to 6. [Figure 11A] A perspective view showing an example of a post-wall waveguide according to Embodiment 7 of this disclosure. [Figure 11B] A cross-sectional view from the Y-axis direction showing an example of a post-wall waveguide according to Embodiment 7 of this disclosure. [Figure 11C] A cross-sectional view from the Z-axis direction showing an example of a post-wall waveguide according to Embodiment 7 of this disclosure. [Figure 11D] A partial cross-sectional view from the X-axis direction showing an example of a post-wall waveguide according to Embodiment 7 of this disclosure. [Figure 12A] A perspective view showing an example of a post-wall waveguide according to Embodiment 8 of this disclosure. [Figure 12B] A cross-sectional view from the Y-axis direction showing an example of a post-wall waveguide according to Embodiment 8 of this disclosure. [Figure 12C] A cross-sectional view from the Z-axis direction showing an example of a post-wall waveguide according to Embodiment 8 of this disclosure. [Figure 12D] A partial cross-sectional view from the X-axis direction showing an example of a post-wall waveguide according to Embodiment 8 of this disclosure. [Figure 13A] A perspective view showing an example of a post-wall waveguide according to Embodiment 9 of this disclosure. [Figure 13B] A cross-sectional view from the Y-axis direction showing an example of a post-wall waveguide according to Embodiment 9 of this disclosure. [Figure 13C] A cross-sectional view from the Z-axis direction showing an example of a post-wall waveguide according to Embodiment 9 of this disclosure. [Figure 13D] A partial cross-sectional view from the X-axis direction showing an example of a post-wall waveguide according to Embodiment 9 of this disclosure. [Figure 14]This figure shows an example of simulation results for the loss of a post-wall waveguide using full-stack vias and the post-wall waveguide according to embodiments 7 to 9. [Figure 15] This figure shows an example configuration in which the shape of the stub in Embodiment 9 has been changed. [Figure 16A] A perspective view showing an example of a post-wall waveguide in which the stub of Embodiment 9 is replaced with an EBG. [Figure 16B] A cross-sectional view from the Y-axis direction showing an example of a post-wall waveguide in which the stub of Embodiment 9 has been changed to an EBG. [Figure 16C] A cross-sectional view from the Z-axis direction showing an example of a post-wall waveguide in which the stub of Embodiment 9 has been changed to an EBG. [Figure 16D] A partial cross-sectional view from the X-axis direction showing an example of a post-wall waveguide in which the stub of Embodiment 9 has been changed to an EBG. [Modes for carrying out the invention]

[0015] The embodiments of this disclosure will be described in detail below, with reference to the drawings as appropriate. However, some unnecessarily detailed explanations may be omitted. For example, detailed explanations of already well-known matters and redundant explanations of substantially identical configurations may be omitted. This is to avoid the following explanation becoming unnecessarily verbose and to facilitate understanding for those skilled in the art.

[0016] The attached drawings and the following description are provided to enable a person skilled in the art to fully understand this disclosure, and are not intended to limit the subject matter described in the claims.

[0017] (Embodiment 1) In Embodiment 1 of this disclosure, a post-wall waveguide is constructed using staggered vias, as shown in Figure 1B, which have a configuration in which the via positions are shifted in a step-like manner, rather than stacked vias. Therefore, in staggered vias, in a multilayer dielectric substrate, the vias are arranged at different positions for each adjacent layer when viewed from the Z-axis direction.

[0018] Figure 3A is a perspective view showing an example of a post-wall waveguide 30 according to Embodiment 1. Figure 3B is a cross-sectional view of the a33-a34 plane and a35-a36 plane showing an example of a post-wall waveguide 30 viewed from the Y-axis direction. Figure 3C is a cross-sectional view of the c31-c32 plane, a cross-sectional view of the c33-c34 plane, a section view of the c35-c36 plane, and a cross-sectional view of the c37-c38 plane showing an example of a post-wall waveguide 30 viewed from the Z-axis direction. Figure 3D is a partial cross-sectional view of the a31-a32 plane showing an example of a post-wall waveguide 30 viewed from the X-axis direction.

[0019] For example, as shown in Figure 3D, the post-wall waveguide 30 includes four dielectric layers 3-1-1 to 3-1-4, five conductor layers 3-2-1 to 3-2-5, and two sets of vias 3-3-1-k to 3-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 7). The post-wall waveguide 30 does not include any vias other than the two sets of vias 3-3-1-k to 3-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N).

[0020] Each dielectric layer is formed between two adjacent conductive layers in the Z-axis direction (for example, each conductive layer is formed above or below one of the four dielectric layers 3-1-1 to 3-1-4). However, each dielectric layer is in contact with an adjacent dielectric layer if there is no conductor in the conductive layer.

[0021] Vias 3-3-1-1 to 3-3-1-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 3-3-2-1 to 3-3-2-N, vias 3-3-3-1 to 3-3-3-N, and vias 3-3-4-1 to 3-3-4-N.

[0022] Vias 3-3-1-1 to 3-3-1-N electrically connect two adjacent conductor layers 3-2-1 and 3-2-2, which are formed (stacked) above and below the dielectric layer 3-1-1. Vias 3-3-2-1 to 3-3-2-N electrically connect two adjacent conductor layers 3-2-2 and 3-2-3, which are formed (stacked) above and below the dielectric layer 3-1-2. Vias 3-3-3-1 to 3-3-3-N electrically connect two adjacent conductor layers 3-2-3 and 3-2-4, which are formed (stacked) above and below the dielectric layer 3-1-3. Vias 3-3-4-1 to 3-3-4-N electrically connect two adjacent conductor layers 3-2-4 and 3-2-5, which are formed (stacked) above and below the dielectric layer 3-1-4.

[0023] Two sets of vias 3-3-1-1 to 3-3-1-N are arranged in parallel, two sets of vias 3-3-2-1 to 3-3-2-N are arranged in parallel, two sets of vias 3-3-3-1 to 3-3-3-N are arranged in parallel, and two sets of vias 3-3-4-1 to 3-3-4-N are arranged in parallel. Additionally, two sets of vias 3-3-1-k to 3-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) are also arranged in parallel.

[0024] In this embodiment, as shown in Figures 3C and 3D, the bottom conductor layer 3-2-1 and the top conductor layer 3-2-5 are arranged in a solid plane across the entire surface. However, the bottom conductor layer and the top conductor layer may be placed in the region sandwiched between via group A (one set of two sets of vias 3-3-1-k to 3-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N)) and via group B (the other set of two sets of vias 3-3-1-k to 3-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N)).

[0025] When vias are installed, conductors called via lands, which have a circular shape with a larger radius than the via according to the design rules, may be placed above and below the via. In this embodiment, circular via lands are placed above and below the via in conductor layers 3-2-2 to 3-2-4 (see, for example, the cross-sectional view of plane c35-c36 in Figure 3C). The via lands in conductor layers 3-2-2 to 3-2-4 may or may not be connected to adjacent via lands. In this embodiment, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between vias as narrow as possible, taking into account the constraints of the via lands.

[0026] In this embodiment, by using staggered vias, as shown in Figures 3C and 3D, vias 3-3-1-k and 3-3-3-k are positioned offset in the positive Y-axis direction relative to vias 3-3-2-k and 3-3-4-k when viewed from the Z-axis direction (in the XY plane or dielectric layer plane). On the other hand, as shown in Figures 3C and 3D, vias 3-3-1-k and 3-3-3-k are positioned in the same location when viewed from the Z-axis direction, and vias 3-3-2-k and 3-3-4-k are positioned in the same location when viewed from the Z-axis direction. Furthermore, vias 3-3-1-1 to 3-3-1-N and vias 3-3-2-1 to 3-3-2-N are positioned at equal intervals when viewed from the Z-axis direction, with an interval of half the interval between vias 3-3-1-1 to 3-3-1-N (vias 3-3-2-1 to 3-3-2-N). As shown in Figures 3B and 3D, the two sets of vias 3-3-1-k to 3-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) are not stacked across all four dielectric layers 3-1-1 to 3-1-4, nor are they stacked across two or more of the four dielectric layers 3-1-1 to 3-1-4. For example, the all-conductor layers 3-2-1 to 3-2-5 are not electrically connected via vias at the same location when viewed from the Z-axis direction.

[0027] As shown in Figures 3C and 3D, the waveguide 30 is composed of the lowest conductor layer 3-2-1 and the uppermost conductor layer 3-2-5 in the central part, and via group A and via group B. As shown in Figure 3C, when a high-frequency electromagnetic wave is input from IO1, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO2. When a high-frequency electromagnetic wave is input from IO2, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO1. Via group A and via group B function as conductor walls against electromagnetic waves (they form conductor walls against electromagnetic waves).

[0028] Each of the vias 3-3-1-1~3-3-1-N, 3-3-2-1~3-3-2-N, 3-3-3-1~3-3-3-N, and 3-3-4-1~3-3-4-N from one of the two sets is an example of the first via group relating to this disclosure. Each of the vias 3-3-1-1~3-3-1-N, 3-3-2-1~3-3-2-N, 3-3-3-1~3-3-3-N, and 3-3-4-1~3-3-4-N from the other of the two sets is an example of the second via group relating to this disclosure.

[0029] In this embodiment, all of the two sets of vias 3-3-1-k to 3-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) do not overlap in any of the four dielectric layers 3-1-1 to 3-1-4 when viewed from the Z-axis direction.

[0030] Furthermore, in this embodiment, two sets of vias 3-3-1-1 to 3-3-1-N and two sets of vias 3-3-2-1 to 3-3-2-N are positioned so as not to overlap when viewed from the Z-axis direction. Also, in this embodiment, two sets of vias 3-3-3-1 to 3-3-3-N, two sets of vias 3-3-2-1 to 3-3-2-N and two sets of vias 3-3-4-1 to 3-3-4-N are positioned so as not to overlap when viewed from the Z-axis direction.

[0031] (Embodiment 2) In Embodiment 2 of this disclosure, a post-wall waveguide is constructed using staggered vias, similar to Embodiment 1. However, in Embodiment 2, the conductor layers 3-2-2 to 3-2-4, which had circular via lands in Embodiment 1, are replaced with conductor layers 4-2-2 to 4-2-4, which have linear conductors. Conductor layers 4-2-2 to 4-2-4 are inner layers, while conductor layers 4-2-1 and 4-2-5 are outer layers.

[0032] Figure 4A is a perspective view showing an example of a post-wall waveguide 40 according to Embodiment 2. Figure 4B is a cross-sectional view of the a43-a44 plane and a45-a46 plane showing an example of a post-wall waveguide 40 viewed from the Y-axis direction. Figure 4C is a cross-sectional view of the c41-c42 plane, c43-c44 plane, c45-c46 plane and c47-c48 plane showing an example of a post-wall waveguide 40 viewed from the Z-axis direction. Figure 4D is a partial cross-sectional view of the a41-a42 plane showing an example of a post-wall waveguide 40 viewed from the X-axis direction.

[0033] For example, as shown in Figure 4D, the post-wall waveguide 40 includes four dielectric layers 4-1-1 to 4-1-4, five conductor layers 4-2-1 to 4-2-5, and two sets of vias 4-3-1-k to 4-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 7). The post-wall waveguide 40 does not include any vias other than the two sets of vias 4-3-1-k to 4-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N).

[0034] Each dielectric layer is formed between two adjacent conductive layers in the Z-axis direction (for example, each conductive layer is formed above or below one of the four dielectric layers 4-1-1 to 4-1-4). However, each dielectric layer is in contact with an adjacent dielectric layer if there is no conductor in the conductive layer.

[0035] Vias 4-3-1-1 to 4-3-1-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 4-3-2-1 to 4-3-2-N, vias 4-3-3-1 to 4-3-3-N, and vias 4-3-4-1 to 4-3-4-N.

[0036] Vias 4-3-1-1 to 4-3-1-N electrically connect two adjacent conductor layers 4-2-1 and 4-2-2, which are formed (stacked) above and below the dielectric layer 4-1-1. Vias 4-3-2-1 to 4-3-2-N electrically connect two adjacent conductor layers 4-2-2 and 4-2-3, which are formed (stacked) above and below the dielectric layer 4-1-2. Vias 4-3-3-1 to 4-3-3-N electrically connect two adjacent conductor layers 4-2-3 and 4-2-4, which are formed (stacked) above and below the dielectric layer 4-1-3. Vias 4-3-4-1 to 4-3-4-N electrically connect two adjacent conductor layers 4-2-4 and 4-2-5, which are formed (stacked) above and below the dielectric layer 4-1-4.

[0037] Two sets of vias 4-3-1-1 to 4-3-1-N are arranged in parallel, two sets of vias 4-3-2-1 to 4-3-2-N are arranged in parallel, two sets of vias 4-3-3-1 to 4-3-3-N are arranged in parallel, and two sets of vias 4-3-4-1 to 4-3-4-N are arranged in parallel. Additionally, two sets of vias 4-3-1-k to 4-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) are also arranged in parallel.

[0038] In this embodiment, as shown in Figures 4C and 4D, the bottom conductor layer 4-2-1 and the top conductor layer 4-2-5 are arranged in a solid plane across the entire surface. However, the bottom conductor layer and the top conductor layer may be placed in the region sandwiched between via group A (one set of two sets of vias 4-3-1-k to 4-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N)) and via group B (the other set of two sets of vias 4-3-1-k to 4-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N)).

[0039] In this embodiment, as described above, linear conductors are arranged in the conductor layers 4-2-2 to 4-2-4 (inner layers) above and below the via, excluding the bottommost conductor layer 4-2-1 and the topmost conductor layer 4-2-5 (outer layer) (see, for example, the cross-sectional view of the c45-c46 plane in Figure 4C). In this embodiment as well, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between vias as narrow as possible, taking into consideration the above constraints.

[0040] In this embodiment as well, by using staggered vias, as shown in Figures 4C and 4D, vias 4-3-1-k and 4-3-3-k are offset in the positive Y-axis direction relative to vias 4-3-2-k and 4-3-4-k when viewed from the Z-axis direction. On the other hand, as shown in Figures 4C and 4D, vias 4-3-1-k and 4-3-3-k are located in the same place when viewed from the Z-axis direction, and vias 4-3-2-k and 4-3-4-k are located in the same place when viewed from the Z-axis direction. Furthermore, vias 4-3-1-1 to 4-3-1-N and vias 4-3-2-1 to 4-3-2-N are equally spaced with a spacing that is half the spacing between vias 4-3-1-1 to 4-3-1-N (vias 4-3-2-1 to 4-3-2-N) when viewed from the Z-axis direction. As shown in Figures 4B and 4D, the two sets of vias 4-3-1-k to 4-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) are not stacked across all four dielectric layers 4-1-1 to 4-1-4, nor are they stacked across two or more of the four dielectric layers 4-1-1 to 4-1-4. For example, the all-conductor layers 4-2-1 to 4-2-5 are not electrically connected via vias at the same location when viewed from the Z-axis direction.

[0041] As shown in Figures 4C and 4D, the waveguide 40 is composed of the lowest conductor layer 4-2-1 and the uppermost conductor layer 4-2-5 in the central part, and via group A and via group B. As shown in Figure 4C, when a high-frequency electromagnetic wave is input from IO1, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO2. When a high-frequency electromagnetic wave is input from IO2, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO1. Via group A and via group B function as conductor walls against electromagnetic waves (they form conductor walls against electromagnetic waves).

[0042] Each of the vias 4-3-1-1~4-3-1-N, 4-3-2-1~4-3-2-N, 4-3-3-1~4-3-3-N, and 4-3-4-1~4-3-4-N from one of the two sets is an example of the first via group relating to this disclosure. Each of the vias 4-3-1-1~4-3-1-N, 4-3-2-1~4-3-2-N, 4-3-3-1~4-3-3-N, and 4-3-4-1~4-3-4-N from the other of the two sets is an example of the second via group relating to this disclosure.

[0043] In this embodiment, all of the two sets of vias 4-3-1-k to 4-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) do not overlap in any of the four dielectric layers 4-1-1 to 4-1-4 when viewed from the Z-axis direction.

[0044] Furthermore, in this embodiment, the two sets of vias 4-3-1-1 to 4-3-1-N and the two sets of vias 4-3-2-1 to 4-3-2-N are positioned so as not to overlap when viewed from the Z-axis direction. Also, in this embodiment, the two sets of vias 4-3-3-1 to 4-3-3-N, the two sets of vias 4-3-2-1 to 4-3-2-N and the two sets of vias 4-3-4-1 to 4-3-4-N are positioned so as not to overlap when viewed from the Z-axis direction.

[0045] (Embodiment 3) In Embodiment 3 of this disclosure, a post-wall waveguide is constructed using staggered vias, similar to Embodiments 1 and 2. On the other hand, in Embodiment 3, the conductor layers 4-2-2 to 4-2-4, which have linear conductors arranged in Embodiment 2, are replaced with conductor layers 5-2-2 to 5-2-4, which have stub-shaped conductors added to the linear conductors.

[0046] Figure 5A is a perspective view showing an example of a post-wall waveguide 50 according to Embodiment 3. Figure 5B is a cross-sectional view of the a53-a54 plane and the a55-a56 plane showing an example of a post-wall waveguide 50 viewed from the Y-axis direction. Figure 5C is a cross-sectional view of the c51-c52 plane, the c53-c54 plane, the c55-c56 plane and the c57-c58 plane showing an example of a post-wall waveguide 50 viewed from the Z-axis direction. Figure 5D is a part of the cross-sectional view of the a51-a52 plane showing an example of a post-wall waveguide 50 viewed from the X-axis direction.

[0047] For example, as shown in Figure 5D, the post-wall waveguide 50 includes four dielectric layers 5-1-1 to 5-1-4, five conductor layers 5-2-1 to 5-2-5, two sets of vias 5-3-1-k to 5-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 7), and three sets of stubs 5-4-1-i to 5-4-2-i (where i is any integer satisfying 1 ≤ i ≤ M (where M is an integer greater than or equal to 2); in this embodiment, M = 13). The post-wall waveguide 50 does not include any vias other than the two sets of vias 5-3-1-k to 5-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N).

[0048] Each dielectric layer is formed between two adjacent conductive layers in the Z-axis direction (for example, each conductive layer is formed above or below one of the four dielectric layers 5-1-1 to 5-1-4). However, each dielectric layer is in contact with an adjacent dielectric layer if there is no conductor in the conductive layer.

[0049] Vias 5-3-1-1 to 5-3-1-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 5-3-2-1 to 5-3-2-N, vias 5-3-3-1 to 5-3-3-N, and vias 5-3-4-1 to 5-3-4-N.

[0050] Vias 5-3-1-1 to 5-3-1-N electrically connect two adjacent conductor layers 5-2-1 and 5-2-2, which are formed (stacked) above and below the dielectric layer 5-1-1. Vias 5-3-2-1 to 5-3-2-N electrically connect two adjacent conductor layers 5-2-2 and 5-2-3, which are formed (stacked) above and below the dielectric layer 5-1-2. Vias 5-3-3-1 to 5-3-3-N electrically connect two adjacent conductor layers 5-2-3 and 5-2-4, which are formed (stacked) above and below the dielectric layer 5-1-3. Vias 5-3-4-1 to 5-3-4-N electrically connect two adjacent conductor layers 5-2-4 and 5-2-5, which are formed (stacked) above and below the dielectric layer 5-1-4.

[0051] Two sets of vias 5-3-1-1 to 5-3-1-N are arranged in parallel, two sets of vias 5-3-2-1 to 5-3-2-N are arranged in parallel, two sets of vias 5-3-3-1 to 5-3-3-N are arranged in parallel, and two sets of vias 5-3-4-1 to 5-3-4-N are arranged in parallel. Additionally, two sets of vias 5-3-1-k to 5-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) are also arranged in parallel.

[0052] Stubs 5-4-1-1 to 5-4-1-M are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to stubs 5-4-2-1 to 5-4-2-M. For example, stubs 5-4-1-1 to 5-4-1-M are arranged at equal intervals along the longitudinal direction of a linear conductor, and stubs 5-4-2-1 to 5-4-2-M are arranged at equal intervals along the longitudinal direction of a linear conductor.

[0053] In this embodiment, as shown in Figures 5C and 5D, the bottom conductor layer 5-2-1 and the top conductor layer 5-2-5 are arranged in a solid plane across the entire surface. However, the bottom conductor layer and the top conductor layer may be placed in the region sandwiched between via group A (one set of two sets of vias 5-3-1-k to 5-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N)) and via group B (the other set of two sets of vias 5-3-1-k to 5-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N)).

[0054] In this embodiment, as described above, linear conductors are arranged in the upper and lower conductor layers 5-2-2 to 5-2-4 of the via (see, for example, the cross-sectional view of the c55-c56 plane in Figure 5C). In this embodiment as well, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between vias as narrow as possible, taking into account the constraints described above. In this embodiment, further, linear and stub-shaped conductors 5-4-1-i to 5-4-2-i are arranged outside the waveguide from the linear conductor (in the vertical direction in the cross-sectional view of the c55-c56 plane in Figure 5C). The length of the linear stub is about 1 / 4 of the wavelength of the electromagnetic wave to be passed through the waveguide in order to suppress electromagnetic wave leakage. In this embodiment as well, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between stubs as narrow as possible, taking into account the line-and-space constraints.

[0055] In this embodiment as well, by using staggered vias, as shown in Figures 5C and 5D, vias 5-3-1-k and 5-3-3-k are positioned offset in the positive Y-axis direction relative to vias 5-3-2-k and 5-3-4-k when viewed from the Z-axis direction. On the other hand, as shown in Figures 5C and 5D, vias 5-3-1-k and 5-3-3-k are positioned in the same location when viewed from the Z-axis direction, and vias 5-3-2-k and 5-3-4-k are positioned in the same location when viewed from the Z-axis direction. Furthermore, vias 5-3-1-1 to 5-3-1-N and vias 5-3-2-1 to 5-3-2-N are positioned at equal intervals, half the distance between vias 5-3-1-1 to 5-3-1-N (vias 5-3-2-1 to 5-3-2-N), when viewed from the Z-axis direction. As shown in Figures 5B and 5D, the two sets of vias 5-3-1-k to 5-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) are not stacked across all four dielectric layers 5-1-1 to 5-1-4, nor are they stacked across two or more of the four dielectric layers 5-1-1 to 5-1-4. The all-conductor layers 5-2-1 to 5-2-5 are not electrically connected via vias at the same location when viewed from the Z-axis direction.

[0056] As shown in Figures 5C and 5D, the waveguide 50 is composed of the lowest conductor layer 5-2-1 and the uppermost conductor layer 5-2-5 in the central part, and via group A and via group B. As shown in Figure 5C, when a high-frequency electromagnetic wave is input from IO1, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO2. When a high-frequency electromagnetic wave is input from IO2, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO1. In this way, via group A and via group B function as a conductor wall against electromagnetic waves (form a conductor wall against electromagnetic waves).

[0057] Each of the vias 5-3-1-1~5-3-1-N, 5-3-2-1~5-3-2-N, 5-3-3-1~5-3-3-N, and 5-3-4-1~5-3-4-N from one of the two sets is an example of the first via group relating to this disclosure. Each of the vias 5-3-1-1~5-3-1-N, 5-3-2-1~5-3-2-N, 5-3-3-1~5-3-3-N, and 5-3-4-1~5-3-4-N from the other of the two sets is an example of the second via group relating to this disclosure.

[0058] In this embodiment, all of the two sets of vias 5-3-1-k to 5-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) do not overlap in any of the four dielectric layers 5-1-1 to 5-1-4 when viewed from the Z-axis direction.

[0059] Furthermore, in this embodiment, the two sets of vias 5-3-1-1 to 5-3-1-N and the two sets of vias 5-3-2-1 to 5-3-2-N are positioned so as not to overlap when viewed from the Z-axis direction. Also, in this embodiment, the two sets of vias 5-3-3-1 to 5-3-3-N, the two sets of vias 5-3-2-1 to 5-3-2-N and the two sets of vias 5-3-4-1 to 5-3-4-N are positioned so as not to overlap when viewed from the Z-axis direction.

[0060] (Effects of Embodiments 1-3) In Figure 6, the configuration of the full-stack post-wall waveguide 20 and the configuration of the post-wall waveguides 30-50 according to Embodiments 1-3 have the same center spacing between vias in adjacent layers. For example, the center spacing between vias in the same layer of the post-wall waveguides 30-50 according to Embodiments 1-3 is twice the center spacing between vias in the same layer of the full-stack post-wall waveguide 20. Therefore, in the post-wall waveguides 30-50 according to Embodiments 1-3, electromagnetic waves are more likely to radiate from between the vias.

[0061] As seen in the loss simulation results in Figure 6, the radiation loss in the full-stack post-wall waveguide 20 is so small that it is difficult to observe visually, whereas the radiation loss in the post-wall waveguides 30 to 50 according to embodiments 1 to 3 is large.

[0062] Thus, from the standpoint of radiation loss, the full-stack post-wall waveguide 20 is considered to have the best performance. However, manufacturing a full-stack post-wall waveguide 20 is very costly, and the yield is poor due to breakage and peeling of the copper foil during manufacturing. Therefore, manufacturing a full-stack post-wall waveguide 20 is not practical.

[0063] Note that in the simulations shown in Figure 6, etc., the via spacing is set to be larger in order to explain the effects of this embodiment and subsequent embodiments. By setting the via spacing of staggered vias to less than 1 / 4 wavelength of the electromagnetic wave to be passed through the waveguide, the radiation loss is extremely small, comparable to that of a full-stack configuration, even with staggered via spacing. How small the via spacing of staggered vias can be depends on the design rules during substrate manufacturing.

[0064] As shown in Embodiments 1 to 3, by arranging vias in a staggered pattern without stacking them, the risk of damage due to thermal expansion can be reduced, thereby suppressing a decrease in reliability and a deterioration in yield. Furthermore, from the viewpoint of suppressing an increase in radiation loss, it is desirable that the spacing between vias be 1 / 4 wavelength or less of the electromagnetic wave to be passed through the waveguide.

[0065] Comparing the simulation results of the losses of post-wall waveguides 30 to 50 according to Embodiments 1 to 3 shown in Figure 6, it can be confirmed that the radiation loss of post-wall waveguides 40 and 50 according to Embodiments 2 and 3 is smaller than that of post-wall waveguide 30 according to Embodiment 1. For example, by arranging linear or stub-shaped conductors in the conductor layers above and below the vias, as in post-wall waveguides 40 and 50 according to Embodiments 2 and 3, the radiation loss can be reduced compared to post-wall waveguide 30 according to Embodiment 1. Furthermore, it can be seen that the conductor loss of post-wall waveguides 40 and 50 according to Embodiments 2 and 3 is smaller than that of post-wall waveguide 30 according to Embodiment 1, confirming that conductor loss can be reduced by arranging linear or stub-shaped conductors.

[0066] (Embodiment 4) In Embodiment 4 of this disclosure, a post-wall waveguide is configured using two rows of staggered vias for the purpose of reducing radiation loss.

[0067] Figure 7A is a perspective view showing an example of a post-wall waveguide 70 according to Embodiment 4. Figure 7B is a cross-sectional view of the a75-a76 plane and a77-a78 plane showing an example of a post-wall waveguide 70 viewed from the Y-axis direction. Figure 7C is a cross-sectional view of the c71-c72 plane, c73-c74 plane, c75-c76 plane and c77-c78 plane showing an example of a post-wall waveguide 70 viewed from the Z-axis direction. Figure 7D is a partial cross-sectional view of the a71-a72 plane and a partial cross-sectional view of the a73-a74 plane showing an example of a post-wall waveguide 70 viewed from the X-axis direction.

[0068] For example, as shown in Figure 7D, the post-wall waveguide 70 includes four dielectric layers 7-1-1 to 7-1-4, five conductor layers 7-2-1 to 7-2-5, two sets of vias 7-3-1-k to 7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 7), and two sets of vias 7-3-5-k to 7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 7). The post-wall waveguide 70 does not include any vias other than the two sets of vias 7-3-1-k to 7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and the two sets of vias 7-3-5-k to 7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N).

[0069] Each dielectric layer is formed between two adjacent conductive layers in the Z-axis direction (for example, each conductive layer is formed above or below one of the four dielectric layers 7-1-1 to 7-1-4). However, each dielectric layer is in contact with an adjacent dielectric layer if there is no conductor in the conductive layer.

[0070] Vias 7-3-1-1 to 7-3-1-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 7-3-2-1 to 7-3-2-N, vias 7-3-3-1 to 7-3-3-N, and vias 7-3-4-1 to 7-3-4-N.

[0071] Furthermore, vias 7-3-5-1 to 7-3-5-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 7-3-6-1 to 7-3-6-N, vias 7-3-7-1 to 7-3-7-N, and vias 7-3-8-1 to 7-3-8-N.

[0072] Vias 7-3-1-1 to 7-3-1-N and vias 7-3-5-1 to 7-3-5-N electrically connect two adjacent conductor layers 7-2-1 and 7-2-2, which are formed (stacked) above and below the dielectric layer 7-1-1. Vias 7-3-2-1 to 7-3-2-N and vias 7-3-6-1 to 7-3-6-N electrically connect two adjacent conductor layers 7-2-2 and 7-2-3, which are formed (stacked) above and below the dielectric layer 7-1-2. Vias 7-3-3-1 to 7-3-3-N and vias 7-3-7-1 to 7-3-7-N electrically connect two adjacent conductor layers 7-2-3 and 7-2-4, which are formed (stacked) above and below the dielectric layer 7-1-3. Vias 7-3-4-1 to 7-3-4-N and vias 7-3-8-1 to 7-3-8-N electrically connect two adjacent conductor layers 7-2-4 and 7-2-5, which are formed (stacked) above and below the dielectric layer 7-1-4.

[0073] Two sets of vias (7-3-1-1~7-3-1-N and 7-3-5-1~7-3-5-N) are arranged in parallel, two sets of vias (7-3-2-1~7-3-2-N and 7-3-6-1~7-3-6-N) are arranged in parallel, two sets of vias (7-3-3-1~7-3-3-N and 7-3-7-1~7-3-7-N) are arranged in parallel, and two sets of vias (7-3-4-1~7-3-4-N and 7-3-8-1~7-3-8-N) are arranged in parallel. Additionally, two sets of vias (7-3-1-k ~ 7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and 7-3-5-k ~ 7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) are arranged in parallel.

[0074] In this embodiment, as shown in Figures 7C and 7D, the bottom conductor layer 7-2-1 and the top conductor layer 7-2-5 are arranged in a solid plane across the entire surface. However, the bottom conductor layer and the top conductor layer may be placed in the region sandwiched between via group A (one of two sets of vias 7-3-1-k to 7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 7-3-5-k to 7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) and via group B (the other of two sets of vias 7-3-1-k to 7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 7-3-5-k to 7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)).

[0075] When vias are installed, conductors called via lands, which have a circular shape with a larger radius than the via based on the design rules, may be placed above and below the via. In this embodiment, circular via lands are placed above and below the via in conductor layers 7-2-2 to 7-2-4 (see, for example, the cross-sectional view of the c75-c76 plane in Figure 7C). The via lands in conductor layers 7-2-2 to 7-2-4 may or may not be connected to adjacent via lands. In this embodiment as well, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between vias as narrow as possible, taking into consideration the above constraints.

[0076] In this embodiment, as shown in the lower half of the cross-sectional view of the c73-c74 plane in Figures 7D and 7C, vias 7-3-1-k to 7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged outward in the X-axis direction within a plane perpendicular to the Z-axis direction, while vias 7-3-5-k to 7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged inward in the X-axis direction. For example, vias 7-3-1-k to 7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 7-3-5-k to 7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged in two rows. Furthermore, as shown in the cross-sectional views of the c73-c74 plane and the c77-c78 plane in Figure 7C, the two rows of vias 7-3-1-k to 7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 7-3-5-k to 7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged alternately in the dielectric layers 7-1-1 to 7-1-4, in order to prevent them from overlapping (to prevent them from forming a straight line parallel to the X-axis). More specifically, the two rows of vias 7-3-1-k~7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 7-3-5-k~7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N), shown in the lower half of the cross-sectional view of the c73-c74 plane in Figure 7C, are arranged such that the points obtained by projecting these two rows onto the Y-axis are equally spaced. The same applies to the two rows of vias 7-3-1-k to 7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and 7-3-5-k to 7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) shown in the upper half of the cross-sectional view of the c73-c74 plane in Figure 7C. This makes it possible to suppress electromagnetic wave leakage.

[0077] In this embodiment as well, by using staggered vias in via group A and via group B, as shown in Figures 7C and 7D, vias 7-3-1-k and 7-3-3-k are positioned offset in the positive Y-axis direction relative to vias 7-3-2-k and 7-3-4-k when viewed from the Z-axis direction. On the other hand, as shown in Figures 7C and 7D, vias 7-3-1-k and 7-3-3-k are positioned in the same location when viewed from the Z-axis direction, and vias 7-3-2-k and 7-3-4-k are positioned in the same location when viewed from the Z-axis direction. The same applies to vias 7-3-5-k to 7-3-8-k. As shown in Figures 7B and 7D, the two sets of vias (vias 7-3-1-k to 7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 7-3-5-k to 7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) are not stacked across all four dielectric layers 7-1-1 to 7-1-4, nor are they stacked across two or more of the four dielectric layers 7-1-1 to 7-1-4. For example, the all-conductor layers 7-2-1 to 7-2-5 are not electrically connected via vias at the same location when viewed from the Z-axis direction.

[0078] As shown in Figures 7C and 7D, the waveguide 70 is composed of the lowest conductor layer 7-2-1 and the uppermost conductor layer 7-2-5 in the central part, and via group A and via group B. As shown in Figure 7C, when a high-frequency electromagnetic wave is input from IO1, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO2. When a high-frequency electromagnetic wave is input from IO2, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO1. Via group A and via group B function as conductor walls against electromagnetic waves (they form conductor walls against electromagnetic waves).

[0079] Each of the two sets (vias 7-3-1-1 to 7-3-1-N and vias 7-3-5-1 to 7-3-5-N), (vias 7-3-2-1 to 7-3-2-N and vias 7-3-6-1 to 7-3-6-N), (vias 7-3-3-1 to 7-3-3-N and vias 7-3-7-1 to 7-3-7-N), and (vias 7-3-4-1 to 7-3-4-N and vias 7-3-8-1 to 7-3-8-N) is an example of the first via group relating to this disclosure. Each of the other set of the two sets (vias 7-3-1-1 to 7-3-1-N and vias 7-3-5-1 to 7-3-5-N), (vias 7-3-2-1 to 7-3-2-N and vias 7-3-6-1 to 7-3-6-N), (vias 7-3-3-1 to 7-3-3-N and vias 7-3-7-1 to 7-3-7-N), and (vias 7-3-4-1 to 7-3-4-N and vias 7-3-8-1 to 7-3-8-N) is an example of the second via group relating to this disclosure.

[0080] In this embodiment, all of the two sets of vias (7-3-1-k to 7-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and 7-3-5-k to 7-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) do not overlap in any of the four dielectric layers 7-1-1 to 7-1-4 when viewed from the Z-axis direction.

[0081] (Embodiment 5) In Embodiment 5 of this disclosure, similar to Embodiment 4, a post-wall waveguide is constructed using two rows of staggered vias in via group A and via group B, respectively, for the purpose of reducing radiation loss. On the other hand, in Embodiment 5, the conductor layers 7-2-2 to 7-2-4, which had circular via lands in Embodiment 4, are replaced with conductor layers 8-2-2 to 8-2-4, which have linear conductors. Conductor layers 8-2-2 to 8-2-4 are inner layers, while conductor layers 8-2-1 and 8-2-5 are outer layers.

[0082] Figure 8A is a perspective view showing an example of a post-wall waveguide 80 according to Embodiment 5. Figure 8B is a cross-sectional view of the a85-a86 plane and a87-a88 plane showing an example of a post-wall waveguide 80 viewed from the Y-axis direction. Figure 8C is a cross-sectional view of the c81-c82 plane, c83-c84 plane, c85-c86 plane, and c87-c88 plane showing an example of a post-wall waveguide 80 viewed from the Z-axis direction. Figure 8D is a partial cross-sectional view of the a81-a82 plane and a partial cross-sectional view of the a83-a84 plane showing an example of a post-wall waveguide 80 viewed from the X-axis direction.

[0083] For example, as shown in Figure 8D, the post-wall waveguide 80 includes four dielectric layers 8-1-1 to 8-1-4, five conductor layers 8-2-1 to 8-2-5, two sets of vias 8-3-1-k to 8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 7), and two sets of vias 8-3-5-k to 8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 7). The post-wall waveguide 80 does not include any vias other than the two sets of vias 8-3-1-k to 8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and the two sets of vias 8-3-5-k to 8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N).

[0084] Each dielectric layer is formed between two adjacent conductive layers in the Z-axis direction (for example, each conductive layer is formed above or below one of the four dielectric layers 8-1-1 to 8-1-4). However, each dielectric layer is in contact with an adjacent dielectric layer if there is no conductor in the conductive layer.

[0085] Vias 8-3-1-1 to 8-3-1-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 8-3-2-1 to 8-3-2-N, vias 8-3-3-1 to 8-3-3-N, and vias 8-3-4-1 to 8-3-4-N.

[0086] Furthermore, vias 8-3-5-1 to 8-3-5-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 8-3-6-1 to 8-3-6-N, vias 8-3-7-1 to 8-3-7-N, and vias 8-3-8-1 to 8-3-8-N.

[0087] Vias 8-3-1-1 to 8-3-1-N and vias 8-3-5-1 to 8-3-5-N electrically connect two adjacent conductor layers 8-2-1 and 8-2-2, which are formed (stacked) above and below the dielectric layer 8-1-1. Vias 8-3-2-1 to 8-3-2-N and vias 8-3-6-1 to 8-3-6-N electrically connect two adjacent conductor layers 8-2-2 and 8-2-3, which are formed (stacked) above and below the dielectric layer 8-1-2. Vias 8-3-3-1 to 8-3-3-N and vias 8-3-7-1 to 8-3-7-N electrically connect two adjacent conductor layers 8-2-3 and 8-2-4, which are formed (stacked) above and below the dielectric layer 8-1-3. Vias 8-3-4-1 to 8-3-4-N and vias 8-3-8-1 to 8-3-8-N electrically connect two adjacent conductor layers 8-2-4 and 8-2-5, which are formed (stacked) above and below the dielectric layer 8-1-4.

[0088] Two sets of vias (8-3-1-1~8-3-1-N and 8-3-5-1~8-3-5-N) are arranged in parallel, two sets of vias (8-3-2-1~8-3-2-N and 8-3-6-1~8-3-6-N) are arranged in parallel, two sets of vias (8-3-3-1~8-3-3-N and 8-3-7-1~8-3-7-N) are arranged in parallel, and two sets of vias (8-3-4-1~8-3-4-N and 8-3-8-1~8-3-8-N) are arranged in parallel. Additionally, two sets of vias (8-3-1-k ~ 8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and 8-3-5-k ~ 8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) are arranged in parallel.

[0089] In this embodiment, as shown in Figures 8C and 8D, the bottom conductor layer 8-2-1 and the top conductor layer 8-2-5 are arranged in a solid plane across the entire surface. However, the bottom conductor layer and the top conductor layer may be placed in the region sandwiched between via group A (one of two sets of vias 8-3-1-k to 8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 8-3-5-k to 8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) and via group B (the other of two sets of vias 8-3-1-k to 8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 8-3-5-k to 8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)).

[0090] In this embodiment, as described above, linear conductors are arranged in the conductor layers 8-2-2 to 8-2-4 (inner layers) above and below the via, excluding the bottommost conductor layer 8-2-1 and the topmost conductor layer 8-2-5 (outer layer) (see, for example, the cross-sectional view of the c85-c86 plane in Figure 8C). In this embodiment as well, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between vias as narrow as possible, taking into consideration the constraints described above.

[0091] In this embodiment, as shown in the lower half of the cross-sectional view of the c83-c84 plane in Figures 8D and 8C, vias 8-3-1-k to 8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged outward in the X-axis direction within a plane perpendicular to the Z-axis direction, while vias 8-3-5-k to 8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged inward in the X-axis direction. For example, vias 8-3-1-k to 8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 8-3-5-k to 8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged in two rows. Furthermore, as shown in the cross-sectional views of the c83-c84 plane and the c87-c88 plane in Figure 8C, the two rows of vias 8-3-1-k to 8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 8-3-5-k to 8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged alternately in the dielectric layers 8-1-1 to 8-1-4, with the outer first row and the inner second row alternating, so as not to overlap (so as not to form a straight line parallel to the X-axis). More specifically, the two rows of vias 8-3-1-k~8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 8-3-5-k~8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N), shown in the lower half of the cross-sectional view of the c83-c84 plane in Figure 8C, are arranged such that the points obtained by projecting these two rows onto the Y-axis are equally spaced. The same applies to the two rows of vias 8-3-1-k to 8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and 8-3-5-k to 8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) shown in the upper half of the cross-sectional view of the c3-c4 plane in Figure 8C. This makes it possible to suppress electromagnetic wave leakage.

[0092] In this embodiment as well, by using staggered vias, as shown in Figures 8C and 8D, vias 8-3-1-k and 8-3-3-k are positioned offset in the positive Y-axis direction relative to vias 8-3-2-k and 8-3-4-k when viewed from the Z-axis direction. On the other hand, as shown in Figures 8C and 8D, vias 8-3-1-k and 8-3-3-k are positioned in the same location when viewed from the Z-axis direction, and vias 8-3-2-k and 8-3-4-k are positioned in the same location when viewed from the Z-axis direction. The same applies to vias 8-3-5-k to 8-3-8-k. As shown in Figures 8B and 8D, the two sets of vias (8-3-1-k to 8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and 8-3-5-k to 8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) are not stacked across all four dielectric layers 8-1-1 to 8-1-4, nor are they stacked across two or more of the four dielectric layers 8-1-1 to 8-1-4. For example, the all-conductor layers 8-2-1 to 8-2-5 are not electrically connected via vias at the same location when viewed from the Z-axis direction.

[0093] As shown in Figures 8C and 8D, the waveguide 80 is composed of the lowest conductor layer 8-2-1 and the uppermost conductor layer 8-2-5 in the central part, and via group A and via group B. As shown in Figure 8C, when a high-frequency electromagnetic wave is input from IO1, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO2. When a high-frequency electromagnetic wave is input from IO2, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO1. Via group A and via group B function as conductor walls against electromagnetic waves (they form conductor walls against electromagnetic waves).

[0094] Each of the two sets (vias 8-3-1-1 to 8-3-1-N and vias 8-3-5-1 to 8-3-5-N), (vias 8-3-2-1 to 8-3-2-N and vias 8-3-6-1 to 8-3-6-N), (vias 8-3-3-1 to 8-3-3-N and vias 8-3-7-1 to 8-3-7-N), and (vias 8-3-4-1 to 8-3-4-N and vias 8-3-8-1 to 8-3-8-N) is an example of the first via group relating to this disclosure. Each of the other set of the two sets (vias 8-3-1-1 to 8-3-1-N and vias 8-3-5-1 to 8-3-5-N), (vias 8-3-2-1 to 8-3-2-N and vias 8-3-6-1 to 8-3-6-N), (vias 8-3-3-1 to 8-3-3-N and vias 8-3-7-1 to 8-3-7-N), and (vias 8-3-4-1 to 8-3-4-N and vias 8-3-8-1 to 8-3-8-N) is an example of the second via group relating to this disclosure.

[0095] In this embodiment, all of the two sets of vias (8-3-1-k to 8-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and 8-3-5-k to 8-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) do not overlap in any of the four dielectric layers 8-1-1 to 8-1-4 when viewed from the Z-axis direction.

[0096] (Embodiment 6) In Embodiment 6 of this disclosure, similar to Embodiments 4 and 5, a post-wall waveguide is configured using two rows of staggered vias for the purpose of reducing radiation loss. On the other hand, in Embodiment 6, the conductor layers 8-2-2 to 8-2-4, which have linear conductors arranged in Embodiment 5, are replaced with conductor layers 9-2-2 to 9-2-4, in which stub-shaped conductors are added to the linear conductors.

[0097] Figure 9A is a perspective view showing an example of a post-wall waveguide 90 according to Embodiment 6. Figure 9B is a cross-sectional view of the a95-a96 plane and a97-a98 plane showing an example of a post-wall waveguide 90 viewed from the Y-axis direction. Figure 9C is a cross-sectional view of the c91-c92 plane, c93-c94 plane, c95-c96 plane and c97-c98 plane showing an example of a post-wall waveguide 90 viewed from the Z-axis direction. Figure 9D is a partial cross-sectional view of the a91-a92 plane and a partial cross-sectional view of the a93-a94 plane showing an example of a post-wall waveguide 90 viewed from the X-axis direction.

[0098] For example, as shown in Figure 9D, the post-wall waveguide 90 includes four dielectric layers 9-1-1 to 9-1-4, five conductor layers 9-2-1 to 9-2-5, two sets of vias 9-3-1-k to 9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 7), two sets of vias 9-3-5-k to 9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 7), and three sets of stubs 9-4-1-i to 9-4-2-i (where i is any integer satisfying 1 ≤ i ≤ M (where M is an integer greater than or equal to 2); in this embodiment, M = 13). The post-wall waveguide 90 does not contain any vias other than two sets of vias 9-3-1-k to 9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and two sets of vias 9-3-5-k to 9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N).

[0099] Each dielectric layer is formed between two adjacent conductive layers in the Z-axis direction (for example, each conductive layer is formed above or below one of the four dielectric layers 9-1-1 to 9-1-4). However, each dielectric layer is in contact with an adjacent dielectric layer if there is no conductor in the conductive layer.

[0100] Vias 9-3-1-1 to 9-3-1-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 9-3-2-1 to 9-3-2-N, vias 9-3-3-1 to 9-3-3-N, and vias 9-3-4-1 to 9-3-4-N.

[0101] Furthermore, vias 9-3-5-1 to 9-3-5-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 9-3-6-1 to 9-3-6-N, vias 9-3-7-1 to 9-3-7-N, and vias 9-3-8-1 to 9-3-8-N.

[0102] Vias 9-3-1-1 to 9-3-1-N and vias 9-3-5-1 to 9-3-5-N electrically connect two adjacent conductor layers 9-2-1 and 9-2-2, which are formed (stacked) above and below the dielectric layer 9-1-1. Vias 9-3-2-1 to 9-3-2-N and vias 9-3-6-1 to 9-3-6-N electrically connect two adjacent conductor layers 9-2-2 and 9-2-3, which are formed (stacked) above and below the dielectric layer 9-1-2. Vias 9-3-3-1 to 9-3-3-N and vias 9-3-7-1 to 9-3-7-N electrically connect two adjacent conductor layers 9-2-3 and 9-2-4, which are formed (stacked) above and below the dielectric layer 9-1-3. Vias 9-3-4-1 to 9-3-4-N and vias 9-3-8-1 to 9-3-8-N electrically connect two adjacent conductor layers 9-2-4 and 9-2-5, which are formed (stacked) above and below the dielectric layer 8-1-4.

[0103] Two sets of vias (9-3-1-1~9-3-1-N and 9-3-5-1~9-3-5-N) are arranged in parallel, two sets of vias (9-3-2-1~9-3-2-N and 9-3-6-1~9-3-6-N) are arranged in parallel, two sets of vias (9-3-3-1~9-3-3-N and 9-3-7-1~9-3-7-N) are arranged in parallel, and two sets of vias (9-3-4-1~9-3-4-N and 9-3-8-1~9-3-8-N) are arranged in parallel. Additionally, two sets of vias (via 9-3-1-k ~ 9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and via 9-3-5-k ~ 9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) are arranged in parallel.

[0104] Stubs 9-4-1-1 to 5-4-1-M are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to stubs 9-4-2-1 to 9-4-2-M. For example, stubs 9-4-1-1 to 9-4-1-M are arranged at equal intervals along the longitudinal direction of a linear conductor, and stubs 9-4-2-1 to 9-4-2-M are arranged at equal intervals along the longitudinal direction of a linear conductor.

[0105] In this embodiment, as shown in Figures 9C and 9D, the bottom conductor layer 9-2-1 and the top conductor layer 9-2-5 are arranged in a solid plane across the entire surface. However, the bottom conductor layer and the top conductor layer may be placed in the region sandwiched between via group A (one of two sets of vias 9-3-1-k to 9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 9-3-5-k to 9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) and via group B (the other of two sets of vias 9-3-1-k to 9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 9-3-5-k to 9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)).

[0106] In this embodiment, as described above, linear conductors are arranged in the upper and lower conductor layers 9-2-2 to 9-2-4 of the via (see, for example, the cross-sectional view of the c95-c96 plane in Figure 9C). In this embodiment as well, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between vias as narrow as possible, taking into account the constraints described above. In this embodiment, further, linear and stub-shaped conductors 9-4-1-i to 9-4-2-i are arranged outside the waveguide from the linear conductor (in the vertical direction in the cross-sectional view of the c95-c96 plane in Figure 9C). The length of the linear stub is about 1 / 4 of the wavelength of the electromagnetic wave to be passed through the waveguide in order to suppress electromagnetic wave leakage. In this embodiment as well, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between stubs as narrow as possible, taking into account the constraints described above.

[0107] In this embodiment, as shown in the lower half of the cross-sectional view of the c93-c94 plane in Figures 9D and 9C, vias 9-3-1-k to 9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged outward in the X-axis direction within a plane perpendicular to the Z-axis direction, while vias 9-3-5-k to 9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged inward in the X-axis direction. For example, vias 9-3-1-k to 9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 9-3-5-k to 9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged in two rows. Furthermore, as shown in the cross-sectional views of the c93-c94 plane and the c97-c98 plane in Figure 9C, the two rows of vias 9-3-1-k to 9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 9-3-5-k to 9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) are arranged alternately in the dielectric layers 9-1-1 to 9-1-4, in order to prevent them from overlapping (to prevent them from forming a straight line parallel to the X-axis). More specifically, the two rows of vias 9-3-1-k~9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 9-3-5-k~9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N), shown in the lower half of the cross-sectional view of the c93-c94 plane in Figure 9C, are arranged such that the points obtained by projecting these two rows onto the Y-axis are equally spaced. The same applies to the two rows of vias 9-3-1-k to 9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and 9-3-5-k to 9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N) shown in the upper half of the cross-sectional view of the c93-c94 plane in Figure 9C. This makes it possible to suppress electromagnetic wave leakage.

[0108] In this embodiment as well, by using staggered vias, as shown in Figures 9C and 9D, vias 9-3-1-k and 9-3-3-k are positioned offset in the positive Y-axis direction relative to vias 9-3-2-k and 9-3-4-k when viewed from the Z-axis direction. On the other hand, as shown in Figures 9C and 9D, vias 9-3-1-k and 9-3-3-k are positioned in the same location when viewed from the Z-axis direction, and vias 9-3-2-k and 9-3-4-k are positioned in the same location when viewed from the Z-axis direction. The same applies to vias 9-3-5-k to 9-3-8-k. As shown in Figures 9B and 9D, the two sets of vias (vias 9-3-1-k to 9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 9-3-5-k to 9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) are not stacked across all four dielectric layers 9-1-1 to 9-1-4, nor are they stacked across two or more of the four dielectric layers 9-1-1 to 9-1-4. For example, the all-conductor layers 9-2-1 to 9-2-5 are not electrically connected via vias at the same location when viewed from the Z-axis direction.

[0109] As shown in Figures 9C and 9D, the waveguide 90 is composed of the lowest conductor layer 9-2-1 and the uppermost conductor layer 9-2-5 in the central part, and via group A and via group B. As shown in Figure 9C, when a high-frequency electromagnetic wave is input from IO1, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO2. When a high-frequency electromagnetic wave is input from IO2, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO1. Via group A and via group B function as conductor walls against electromagnetic waves (they form conductor walls against electromagnetic waves).

[0110] Each of the two sets (vias 9-3-1-1 to 9-3-1-N and vias 9-3-5-1 to 9-3-5-N), (vias 9-3-2-1 to 9-3-2-N and vias 9-3-6-1 to 9-3-6-N), (vias 9-3-3-1 to 9-3-3-N and vias 9-3-7-1 to 9-3-7-N), and (vias 9-3-4-1 to 9-3-4-N and vias 9-3-8-1 to 9-3-8-N) is an example of the first via group relating to this disclosure. Each of the other set of the two sets (vias 9-3-1-1 to 9-3-1-N and vias 9-3-5-1 to 9-3-5-N), (vias 9-3-2-1 to 9-3-2-N and vias 9-3-6-1 to 9-3-6-N), (vias 9-3-3-1 to 9-3-3-N and vias 9-3-7-1 to 9-3-7-N), and (vias 9-3-4-1 to 9-3-4-N and vias 9-3-8-1 to 9-3-8-N) is an example of the second via group relating to this disclosure.

[0111] In this embodiment, all of the two sets of vias (vias 9-3-1-k to 9-3-4-k (where k is any integer satisfying 1 ≤ k ≤ N) and vias 9-3-5-k to 9-3-8-k (where k is any integer satisfying 1 ≤ k ≤ N)) do not overlap in any of the four dielectric layers 9-1-1 to 9-1-4 when viewed from the Z-axis direction.

[0112] (Effects of Embodiments 4-6) In Figure 10, the configuration of the post-wall waveguide 20 in a full-stack configuration and the configuration of the post-wall waveguides 70-90 according to embodiments 4-6 have the same center spacing of vias in adjacent layers. For example, the center spacing of vias in the same layer of the post-wall waveguides 70-90 according to embodiments 4-6 is twice the center spacing of vias in the same layer of the post-wall waveguide 20 in a full-stack configuration. Therefore, in the post-wall waveguides 70-90 according to embodiments 4-6, electromagnetic waves are more likely to be radiated from between the vias, but by arranging the vias in two rows, the radiation of electromagnetic waves from between the vias can be suppressed.

[0113] As shown in embodiments 4 to 6, by arranging vias in a staggered pattern without stacking them, the risk of damage due to thermal expansion can be reduced, thereby suppressing a decrease in reliability and a deterioration in yield. Furthermore, by arranging vias in two rows, radiation loss can be reduced.

[0114] As can be seen from the loss simulation results shown in Figure 10, the radiated loss of post-wall waveguides 70 to 90 according to embodiments 4 to 6 is smaller than that of post-wall waveguides 30 to 50 according to embodiments 1 to 3 shown in Figure 6.

[0115] Comparing the simulation results of the losses of post-wall waveguides 70 to 90 according to embodiments 4 to 6 shown in Figure 10, it can be confirmed that the radiation loss of post-wall waveguide 90 according to embodiment 6 is smaller than the radiation loss of post-wall waveguide 70 according to embodiment 4. For example, by arranging the conductors above and below the via in a stub shape, as in post-wall waveguide 90 according to embodiment 6, the radiation loss can be reduced compared to post-wall waveguide 70 according to embodiment 4. Furthermore, it can be seen that the conductor loss of post-wall waveguides 80 and 90 according to embodiments 5 and 6 is smaller than the conductor loss of post-wall waveguide 70 according to embodiment 4, confirming that conductor loss can be reduced by arranging linear or stub-shaped conductors.

[0116] (Embodiment 7) In Embodiment 7 of this disclosure, stacked vias are used, but a full stack is avoided by not making via connections in some layers, and a post-wall waveguide is constructed with a stack of two stages (two layers) or less.

[0117] Figure 11A is a perspective view showing an example of a post-wall waveguide 110 according to Embodiment 7. Figure 11B is a cross-sectional view of the a113-a114 plane showing an example of a post-wall waveguide 110 viewed from the Y-axis direction. Figure 11C is a cross-sectional view of the c111-c112 plane, the c113-c114 plane, and the c115-c116 plane showing an example of a post-wall waveguide 110 viewed from the Z-axis direction. Figure 11D is a partial cross-sectional view of the a111-a112 plane showing an example of a post-wall waveguide 110 viewed from the X-axis direction.

[0118] For example, as shown in Figure 11D, the post-wall waveguide 110 includes four dielectric layers 11-1-1 to 11-1-4, five conductor layers 11-2-1 to 11-2-5, and two sets of vias 11-3-1-k to 11-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 14). The post-wall waveguide 110 does not include any vias other than the two sets of vias 11-3-1-k to 11-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N).

[0119] Each dielectric layer is formed between two adjacent conductive layers in the Z-axis direction (for example, each conductive layer is formed above or below one of the four dielectric layers 11-1-1 to 11-1-4). However, each dielectric layer is in contact with an adjacent dielectric layer if there is no conductor in the conductive layer.

[0120] Vias 11-3-1-1 to 11-3-1-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 11-3-2-1 to 11-3-2-N and vias 11-3-3-1 to 11-3-3-N.

[0121] Vias 11-3-1-1 to 11-3-1-N electrically connect two adjacent conductor layers 11-2-1 and 11-2-2, which are formed (stacked) above and below the dielectric layer 11-1-1. Vias 11-3-2-1 to 11-3-2-N electrically connect two adjacent conductor layers 11-2-3 and 11-2-4, which are formed (stacked) above and below the dielectric layer 11-1-3. Vias 11-3-3-1 to 11-3-3-N electrically connect two adjacent conductor layers 11-2-4 and 11-2-5, which are formed (stacked) above and below the dielectric layer 11-1-4.

[0122] In this embodiment, as described above, vias are not placed in the dielectric layer 11-1-2 in order to avoid full stacking. This prevents via damage due to full stacking.

[0123] Two sets of vias 11-3-1-1 to 11-3-1-N are arranged in parallel, two sets of vias 11-3-2-1 to 11-3-2-N are arranged in parallel, and two sets of vias 11-3-3-1 to 11-3-3-N are arranged in parallel. Additionally, two sets of vias 11-3-1-k to 11-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N) are also arranged in parallel.

[0124] In this embodiment, as shown in Figures 11C and 11D, the bottom conductor layer 11-2-1 and the top conductor layer 11-2-5 are arranged in a solid plane across the entire surface. However, the bottom conductor layer and the top conductor layer may be placed in the region sandwiched between via group A (one set of two sets of vias 11-3-1-k to 11-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N)) and via group B (the other set of two sets of vias 11-3-1-k to 11-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N)).

[0125] When vias are installed, conductors called via lands, which have a circular shape with a larger radius than the via based on the design rules, may be placed above and below the via. In this embodiment, circular via lands are placed above and below the via in conductor layers 11-2-2 to 11-2-4 (see, for example, the cross-sectional view of the c115-c116 plane in Figure 11C). The via lands in conductor layers 11-2-2 to 11-2-4 may or may not be connected to adjacent via lands. In this embodiment as well, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between vias as narrow as possible, taking into consideration the above constraints.

[0126] In this embodiment, by using stacked vias in some areas, vias 11-3-2-k and 11-3-3-k are stacked, as shown in Figures 11C and 11D, and vias 11-3-1-k, 11-3-2-k, and 11-3-3-k are located in the same place when viewed from the Z-axis direction. As shown in Figures 11B and 11D, the two sets of vias 11-3-1-k to 11-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N) are not stacked across all four dielectric layers 11-1-1 to 11-1-4, nor are they stacked across three or more of the four dielectric layers 11-1-1 to 11-1-4. For example, the all-conductor layers 11-2-1 to 11-2-5 are not electrically connected via vias in the same place when viewed from the Z-axis direction.

[0127] As shown in Figures 11C and 11D, the waveguide 110 is composed of the lowest conductor layer 11-2-1 and the uppermost conductor layer 11-2-5 in the central part, and via group A and via group B. As shown in Figure 11C, when a high-frequency electromagnetic wave is input from IO1, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO2, and when it is input from IO2, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO1. Via group A and via group B function as conductor walls against electromagnetic waves (they form conductor walls against electromagnetic waves).

[0128] Each of the vias 11-3-1-1~11-3-1-N, 11-3-2-1~11-3-2-N, and 11-3-3-1~11-3-3-N from one of the two sets is an example of the first via group relating to this disclosure. Each of the vias 11-3-1-1~11-3-1-N, 11-3-2-1~11-3-2-N, and 11-3-3-1~11-3-3-N from the other of the two sets is an example of the second via group relating to this disclosure.

[0129] In this embodiment, all of the two sets of vias 11-3-1-k to 11-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N) do not overlap in any of the four dielectric layers 11-1-1 to 11-1-4 when viewed from the Z-axis direction.

[0130] Note that more than two vias may be removed. For example, the number of first via groups and second via groups may be less than the number of dielectric layers. For example, in the above example, the number of first via groups and second via groups is 3, and the number of dielectric layers is 4, so the number of first via groups and second via groups is less than the number of dielectric layers.

[0131] (Embodiment 8) In Embodiment 8 of this disclosure, stacked vias are used, but a full stack is avoided by not making via connections in some layers, and a post-wall waveguide is constructed with a stack of two stages (two layers) or less. On the other hand, in Embodiment 8, the conductor layers 11-2-2 to 11-2-4, which had circular via lands in Embodiment 7, are replaced with conductor layers 12-2-2 to 12-2-4, which have linear conductors. Conductor layers 12-2-2 to 12-2-4 are inner layers, while conductor layers 12-2-1 and 12-2-5 are outer layers.

[0132] Figure 12A is a perspective view showing an example of a post-wall waveguide 120 according to Embodiment 8. Figure 12B is a cross-sectional view of the a123-a124 plane showing an example of a post-wall waveguide 120 viewed from the Y-axis direction. Figure 12C is a cross-sectional view of the c121-c122 plane, the c123-c124 plane, and the c125-c126 plane showing an example of a post-wall waveguide 120 viewed from the Z-axis direction. Figure 12D is a partial cross-sectional view of the a121-a122 plane showing an example of a post-wall waveguide 120 viewed from the X-axis direction.

[0133] For example, as shown in Figure 12D, the post-wall waveguide 120 includes four dielectric layers 12-1-1 to 12-1-4, five conductor layers 12-2-1 to 12-2-5, and two sets of vias 12-3-1-k to 12-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 14). The post-wall waveguide 120 does not include any vias other than the two sets of vias 12-3-1-k to 12-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N).

[0134] Each dielectric layer is formed between two adjacent conductive layers in the Z-axis direction (for example, each conductive layer is formed above or below one of the four dielectric layers 12-1-1 to 12-1-4). However, each dielectric layer is in contact with an adjacent dielectric layer if there is no conductor in the conductive layer.

[0135] Vias 12-3-1-1 to 12-3-1-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 12-3-2-1 to 12-3-2-N and vias 12-3-3-1 to 12-3-3-N.

[0136] Vias 12-3-1-1 to 12-3-1-N electrically connect two adjacent conductor layers 12-2-1 and 12-2-2, which are formed (stacked) above and below the dielectric layer 12-1-1. Vias 12-3-2-1 to 12-3-2-N electrically connect two adjacent conductor layers 12-2-3 and 12-2-4, which are formed (stacked) above and below the dielectric layer 12-1-3. Vias 12-3-3-1 to 12-3-3-N electrically connect two adjacent conductor layers 12-2-4 and 12-2-5, which are formed (stacked) above and below the dielectric layer 12-1-4.

[0137] In this embodiment, as described above, vias are not placed in the dielectric layer 12-1-2 in order to avoid full stacking. This prevents via damage due to full stacking.

[0138] Two sets of vias 12-3-1-1 to 12-3-1-N are arranged in parallel, two sets of vias 12-3-2-1 to 12-3-2-N are arranged in parallel, and two sets of vias 12-3-3-1 to 12-3-3-N are arranged in parallel. Additionally, two sets of vias 12-3-1-k to 12-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N) are also arranged in parallel.

[0139] In this embodiment, as shown in Figures 12C and 12D, the bottom conductor layer 12-2-1 and the top conductor layer 12-2-5 are arranged in a solid plane across the entire surface. However, the bottom conductor layer and the top conductor layer may be placed in the region sandwiched between via group A (one set of two sets of vias 12-3-1-k to 12-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N)) and via group B (the other set of two sets of vias 12-3-1-k to 12-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N)).

[0140] In this embodiment, as described above, linear conductors are arranged in the conductor layers 12-2-2 to 12-2-4 (inner layers) above and below the via, excluding the bottommost conductor layer 12-2-1 and the topmost conductor layer 12-2-5 (outer layer) (see, for example, the cross-sectional view of the c125-c126 plane in Figure 12C). In this embodiment as well, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between vias as narrow as possible, taking into account the constraints described above.

[0141] In this embodiment, by using stacked vias in some areas, vias 12-3-2-k and 12-3-3-k are stacked, as shown in Figures 12C and 12D, and vias 12-3-1-k, 12-3-2-k, and 12-3-3-k are located in the same place when viewed from the Z-axis direction. As shown in Figures 12B and 12D, the two sets of vias 12-3-1-k to 12-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N) are not stacked across all four dielectric layers 12-1-1 to 12-1-4, nor are they stacked across three or more of the four dielectric layers 12-1-1 to 12-1-4. For example, the all-conductor layers 12-2-1 to 12-2-5 are not electrically connected via vias in the same place when viewed from the Z-axis direction.

[0142] As shown in Figures 12C and 12D, the waveguide 120 is composed of the lowest conductor layer 12-2-1 and the uppermost conductor layer 12-2-5 in the central part, and via group A and via group B. As shown in Figure 12C, when a high-frequency electromagnetic wave is input from IO1, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO2. When a high-frequency electromagnetic wave is input from IO2, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO1. Via group A and via group B function as conductor walls against electromagnetic waves (they form conductor walls against electromagnetic waves).

[0143] Each of the vias 12-3-1-1~12-3-1-N, 12-3-2-1~12-3-2-N, and 12-3-3-1~12-3-3-N in one of the two sets is an example of the first via group relating to this disclosure. Each of the vias 12-3-1-1~12-3-1-N, 12-3-2-1~12-3-2-N, and 12-3-3-1~12-3-3-N in the other of the two sets is an example of the second via group relating to this disclosure.

[0144] In this embodiment, all of the two sets of vias 12-3-1-k to 12-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N) do not overlap in any of the four dielectric layers 12-1-1 to 12-1-4 when viewed from the Z-axis direction.

[0145] Note that more than two vias may be removed. For example, the number of first via groups and second via groups may be less than the number of dielectric layers. For example, in the above example, the number of first via groups and second via groups is 3, and the number of dielectric layers is 4, so the number of first via groups and second via groups is less than the number of dielectric layers.

[0146] (Embodiment 9) In Embodiment 9 of this disclosure, stacked vias are used, but a full stack is avoided by not making via connections in some layers, and a post-wall waveguide is constructed with a stack of two stages (two layers) or less. On the other hand, in Embodiment 9, among the conductor layers 12-2-2 to 12-2-4 in Embodiment 8, conductor layers 12-2-2 to 12-2-3, which have linear conductors arranged therein, are replaced with conductor layers 13-2-2 to 13-2-3, which have stub-shaped conductors added to the linear conductors.

[0147] Figure 13A is a perspective view showing an example of a post-wall waveguide 130 according to Embodiment 9. Figure 13B is a cross-sectional view of the a133-a134 plane showing an example of a post-wall waveguide 130 viewed from the Y-axis direction. Figure 13C is a cross-sectional view of the c131-c132 plane, the c133-c134 plane, the c135-c136 plane, and the c137-c138 plane (c139-c1310 plane) showing an example of a post-wall waveguide 130 viewed from the Z-axis direction. Figure 13D is a cross-sectional view of a portion of the a131-a132 plane showing an example of a post-wall waveguide 130 viewed from the X-axis direction.

[0148] For example, as shown in Figure 13D, the post-wall waveguide 130 includes four dielectric layers 13-1-1 to 13-1-4, five conductor layers 13-2-1 to 13-2-5, two sets of vias 13-3-1-k to 13-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N (where N is an integer greater than or equal to 2); in this embodiment, N = 14), and two sets of stubs 13-4-1-i to 13-4-2-i (where i is any integer satisfying 1 ≤ i ≤ M (where M is an integer greater than or equal to 2); in this embodiment, M = 13). The post-wall waveguide 130 does not include any vias other than the two sets of vias 13-3-1-k to 13-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N).

[0149] Each dielectric layer is formed between two adjacent conductive layers in the Z-axis direction (for example, each conductive layer is formed above or below one of the four dielectric layers 13-1-1 to 13-1-4). However, each dielectric layer is in contact with an adjacent dielectric layer if there is no conductor in the conductive layer.

[0150] Vias 13-3-1-1 to 13-3-1-N are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to vias 13-3-2-1 to 13-3-2-N and vias 13-3-3-1 to 13-3-3-N.

[0151] Vias 13-3-1-1 to 13-3-1-N electrically connect two adjacent conductor layers 13-2-1 and 13-2-2, which are formed (stacked) above and below the dielectric layer 13-1-1. Vias 13-3-2-1 to 13-3-2-N electrically connect two adjacent conductor layers 13-2-3 and 13-2-4, which are formed (stacked) above and below the dielectric layer 13-1-3. Vias 13-3-3-1 to 13-3-3-N electrically connect two adjacent conductor layers 13-2-4 and 13-2-5, which are formed (stacked) above and below the dielectric layer 13-1-4.

[0152] In this embodiment, as described above, vias are not placed in the dielectric layer 13-1-2 in order to avoid full stacking. This prevents via damage due to full stacking.

[0153] Two sets of vias 13-3-1-1 to 13-3-1-N are arranged in parallel, two sets of vias 13-3-2-1 to 13-3-2-N are arranged in parallel, and two sets of vias 13-3-3-1 to 13-3-3-N are arranged in parallel. Additionally, two sets of vias 13-3-1-k to 13-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N) are also arranged in parallel.

[0154] Furthermore, stubs 13-4-1-1 to 13-4-1-M are arranged at equal intervals in a plane perpendicular to the Z-axis, and the same applies to stubs 13-4-2-1 to 13-4-2-M. For example, stubs 13-4-1-1 to 13-4-1-M are arranged at equal intervals along the longitudinal direction of the linear conductor, and stubs 13-4-2-1 to 13-4-2-M are arranged at equal intervals along the longitudinal direction of the linear conductor.

[0155] In this embodiment, as shown in Figures 13C and 13D, the bottom conductor layer 13-2-1 and the top conductor layer 13-2-5 are arranged in a solid plane across the entire surface. However, the bottom conductor layer and the top conductor layer may be placed in the region sandwiched between via group A (one set of two sets of vias 13-3-1-k to 13-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N)) and via group B (the other set of two sets of vias 13-3-1-k to 13-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N)).

[0156] In this embodiment, as described above, linear conductors are arranged in the conductor layers 13-2-2 to 13-2-4 above and below the via (see, for example, the cross-sectional views of the c135-c136 plane and the c137-c138 plane (c139-c1310 plane) in Figure 13C). In this embodiment as well, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between vias as narrow as possible, taking into consideration the constraints described above. In this embodiment, further, linear and stub-shaped conductors 13-4-1-i to 13-4-2-i are arranged outside the waveguide from the linear conductors of the conductor layers 13-2-2 to 13-2-3 (in the vertical direction in the cross-sectional view of the c137-c138 plane (c139-c1310 plane) in Figure 13C). The length of the linear stub is about 1 / 4 of the wavelength of the electromagnetic wave to be passed through the waveguide in order to suppress electromagnetic wave leakage. In this embodiment as well, in order to suppress electromagnetic wave leakage, it is desirable to make the spacing between stubs as narrow as possible, taking into consideration the constraints mentioned above. Alternatively, linear and stub-shaped conductors 13-4-1-i to 13-4-2-i may be arranged outside the waveguide from the linear conductor of the conductor layer 13-2-4.

[0157] In this embodiment, the stub-shaped conductors 13-4-1-i to 13-4-2-i can suppress electromagnetic wave leakage from the dielectric layer 13-1-2 from which the vias have been removed.

[0158] In this embodiment, by using stacked vias in some areas, vias 13-3-2-k and 13-3-3-k are stacked, as shown in Figures 13C and 13D, and vias 13-3-1-k, 13-3-2-k, and 13-3-3-k are located in the same place when viewed from the Z-axis direction. As shown in Figures 13B and 13D, the two sets of vias 13-3-1-k to 13-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N) are not stacked across all four dielectric layers 13-1-1 to 13-1-4, nor are they stacked across three or more of the four dielectric layers 13-1-1 to 13-1-4. For example, the all-conductor layers 13-2-1 to 13-2-5 are not electrically connected via vias in the same place when viewed from the Z-axis direction.

[0159] As shown in Figures 13C and 13D, the waveguide 130 is composed of the lowest conductor layer 13-2-1 and the uppermost conductor layer 13-2-5 in the central part, and via group A and via group B. As shown in Figure 13C, when a high-frequency electromagnetic wave is input from IO1, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO2. When a high-frequency electromagnetic wave is input from IO2, it propagates in the region between via group A and via group B as indicated by the arrows and is output to IO1. Via group A and via group B function as conductor walls against electromagnetic waves (they form conductor walls against electromagnetic waves).

[0160] Each of the vias 13-3-1-1 to 13-3-1-N, 13-3-2-1 to 13-3-2-N, and 13-3-3-1 to 13-3-3-N in one of the two sets is an example of the first via group relating to this disclosure. Each of the vias 13-3-1-1 to 13-3-1-N, 13-3-2-1 to 13-3-2-N, and 13-3-3-1 to 13-3-3-N in the other of the two sets is an example of the second via group relating to this disclosure.

[0161] In this embodiment, all of the two sets of vias 13-3-1-k to 13-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N) do not overlap in any of the four dielectric layers 13-1-1 to 13-1-4 when viewed from the Z-axis direction.

[0162] Note that more than two vias may be removed. For example, the number of first via groups and second via groups may be less than the number of dielectric layers. For example, in the above example, the number of first via groups and second via groups is 3, and the number of dielectric layers is 4, so the number of first via groups and second via groups is less than the number of dielectric layers.

[0163] (Effects of Embodiments 7-9) In Figure 14, the via center spacing is matched between the configuration of the post-wall waveguide 20 in the full-stack configuration shown in Figures 2A to 2D and the configuration of the post-wall waveguides 110 to 130 according to embodiments 7 to 9.

[0164] As shown in embodiments 7 to 9, by removing one via layer to avoid full stacking, the risk of damage due to thermal expansion can be reduced, and a decrease in reliability and yield can be suppressed. Furthermore, removing one via layer can also suppress substrate delamination. In addition, radiation loss can be reduced by placing stubs on the upper and lower conductors of the layer from which the vias were removed.

[0165] Figure 14 shows the simulation results for the losses of Land (post-wall waveguide 110), Line (post-wall waveguide 120), and Full-Stack (post-wall waveguide 20 in a full-stack configuration). It can be seen that the radiation loss is high for Land and Line. This is thought to be due to the removal of vias in one layer. On the other hand, Figure 14 shows the simulation results for the losses of Stub (post-wall waveguide 130) and Full-stack. The radiation loss for both is at a similar level. This is thought to be due to the placement of stubs on the upper and lower conductors of the layer from which the vias have been removed, as in the post-wall waveguide 130 according to Embodiment 9. Thus, it can be seen that the post-wall waveguide 130 according to Embodiment 9 can suppress losses to the same level as the post-wall waveguide 20 in a full-stack configuration. For example, in the post-wall waveguide 130 according to Embodiment 9, by removing vias and placing stubs, the risk of via damage due to full-stack configuration is reduced, and loss characteristics equivalent to those of a post-wall waveguide in a full-stack configuration can be obtained.

[0166] (Modified version of Embodiment 9) [Example 1] As shown in Figure 15, in configuration example 15, the corners of the tips of the stub-shaped conductors 13-4-1-i to 13-4-2-i in embodiment 9 are rounded. By changing the shape of the stub in this way, conductor loss and radiation loss can be further reduced. Conductor loss can also be reduced by making the part that connects to the linear conductor gentler (for example, rounded). Alternatively, the stub may be trapezoidal and the part that connects to the linear conductor be angled.

[0167] [Differentiation 2] Figures 16A to 16D show an example of a post-wall waveguide 160 in which the stub of Embodiment 9 is replaced with an EBG (Electromagnetic Band Gap). The EBG has a mushroom shape.

[0168] Figure 16A is a perspective view showing an example of a post-wall waveguide 160 according to Modification 2. Figure 16B is a cross-sectional view of the a163-a164 plane showing an example of a post-wall waveguide 160 viewed from the Y-axis direction. Figure 16C is a cross-sectional view of the c161-c162 plane, the c163-c164 plane, the c165-c166 plane, the c167-c168 plane, and the c169-c1610 plane showing an example of a post-wall waveguide 160 viewed from the Z-axis direction. Figure 16D is a partial cross-sectional view of the a161-a162 plane showing an example of a post-wall waveguide 160 viewed from the X-axis direction.

[0169] In this modified example, the four dielectric layers 13-1-1 to 13-1-4 in Embodiment 9 are each replaced by four dielectric layers 16-1-1 to 16-1-4, and the five conductor layers 13-2-1 to 13-2-5 in Embodiment 9 are each replaced by five conductor layers 16-2-1 to 16-2-5. Also in this modified example, the two sets of vias 13-3-1-k to 13-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N) in Embodiment 9 are each replaced by two sets of vias 16-3-1-k to 16-3-3-k (where k is any integer satisfying 1 ≤ k ≤ N).

[0170] In this modified example, instead of the two sets of stubs 13-4-1-i to 13-4-2-i in Embodiment 9, mushroom-shaped EBGs may be arranged in one or more rows along the post-wall waveguide 160, as shown in Figure 16C. By arranging the EBGs in this way, electromagnetic wave radiation can be suppressed, and radiation loss can be reduced.

[0171] [Further variations] Although an example using a dielectric layer was described in the above embodiment, a semiconductor layer may be used instead of a dielectric layer.

[0172] In the above-described embodiment, an example was given in which there are four dielectric layers and five conductive layers. However, the dielectric layers can be any number of two or more layers, and the conductive layers can be any number of three or more layers.

[0173] In the above-described embodiment, an example was given in which vias and stubs are arranged at equal intervals, but vias and stubs may also be arranged at unequal intervals. For example, in bends, the spacing between vias may be looser (longer).

[0174] In the embodiments 1 to 3 described above, examples were explained in which the number of vias formed in each dielectric layer was the same. However, the number of vias formed in each dielectric layer may be the same or different.

[0175] Furthermore, in the embodiments 1 to 3 described above, the number of vias formed in each dielectric layer included in via group A constituting the conductor wall and the number of vias formed in each dielectric layer included in via group B constituting the conductor wall may be the same or different.

[0176] Furthermore, while embodiments 1 to 3 described above have explained examples in which vias are not stacked across two or more of the four dielectric layers, vias do not necessarily have to be stacked across three or more of the four dielectric layers (for example, a portion of a via may be stacked across two dielectric layers).

[0177] In embodiments 4 to 6 described above, examples were explained in which via groups A and B have two rows, but the number of rows may be three or more. In this case as well, in order to suppress electromagnetic wave leakage, it is desirable that the vias included in each row are arranged so as not to form a straight line parallel to the X-axis as shown in the various drawings.

[0178] Furthermore, in embodiments 4 to 6 described above, the number of columns in via group A and the number of columns in via group B may be the same or different. For example, via group A may have 1 column and via group B may have 3 columns.

[0179] Furthermore, in embodiments 4 to 6 described above, an example was explained in which the number of vias in each of the two rows of via group A (or via group B) is the same. However, the number of vias in each row may be different. In this case as well, in order to suppress electromagnetic wave leakage, it is desirable that the vias in each row are arranged so as not to form a straight line parallel to the X-axis as shown in the various drawings.

[0180] Furthermore, while embodiments 4 to 6 described above describe examples where vias are not stacked across two or more of the four dielectric layers, vias do not necessarily have to be stacked across three or more of the four dielectric layers (for example, a portion of a via may be stacked across two dielectric layers).

[0181] In embodiments 7 to 9 described above, examples were explained in which vias are not stacked across three or more of the four dielectric layers. However, vias do not necessarily have to be stacked across two or more of the four dielectric layers.

[0182] Furthermore, for example, in via groups A and B that constitute the conductor wall, any combination of the conductor layer configuration (via land) described in Embodiments 1, 4, and 7, the conductor layer configuration (linear) described in Embodiments 2, 5, and 8, and the conductor layer configuration (linear and stub) described in Embodiments 3, 6, and 9 may be adopted. For example, via land configurations and linear configurations may be mixed, via land configurations and linear and stub configurations may be mixed, linear configurations and linear and stub configurations may be mixed, and via land configurations, linear configurations and linear and stub configurations may be mixed.

[0183] Furthermore, the part described as using a solid conductor may be modified by inserting slits in which a portion of the conductor is removed, or by arranging a large number of slits in a grid pattern.

[0184] Furthermore, the length of the waveguide (transmission line) is arbitrary, and there are no restrictions on the number of vias.

[0185] When constructing a waveguide using a conductor layer and vias, it may be affected by both via misalignment and conductor layer pattern misalignment. For this reason, when using stubs in the conductor layer, the vias may be omitted when constructing the waveguide. By omitting the vias and constructing the waveguide with a conductor layer pattern that includes stubs, via misalignment can be eliminated, thereby improving manufacturing accuracy.

[0186] (Summary of the embodiments) The waveguide in the embodiment of the present disclosure comprises three or more stacked conductor layers, two or more stacked dielectric layers formed between two adjacent conductor layers among the three or more conductor layers, and a first via group and a second via group, each including one or more vias disposed inside at least one of the dielectric layers among the two or more dielectric layers, wherein the first via group and the second via group are arranged in parallel, and among the vias included in the first via group and the second via group, the vias disposed in at least one of the two or more dielectric layers are positioned differently on the dielectric layer plane from the vias disposed in the remaining dielectric layers. This configuration prevents vias from being fully stacked, thereby reducing the risk of damage due to thermal expansion associated with full via stacking, and suppressing a decrease in reliability and yield during waveguide manufacturing.

[0187] While embodiments have been described above with reference to the drawings, this disclosure is not limited to such examples. It will be apparent to those skilled in the art that various modifications or alterations can be conceived within the scope of the claims. Such modifications or alterations are also understood to fall within the technical scope of this disclosure. Furthermore, the components in the embodiments may be combined in any way without departing from the spirit of this disclosure.

[0188] All disclosures in the specification, drawings, and abstract contained in the Japanese application 2022-007114, filed on January 20, 2022, are incorporated herein by reference. [Industrial applicability]

[0189] One embodiment of the present disclosure can be applied to a waveguide for transmitting high-frequency signals. [Explanation of Symbols]

[0190] 20 Post-Wall Waveguides 2-1-1~2-1-4 Dielectric layer 2-2-1~2-2-5 Conductor Layers 2-3-1-k~2-3-4-k Beer 30 Post-Wall Waveguides 3-1-1~3-1-4 Dielectric layer 3-2-1~3-2-5 Conductor Layers 3-3-1-k~3-3-4-k Beer 40 Post-Wall Waveguides 4-1-1~4-1-4 Dielectric layer 4-2-1~4-2-5 Conductor layer 4-3-1-k~4-3-4-k Beer 50 Post Wall Waveguides 5-1-1~5-1-4 Dielectric layer 5-2-1~5-2-5 Conductor layer 5-3-1-k~5-3-4-k Beer 5-4-1-i~5-4-2-i Stub 70 Post-Wall Waveguide 7-1-1~7-1-4 Dielectric layer 7-2-1~7-2-5 Conductor Layers 7-3-1-k~7-3-4-k,7-3-5-k~7-3-8-k Beer 8-1-1~8-1-4 Dielectric layer 80 Post-Wall Waveguide 8-2-1~8-2-5 Conductor layer 8-3-1-k~8-3-4-k,8-3-5-k~8-3-8-k Beer 90 Post-Wall Waveguide 9-1-1~9-1-4 Dielectric layer 9-2-1~9-2-5 Conductor Layers 9-3-1-k~9-3-4-k,9-3-5-k~9-3-8-k Beer 9-4-1-i~9-4-2-i Stub 110 Post-Wall Waveguide 11-1-1~11-1-4 Dielectric layer 11-2-1~11-2-5 Conductor layer 11-3-1-k~11-3-3-k Beer 120 Post-Wall Waveguide 12-1-1~12-1-4 Dielectric layer 12-2-1~12-2-5 Conductor Layers 12-3-1-k~12-3-3-k Beer 130 Post-Wall Waveguide 13-1-1~13-1-4 Dielectric layer 13-2-1~13-2-5 Conductor layer 13-3-1-k~13-3-3-k Beer 13-4-1-i~13-4-2-i Stub 160 Post-Wall Waveguide 16-1-1~16-1-4 Dielectric layer 16-2-1~16-2-5 Conductor layer 16-3-1-k~16-3-3-k Beer

Claims

1. Three or more stacked conductive layers, Two or more laminated dielectric layers are formed between two adjacent conductive layers among the three or more conductive layers, A first via group and a second via group, each including one or more vias disposed inside at least one of the two or more dielectric layers, Equipped with, The first via group and the second via group are arranged in parallel. At least one of the two or more dielectric layers is a layer on which the first via group and the second via group are not arranged. Waveguide.

2. Either the first via group or the second via group includes one or more rows containing multiple vias. Waveguide according to claim 1.

3. Each of the first via group and the second via group is connected by a linear conductor in one of the inner layers of the three or more conductor layers. Waveguide according to claim 1.

4. The linear conductor further includes a plurality of stubs arranged along the longitudinal direction of the linear conductor. Waveguide according to claim 3.

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