Semiconductor device manufacturing method

Abstract

The present invention relates to a method for manufacturing a semiconductor device. According to one embodiment, a method for manufacturing a semiconductor device may include a gap-fill process for forming a gap-fill oxide film by filling a gap-fill oxide inside a trench formed on a substrate. In one embodiment, the gap-fill process may include a high-pressure oxidation (HPO) process. According to this embodiment, a semiconductor device having improved electrical characteristics can be manufactured.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device.

Background Art

[0002] When manufacturing a semiconductor device, an element isolation technique is used to electrically isolate individual elements such as transistors and capacitors from each other. In recent years, in the field of manufacturing high-integration memory devices, the STI (Shallow Trench Isolation) technique has been applied, in which a trench is formed in a substrate, a gap-fill oxide film is embedded in this trench, and an element isolation region is formed.

[0003] FIG. 1 is a cross-sectional view showing an element isolation region of a semiconductor device according to the prior art.

[0004] As shown in the figure, a semiconductor device 1 according to the prior art includes a substrate 11 and an element isolation region formed in the substrate 11. According to the prior art, in the process of forming the element isolation region, a liner nitride film 13 is formed inside a trench 12, and a liner oxide film 14 is formed on the liner nitride film 13. After the liner oxide film 14 is formed, a gap-fill oxide is gap-filled inside the trench 12 to form a gap-fill oxide film 15, and planarization is performed by a chemical mechanical polishing (CMP) process, thereby completing the element isolation region.

[0005] When the trench width for forming the element isolation region is 30 nm or less, plasma and thermochemical deposition methods face limitations in gap filling due to the need for high aspect ratios and low-temperature processes, making the development of gap filling processes using flow-type materials essential. A typical method using flow characteristics is the coating method using SOG (Spin-On-Glass). However, with the SOG coating method, securing the necessary conditions for subsequent thermal processes to densify and stabilize the gap fill oxide film is difficult, and deterioration of the electrical properties of the semiconductor device can occur due to voids (V1, V2) within the gap fill oxide film and rupture of the gap fill oxide film.

[0006] Due to the aforementioned problems, gap fill oxide films can be produced using chemical vapor deposition (CVD), a method other than coating. However, with the CVD method, during subsequent heat treatment, deterioration of the adhesive strength of the gap fill oxide and changes due to stress can lead to rupture of the gap fill oxide film and subsequent deterioration of the electrical properties of the semiconductor device. [Overview of the project] [Problems that the invention aims to solve]

[0007] The objective of this specification is to provide a method for manufacturing a semiconductor device that can reduce the voids generated within the gap fill oxide film and reduce the rupture phenomenon of the gap fill oxide film.

[0008] The objective of this specification is to provide a method for manufacturing semiconductor devices having improved electrical characteristics compared to conventional methods.

[0009] The purposes of this specification are not limited to those mentioned above. Other purposes and advantages of this specification not mentioned can be better understood from the examples described below. Furthermore, the purposes and advantages of this specification can be achieved by the components and combinations thereof described in the claims. [Means for solving the problem]

[0010] A semiconductor device manufacturing method according to one embodiment may include a gap-fill step in which a gap-fill oxide is embedded inside a trench formed on a substrate to form a gap-fill oxide film.

[0011] In one embodiment, the gap-filling process may include an HPO (High Pressure Oxidation) process.

[0012] In one embodiment, the HPO process can be carried out in a processing apparatus supplied with at least one of O2, O3, H2O, D2O, N2O, CO, and CO2.

[0013] In one embodiment, when the above HPO process is performed, the internal pressure of the apparatus can be maintained at 2 to 50 atmospheres.

[0014] In one embodiment, when the above HPO process is carried out, the internal temperature of the processing apparatus can be maintained at 200 to 1000°C.

[0015] In one embodiment, the gap fill oxide film may be formed by performing the HPO step after the FCVD (Flowable Chemical Vapor Deposition) step using the gap fill oxide.

[0016] A method for manufacturing a semiconductor device according to another embodiment may include the steps of: etching a substrate to form a trench; forming a liner layer on the inner surface of the trench; forming a gap fill oxide film on the liner layer to gap fill the inside of the trench; and planarizing the gap fill oxide film.

[0017] In other embodiments, the gap fill oxide film may be formed by a gap fill process that includes an HPO (High Pressure Oxidation) step.

[0018] In other embodiments, the HPO step can be carried out in a processing apparatus supplied with at least one of O2, O3, H2O, D2O, N2O, CO, and CO2.

[0019] In other embodiments, when the above HPO process is performed, the internal pressure of the apparatus can be maintained at 2 to 50 atmospheres.

[0020] In other embodiments, when the above HPO process is carried out, the internal temperature of the apparatus can be maintained at 200 to 1000°C.

[0021] In other embodiments, the gap fill oxide film can be formed by performing the HPO step after the FCVD (Flowable Chemical Vapor Deposition) step.

[0022] In other embodiments, the liner layer may have a single-layer or multi-layer structure consisting of at least one component from a nitride film, an oxide film, and polysilicon. [Effects of the Invention]

[0023] According to the example, during the process of creating the element isolation region of a semiconductor device, the voids generated within the gap fill oxide film are reduced, and the density of the gap fill oxide film increases. Furthermore, the phenomenon of gap fill oxide film rupture can be reduced during the process of creating the element isolation region of a semiconductor device. As a result, it becomes possible to manufacture semiconductor devices with improved electrical characteristics compared to conventional methods. [Brief explanation of the drawing]

[0024] [Figure 1] This is a cross-sectional view showing the element isolation region of a semiconductor device using conventional technology. [Figure 2] It is a diagram showing the formation process of the element isolation region of a semiconductor element according to an embodiment. [Figure 3] It is a diagram showing the formation process of the element isolation region of a semiconductor element according to an embodiment. [Figure 4] It is a diagram showing the formation process of the element isolation region of a semiconductor element according to an embodiment. [Figure 5] It is a diagram showing the formation process of the element isolation region of a semiconductor element according to an embodiment. [Figure 6] It is a diagram showing the formation process of the element isolation region of a semiconductor element according to an embodiment. [Figure 7] It is a diagram showing the formation process of the element isolation region of a semiconductor element according to an embodiment. [Figure 8] It is a cross-sectional view of a capacitor element including a gap-fill oxide film. [Figure 9] It is a graph showing leakage current values measured when a voltage is applied to capacitor elements each including a gap-fill oxide film according to the prior art and a gap-fill oxide film according to an embodiment. [Figure 10] It is a graph showing charge retention times measured when a voltage is applied to capacitor elements each including a gap-fill oxide film according to the prior art and a gap-fill oxide film according to an embodiment. [Figure 11] It is a graph showing the etching rates of a gap-fill oxide film according to the prior art and a gap-fill oxide film according to an embodiment.

Embodiments for Carrying Out the Invention

[0025] The aforementioned objectives, features, and advantages will be described in detail below with reference to the accompanying drawings, so that a person with ordinary skill in the art to which this specification belongs can easily implement the embodiments of this specification. In describing this specification, if a specific description of known technology relating to this specification is deemed to obscure the gist of this specification, then such detailed description will be omitted. Hereafter, preferred embodiments of this specification will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or similar components.

[0026] The embodiments described herein include a gap-fill step for trenches formed on a substrate and are applicable without limitation to any method for manufacturing semiconductor devices in which a gap-fill oxide film is formed by the gap-fill step.

[0027] The features of the present invention will be described below with reference to the attached drawings, using the STI (Shallow Trench Isolation) technology as one example; however, it will be apparent to those skilled in the art that the present invention is not limited thereto.

[0028] Figures 2 to 7 show the process of forming the element isolation region of a semiconductor device according to one embodiment.

[0029] For the time being, as shown in Figure 2, the first pad oxide film 22, the pad nitride film 23, and the second pad oxide film 24 are sequentially deposited on the semiconductor substrate 21. In other embodiments, the second pad oxide film 24 may not be deposited.

[0030] The semiconductor substrate 21 may consist of at least one component from Si and SiGe. In one embodiment, the semiconductor substrate 21 may be a single layer made of Si or a single layer made of SiGe. In another embodiment, the semiconductor substrate 21 may have a multilayer structure in which a first layer made of Si and a second layer made of SiGe are alternately stacked.

[0031] Next, through a patterning process and an etching process using an element isolation mask, a portion of the first pad oxide film 22, the pad nitride film 23, and the second pad oxide film 24 are etched, thereby forming trenches 200 that become element isolation regions of the semiconductor substrate 21.

[0032] Next, a liner layer may be formed on the semiconductor element 2. For example, as shown in Figures 3 and 4, a liner nitride film 25 may be first laminated on the semiconductor element 2, and the liner nitride film 25 may oxidize to form a liner oxide film 26, thereby forming two liner layers 25 and 26.

[0033] The liner nitride film 25 is intended to compensate for the compressive stress caused by the gap fill oxide embedded in the trench 200. In other words, the compressive stress applied to the semiconductor substrate 21 by the gap fill oxide is offset by the tensile stress of the liner nitride film 25, thereby preventing a decrease in the electrical characteristics of the semiconductor element 2 due to the element isolation region.

[0034] In particular, the liner nitride film 25 works to improve the refresh characteristics of the cell region by blocking the diffusion of defects occurring in the active region of the semiconductor element 2 into the element isolation region. A silicon nitride film (Si3N4) can be used for the liner nitride film 25. The liner nitride film 25 can be formed by low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition, but is not limited to these methods.

[0035] Although not shown in the diagram, a wall oxide film may be formed on the surface of the trench 200 by oxidizing the surface of the trench 200 before the liner nitride film 25 is formed. The wall oxide film is intended to repair defects such as lattice defects and plasma damage that may occur during the formation of the trench 200. If a wall oxide film is formed, the liner nitride film 25 may be formed on top of the wall oxide film.

[0036] The liner oxide film 26 is intended to prevent damage to the liner nitride film 25 when the gap fill oxide is embedded inside the trench 200 and the gap fill oxide film 27 is formed.

[0037] Figures 3 and 4 show an embodiment in which the liner layers 25 and 26 have a multilayer structure including a liner nitride film 25 and a liner oxide film 26 laminated on the liner nitride film 25. However, in other embodiments, the liner layer may consist of a liner oxide film and a liner nitride film laminated on the liner oxide film. In yet another embodiment, the liner layer may consist of a liner oxide film and a polysilicon layer laminated on the liner oxide film.

[0038] In other embodiments, the liner layer may have a single-layer structure. For example, the liner layer may consist only of a polysilicon layer.

[0039] Next, as shown in Figure 5, the gap fill oxide film 27 is formed by embedding the gap fill oxide inside the trench 200.

[0040] In one embodiment, the gap fill oxide film 27 may be formed by a gap fill process that includes an FCVD (Flowable Chemical Vapor Deposition) step and a high-pressure oxidation (HPO) step performed after the FCVD step.

[0041] In one embodiment, an FCVD process may be performed first to form the gap fill oxide film 27. According to the FCVD process, a flowable film containing Si components, which is like a liquid or gel, can be deposited inside the trench 200 as a gap fill oxide. After the gap fill oxide is embedded inside the trench 200, curing or annealing can be performed so that the materials in the gap fill oxide bond with each other.

[0042] After the FCVD process is performed, the HPO process can be carried out. When the HPO process is carried out, at least one of the following gases may be supplied to the processing apparatus (e.g., chamber or furnace) in which the substrate 21 is loaded: O2, O3, H2O (steam), D2O (steam), N2O, CO, or CO2. Also, when the HPO process is carried out, the internal pressure of the processing apparatus in which the substrate 21 is loaded may be maintained at 2 to 50 atmospheres. Also, when the HPO process is carried out, the internal temperature of the processing apparatus in which the substrate 21 is loaded may be maintained at 200°C to 1000°C. By carrying out the HPO process under these conditions, a gap fill oxide film 27 can be formed.

[0043] As described above, in the semiconductor device manufacturing process according to one embodiment, the gap fill oxide film 27 may be produced by an HPO process carried out in a high-pressure (2 to 50 atmospheres) oxygen atmosphere and low-temperature (200°C to 1000°C) environment after the FCVD process.

[0044] As the gap fill oxide film 27 is formed by the sequential FCVD and HPO processes, the gap fill oxide film 27 can have a higher density than conventionally formed gap fill oxide film 27 because any foreign matter removed during the formation process, or any voids that may be created due to physical changes in the film (stress generated as the film changes into a solid) that may occur during curing or annealing in the FCVD process, are filled with at least one gas from among O2, O3, H2O (steam), D2O (steam), N2O, CO, and CO2. Thus, the density of the gap fill oxide film 27 can be higher than conventionally formed gap fill oxide film 27. When the quality of the gap fill oxide film 27 is improved in this way, the electrical characteristics of the semiconductor device 2 can be improved compared to conventionally formed gap fill oxide film 27.

[0045] Next, as shown in Figure 6, the gap fill oxide film 27 is flattened by performing a chemical mechanical polishing (CMP) process with the liner oxide film 26 as the polishing stop film.

[0046] Next, as shown in Figure 7, the liner oxide film 26, liner nitride film 25, second pad oxide film 24, and pad nitride film 23 are sequentially removed to complete the element isolation region.

[0047] Figure 8 is a cross-sectional view of a capacitor element containing a gap fill oxide film. Figure 9 is a graph showing the leakage current values ​​measured when a voltage is applied to capacitor elements containing a gap fill oxide film according to the conventional technology and a gap fill oxide film according to one embodiment. Figure 10 is a graph showing the charge retention time measured when a voltage is applied to capacitor elements containing a gap fill oxide film according to the conventional technology and a gap fill oxide film according to one embodiment.

[0048] The capacitor element shown in Figure 8 is intended to confirm the electrical characteristics of a semiconductor element containing a gap fill oxide film according to conventional technology and the electrical characteristics of a semiconductor element containing a gap fill oxide film according to one embodiment.

[0049] Referring to Figure 8, the capacitor element 3 according to one embodiment includes a substrate 31, an oxide film 32, a dielectric layer 33, and an electrode 34.

[0050] The substrate 31 is made of a material such as silicon (Si) and can be doped to a P-type.

[0051] In other embodiments, the substrate 31 may consist of at least one component of Si and SiGe. For example, the substrate 31 may be a single layer of Si or a single layer of SiGe. In other examples, the substrate 31 may have a multilayer structure in which a first layer of Si and a second layer of SiGe are alternately stacked.

[0052] The oxide film 32 is an insulating layer and may be formed by at least one of the following processes: HDP (High Density Plasma), FCVD (Flowable Chemical Vapor Deposition), and HPO (High Pressure Oxidation).

[0053] The dielectric layer 33 is made of a dielectric material (for example, HfO3) and functions to induce an electric charge between the substrate 31 and the electrode 34.

[0054] The electrode 34 may be made of a metallic material (for example, TiN).

[0055] Figures 9 and 10 show the electrical characteristics of the capacitor element 3, namely the leakage current and retention time, measured when a voltage is applied to the capacitor element 3 shown in Figure 8. In Figures 9 and 10, M1 represents a capacitor element in which the oxide film 32 is formed by an HDP process, M2 represents a capacitor element in which the oxide film 32 is formed by an FCVD process followed by an HDP process, and M3 represents a capacitor element in which the oxide film 32 is formed by an FCVD process according to the above-described embodiment followed by an HPO process.

[0056] As shown in Figure 9, the leakage current of the capacitor element (M3) containing the oxide film 32 formed by the HPO process after the FCVD process according to one embodiment is smaller than the leakage current of the capacitor elements (M1, M2) containing oxide films formed by other processes. Also, as shown in Figure 10, the charge retention time of the capacitor element (M3) containing the oxide film 32 formed by the HPO process after the FCVD process according to one embodiment is longer than the charge retention time of the capacitor elements (M1, M2) containing oxide films formed by other processes.

[0057] Therefore, a semiconductor device containing an oxide film formed by performing an HPO process after the FCVD process according to one embodiment can exhibit superior electrical characteristics compared to a semiconductor device containing an oxide film formed by an HDP process or an oxide film formed by performing an HDP process after the FCVD process.

[0058] Figure 11 is a graph showing the etching rates of a gap fill oxide film produced by conventional technology and a gap fill oxide film produced by one embodiment.

[0059] In Figure 11, F1 represents a gap fill oxide film formed by a normal wet oxidation process, and F2 represents a gap fill oxide film formed by an HDP process. Furthermore, F3 represents a gap fill oxide film formed by an HDP process after an FCVD process, and F4 represents a gap fill oxide film formed by an HPO process after an FCVD process according to one embodiment.

[0060] Figure 11 shows the wet etching rate (WER) measured when each gap fill oxide film (F1-F4) was wet-etched under the same conditions. As shown in Figure 11, the etching rate of the gap fill oxide film (F4), which was formed by performing the HPO process after the FCVD process according to one embodiment, is lower than that of the other gap fill oxide films (F1, F2, F3). These results mean that the density of the gap fill oxide film (F4), which was formed by performing the HPO process after the FCVD process according to one embodiment, is higher than that of the gap fill oxide films (F1, F2, F3) formed by the other processes. Therefore, as in one embodiment, when the gap fill oxide film is formed by performing the HPO process after the FCVD process, the gap fill oxide film becomes denser and more stable, and the density of the gap fill oxide film increases, thus preventing the gap fill oxide film from breaking during the formation of the device isolation region.

[0061] As described above, the semiconductor device manufacturing method according to the present invention includes a high-pressure oxidation (HPO) step followed by a gap-fill step to form a gap-fill oxide film. In particular, semiconductor devices containing an oxide film formed by performing an FCVD (Flowable Chemical Vapor Deposition) step followed by an HPO (High Pressure Oxidation) step exhibit superior electrical characteristics compared to semiconductor devices containing oxide films formed by conventional processes.

[0062] On the other hand, in yet another embodiment, a gap fill oxide film can be formed by sequentially performing an FCVD process and an HPO process, followed by an HDP process.

[0063] As described above, this specification has been explained with reference to the illustrative drawings, but this specification is not limited to the embodiments and drawings disclosed herein, and various modifications can be made by a person of the ordinary skill. In addition, even if the effects of the configuration described herein are not explicitly stated and explained in the embodiments described herein, the effects that can be predicted by such configuration should also be recognized.

Claims

1. The steps include etching the substrate to form trenches, The steps include forming a liner layer on the inner surface of the trench, which includes a liner nitride film having tensile stress that counteracts the compressive stress caused by gap fill oxides embedded in the trench, The steps include forming a gap fill oxide film on the liner layer to gap fill the inside of the trench, The steps include planarizing the gap fill oxide film, Includes, The gap fill oxide film is formed by performing an FCVD process using gap fill oxide, followed by a high-pressure oxidation (HPO) process, while maintaining the liner nitride film of the liner layer. A method for manufacturing semiconductor devices.

2. The above HPO process is O ２ , O ３ , H ２ O, D ２ O, N ２ O, CO, CO ２ At least one of the following is performed within the supplied processing unit: A method for manufacturing a semiconductor device according to claim 1.

3. When the above HPO process is performed, the internal pressure of the processing apparatus is maintained at 2 to 50 atmospheres. A method for manufacturing a semiconductor device according to claim 1.

4. When the above HPO process is performed, the internal temperature of the processing apparatus is maintained at 200 to 1000°C. A method for manufacturing a semiconductor device according to claim 1.

5. The liner layer is Having a single-layer or multi-layer structure consisting of at least one component from nitride film, oxide film, and polysilicon, A method for manufacturing a semiconductor device according to claim 1.

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