Method and semiconductor structure (multi-Vt nanosheet device)

Abstract

To solve a problem in which devices needing a thicker dielectric for high-voltage operation are limited in allowable dimensions.SOLUTION: A method for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices includes: forming sets of nanosheet stacks having a second intersheet spacing and a first intersheet spacing greater than the second intersheet spacing; depositing a high-k (HK) layer within first and second nanosheet stacks; depositing a material stack that, when annealed, creates a crystallized HK layer 50 in a first set of nanosheet stacks and an amorphous HK layer 34 in a second nanosheet stacks; depositing a dipole material 55; and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] This invention relates to semiconductor devices in general, and more specifically to constructing nanosheet stacks with different threshold voltages without degrading the performance of logic devices. [Background technology]

[0002] In nanometer-scale devices, gate structures are often positioned between other conductive structures such as fin structures or nanosheets. Often, scaling to smaller node technology sizes causes conductive or semiconducting structures to form closer together. [Overview of the project] [Problems that the invention aims to solve]

[0003] This can be a limiting factor in reducing device size. Fin field-effect transistors (finFETs), nanosheets, or combinations thereof can benefit from narrower device spacing, but these dimensions can limit device scaling. Furthermore, devices requiring thicker dielectrics for high-voltage operation have even greater limitations on allowable dimensions. High-voltage devices for input or output circuits, or combinations thereof, require thicker gate dielectrics compared to standard gate devices that may be used, for example, in logic devices with lower voltages. [Means for solving the problem]

[0004] According to one embodiment, a method is provided for achieving different gate threshold voltages across a plurality of field-effect transistor (FET) devices without patterning between nanosheet channels. The method comprises the steps of: forming a first set of nanosheet stacks having a first inter-sheet spacing; forming a second set of nanosheet stacks having a second inter-sheet spacing, wherein the first inter-sheet spacing is greater than the second inter-sheet spacing; depositing high dielectric constant (HK) layers within the first and second nanosheet stacks; depositing a material stack that, upon annealing, forms a crystalline HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second set of nanosheet stacks; depositing a dipole material; and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the plurality of FET devices with different gate threshold voltages.

[0005] According to another embodiment, a method is provided for modulating a threshold voltage for a nanosheet stack without patterning between nanosheet channels. The method comprises the steps of: forming a first nanosheet stack having a first inter-sheet spacing; forming a second nanosheet stack having a second inter-sheet spacing, wherein the first inter-sheet spacing is greater than the second inter-sheet spacing; constructing a crystalline high dielectric constant (HK) layer within the first nanosheet stack; constructing an amorphous high dielectric constant (HK) layer within the second nanosheet stack; depositing a dipole material; and selectively diffusing the dipole material into the amorphous HK layer of the second nanosheet stack to modulate the threshold voltage of the nanosheet stack.

[0006] In yet another embodiment, a semiconductor structure is provided. The semiconductor structure comprises a first nanosheet stack having a first inter-sheet spacing, a second nanosheet stack having a second inter-sheet spacing, wherein the first inter-sheet spacing is greater than the second inter-sheet spacing, a crystalline high dielectric constant (HK) layer disposed within the first nanosheet stack, an amorphous high dielectric constant (HK) layer disposed within the second nanosheet stack, and a dipole material disposed within the first and second nanosheet stacks, wherein the dipole material is selectively diffused into the amorphous HK layer of the second nanosheet stack, modulating the threshold voltage for the nanosheet stack.

[0007] It should be noted that the exemplary embodiments are described with reference to different subject matter. In particular, some embodiments are described with reference to method-type claims, while others are described with reference to apparatus-type claims. However, those skilled in the art will infer from the above and below descriptions that, unless otherwise notified, any combination of features belonging to one type of subject matter, as well as any combination of features relating to different subject matter, in particular, any combination of features of method-type claims and features of apparatus-type claims, are also described herein.

[0008] These and other features and advantages will become apparent from the following detailed description of these exemplary embodiments, when read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0009] The present invention provides further details of preferred embodiments in the following description with reference to the following drawings.

[0010] [Figure 1] This is a cross-sectional view of a semiconductor structure including a nanosheet stack formed on a substrate, according to one embodiment of the present invention, showing that the sacrificial layer in a first region of the semiconductor structure has a first thickness, and the sacrificial layer in a second region of the semiconductor structure has a second thickness.

[0011] [Figure 2] Cross-sectional view of the semiconductor structure of FIG. 1 in which the sacrificial layer of a plurality of nanosheet stacks has been removed, according to an embodiment of the present invention.

[0012] [Figure 3] Cross-sectional view of the semiconductor structure of FIG. 2 in which an interfacial layer / high-k dielectric (IL / HK) is formed adjacent to the remaining layers of a plurality of nanosheet stacks, according to an embodiment of the present invention.

[0013] [Figure 4] Cross-sectional view of the semiconductor structure of FIG. 3 in which a material stack has been deposited, according to an embodiment of the present invention. [[ID=十七]]

[0014] [Figure 5] ]>Cross-sectional view of the semiconductor structure of FIG. 4 in which a part of the material stack is selectively removed and annealing is performed, according to an embodiment of the present invention.

[0015] [Figure 6] Cross-sectional view of the semiconductor structure of FIG. 5 in which a dipole material has been deposited, according to an embodiment of the present invention. [[ID=三十]]

[0016] [Figure 7] Cross-sectional view of the semiconductor structure of FIG. 6 in which a sacrificial layer is deposited, a capping layer is deposited, and annealing is performed to affect the diffusion or non-diffusion of the dipole material, according to an embodiment of the present invention.

[0017] [Figure 8] Cross-sectional view of the semiconductor structure of FIG. 7 in which the sacrificial layer and the capping layer are removed and the undiffused dipole material is also removed, according to an embodiment of the present invention. <000...097> [Figure 9] Cross-sectional view of the semiconductor structure of FIG. 8 in which a gate material has been deposited, according to an embodiment of the present invention.

[0019] Throughout the drawing, identical or similar reference numerals represent identical or similar elements. [Modes for carrying out the invention]

[0020] Embodiments of the present invention provide a method and device for achieving different threshold voltages for field-effect transistor (FET) devices without degrading the performance of logic devices. This method and structure achieves multi-Vt by selective dipole diffusion in selected nanosheet regions. The nanosheet provides a viable device architecture for complementary metal-oxide-semiconductor (CMOS) scaling beyond the 7 nm node. Thin-gate dielectric nanosheet transistors can be used, for example, in logic and static random access memory (SRAM) applications, while thick-gate dielectric nanosheet transistors can be used, for example, in high-voltage and analog applications.

[0021] Embodiments of the present invention provide a method and device for achieving different threshold voltages for an FET device by introducing a dopant into the gate dielectric layer that lowers the crystal temperature of the gate dielectric layer. Furthermore, by selectively crystallizing the gate dielectric in the designed device region, the dipole material can selectively diffuse through the amorphous dielectric layer, but diffusion does not occur in the crystalline dielectric layer. This enables multi-Vt without patterning between nanosheet channels. The dipole-forming element is located in the interface layer between the high-Vt nFET and the low-Vt pFET. Therefore, the high-Vt nFET and the low-Vt pFET have a larger intersheet spacing (T sus ) can be provided with a crystallized HK layer, while low Vt nFETs and high Vt pFETs do not contain dopants in the HK layer and have a smaller intersheet spacing (T sus The material may have an amorphous HK layer having ) . The crystallized HK layer has a dopant such as ZrO due to a lower crystallization temperature than the pure HK material.

[0022] Examples of semiconductor materials that can be used to form such nanosheet structures include silicon (Si), germanium (Ge), silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors, or II-VI compound semiconductors or combinations thereof. III-V compound semiconductors are materials containing at least one element from Group III of the periodic table and at least one element from Group V of the periodic table. II-VI compound semiconductors are materials containing at least one element from Group II of the periodic table and at least one element from Group VI of the periodic table.

[0023] While the present invention is described in relation to a given exemplary architecture, it should be understood that other architectures, structures, substrate materials, and process features and stages / blocks may vary within the scope of the invention. Note that for clarity, certain features may not be shown in all drawings. This is not intended to be construed as limiting any particular embodiment, illustration, or claim.

[0024] Figure 1 is a cross-sectional view of a semiconductor structure including a nanosheet stack formed on a substrate according to one embodiment of the present invention, showing that the sacrificial layer in the first region of the semiconductor structure has a first thickness and the sacrificial layer in the second region of the semiconductor structure has a second thickness.

[0025] In various exemplary embodiments, the semiconductor structure 5 includes shallow trench isolation (STI) regions 12 formed within the substrate 10. Multiple field-effect transistor (FET) devices can be formed on the substrate 10. In one example, two FET devices can be formed on the substrate 10. The FET devices can be formed by constructing nanosheet stacks. In one example, first and second nanosheet stacks 20 can be constructed on the substrate 10.

[0026] Similarly, in various exemplary embodiments, the semiconductor structure 5' includes a shallow trench isolation (STI) region 12 formed within the substrate 10. Multiple field-effect transistor (FET) devices can be formed on the substrate 10. In one example, two FET devices can be formed on the substrate 10. The FET devices can be formed by constructing nanosheet stacks. In one example, first and second nanosheet stacks 20' can be constructed on the substrate 10.

[0027] An isolation layer 14 can be formed between the substrate 10 and the nanosheet stacks 20, 20' of structures 5, 5'. Additionally, a dummy capping layer 26 can be formed on the nanosheet stacks 20, 20' of structures 5, 5'.

[0028] The nanosheet stack 20 of structure 5 may include alternating layers of a first semiconductor layer 22 and a second semiconductor layer 24. The first semiconductor layer 22 may be, for example, silicon germanium (SiGe), and the second semiconductor layer 24 may be, for example, silicon (Si).

[0029] The nanosheet stack 20' of structure 5' may include alternating layers of a first semiconductor layer 22' and a second semiconductor layer 24'. The first semiconductor layer 22' may be, for example, silicon germanium (SiGe), and the second semiconductor layer 24' may be, for example, silicon (Si).

[0030] The difference between structure 5 (left) and structure 5' (right) is the thickness of the sacrificial layers 22 and 22'. The thickness of the first semiconductor layer 22 can be Tsus1, and the thickness of the second semiconductor layer 22' can be Tsus2, where Tsus1 > Tsus2. Note that the nanosheet stacks 20 and 20' can be formed on a common substrate 10. In this way, a dipole device can be formed on a common substrate 10 without a dipole device. The left side shows a nanosheet stack without a dipole device, and the right side shows a nanosheet stack with a dipole device.

[0031] In one or more embodiments, the substrate 10 may be a semiconductor or insulator having an active surface semiconductor layer. The substrate 10 may be crystalline, semicrystalline, microcrystalline, or amorphous. The substrate 10 may be essentially (e.g., excluding contaminants) a single element (e.g., silicon), or primarily (e.g., with doping) a single element, such as silicon (Si) or germanium (Ge), or the substrate 10 may include compounds such as Al2O3, SiO2, GaAs, SiC, or SiGe. The substrate 10 may also have multiple material layers, such as a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), a germanium-on-insulator substrate (GeOI), or a silicon-germanium-on-insulator substrate (SGOI). The substrate 10 may also have other layers forming the substrate 10, including high dielectric constant oxides or nitrides or combinations thereof. In one or more embodiments, the substrate 10 may be a silicon wafer. In one embodiment, the substrate 10 is a single-crystal silicon wafer.

[0032] Shallow trench isolation (STI) regions 12 can be formed by etching trenches into doped bottom source / drain (S / D) regions (not shown) using conventional dry etching processes such as reactive ion etching (RIE) or plasma etching. The trenches can optionally be lined with a conventional liner material, such as silicon nitride or silicon oxynitride, and then filled with silicon oxide or another similar STI dielectric material using chemical vapor deposition (CVD) or another similar deposition process. The STI dielectric can optionally be densified after deposition. Conventional planarization processes, such as chemical mechanical polishing (CMP), can optionally be used to provide a flat structure.

[0033] For example, referring to the first nanosheet stack 20, the first semiconductor layer 22 may be the first layer in a stack of alternating material sheets. The first nanosheet stack 20 includes the first semiconductor layer 22 and the second semiconductor layer 24. While it is particularly intended that the first semiconductor layer 22 may be formed from silicon germanium and the second semiconductor layer 24 may be formed from silicon, it should be understood that any suitable material can be used instead, as long as the two semiconductor materials have etching selectivity with respect to each other. As used herein, the term “selective” in relation to a material removal process means that the material removal rate for the first material is greater than the material removal rate for at least one other material in the structure to which the material removal process is applied. The alternating semiconductor layers 22 / 24 can be deposited by any suitable mechanism. While the primary intention is for the semiconductor layers 22 / 24 to be able to grow epitaxially from one another, alternative deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition are also envisioned. Similar processes can be applied to the semiconductor layers 22' / 24' of the nanosheet stack 20' in structure 5'.

[0034] Figure 2 is a cross-sectional view of the semiconductor structure of Figure 1 in which the sacrificial layers of multiple nanosheet stacks have been removed, according to one embodiment of the present invention.

[0035] In various exemplary embodiments, the nanosheet stacks 20, 20' are etched. Etching can include, for example, dry etching processes such as reactive ion etching, plasma etching, ion etching, and laser ablation. Etching can further include wet chemical etching processes that use one or more chemical etchants to remove portions of the blanket layer not protected by the patterned photoresist.

[0036] In some cases, selective wet etching or selective dry etching can selectively remove the entirety of the first semiconductor layers 22, 22' while leaving all or part of the second semiconductor layers 24, 24'. This removal creates gaps or openings 30 between the second semiconductor layers 24 of the FET device in structure 5 (left side) and gaps or openings 30' between the second semiconductor layers 24' of the FET device in structure 5' (right side).

[0037] Dry and wet etching processes can have adjustable etching parameters, such as the etchant used, etching temperature, etching solution concentration, etching pressure, power supply, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. Dry etching processes can include biased plasma etching processes using chlorine-based chemicals. Other dry etchant gases include tetrafluoromethane (CF4), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), helium (He), and chlorine trifluoride (ClF3). Anisotropic dry etching can also be performed using mechanisms such as deep reactive-ion etching (DRIE). As a selective etching method, chemical vapor deposition (CVD) can be used, and the etching gas can include a gas mixture of hydrogen chloride (HCl), tetrafluoromethane (CF4), and hydrogen (H2). Chemical vapor deposition can be carried out by CVD at suitable pressure and temperature.

[0038] Furthermore, etching exposes the upper surface of the STI region 12.

[0039] Figure 3 is a cross-sectional view of the semiconductor structure shown in Figure 2, according to one embodiment of the present invention, in which an interface layer / high dielectric (IL / HK) is formed adjacent to the remaining layers of a plurality of nanosheet stacks.

[0040] In various exemplary embodiments, the interface layer / high dielectric (IL / HK) 32 / 34 is formed around each of the semiconductor layers 24, 24' of the FET device in structures 5, 5'. The HK 34 can also be formed on the STI region 12 and on the isolation layer 14.

[0041] In some embodiments, the interface layer (IL) 32 can be formed by wrapping around the second semiconductor layers 24, 24'. The IL 32 can be deposited by any suitable method, such as ALD, CVD, or ozono-oxidation. The IL 32 may include, for example, oxides, HfSiO, or oxynitrides.

[0042] The HK dielectric layer 34 can be deposited on and wrapped around the IL 32 by any suitable technique, such as ALD, CVD, metal-organic CVD (MOCVD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, or other suitable techniques. The HK dielectric layer 34 may include, for example, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), or other suitable materials.

[0043] The HK dielectric layer 34 may include a single layer or multiple layers, such as a metal layer, a liner layer, a wetting layer, or an adhesive layer. The HK dielectric layer 34 may include, for example, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, or any suitable material. The HK dielectric layer 34 may be formed by ALD, PVD, CVD, or any other suitable process. A CMP process may be performed to remove excess HK dielectric layer 34.

[0044] Figure 4 is a cross-sectional view of the semiconductor structure of Figure 3 in which a material stack is deposited, according to one embodiment of the present invention.

[0045] In various exemplary embodiments, the material stack can be formed to wrap around the IL / HK32 / 34. The material stack may include three layers. The first layer may be, for example, a titanium nitride (TiN) layer 43, the second layer may be, for example, a zirconium oxide (ZrO) layer 42, and the third layer may be, for example, a TiN layer 40.

[0046] In structure 7, the ZrO layers 42 are individually wrapped around each Si layer 24 such that TiN regions 43 remain between the ZrO layers 42. That is, the ZrO layers 42 are selectively driven into the intermediate region containing the HK dielectric layer 34. By performing rapid heating annealing (RTA) at approximately 950°C to reduce the thickness of the TiN region 43 to approximately 2 nm, the ZrO layers 42 can diffuse into the HK dielectric layer 34 through the 2 nm TiN region 43. Thus, the ZrO layers 42 are shown to encompass or surround each of the Si layers 24.

[0047] In contrast, in structure 7', the ZrO layer 42' is wrapped around all the Si layers 24 together, such that a TiN region 44 remains between the HK dielectric layers 34. In other words, the TiN region 44 is sandwiched in such a way that the ZrO layer 42' does not diffuse into the HK dielectric layer 34.

[0048] Figure 5 is a cross-sectional view of the semiconductor structure shown in Figure 4, according to one embodiment of the present invention, in which a portion of the material stack is selectively removed and annealing is performed.

[0049] In various exemplary embodiments, material stacks are selectively removed from the nanosheet stacks 20 in structure 7 and from the nanosheet stacks 20' in structure 7'. Selective removal of material stacks can be achieved by etching, such as RIE etching.

[0050] Removal of the material stack forms a crystallized HK layer 50 with a blanket PDA in structure 7 (left). The PDA can be applied without coating at a temperature of approximately 500-700°C, which causes only the HK layer in structure 7 to crystallize (because Zr-doped HK has a lower crystallization temperature than pure HK). In contrast, in structure 7' (right), the Si-doped HK layer 34 has a higher crystallization temperature than pure HK. Therefore, in structure 7', the HK layer 34 remains in an amorphous state, while in structure 7, the HK layer 34 is converted to a crystalline state designated as 50.

[0051] Note that IL32 remains unchanged in both structures 7 and 7'.

[0052] Therefore, exemplary embodiments of the present invention have different sheet spacings (T sus ) adopted, sus In region (structure 7), HK is selectively doped with a dopant that lowers the crystallization temperature, such as Zr. That is, the intentional doping of HK is employed to selectively lower the crystallization temperature only for a specific region. Therefore, HK in structure 7' remains in an amorphous state.

[0053] Figure 6 is a cross-sectional view of the semiconductor structure of Figure 5 in which dipole material is deposited, according to one embodiment of the present invention.

[0054] In various exemplary embodiments, the dipole material 55 is deposited.

[0055] The dipole material 55 has an amorphous HK layer 34 wrapped around it in structure 7' and a crystalline HK layer 50 wrapped around it in structure 7. In one example, the dipole material 55 may be, for example, lanthanum oxide (LaO). Those skilled in the art may envision, but are not limited to, other earth elements used for diffusion into the HK layer, such as dysprosium (Dy).

[0056] Therefore, exemplary embodiments of the present invention employ dipole deposition and annealing so that dipoles diffuse only through non-dipole devices. Thus, different threshold voltages (Vt) can be provided. That is, by employing dipole materials and crystallization, large T sus Crystallized HK in the region, small T sus Amorphous HK is constructed in the region to modulate Vt. This results in a gate-all-around device that can be constructed with different inter-sheet spacings and selective dipole diffusion to modulate Vt.

[0057] Figure 7 is a cross-sectional view of the semiconductor structure of Figure 6, according to one embodiment of the present invention, in which a sacrificial layer is deposited, a capping layer is deposited, and annealing is performed to affect the diffusion or non-diffusion of the dipole material.

[0058] In various exemplary embodiments, a sacrificial layer 57 is deposited, a capping layer 59 is deposited, and annealing is performed to affect the diffusion or non-diffusion of the dipole material 55. The sacrificial layer 57 can be, for example, TiN, while the capping layer 59 can be, for example, amorphous silicon (a-Si). Annealing prevents the dipole material 55 from diffusing in the crystalline HK layer 50 (left side), but allows it to diffuse in the amorphous HK layer 34 (right side). This effectively modulates the threshold voltage without patterning between nanosheet channels.

[0059] Figure 8 is a cross-sectional view of the semiconductor structure of Figure 7, according to one embodiment of the present invention, in which the sacrificial layer and capping layer have been removed, and the undiffused dipole material has also been removed.

[0060] In various exemplary embodiments, the sacrificial layer 57 and the capping layer 59 are removed. The dipole material 55 does not diffuse in the crystalline HK layer 50. Instead, the dipole material 55 diffuses only into the amorphous HK 34 (right side) to form diffused dipole material 60. The diffused dipole material 60 is exemplified within the amorphous HK layer 34. In contrast, the dipole material 60 is completely removed from the crystalline HK layer 50 and the isolation layer 14. The diffused dipole material 60 is shown adjacent to only one face of the dummy capping layer 26 in the right-hand structure.

[0061] As a result, the non-dipole device contains a crystalline HK material 50 in which the HK layer is doped with Zr, and the crystalline HK material 50 does not contain the dipole material 55. The dipole material 55 cannot diffuse into the crystalline HK material 50. In contrast, the dipole device contains an amorphous HK material 34, and the dipole material 55 can diffuse into the amorphous HK material 34.

[0062] Figure 9 is a cross-sectional view of the semiconductor structure shown in Figure 8, on which gate material has been deposited, according to one embodiment of the present invention.

[0063] In various exemplary embodiments, work function metal (WFM) 65 can be deposited. The WFM 65 encompasses a non-dipole device 70 and a dipole device 70'.

[0064] WFM65 can be a metal such as, for example, copper (Cu), cobalt (Co), aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), nitride (N) or any combination thereof. The metal can be deposited by a suitable deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), electroplating, thermal or electron beam evaporation, or sputtering. In various exemplary embodiments, the height of WFM65 can be reduced by chemical mechanical polishing (CMP) or etching or a combination thereof. Thus, the planarization process can be provided by CMP. Other planarization processes can include grinding and polishing.

[0065] In some embodiments, the nanosheet stack can include a thin layer made of a conductive channel material. For example, in some embodiments, one or more of the nanosheet stacks can include a group III-V semiconductor material such as Si, SiGe, Ge or InGaAs or a combination thereof, but the concept of the present invention is not limited thereto. The term "Si nanosheet FET" means a nanosheet containing Si, or a nanosheet containing Si in a large proportion, for example Si where x is greater than about 0.3 x Ge 1-x , having a nanosheet FET. The term "non-Si nanosheet FET" means a nanosheet that does not contain Si, such as indium gallium arsenide (InGaAs), or a nanosheet that contains Si in a small proportion, for example Si where y is less than about 0.3 y Ge 1-y , having a nanosheet FET.

[0066] Non-Si nanosheet FETs can have higher channel carrier mobility than equivalent Si nanosheet FETs. Higher channel carrier mobility can lead to higher performance. However, non-Si nanosheet FETs can also have higher interband tunneling (BTBT) leakage current than equivalent Si nanosheet FETs. Generally, high BTBT leakage current can occur within the same device design range as high channel carrier mobility. In non-Si nanosheet FETs, several factors can induce higher BTBT leakage current. For example, parasitic bipolar effects (PBE) can occur when y is less than approximately 0.3 in Si nanosheet FETs. y Ge 1-y For non-Si nanosheet FETs having nanosheets containing [specific material], a large value can be effectively multiplied by the BTBT leakage current, resulting in a significantly high net BTBT induced leakage current.

[0067] In conclusion, exemplary embodiments of the present invention introduce a dopant (e.g., ZrO) that lowers the crystal temperature into the gate dielectric layer. Furthermore, selective crystallization of the gate dielectric in the designed device region allows for selective diffusion of the dipole material through the amorphous dielectric layer, while diffusion does not occur in the crystalline dielectric layer. This enables multi-Vt without patterning between nanosheet channels. The dipole-forming element resides in the interface layer between the high-Vt nFET and the low-Vt pFET. Therefore, the high-Vt nFET and low-Vt pFET have a larger intersheet spacing (T sus ) can include a crystallized HK layer having ), while low Vt nFETs and high Vt pFETs do not contain dopants in the HK layer and have a smaller intersheet spacing (T sus It may include an amorphous HK layer having ) . The crystallized HK layer has dopants such as ZrO due to a lower crystallization temperature than pure HK material.

[0068] In conclusion, a method, structure, or combination thereof is presented for introducing a dopant into the amorphous gate dielectric layer in two types of nanosheet FET gate-all-around stacks without patterning, in order to achieve multi-Vt for nanosheet stacks in a selected region. Here, each type is formed using different thicknesses of sacrificial SiGe between silicon channels. This allows the dopant to diffuse into the gate dielectric layer of stacks formed using the thicker thickness of SiGe, but not into the gate dielectric of stacks formed using the thinner thickness of SiGe. Therefore, the crystal temperature of the gate dielectric layer in stacks formed using the thicker thickness of SiGe is reduced by using blanket annealing to selectively crystallize the gate dielectric in the doped gate dielectric layer in stacks formed between silicon channels using the thicker sacrificial thickness, and by introducing a dipole material and then using spike annealing to selectively diffuse the dipole material through the amorphous dielectric layer but not through the crystalline dielectric layer. Thus, different threshold voltages (Vt) are formed in each of the two nanosheet FET stacks.

[0069] Regarding Figures 1-9, deposition is any process of growing, coating, or otherwise transferring material onto a wafer. Available techniques include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and, more recently, atomic layer deposition (ALD). As used herein, “deposition” may include, but is not limited to, any currently known or subsequently developed techniques appropriate for the material to be deposited, including, for example, chemical vapor deposition (CVD), reduced-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), near-atmospheric pressure CVD (SACVD), and high-density plasma CVD (HDPCVD), rapid heating CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited-reaction-process CVD (LRPCVD), metalloorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and vapor deposition methods.

[0070] As used herein, the term “processing” includes deposition, patterning, exposure, development, etching, washing, stripping, injection, doping, stressing, lamination, removal of material or photoresist, or any combination thereof, of material or photoresist necessary to form the described structure.

[0071] While the present invention is described in relation to a given exemplary architecture, it should be understood that other architectures, structures, substrate materials, process features, and stages / blocks may vary within the scope of the invention.

[0072] When an element such as a layer, region, or substrate is described as being "on" or "over" another element, it will be understood that it may be directly on that other element, or that there may be an intervening element. In contrast, when an element is described as being "directly on" or "directly over" another element, there is no intervening element. When an element is described as being "connected" or "linked" to another element, it will also be understood that it may be directly connected or linked to that other element, and that there may be an intervening element. In contrast, when an element is described as being "directly connected" or "directly linked" to another element, there is no intervening element.

[0073] This embodiment may include a design for an integrated circuit chip, which is created in a graphical computer programming language and can be stored on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, such as within a storage access network). If the designer does not manufacture the chip or the photolithography mask used to manufacture the chip, the designer may transmit the resulting design to such an entity directly or indirectly, either by a physical mechanism (e.g., by providing a copy of the storage medium that stores the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for processing a photolithography mask, which typically contains multiple copies of the chip design in question that will be formed on a wafer. The photolithography mask is used to define areas on the wafer (or layers thereon, or a combination thereof) to be etched or otherwise processed.

[0074] The methods described herein can be used to process integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of a raw wafer (i.e., a single wafer with multiple unpackaged chips), a bare die, or a packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with lead wires that are anchored to a motherboard or other higher carrier) or in a multi-chip package (such as a ceramic carrier with either surface-mounted or embedded wiring, or both). In any case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices or combinations thereof as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product featuring integrated circuit chips ranging from toys and other low-end applications to displays, keyboards or other input devices, or advanced computer products with central processing units.

[0075] Furthermore, it should be understood that material compounds can also be described in terms of enumerated elements, such as SiGe. These compounds contain different proportions of elements within the compound; for example, SiGe contains Si where x is less than or equal to 1. x Ge 1-x This includes, for example, the inclusion of other elements in the compound. Furthermore, even if other elements are included in the compound, the functions according to this embodiment can still be exhibited. In this specification, compounds containing additional elements will be referred to as alloys.

[0076] Any reference in this specification to “one embodiment” or “one embodiment” of the present invention, as well as to other variations thereof, means that the specific aspects, structures, characteristics, etc., described in relation to the embodiments are included in at least one embodiment of the present invention. Therefore, the phrases “in one embodiment” or “in one embodiment” and any other variations appearing in various places throughout this specification do not necessarily all refer to the same embodiment.

[0077] Please understand that the use of " / ", "and / or", or "at least one of" is intended to encompass the selection of only the first enumerated option (A), or only the second enumerated option (B), or both options (A and B), for example, in the cases of "A / B", "A and / or B", or "at least one of A and B". As further examples, in the cases of "A, B or C or a combination thereof" and "at least one of A, B and C", such phrasing is intended to encompass the selection of only the first enumerated option (A), or only the second enumerated option (B), or only the third enumerated option (C), or only the first and second enumerated options (A and B), or only the first and third enumerated options (A and C), or only the second and third enumerated options (B and C), or all three options (A, B, and C). This can be extended to many of the listed items, as will be readily apparent to those skilled in the art in the relevant and related fields.

[0078] The terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit the exemplary embodiments. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context clearly indicates otherwise. Where used herein, the terms “comprise,” “comprising,” “includes,” or “including,” or any combination thereof, specify the presence of a described feature, integer, step, operation, element, or component or combination thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof or combinations thereof.

[0079] Spatially relative terms, such as “underside,” “bottom,” “lower,” “up,” and “upper,” may be used herein to describe the relationship of one element or feature to another, as illustrated in the figures, for the sake of clarity. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if the device in the figure is turned over, an element described as “below” or “underside” another element or feature will then be oriented as “above” another element or feature. Thus, the term “bottom” can encompass both up and down orientations. The device may be in other orientations (rotated 90 degrees, or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. It will also be understood that when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0080] In this specification, various elements may be described using terms such as "first," "second," etc., but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. Therefore, the first element described later can be referred to as the second element without deviating from the scope of this concept.

[0081] While preferred embodiments (intended to be illustrative and not limiting) of a method for achieving different gate threshold voltages across multiple field-effect transistor (FET) devices without patterning between nanosheet channels have been described, it is noted that modifications and variations may be made in light of the teachings above by those skilled in the art. Therefore, it will be understood that modifications may be made in the specific embodiments described within the scope of the invention outlined by the appended claims. Accordingly, while aspects of the invention have been described with the detail and specificity required by patent law, what is claimed and desired to be protected by patent is described in the appended claims.

Claims

1. A method for achieving different gate threshold voltages across multiple field-effect transistor (FET) devices without patterning between nanosheet channels, wherein the method is: The steps include forming a first set of nanosheet stacks having a first inter-sheet spacing, A step of forming a second set of nanosheet stacks having a second inter-sheet spacing, wherein the first inter-sheet spacing is greater than the second inter-sheet spacing. The steps include depositing a high dielectric constant (HK) layer within a first set of nanosheet stacks and a second set of nanosheet stacks, The step of depositing a material stack in which a crystalline HK layer is formed on the first set of nanosheet stacks and an amorphous HK layer is formed on the second set of nanosheet stacks when annealed, The step of depositing the dipole material, The steps include selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the multiple FET devices with the different gate threshold voltages. A method that includes [something].

2. The method according to claim 1, wherein the material stack comprises a first titanium nitride (TiN) layer, a zirconium oxide (ZrO) layer, and a second titanium nitride layer.

3. The method according to claim 2, wherein the material stack is made by selectively doping the HK layer with zirconium (Zr) to lower the crystallization temperature, and forming the crystallized HK layer on a first set of nanosheet stacks having the first intersheet spacing.

4. The method according to any one of claims 1 to 3, wherein the dipole material is lanthanum oxide (LaO).

5. The method according to any one of claims 1 to 3, wherein a sacrificial layer and a capping layer are deposited after the deposition of the dipole material to allow the diffusion of the dipole material into the amorphous HK layer of the second set of nanosheet stacks.

6. The method according to claim 5, wherein the sacrificial layer is TiN and the capping layer is amorphous silicon (a-Si).

7. The method according to any one of claims 1 to 3, further comprising the step of depositing a gate metal on the nanosheet stack in the first set and on the nanosheet stack in the second set.

8. A method for modulating a threshold voltage for a nanosheet stack without patterning between nanosheet channels, wherein the method is The steps include forming a first nanosheet stack having a first inter-sheet spacing, A step of forming a second nanosheet stack having a second inter-sheet spacing, wherein the first inter-sheet spacing is greater than the second inter-sheet spacing. The steps include constructing a crystalline high dielectric constant (HK) layer within the first nanosheet stack, The steps include constructing an amorphous high dielectric constant (HK) layer within the second nanosheet stack, The step of depositing the dipole material, The steps include selectively diffusing the dipole material into the amorphous HK layer of the second nanosheet stack and modulating the threshold voltage for the nanosheet stack. A method that includes [something].

9. The method according to claim 8, further comprising the step of depositing a material stack that forms the crystallized HK layer on the first nanosheet stack and the amorphous HK layer on the second nanosheet stack when annealed.

10. The method according to claim 9, wherein the material stack comprises a first titanium nitride (TiN) layer, a zirconium oxide (ZrO) layer, and a second titanium nitride layer.

11. The method according to claim 10, wherein the material stack is formed by selectively doping the HK layer with zirconium (Zr) to lower the crystallization temperature, and forming the crystallized HK layer on the first nanosheet stack having the first intersheet spacing.

12. The method according to any one of claims 8 to 11, wherein the dipole material is lanthanum oxide (LaO).

13. The method according to any one of claims 8 to 11, wherein a sacrificial layer and a capping layer are deposited after the deposition of the dipole material to enable the diffusion of the dipole material into the amorphous HK layer of the second nanosheet stack.

14. The method according to claim 13, wherein the sacrificial layer is TiN and the capping layer is amorphous silicon (a-Si).

15. The method according to any one of claims 8 to 11, further comprising the step of depositing a gate metal on the first nanosheet stack and the second nanosheet stack.

16. A first nanosheet stack having a first inter-sheet spacing, A second nanosheet stack having a second inter-sheet spacing, wherein the first inter-sheet spacing is greater than the second inter-sheet spacing, A crystalline high dielectric constant (HK) layer disposed within the first nanosheet stack, An amorphous high dielectric constant (HK) layer disposed within the second nanosheet stack, A dipole material present in the second nanosheet stack and not present in the first nanosheet stack A semiconductor structure comprising the features described above.

17. The semiconductor structure according to claim 16, wherein the dipole material is lanthanum oxide (LaO).

18. The semiconductor structure according to claim 16 or 17, wherein the crystallized HK layer includes a dopant that reduces the crystallization temperature.

19. The semiconductor structure according to claim 18, wherein the dopant is zirconium oxide (ZrO).

20. The semiconductor structure according to claim 16 or 17, wherein the gate metal is in direct contact with the crystalline HK layer in the first nanosheet stack and the amorphous HK layer in the second nanosheet stack.

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