Quantum mechanical circuit, superconducting quantum mechanical computer, and method for manufacturing a quantum mechanical circuit

Abstract

The quantum mechanical circuit includes a substrate, a first conductor and a second conductor disposed on the substrate and spaced apart to provide a gap therebetween, and a third conductor electrically connecting the first conductor and the second conductor, the third conductor being a poor thermal conductor.

Description

Technical Field

[0001] The embodiments currently recited in the claims of the present invention relate to quantum mechanical circuits, and more specifically, to quantum mechanical circuits having electrical conductors that are low thermal conductors.

[0002] In a typical printed circuit board (PCB), generally a relatively large continuous ground plane is provided. The return current from a signal that travels across a typical PCB proceeds unobstructed. This may be desirable in normal electrical applications, but in electrical applications where heat insulation plays an important role, the continuous conductive ground plane, together with everything connected to it, will also short-circuit thermally. This can cause problems in any application that is affected by temperature gradients.

[0003] In applications where a common electrical ground is required, splitting a ground plane where multiple signals need to cross the boundary between two split ground planes is usually completely avoided. A conventional method for reducing heat transfer is to use a capacitor to fill the gap between these two separated or split ground planes. In applications affected by temperature gradients, due to the above-mentioned thermal short-circuit problem, PCBs are typically not used.

[0004] As a result, there remains a need for electrical circuits that enable electrical conduction while reducing heat transfer. Therefore, it would be desirable to solve this and other problems of the prior art by providing a new type of circuit used in quantum computers, such as superconducting quantum computers, where heat dissipation or transmission is often undesirable.

Summary of the Invention

[0005] One aspect of the present invention is to provide a quantum mechanical circuit. The quantum mechanical circuit includes a substrate; a first conductor and a second conductor provided on the substrate and spaced apart so as to provide a gap therebetween; and a third conductor for electrically connecting the first conductor and the second conductor. The third conductor is a low thermal conductor.

[0006] In one embodiment, the third conductor comprises at least one of copper-nickel (CuNi) or stainless steel. In one embodiment, CuNi has an electrical resistivity of about 3.8 × 10⁻⁸ Ωm at ambient temperature and a thermal conductivity of 25 W / m·K to 40 W / m·K. In one embodiment, the first and second conductors comprise copper (Cu). In one embodiment, the first, second, and third conductors are configured to transmit radio frequency current. In one embodiment, the third conductor is bonded to a substrate using fasteners. In one embodiment, the fasteners comprise brass. In one embodiment, the first and second conductors are connected to electrical ground. In one embodiment, the first and second conductors are electrically isolated by providing a gap or channel between them in the substrate. In one embodiment, the quantum mechanical circuit further comprises attenuator chips electrically coupled to the first and second conductors.

[0007] Another aspect of the present invention is a superconducting quantum mechanical computer. The superconducting quantum mechanical computer includes a cooling system having a temperature-controlled vessel; a quantum processor having a plurality of qubits disposed within the temperature-controlled vessel; and a superconducting circuit disposed within the temperature-controlled vessel. The superconducting circuit includes a substrate; a first conductor and a second conductor provided on the substrate and spaced apart with a gap between them; and a third conductor for electrically connecting the first and second conductors, the third conductor being a low thermal conductor. Each of the plurality of qubits is provided on the substrate and is electrically connected to ground, at least via at least one of the first or second conductors.

[0008] Yet another aspect of the present invention is to provide a method for manufacturing quantum mechanical circuits. The method includes the steps of: providing a substrate having an upper surface and a lower surface; forming a conductive layer on at least one of the upper surface and the lower surface of the substrate; forming a conductor on the substrate in a selected pattern by removing a plurality of portions of the conductive layer, wherein the conductor comprises a first conductor and a second conductor on the substrate, the first conductor and the second conductor being separated and isolated by a gap between them; and electrically connecting the first conductor and the second conductor using a third conductor, the third conductor being a low thermal conductor. [Brief explanation of the drawing]

[0009] The present disclosure, as well as the operation and function of the relevant structural elements, the combination of parts, and the economics of manufacture, will become more apparent upon consideration of the following description and the appended claims with reference to the appended drawings, all of which form part of this specification, and similar reference numerals designate corresponding parts in various drawings. However, it should be clearly understood that these drawings are for illustrative and illustrative purposes only and are not intended as definitions of the limitations of the present invention.

[0010] [Figure 1] This is an electronic schematic diagram of a quantum machine circuit 100 according to one embodiment of the present invention.

[0011] [Figure 2] This is a three-dimensional perspective view of the electrical coupling between a first conductor, a second conductor, and a third conductor according to one embodiment of the present invention.

[0012] [Figure 3] This is a three-dimensional perspective view of the configuration of the first conductor and the second conductor according to one embodiment of the present invention.

[0013] [Figure 4] This is a schematic diagram showing a superconducting quantum mechanical computer according to one embodiment of the present invention.

[0014] [Figure 5] This is a flowchart illustrating a method for manufacturing a quantum mechanical circuit according to one embodiment of the present invention. [Modes for carrying out the invention]

[0015] Figure 1 is an electronic schematic diagram of a quantum mechanical circuit 100 according to one embodiment of the present invention. The quantum mechanical circuit 100 includes a substrate 102. The quantum mechanical circuit 100 also includes a first conductor 104 and a second conductor 106 provided on the substrate 102. The quantum mechanical circuit 100 further includes a third conductor 108 (shown in Figure 2) for electrically connecting the first conductor 104 and the second conductor 106. The third conductor 108 is a low thermal conductor. The term “low thermal conductor” is used broadly herein to mean that the third conductor 108 has a thermal conductivity substantially lower than that of the first conductor 104 and the second conductor 106. In one embodiment, the material of the third conductor 108 (low thermal conductor) may be selected to have a sufficiently low thermal conductivity so that the cooling device (e.g., cooling container) in which the circuit 100 is used can sufficiently cool the circuit 100 to a desired temperature (e.g., the operating temperature of the circuit). The selection of a material with a specific thermal conductivity depends on the system in which the circuit 100 is used. For example, if the cooling device (e.g., cooling container) has sufficient cooling capacity, a material with a higher thermal conductivity may be acceptable.

[0016] Figure 2 is a three-dimensional perspective view of the electrical coupling between a first conductor 104, a second conductor 106, and a third conductor 108 according to one embodiment of the present invention. As shown in Figure 2, the third conductor 108 is configured to electrically connect the first conductor 104 and the second conductor 106. In one embodiment, the third conductor 108 comprises at least one of copper-nickel (CuNi) or stainless steel. In one embodiment, CuNi has an electrical resistivity of about 3.8 × 10⁻⁸ Ωm at ambient temperature and a thermal conductivity of about 25 W / m·K to 40 W / m·K. However, as will be understood, other materials having lower thermal conductivity may also be used for the third conductor 108.

[0017] In one embodiment, the first conductor 104 and the second conductor 106 contain copper (Cu). The material of the third conductor 108 is different from the material of the first conductor 104 and the second conductor 106. In one embodiment, the material of the first conductor 104 and the material of the second conductor 106 may be substantially the same. For example, both the material of the first conductor 104 and the material of the second conductor 106 may be essentially copper (Cu), while the material of the third conductor 108 is essentially CuNi or stainless steel or a combination thereof. In one embodiment, the substrate 102 is an electrically non-conductive (electrically insulating) material, such as silicon (Si), sapphire (Al2O3), printed circuit board material (e.g., FR-4 (woven glass and epoxy) or other laminated boards, fiberglass) or polymer (e.g., polyimide).

[0018] In one embodiment, the third conductor 108 is bonded to the substrate 102 using a fastener 110. In one embodiment, the fastener 110 includes, for example, a brass fastener. However, other types of fasteners may also be used. In addition, in another embodiment, the third conductor 108 may also be bonded to the substrate 102 by other means, such as by using an adhesive.

[0019] In one embodiment, the first conductor 104, the second conductor 106, and the third conductor 108 are configured to transmit radio frequency (RF) current. In one embodiment, the first conductor 104 and the second conductor 106 are connected to ground potential.

[0020] In one embodiment, the first conductor 104 and the second conductor 106 are electrically isolated by providing a discontinuity, gap, or channel 112 between the first conductor 104 and the second conductor 106 within the substrate 102. The first conductor 104 and the second conductor 106 are spaced apart to provide a gap 112 between them.

[0021] Figure 3 is a three-dimensional perspective view of the configuration of a first conductor 104 and a second conductor 106 according to one embodiment of the present invention. As shown in Figure 3, a discontinuity, gap, or channel 112 is provided between the first conductor 104 and the second conductor 106. In the embodiment, as shown in Figure 3, the two layers 116A and 116B can be used for signal transmission. For example, the discontinuity, channel, or gap 112 in layers 116A and 116B improves thermal insulation and assists in steering the return current. This dual-sided configuration increases density. In addition, in one embodiment, the top and bottom splitting positions 112 are offset by removing the internal ground surface from the internal layers of the substrate 102 (not shown) and by providing blind vias (i.e., vias on layers 116A and 11B that are not aligned with each other) to reduce electrical coupling.

[0022] Furthermore, as shown in Figure 3, the provision of attenuator chips 114 above and below layers 116A and 116B can improve electrical signal isolation. The attenuator chips 114 are electrically coupled (e.g., by wire bonding or soldering) to the first and second conductors 104 and 106. In one embodiment, the attenuator chips 114 may be wire-bonded or soldered (e.g., by surface-mount soldering or ball grid array soldering) across the grounding division 112. In addition, in other embodiments, other types of components, such as filtering, may be used in addition to or instead of the attenuator chips 114. In one embodiment, as shown in Figure 3, the provision of discontinuities or gaps 112 in both layers 116A and 116B can eliminate the grounding surface inside the substrate 102 (not shown), thereby reducing coupling and improving insulation. Furthermore, the provision of vias 118 within the substrate 102 (not shown) can further reduce coupling by ensuring that the electrical signals have appropriate electromagnetic mode conversion. Thus, the electromagnetic (EM) field can more efficiently utilize the ground potential for the return current path across the discontinuity 112 in the grounding surface (i.e., the discontinuity, gap, or channel 112 between the first conductor 104 and the second conductor in both layers 116A and 116B). Therefore, the ground potential is provided by the first conductor 104, the second conductor 106, and the third conductor 108, which are connected to each other and to ground.

[0023] Therefore, as can be understood from the above paragraphs, in some embodiments of the present invention, by dividing the ground plane, the problem of heat insulation can be addressed. The ground plane corresponds to a first conductor 104 and a second conductor 106 both connected to the ground potential. Thus, the division in the ground plane corresponds to a gap or discontinuity or channel 112 provided between the first conductor 104 and the second conductor 106. The gap or channel 112 provides good heat insulation, but this can cause many problems associated with the return current path. As a result, a third conductor 108 is provided to be electrically connected to the first conductor 104 and the second conductor 106. However, in order to provide heat insulation between the first conductor 104 and the second conductor 106 (in this example, in the ground plane), the third conductor 108 is selected to be a low thermal conductor, such as a CuNi alloy or stainless steel, for example. CuNi is a relatively good electrical conductor but a low thermal conductor.

[0024] FIG. 4 is a schematic diagram showing a superconducting quantum computer 200 according to an embodiment of the present invention. The superconducting quantum computer 200 includes a cooling system including a temperature-controlled container 202. The superconducting quantum computer includes a quantum processor 204 disposed within the temperature-controlled container 202, and the quantum processor includes a plurality of qubits 206. The superconducting quantum computer 200 further includes a quantum machine circuit 100 disposed inside the temperature-controlled container 202. As shown in FIG. 1, the circuit 100 includes a substrate 102, a first conductor 104 and a second conductor 106 provided on the substrate 102. The circuit 100 also includes a third conductor 108 that electrically connects the first conductor 104 and the second conductor 106, and the third conductor 108 is a low thermal conductor. Each of the plurality of qubits 206 is provided on the substrate 102 and is electrically connected to the ground through at least one of the first or second conductors 104 and 106.

[0025] FIG. 5 is a flowchart of a method for manufacturing a quantum machine circuit according to an embodiment of the present invention. This method includes 1. At S100, providing a substrate 102 having a top surface and a bottom surface (e.g., silicon, polymer, laminated board, glass fiber, etc.); 2. At S102, forming a conductive layer (e.g., a copper layer) on at least one of the top surface and the bottom surface of the substrate; 3. At S104, forming conductive lines on the substrate 102 in a selected pattern by removing a plurality of portions of the conductive layer, the conductive lines including a first conductor 104 and a second conductor 106 on the substrate 102, and the first conductor 104 and the second conductor 106 being separated and spaced apart by a gap therebetween; and 4. At S106, electrically connecting the first conductor 104 and the second conductor 106 using a third conductor 108 (shown in FIG. 2), the third conductor 108 being a low thermal conductor (e.g., CuNi or stainless steel) including. In one embodiment, the first and second conductors 104 and 106 may be connected to electrical ground.

[0026] This method may further include, before forming the conductive lines on the substrate 102 in a selected pattern, 5. Attaching a photoresist layer to the conductive layer; 6. Attaching a light absorber to the photoresist layer in a selected pattern to cover a plurality of portions of the photoresist layer corresponding to the selected pattern; 7. Irradiating the photoresist layer with electromagnetic radiation (e.g., ultraviolet radiation) to cure a plurality of regions of the photoresist layer not covered by the light absorber; 8. Removing a plurality of regions of the photoresist layer corresponding to a plurality of covered portions of the photoresist layer not cured by the electromagnetic radiation to expose a plurality of portions of the conductive layer; 9. Etching and removing the plurality of exposed portions of the conductive layer without etching the plurality of portions of the conductive layer under the cured regions of the photoresist; 10. The step of removing multiple cured regions of the photoresist layer to expose multiple portions of the unetched conductive layer, the multiple portions of the unetched conductive layer corresponding to selected patterns to form a wire; and 11. Step of forming vias within the substrate at selected locations within the substrate. It also includes.

[0027] The descriptions of various embodiments of the present invention have been presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best describe the principles of the embodiments, the practical application or technical improvement of the technology found in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. substrate; A first conductor and a second conductor, which are conductive layers connected to electrical ground, provided on the same surface of the substrate and spaced apart with a gap between them; and A third conductor for electrically connecting the first conductor and the second conductor in the gap. Equipped with, The third conductor has a lower thermal conductivity than the first and second conductors, and comprises at least one of copper-nickel (CuNi) or stainless steel. CuNi has a temperature of 3.8 × 10⁻¹⁰ at ambient temperature. －８ It has an electrical resistivity of Ωm and a thermal conductivity of 25 W / m·K to 40 W / m·K. The third conductor is configured to connect the upper surface of the first conductor and the upper surface of the second conductor, and to connect the lower surface of the first conductor and the lower surface of the second conductor. Quantum mechanical circuit.

2. The quantum mechanical circuit according to claim 1, wherein the first conductor and the second conductor are made of copper (Cu).

3. The quantum mechanical circuit according to claim 1 or 2, wherein the first conductor, the second conductor, and the third conductor are configured to transmit radio frequency current.

4. The quantum mechanical circuit according to any one of claims 1 to 3, wherein the third conductor is bonded to the substrate using fasteners.

5. The fastener is made of brass, as described in claim 4 of the quantum mechanical circuit.

6. The quantum mechanical circuit according to any one of claims 1 to 5, wherein the first conductor and the second conductor are electrically isolated within the substrate by providing the gap between the first conductor and the second conductor.

7. The quantum mechanical circuit according to any one of claims 1 to 6, further comprising an attenuator chip electrically coupled to the first conductor and the second conductor.

8. A cooling system with a temperature-controlled container; A quantum processor disposed within the temperature-controlled container, the quantum processor having a plurality of qubits; A superconducting circuit is placed inside the temperature-controlled container. Equipped with, The superconducting circuit is substrate; A first conductor and a second conductor, which are conductive layers connected to electrical ground, provided on the same surface of the substrate and spaced apart with a gap between them; and A third conductor electrically connects the first conductor and the second conductor in the gap, It has, The third conductor has a lower thermal conductivity than the first and second conductors, and comprises at least one of copper-nickel (CuNi) or stainless steel. CuNi has a temperature of 3.8 × 10⁻¹⁰ at ambient temperature. －８ It has an electrical resistivity of Ωm and a thermal conductivity of 25 W / m·K to 40 W / m·K. Each of the plurality of cubits is provided on the substrate and is electrically connected to earth via at least one of the first conductor or the second conductor. The third conductor is configured to connect the upper surface of the first conductor and the upper surface of the second conductor, and to connect the lower surface of the first conductor and the lower surface of the second conductor. Superconducting quantum mechanical computer.

9. The superconducting quantum mechanical computer according to claim 8, wherein the first conductor and the second conductor are made of copper (Cu).

10. The superconducting quantum mechanical computer according to claim 8 or 9, wherein the first conductor, the second conductor, and the third conductor are configured to transmit radio frequency current.

11. The superconducting quantum mechanical computer according to any one of claims 8 to 10, wherein the third conductor is bonded to the substrate using fasteners.

12. The superconducting quantum mechanical computer according to any one of claims 8 to 11, wherein the first conductor and the second conductor are electrically isolated in the substrate by providing the gap between the first conductor and the second conductor.

13. A superconducting quantum mechanical computer according to any one of claims 8 to 12, further comprising an attenuator chip electrically coupled to the first conductor and the second conductor.

14. A step of providing a substrate having an upper surface and a lower surface; A step of forming a conductive layer on at least one of the upper surface and the bottom surface of the substrate; The step of forming a conductor on the substrate in a selected pattern by removing a plurality of portions of the conductive layer, wherein the conductor includes a first conductor and a second conductor on the same plane of the substrate, the first conductor and the second conductor being separated and isolated by a gap between them, and the conductive layer being connected to electrical ground; and The step of electrically connecting the first conductor and the second conductor using a third conductor, wherein the third conductor has a lower thermal conductivity than the first conductor and the second conductor and is made of at least one of copper-nickel (CuNi) or stainless steel, and CuNi has a thermal conductivity of 3.8 × 10⁻¹⁶ at ambient temperature. －８ It has an electrical resistivity of Ωm and a thermal conductivity of 25 W / m·K to 40 W / m·K. Equipped with, The step of electrically connecting the first conductor and the second conductor using the third conductor includes the steps of connecting the upper surface of the first conductor and the upper surface of the second conductor, and connecting the lower surface of the first conductor and the lower surface of the second conductor, A method for manufacturing quantum mechanical circuits.

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