High-density memory devices using oxide gap fills

Abstract

A semiconductor structure forms two or more narrow pitch memory devices using a dielectric material for gap fill material. The method includes providing two adjacent bottom electrodes in a layer of insulating material and above a metal layer. Two adjacent pillars each overlie one of the two adjacent bottom electrodes, each of the two adjacent pillars being comprised of a stack of materials for the memory devices. A spacer circumscribes a vertical side of each of the two adjacent pillars. A dielectric material abuts the spacer circumscribes a vertical side of each of the two adjacent pillars and overlies the insulating material layer between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of the gap between the two adjacent pillars. A low-k material covers the dielectric material and the exposed portion of the layer of insulating material.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor device manufacturing, and more particularly to the formation of high-density memory device structures.

Background Art

[0002] The expansion of computing capabilities that require both more device circuits and faster processing speeds continues for computer systems and applications. In particular, the use of deep neural networks is becoming widespread in many end-use computer applications. Deep neural networks are typically used in artificial intelligence (AI) applications. Training deep neural networks places a heavy burden on the memory system of a computer system that executes AI using the deep neural network.

[0003] Due to the increasing demand for high-performance memory systems, the development of new advanced memory devices within memory chips continues. The development of advanced memory devices includes magnetoresistive random-access memory (MRAM), a type of non-volatile random-access memory that stores data in magnetic domains, resistive random-access memory (RRAM (R) or ReRAM) that operates by changing the resistance at both ends of a dielectric solid material, and phase change random-access memory (PCRAM (phase change random-access memory) or PCM (phase change memory)) that uses a phase change material that usually has at least two solid phases with significantly different electrical properties, namely a crystalline state and an amorphous state.

[0004] The demand for high-performance memory systems in current computer applications is driving increased density of memory devices within memory chips. By reducing the pitch, or the spacing between memory devices, the number of usable memory devices within a memory chip increases, while simultaneously reducing the distance between memory devices, thus improving the performance of the memory chip. [Overview of the project]

[0005] Embodiments of the present invention disclose a semiconductor structure comprising two adjacent lower electrodes located within a layer of a first dielectric material and above a metal layer. The semiconductor structure comprises two adjacent pillars, each located above one of the two adjacent lower electrodes, and each pillar of the two adjacent pillars is composed of a stack of memory device material. In addition, the semiconductor structure comprises spacers around the vertical sides of each of the two adjacent pillars. The semiconductor structure comprises a second dielectric material in contact with the spacers around the vertical sides of each of the two adjacent pillars and located on the layer of the first dielectric material between the two adjacent lower electrodes, the second dielectric material filling at least a first portion of the gap between the two adjacent pillars. The semiconductor structure comprises an oxide material and a low-k material covering the exposed portion of the layer of the first dielectric material.

[0006] Embodiments of the present invention disclose a semiconductor structure comprising two adjacent lower electrodes located within a layer of a first dielectric material and above a metal layer. The semiconductor structure comprises two adjacent pillars, each located above one of the two adjacent lower electrodes, and each pillar of the two adjacent pillars is composed of a stack of memory device material. In addition, the semiconductor structure comprises two spacers, each spacer located around one of the two adjacent pillars. The semiconductor structure comprises a second dielectric material covering each of the two spacers and filling a first portion of the gap between the two adjacent pillars. The semiconductor structure comprises voids in the second dielectric material adjacent to one or more or two lower electrodes in the lower portion of the material stack. The semiconductor structure further comprises two upper electrodes on the two adjacent pillars and a low-k dielectric material in contact with the oxide material, surrounding the two upper electrodes, and above the exposed portion of the layer of the first dielectric material adjacent to the second dielectric material.

[0007] Embodiments of the present invention disclose a semiconductor structure comprising two adjacent lower electrodes located within a layer of a first dielectric material and above a metal layer. The semiconductor structure comprises two adjacent pillars, each located above one of the two adjacent lower electrodes, with each pillar of the two adjacent pillars comprising a stack of memory device material. The semiconductor structure comprises a layer of spacer material around the vertical sides of each of the two adjacent pillars and a thinner portion of the spacer material layer on the surface of the first dielectric material. The semiconductor structure comprises a second dielectric material in contact with the spacers around the vertical sides of each of the two adjacent pillars and above the thinner portion of the spacer material on the surface of the first dielectric material, filling at least a first portion of the gap between the two adjacent pillars. In addition, the semiconductor structure comprises a second dielectric material, a low-k material covering the exposed portion of the thinner portion of the spacer material layer on the surface of the first dielectric material, and an upper electrode located in the low-k dielectric material above the top of each of the two adjacent pillars.

[0008] Embodiments of the present invention provide a method for forming a narrow-pitch memory device using a second dielectric material for gap-filling between vertical structures of a narrow-pitch semiconductor device. The method includes forming at least two vertical memory structures on at least two adjacent lower electrodes in a first dielectric layer, each of the at least two vertical memory structures being a pillar for a magnetoresistive random-access memory device. The method includes forming spacers in contact with each vertical memory structure and depositing a second dielectric material so as to cover the at least two vertical memory structures and the first dielectric layer. The method includes etching the second dielectric material, the etching leaving the second dielectric material on the vertical surfaces of the spacers in contact with each vertical memory structure and on the first dielectric layer between at least two lower electrodes. The method includes depositing a low-k dielectric material so as to cover the second dielectric material and on the exposed portions of the first dielectric layer and forming upper electrodes on each pillar of the magnetoresistive random-access memory device.

[0009] The above and other embodiments, features, and advantages of various embodiments of the present invention will become more apparent from the following description in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] This figure shows a cross-sectional view of a semiconductor structure having a personalized metal layer in an interlevel dielectric (ILD) according to one embodiment of the present invention. [Figure 2] This figure shows a cross-sectional view of a semiconductor structure after a dielectric layer has been deposited, according to one embodiment of the present invention. [Figure 3] This figure shows a cross-sectional view of a semiconductor structure after a lower electrode with a metal liner has been formed, according to one embodiment of the present invention. [Figure 4]This figure shows a cross-sectional view of a semiconductor structure after depositing a stack of material layers for a magnetic tunnel junction (MTJ) and a hard mask layer, according to one embodiment of the present invention. [Figure 5] This figure shows a cross-sectional view of a semiconductor structure covered with a personalized anti-reflection (AR) coating after depositing an optical planarization layer (OPL) according to one embodiment of the present invention. [Figure 6] This figure shows a cross-sectional view of a semiconductor structure after an etching process according to one embodiment of the present invention. [Figure 7] This is a cross-sectional view of a semiconductor structure after deposition of dielectric spacer material according to one embodiment of the present invention. [Figure 8] This figure shows a cross-sectional view of a semiconductor structure after spacer formation according to one embodiment of the present invention. [Figure 9] This figure shows a cross-sectional view of a semiconductor structure after depositing a layer of oxide material according to one embodiment of the present invention. [Figure 10] This figure shows a cross-sectional view of a semiconductor structure after etching an oxide material according to one embodiment of the present invention. [Figure 11] This figure shows a cross-sectional view of a semiconductor structure after depositing a low-k dielectric material according to one embodiment of the present invention. [Figure 12] This figure shows a cross-sectional view of a semiconductor structure after the upper electrode has been formed, according to one embodiment of the present invention. [Figure 13] This figure shows a cross-sectional view of a semiconductor structure having voids in an oxide, according to one embodiment of the present invention. [Figure 14] This figure shows a cross-sectional view of a semiconductor structure after etching a layer of spacer material to form a spacer, according to another embodiment of the present invention. [Figure 15] This figure shows a cross-sectional view of a semiconductor structure after oxide material has been deposited, according to one embodiment of the present invention. [Figure 16]This figure shows a cross-sectional view of a semiconductor structure after etching a portion of the oxide material, according to one embodiment of the present invention. [Figure 17] This figure shows a cross-sectional view of a semiconductor structure after depositing a low-k dielectric material according to one embodiment of the present invention. [Figure 18] This figure shows a cross-sectional view of a semiconductor structure after the upper electrode has been formed, according to one embodiment of the present invention. [Figure 19] This figure shows a cross-sectional view of a semiconductor structure having voids in an oxide material according to one embodiment of the present invention. [Modes for carrying out the invention]

[0011] In embodiments of the present invention, it is recognized that computer applications for artificial intelligence require a highly functional memory system. In embodiments of the present invention, it is recognized that as the functionality of the memory system is enhanced, further advancements in semiconductor devices, including several advanced memory device structures, will continue.

[0012] In embodiments of the present invention, it is recognized that achieving high functionality in memory systems will not only advance the development of advanced memory device structures but also lead to continuous increases in the density of memory devices. In embodiments of the present invention, it is recognized that in order to focus on improving the performance of computer applications, particularly deep neural networks, more advanced memory devices and narrower memory device pitches are necessary to provide a more functional memory system.

[0013] In embodiments of the present invention, when developing advanced memory devices highly integrated using leading-edge 14nm and future 7nm semiconductor device technologies, it is recognized that the challenges of semiconductor processes increase. The challenges related to semiconductor processes and materials become particularly prominent when advanced memory devices form narrow pitch arrays. In embodiments of the present invention, it is recognized that the ability to fill recesses occurring between vertical structures in advanced memory devices with narrow pitches is becoming increasingly difficult.

[0014] In embodiments of the present invention, it is recognized that when vertical structures in advanced non-volatile memory devices, such as magnetic tunnel junction (MTJ) pillars also known as MRAM pillars, become very high density and densely integrated, the filling of recesses or gaps between the vertical structures may be incomplete. If the filling of the gaps between narrow pitch memory devices is incomplete, seams or voids may occur between the vertical structures of the memory devices that can take in processing chemicals or cause a short circuit between the upper electrodes. In addition, in advanced memory devices, seams or voids occurring between vertical structures, i.e., pillars, reduce the dielectric breakdown strength of the dielectric material used to fill the gaps between the vertical structures of the memory devices. In embodiments of the present invention, new materials and processes that provide the ability to fill gaps and recesses between narrow pitch vertical structures of advanced memory devices are desired.

[0015] Embodiments of the present invention provide a semiconductor structure and method for forming a memory device integrated at high density with effective gap filling between vertical structures of a narrow pitch, high - end memory device. Embodiments of the present invention provide several methods and materials for fabricating a narrow pitch, high - end memory device with a substantially void - free dielectric fill between vertical structures in an array of high - end memory devices. Embodiments of the present invention disclose several methods for forming a narrow pitch MRAM device with a substantially void - free gap fill between MRAM pillars, and embodiments of the present invention also provide methods and materials applicable to other high - end memory devices such as RRAM and PCRAM devices.

[0016] Embodiments of the present invention provide a semiconductor structure for a high - end memory device that uses a dielectric material, such as an oxide material or spin - on glass, to fill the gap between vertical structures in a high - end memory device, such as the gap between adjacent MRAM pillars. In embodiments of the present invention, dielectric materials, such as various oxide materials, are used between narrow pitch MRAM pillars for better conformality, i.e., gap filling, than the low - k materials commonly deposited between MRAM pillars. [[ID=⑥]]

[0017] [[ID=⑦]] [[ID=⑧]]In embodiments of the present invention, a semiconductor structure is provided in which a dielectric material fills the gap between MRAM pillars to prevent void or seam formation between upper electrodes or bit lines in an MRAM device with a close pitch. In addition, embodiments of the present invention include depositing a low - k dielectric between upper electrodes and bit lines in the memory region and in the logic region of a semiconductor chip to improve electrical performance. The low - k dielectric material in the logic region of the semiconductor chip and between upper electrodes and bit lines in the memory region achieves a switching speed better than that of a deposited oxide material or other dielectric material of higher dielectric constant and of similar thickness, and reduces parasitic capacitance. [[ID=⑨]] [[ID=⑩]]

[0018] [[ID=⑪]] Using dielectric materials such as oxide materials with improved gap-fill properties to fill the recesses between the pillars of a memory device's narrow-pitch vertical structure reduces the aspect ratio, or depth, of the low-k dielectric filling between the upper electrodes and bit lines. Embodiments of the present invention that use dielectric materials with superior gap-fill properties compared to currently used low-k dielectric materials provide essentially void-free gap-fill between the pillars of an MRAM device.

[0019] Embodiments of the present invention include materials and processes that enable the deposition of dielectric material to fill the spaces between vertical structures such as MRAM pillars in an MRAM device, thereby forming a essentially void-free semiconductor structure in the upper electrode region of the memory device within the memory region of a semiconductor chip. Furthermore, if small voids are formed in the gaps or recesses between vertical structures or MRAM pillars using the materials and processes of the present invention, these voids are formed in lower portions of the gap away from the upper electrodes or bit lines. Embodiments of the present invention include providing materials and deposition processes that can pinch off the gaps between MRAM pillars. In embodiments of the present invention, the pinched-off portion of the gap during deposition of the dielectric material occurs in the uppermost portion of the gap between adjacent MRAM pillars. In this way, even if small voids are formed in the semiconductor structure between MRAM pillars, these voids will not short-circuit the upper electrodes.

[0020] Embodiments of the present invention provide an embedded memory device in which the packing height of low-k dielectric material between MRAM pillars is reduced. By depositing an oxide material with better gap fill before depositing the low-k material, less low-k material is required to fill the gaps between MRAM pillars. The dielectric material fills most or all of the gaps between the vertical structures of the memory device, reducing the aspect ratio of the gap fill of the low-k dielectric material (for example, reducing the height of the gaps filled by the low-k dielectric). The aspect ratio of the gap fill of the low-k dielectric material is the packing height of the low-k dielectric material divided by the height of the MRAM pillar measured from the top surface of the dielectric material around the lower electrode to the bottom surface of the upper electrode.

[0021] Embodiments of the present invention provide a method for forming narrow-pitch advanced memory devices without creating voids in the upper electrode regions of adjacent advanced memory devices. While the method is described in relation to narrow-pitch MRAM devices, it may be applicable to other advanced memory devices such as RRAM devices and PCRAM devices. The method involves depositing a dielectric layer as a cap on the exposed portion of an ILD layer having an embedded portion of a lower metal layer within the ILD. The dielectric cap layer and the lower metal layer are located above a semiconductor substrate and may be above one or more semiconductor devices. The metal layer may be an M0 layer, an M1 layer, or a layer in the middle of the line (MOL) or back end of line (BEOL) of a semiconductor structure. In embodiments of the present invention, at least two adjacent narrow-pitch MRAM devices are formed by forming the lower electrodes of the MRAM devices. Forming the lower electrodes involves patterning the dielectric cap layer and etching the dielectric cap layer to expose a portion of the lower metal layer. The metal liner material may be deposited in the recesses of the dielectric cap layer and on the exposed metal layer. A layer of electrode material is deposited over the metal liner in the recess using a deposition process such as plasma vapor deposition or chemical vapor deposition. Chemical mechanical polishing removes excess electrode material from the top surface of the dielectric cap layer, forming two or more narrow-pitch lower electrodes on the lower metal layer (e.g., M1).

[0022] This method involves depositing a stack of material layers to form a magnetic tunnel junction (MTJ) for an MRAM device using a hard mask material layer. The stack of material layers for the MTJ is covered with a hard mask. The stack of material layers for the MTJ is deposited so as to cover a dielectric cap layer having a lower electrode.

[0023] Using a known MRAM pillar formation process, etching removes a portion of the material layer stack, hard mask, and uppermost dielectric cap layer for the MTJ. After etching, the MRAM pillar is formed on the lower electrode by the remaining vertical portions of the material layer stack and hard mask, for example, using photolithography and reactive ion etching. The uppermost portion of the metal liner surrounding the lower electrode is exposed, and the lower portion of the metal liner surrounding the lower electrode is surrounded by the remaining portion of the dielectric cap layer.

[0024] A layer of spacer material is deposited to cover the hard mask, the stack of material layers, the remaining exposed portion of the uppermost part of the metal liner around the lower electrode, and the uppermost surface of the dielectric cap layer, and after using a self-alignment process (e.g., reactive ion etching), spacers are formed around each of the MRAM pillars on the lower electrode. In embodiments of the present invention, the MRAM pillar is composed of a stack of material layers with a hard mask.

[0025] In some embodiments of the present invention, partial spacers are formed using a self-aligned spacer formation process. A partial spacer may be a spacer in which anisotropic etching, i.e., reactive ion etching, does not completely remove the spacer material from the horizontal surface of the semiconductor structure. In these embodiments, a thin portion of the spacer material remains on the exposed horizontal surface of the dielectric cap layer and hard mask material.

[0026] Embodiments of the present invention provide several methods for depositing a second dielectric material so as to cover a semiconductor structure. The second dielectric material may be silicon oxide, spin-on oxide, nitride, or another insulating material such as spin-on glass. This deposition may be carried out by plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition, a spin-on process, or by using a fluid oxide material, but is not limited to these. By using these deposition methods for dielectric materials, a void-free deposition, or possibly a nearly void-free deposition, of the second dielectric material can be given between MRAM pillars. If small voids are formed between adjacent narrow-pitch MRAM pillars in the second dielectric material using any of these deposition methods, these small voids occur at lower locations on the MRAM pillars or lower locations on the hard mask within the MRAM pillars. The method further includes removing portions of the second dielectric material covering the dielectric cap layer that are not between adjacent narrow-pitch MRAM pillars. Using a dielectric removal process tailored to the deposition process, the removal process, or etching process, removes the second dielectric material that is not present between adjacent MRAM pillars, while leaving most of the second dielectric material between MRAM pillars. For dielectric materials deposited by PECVD, PVD, CVD, atomic layer deposition (ALD), or spin-on processes, the second dielectric material can be removed using self-aligned processes such as reactive ion etching (RIE) as an anisotropic etching process (for example, the second dielectric material above the exposed horizontal surface of the dielectric cap layer can be removed). Only the uppermost portion of the dielectric material between narrow-pitch MRAM pillars is removed. Because there is little or no space between MRAM pillars, anisotropic etching removes very little dielectric material between MRAM pillars. After anisotropic etching, most of the second dielectric material remains between the MRAM pillars.The second dielectric material may remain between portions of the hard mask material in the MRAM pillar.

[0027] Embodiments of the present invention provide a method for depositing a low-k dielectric material so as to cover a semiconductor structure. Using a conventional electrode formation process, etching of the low-k dielectric material on the hard mask in the MRAM pillar and in a selected region of the logic area of ​​the semiconductor structure is performed. A metal liner is deposited so as to cover the exposed hard mask and inside the recesses formed by the etching of the low-k dielectric. Conductive metal layers are deposited in the recesses on the hard mask and in the recesses formed in the logic area to form one or more upper electrodes on the hard mask in the MRAM pillar and lines or contacts in the logic area, respectively.

[0028] Embodiments of this structure provide a low-k dielectric material that fills the region between the uppermost portions of adjacent narrow-pitch MRAM pillars and covers the logic region connections or devices. By using adjacent narrow-pitch MRAM pillars formed using one of the methods and materials described in embodiments of the present invention, void formation between upper electrodes or near the upper electrodes and bit lines of narrow-pitch advanced memory devices (e.g., MRAM, RRAM, or PCRAM devices) is prevented. By depositing dielectric materials such as oxide materials using improved conformal deposition methods, gap filling between vertical structures of narrow-pitch memory devices is improved.

[0029] The following description relating to the accompanying drawings is provided to assist in a comprehensive understanding of the exemplary embodiments of the invention as defined by the claims and their equivalents. While this description includes various specific details to aid in understanding the embodiments, these are merely illustrative. Therefore, those skilled in the art will recognize that various modifications and alterations of the embodiments described herein can be made without departing from the scope of the invention. Some of the process steps shown can be combined as integrated process steps. In addition, well-known features and configurations may be omitted for clarity and brevity.

[0030] The terms and words used in the following description and claims are not limited to their figurative meanings but are used solely to enable a clear and consistent understanding of the invention. Accordingly, it will be apparent to those skilled in the art that the following description relating to exemplary embodiments of the invention is provided for illustrative purposes only and is not intended to limit the invention as defined by the appended claims and their equivalents.

[0031] It should be understood that the singular forms "a," "an," and "the" refer to multiple objects unless the context requires otherwise. Therefore, for example, a reference to "a component surface" refers to one or more such surfaces unless the context indicates otherwise.

[0032] In the following description, terms such as “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives refer to the structures and methods disclosed, as oriented in the drawings. Terms such as “above,” “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, lies on a second element, such as a second structure, and that intervening elements, such as an interface structure, may exist between the first and second elements. The terms “direct contact” or “contact” mean that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without an intermediate conductive layer, insulating layer, or semiconductor layer.

[0033] To avoid obscuring the presentation of embodiments of the present invention, some processing steps or operations known in the art may be combined in the following detailed description for presentation and illustrative purposes, and in some cases may not be specifically described. In other examples, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the specific features or elements of various embodiments of the present invention.

[0034] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not constitute a complete process flow for manufacturing integrated circuits on semiconductor chips. These embodiments can be implemented together with integrated circuit manufacturing techniques for semiconductor chips and devices currently used in the art and include only those commonly practiced process steps necessary for understanding the embodiments described. Figures show cross-sectional portions of semiconductor chips or substrates, such as semiconductor wafers, during manufacturing and are shown to illustrate features of the embodiments described, not to exact proportions. Certain structural and functional details disclosed herein should not be construed as limiting, but merely as representative basic principles to teach those skilled in the art to employ the methods and structures of this disclosure in various ways. In this specification, well-known features and technical details may be omitted to avoid unnecessarily obscuring the embodiments presented.

[0035] References in this specification to “one embodiment,” “another embodiment,” “another embodiment,” or “one embodiment” indicate that the described embodiments may include certain features, structures, or characteristics, but not all embodiments necessarily include those specific features, structures, or characteristics. Furthermore, such expressions do not necessarily refer to the same embodiment. Moreover, if certain features, structures, or characteristics are described in relation to an embodiment, it is understood that any influence on such features, structures, or characteristics in relation to other embodiments, whether explicitly stated or not, is within the knowledge of those skilled in the art.

[0036] Embodiments of the present invention will now be described in detail, examples of which are shown in the accompanying drawings, and similar reference numerals refer to similar elements throughout.

[0037] Figure 1 shows a cross-sectional view of a semiconductor structure 100 having an Mx10 in an ILD8 according to an embodiment of the present invention. As shown, Figure 1 includes an Mx10 with a metal liner 9, an ILD8, a logic region A, and a memory region B. Logic region A is part of the semiconductor structure 100 and includes locations where one or more logic devices may be formed or exist. Memory region B includes a part of the semiconductor structure 100 that includes one or more memory devices, or where one or more memory devices may be formed.

[0038] Mx10 is part of a metal layer in a semiconductor structure 100. Mx10 may be part of a metal layer formed in a semiconductor manufacturing substrate process (FEOL: front-end of the line), intermediate process (MOL), or wiring process (BEOL). For example, Mx10 may be a lower metal layer of an M1 metal layer. In another example, Mx10 is located in an M0 metal layer. Figure 1 shows three parts of Mx10, but embodiments of the present invention are not limited to this number of Mx10s. Mx10 may be part of a semiconductor device (not shown) or above a semiconductor substrate (not shown). In some examples, one or more of the metals of Mx10 are connected to an underlying semiconductor device (not shown). The underlying semiconductor device may be, but is not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET) device, or a CMOS device based on various architectures such as a planar FET, FinFET, horizontal gate-all-around (h-GAA) FET, or vertical gate-all-around (v-GAA) FET. In some embodiments, Mx10 is used to form a lower electrode (e.g., a lower electrode 30 which may be partially surrounded by a dielectric layer 20). Mx10 may be, but is not limited to, a known metallic material used in the metal layer of the semiconductor chip, such as tungsten (W), copper (Cu), cobalt (Co), or ruthenium (Ru).

[0039] As shown in Figure 1, Mx10 is surrounded by a metal liner 9. The metal liner 9 may consist of a pure metal material, a metal nitride material, or a combination of one or more layers of these materials. For example, the metal liner 9 may consist of one or more metallic materials such as tantalum (Ta), titanium (Ti), W, Co, or Ru, or metal nitride materials such as titanium-nitrogen alloy, tantalum-nitrogen alloy, titanium-aluminum-nitrogen alloy, or tantalum-aluminum-nitrogen alloy. The metal liner 9 is not limited to these materials. In one embodiment, there is no metal liner 9.

[0040] ILD8 can be composed of dielectric materials known to be used as ILD materials in semiconductor chip manufacturing. For example, ILD8 is composed of SiO2. As shown, ILD8 surrounds and separates each of the Mx10 with a metal liner 9.

[0041] Figure 2 shows a cross-sectional view of a semiconductor structure 200 after deposition of a dielectric layer 20 according to an embodiment of the present invention. As shown, Figure 2 includes the ILD8, metal liner 9, Mx10, and dielectric layer 20. The dielectric layer 20 may be, but is not limited to, any insulating material such as silicon nitride (SiN), silicon carbide (SiC), or SiCN. Using known dielectric material deposition processes such as chemical vapor deposition (CVD) or plasma vapor deposition (PVD), the dielectric layer 20 may be deposited as a cap dielectric layer on the uppermost surfaces of the Mx10, metal liner 9, and ILD8. The thickness of the dielectric layer 20 may be in the range of 20 to 500 nm, but is not limited to these thicknesses. For example, a typical thickness of the dielectric layer 20 may be 55 nm.

[0042] Figure 3 shows a cross-sectional view of a semiconductor structure 300 after forming a lower electrode 30 with a metal liner 39 according to an embodiment of the present invention. As shown, Figure 3 includes the ILD8, metal liner 9, Mx10, dielectric layer 20, metal liner 39, and lower electrode 30. Figure 3 includes two adjacent lower electrodes 30, but in other embodiments, there may be two or more adjacent lower electrodes 30. For example, the lower electrodes 30 may be two adjacent lower electrodes 30 in a 4x4 matrix of lower electrodes. In some embodiments, one or both of the metal liners 9 and 39 are absent.

[0043] The lower electrode 30 can be formed using known semiconductor processes and materials for electrode formation in memory devices. For example, the uppermost surface of the dielectric layer 20 can be patterned using known photolithography processes, and the uppermost portion of Mx10 is exposed by etching of the dielectric layer 20 using, for example, a dry or wet etching process. For the metal liner 39, a metal liner material such as Ta, Ti, W, Ru, or a metal nitride alloy can be deposited on the exposed portions of Mx10 and the dielectric layer 20, but is not limited to these. Electrode material such as TaN, TiN, tungsten, or a combination of these materials can be deposited on the metal liner 39, but is not limited to these. Chemical mechanical polishing (CMP) can be performed using the dielectric layer 20 as a CMP stop to remove excess electrode material and metal liner material from the uppermost surface of the dielectric layer 20. The metal liner 39 and the lower electrode 30 remain in the recesses formed during etching of the dielectric layer 20. The electrode material of the lower electrode 30 includes, but is not limited to, copper (Cu), titanium nitride (TiN), Ti, tungsten (W), tungsten nitride (WN), tungsten carbide (WC), tantalum (Ta), TaN, silver (Ag), gold (Au), and aluminum (Al). After the formation of the lower electrode 30, the typical spacing between two adjacent lower electrodes 30 with metal liners 39 may be 7-800 nm, but is not limited to these spacings.

[0044] Figure 4 shows a cross-sectional view of a semiconductor structure 400 after depositing a stack of material layers 41, a hard mask (HM) 42, and a sacrificial material 43 according to an embodiment of the present invention. The stack of material layers 41 can be used to form a magnetic tunnel junction (MTJ) of an MRAM device. While Figure 4 illustrates the stack of material layers 41 forming an MTJ in an MRAM pillar, in other embodiments, the stack of material layers 41 is a stack of material layers 41 for RRAM, PCRAM, DRAM, or other types of memory devices. For example, the stack of material layers 41 for RRAM is an HfO2 layer with a Ti buffer layer, or TaO x It may include layered Ta2O5 layers, where x is an integer. In another example, the stack of material layers 41 for PCRAM may include multiple layers of one or more phase-change materials, heater element materials such as TiN, or electrode materials, or combinations thereof.

[0045] If the stack of material layers 41 is above the dielectric layer 20, the lower electrode 30, and the exposed portion of the metal liner 39, the material for subsequent MRAM pillar formation is provided by depositing sacrificial material 43 on HM 42 on the stack of material layers 41. For example, as is known to those skilled in the art, typical examples of materials in the stack of material for the MRAM pillar (e.g., for the stack of material layers 41) include multiple multilayer ferromagnetic films separated by thin spacers (e.g., tantalum, aluminum oxide, etc.). As shown in Figure 6, the stack of material layers 41 and HM 42 can form an MRAM pillar using a process described later with reference to Figures 5 and 6. In one embodiment, a pedestal (not shown in Figure 4) is deposited on top of the dielectric layer 20 and below the stack of material layers 41. For example, the pedestal may be a layer of metal, metal nitride (e.g., TaN), or a combination of these materials (e.g., a combination of W, Ta, Ti, N, etc.).

[0046] HM42 can be any hard mask material used in semiconductor devices. For example, HM42 can be a metal (e.g., Al, W, Ta, Ti), a metal nitride (e.g., WN, TaN, TiN), or a combination of these materials. In various embodiments, a sacrificial material 43 is deposited on a stack 41 of material layers. For example, the sacrificial material 43 can be silicon dioxide or amorphous carbon. In one embodiment, the sacrificial material 43 is absent.

[0047] Figure 5 shows a cross-sectional view of a semiconductor structure 500 according to an embodiment of the present invention, after deposition of an OPL 52 covered with an AR coating 53 and a patterned resist 54. As shown, Figure 5 includes an ILD 8, a metal liner 9, an Mx 10, a dielectric layer 20, a lower electrode 30, a metal liner 39, a stack of material layers 41, an HM 42, a sacrificial material 43, an OPL 52, an AR coating 53, and a patterned resist 54 (for example, after patterning the resist 54 using photolithography). Two portions of the resist 54 are located on the AR coating 53 above the lower electrode 30.

[0048] OPL52 can use any of the following: spin-on carbon or commercially available OPL material. OPL52 may be applied using a known spin-on process to the top surface of the sacrificial material 43 (if present) or to HM42 (if the sacrificial material 43 is not present).

[0049] In various embodiments, the AR coating 53 is located on the OPL 52. The AR coating 53 may consist of one or more layers of materials commonly used in semiconductor manufacturing to reduce image distortion associated with reflections from the substrate or the surface of the OPL 52 during photolithography. For example, the AR coating 53 may be, but is not limited to, a spin-on oxide material or deposition method.

[0050] The resist 54 is shown after personalization or patterning. Two portions of the resist 54 are present on the AR coating 53 above each of the two lower electrodes 30. These two portions of the resist 54 can be used for patterning memory pillars, i.e., MRAM pillar patterning. For example, these two portions of the resist 54 determine the portion of the stack 41 of material layers remaining in Figure 6 after the etching process has formed two MRAM pillars.

[0051] Figure 6 shows a cross-sectional view of a semiconductor structure 600 after etching of the material layer stack 41 and HM42 according to an embodiment of the present invention. Two MRAM pillars are formed on the lower electrode 30 by etching of the material layer stack 41 and HM42 using a known MRAM pillar formation process. As shown, Figure 6 includes the ILD8, metal liner 9, Mx10, lower portion of the dielectric layer 20, lower electrode 30, metal liner 39, material layer stack 41, and HM42. The exposed portions of the AR coating 53, OPL 52, sacrificial material 43, HM42, upper portion of the dielectric layer 20, and material layer stack 41 can be removed using a patterned resist 54 and an etching process, such as reactive ion etching (RIE), ion beam etching (IBE), or a combination of these processes. After etching, the remaining two portions of the stack 41 of the material layer with HM42 remain above each of the lower electrodes 30, along with the remaining portions of the sacrificial material 43, OPL 52, AR coating 53, and resist 54. The typical spacing between the remaining two portions of the stack 41 of the material layer after RIE may be in the range of 7-800 nm, but is not limited to these spacings.

[0052] One or more additional etching processes may be used to remove the remaining portions of the sacrificial material 43, OPL 52, AR coating 53, and resist 54. For example, a wet etching process with appropriate chemicals can be used to remove the remaining portions of the sacrificial material 43, OPL 52, AR coating 53, and resist 54. In some cases, the resist 54 is removed by wet etching, and the remaining portions of the AR coating 53, OPL 52, and sacrificial material 43 are removed by a second anisotropic etching (e.g., RIE) using the top surface of HM42 as an etch stop. In various embodiments, the top portion of the dielectric layer 20 is removed during etching. The thickness of the remaining lower portion of the dielectric layer 20 may be in the range of 5 to 200 nm, but is not limited to these thicknesses. For example, the remaining lower portion of the dielectric layer 20 may be between 20 nm and 50 nm. The stack of material layers 41 and the remaining portions of HM42 on the lower electrode 30 form two pillars, such as two MRAM pillars.

[0053] Figure 7 shows a cross-sectional view of a semiconductor structure 700 after spacer material 77 has been deposited according to an embodiment of the present invention. As shown, Figure 7 includes the elements of Figure 6 and the spacer material 77. A thin layer of spacer material 77 can be deposited over the semiconductor structure 700 using a spacer material deposition process such as CVD, PVD, electron beam PVD, plasma-enhanced CVD (PECVD), or ALD. The spacer material 77 may include, but is not limited to, SiN, SiC, and SiC(H). The spacer material 77 can be deposited over the semiconductor structure 700 on the exposed surface of the dielectric layer 20, around the exposed surface of the metal liner 39, on the sides of the material layer stack 41, and on the sides and top surface of the HM 42.

[0054] Figure 8 shows a cross-sectional view of the semiconductor structure 800 after spacers have been formed from the spacer material 77 according to an embodiment. Spacers can be formed by etching the spacer material 77 using a self-aligned spacer formation process. In various embodiments, for example, anisotropic etching using RIE removes the spacer material 77 from the horizontal planes of the dielectric layer 20 and HM42, forming spacers around the uppermost part of the metal liner 39, around the sides of the material layer stack 41, and around the sides of the HM42. Hereinafter, in Figures 9 to 12, the spacer material 77 will be referred to as spacer 77. The spacer 77 covers two MRAM pillars.

[0055] In another embodiment (not shown in Figure 8), the uppermost portion of the spacer is partially removed from the horizontal plane above the dielectric layer 20 and HM42. This alternative embodiment will be described in detail later with respect to Figures 14-19.

[0056] Figure 9 shows a cross-sectional view of a semiconductor structure 900 after a layer of oxide 90 has been deposited according to an embodiment of the present invention. As shown, Figure 9 includes the elements of Figure 8 and the oxide 90. The oxide 90 can be deposited to cover the dielectric layer 20, the spacer 77, and the exposed surface of HM42. The oxide 90 is made from silicon oxide (e.g., SiO2 or SiO2) produced from tetraethyl orthosilicate, also known as silane (SiH4) or tetraethoxysilane (TEOS), as a precursor for forming the oxide. xThe oxide 90 may consist of, but is not limited to, these dielectric materials, PECVD "fluid" oxide-like materials such as TEOS, fluid SiCOH, SOD (spin-on dielectric), oxynitride (SiON), or nitride (SiN), or oxide materials such as spin-on glass for oxide 90. Oxide 90 provides good gap fill between the uppermost portion of the lower electrode 30, the spacer 77, and the two pillars formed from HM42. As is well known to those skilled in the art, the above materials such as TEOS, fluid SiCOH, and SOD provide better conformability or gap fill than low-k dielectric materials typically used in the manufacture of MRAM devices.

[0057] In various embodiments, the oxide 90 is deposited by one of the following methods: PECVD, PVD, CVD, or spin-on. The deposition of oxide 90 using one of the following methods covers the dielectric layer 20, the spacer 77, and the HM42. As shown, the layer of oxide 90 extends above the top surface of the HM42.

[0058] In some embodiments, when oxide 90 is deposited to cover the semiconductor structure 900, the region between the two MRAM pillars covered by the spacer 77 is pinched off. When the uppermost part of the gap between the MRAM pillars is pinched off by this deposition process, voids cannot be formed in the region adjacent to HM42, particularly the region adjacent to the uppermost part of HM42. In some cases, when describing the gap fill and H1 between the two MRAM pillars with respect to Figures 10 and 12 later, the two MRAM pillars may be considered to include the uppermost part of the lower electrode 30 above the dielectric layer 20.

[0059] When forming narrow-pitch MRAM devices, particularly narrow-pitch memory arrays, the small space or recess between two MRAM pillars can be filled with oxide 90, which has superior gap-filling capabilities than the low-k dielectrics typically used for gap-filling between adjacent MRAM pillars in MRAM manufacturing. As shown, oxide 90, with improved conformability compared to current low-k dielectric materials, provides void-free filling of the gap between two MRAM pillars (for example, oxide 90 fills the gap or region between spacers 77 in contact with two MRAM pillars).

[0060] In some embodiments, the oxide 90 is deposited as a flowable dielectric material. Using flowable CVD (FCVD) deposition or SOD, the oxide 90 can be deposited to cover the dielectric layer 20, the spacer 77, and the HM42. For example, when silicon dioxide is used as the flowable dielectric material, the oxide 90 covers the uppermost surface of the semiconductor structure 900. In various embodiments, after deposition using a flowable process, the uppermost surface of the oxide 90 is above the uppermost surface of the HM42 and completely fills the recess between the two MRAM pillars. After deposition, this flowable oxide material can be cured or annealed using known processes such as ultraviolet (UV) curing at high temperatures. In one embodiment, depositing the oxide 90 as a flowable dielectric material yields a layer of oxide 90 that covers the sides of the material layer stack 41 and a portion of the sides of the HM42. For example, the flowable oxide 90 may extend to 75-95% of the vertical side of the HM42.

[0061] In one embodiment, small voids are present in the oxide 90 (shown in Figure 13). Voids in the oxide 90 can occur when a deposition process, such as PECVD, pinches off the gaps between MRAM pillars in the uppermost portion of the oxide 90 between the HM42 or the upper portion of the stack 41 of the material layers during the deposition of the oxide 90. Voids can occur below the pinched-off portion of the gap between the MRAM pillars, where the oxide 90 pinches off, or closes, the gap before completely filling the area below the gap being closed. For example, portions of the gap adjacent to and below the HM42, or below the uppermost portion of the stack 41 of the material layers, may not be completely filled, resulting in the formation of small voids in the oxide 90. Similarly, when a fluid dielectric process is used to deposit the oxide 90, the uppermost portion of the oxide 90 between the HM42 or the stack 41 of the material layers is completely filled, i.e., blocked, and the small voids will be located below the hard mask 42 or the uppermost portion of the stack 41 of the material layers.

[0062] Figure 10 shows a cross-sectional view of the semiconductor structure 1000 after etching the oxide 90 according to an embodiment of the present invention. As shown, Figure 10 includes the ILD8, metal liner 9, Mx10, dielectric layer 20, metal liner 39, lower electrode 30, material layer stack 41, HM42, spacer 77, and the remaining portion of oxide 90 surrounding the spacer 77. Figure 10 also shows H1 and H2, which are described later. In some embodiments, the oxide 90 covers each spacer 77 and fills almost all of the gaps between the uppermost portions of the metal liner 39 around the uppermost portion of the lower electrode 30, and the gaps between the spacer 77 around the HM42. In these embodiments, the oxide 90 fills the gap between the two MRAM pillars formed on the lower electrode 30. When the oxide 90 fills the gap between the two MRAM pillars, after the etching process, the uppermost surface of the oxide 90 is at the same height as the uppermost surface of the HM42. In various embodiments, small indentations or recesses occur on the uppermost surface of the oxide 90 between the spacers 77 (for example, recesses shown between spacers 77 adjacent to the uppermost portion of HM42 on the MRAM pillar). In one embodiment, the recesses in the oxide 90 extend to the uppermost portion of the stack 41 of the material layers.

[0063] As shown, H1 is the distance between the top of the dielectric layer 20 and the top of the HM42, and H2 is the distance between the bottom of the surface of the oxide 90 between the HM42 in the MRAM pillars and the top of the HM42. H1 represents the distance or height of the gap to be filled between the MRAM pillars. H2 represents the portion of the distance or height of the gap between the MRAM pillars that is not completely filled by the oxide 90. H2 represents the depth of the gap that needs to be filled by the low-k dielectric in a later process step described with respect to Figure 11. Low-k dielectric materials for MRAM devices have poor conformability and poor gap-filling properties, so it is desirable to make H2 small.

[0064] When oxide 90 is deposited by PECVD, PVD, or CVD, the oxide 90 is removed from the exposed horizontal planes of the dielectric layer 20 and HM42 by etching or directional etching such as RIE. In this case, the dielectric layer 20 and HM42 may be etch stops or endpoints in the RIE process, and small depressions may form on the surface of the oxide 90 between the spacers 77. Because the spacers 77 in contact with the HM42 above the lower electrode 30 and the material layer stack 41 have a narrow pitch (e.g., a narrow pitch between MRAM pillars), the portion of oxide 90 above the dielectric layer 20 between the uppermost portion of the lower electrode 30 above the dielectric layer 20 (e.g., the portion of oxide 90 between the MRAM pillars formed by the material layer stack 41 and HM42) is not removed by etching (e.g., RIE). In some cases, as shown in Figure 10, a small upper portion of oxide 90 between the spacers 77 in contact with the uppermost portion of HM42 may be removed. As shown, slight depressions may occur on the surface of the oxide 90 between the spacers 77 in contact with the HM42 in the MRAM pillar. If these depressions are slight, the H2 value, i.e., the distance, becomes small. As shown in Figure 10, the oxide 90 covers the spacers 77, and after RIE etching, the portion of the oxide 90 remaining in contact with the spacers 77 is adjacent to at least the lower portion or lower half of the HM42.

[0065] In one embodiment, prior to anisotropic etching, CMP and patterning are performed on the uppermost surface of the oxide 90 using HM42 as a CMP stop. For example, after CMP, the uppermost surface of the oxide 90 may be patterned using photolithography (e.g., the oxide 90 between two MRAM pillars is protected with resist), and RIE may remove the oxide 90 from the exposed horizontal planes of the dielectric layer 20 and HM42. In this case, the dielectric layer 20 and HM42 may be etch stops or endpoints of the RIE process, and the patterned resist protects the oxide 90 between the spacers 77 in contact with each of the HM42. In this example, after patterning, etching, and removal of residual resist, the surface of the oxide 90 is essentially flat (e.g., there are no depressions between the MRAM pillars).

[0066] In other embodiments, when the oxide 90 is deposited as a fluid dielectric material (e.g., by SOD), CMP is performed, followed by patterning and etching processes of the oxide 90. In this example, HM42 acts as a CMP stop. After the top surface of the oxide 90 is planarized by CMP, in these embodiments, a resist may be deposited for a photolithography patterning process. The photolithography patterning process exposes portions of the oxide 90 that are not between the MRAM pillars or that are not directly adjacent to the spacers 77 that are in contact with the MRAM pillars. After photolithography patterning, a wet or dry etching process may be performed to remove the exposed portions of the oxide 90. After the patterning and etching processes, the oxide 90 remains above the dielectric layer 20 between the metal liners 39 that are in contact with the sides of the spacers 77 and the lower electrodes 30, on the sides of the material layer stack 41, and on the sides of the HM42 (e.g., on portions of the dielectric layer 20 between the MRAM pillars and adjacent to the spacers 77). In this way, when the oxide 90 is deposited as a fluid oxide material (e.g., using SOD or FCVD), using photolithography patterning and etching of the oxide 90 leaves flat or relatively flat surfaces on the oxide 90 between the HM42 in the MRAM pillars and between the spacers 77. The oxide 90 deposited using SOD or FCVD has good conformability and fills the gaps between narrow-pitch MRAM pillars without forming voids, so little or no other gap fill is needed to fill the gaps between the MRAM pillars. In this example, H2 is small. For example, H2 is in the range of a few nanometers to 15 nm.

[0067] Figure 11 shows a cross-sectional view of a semiconductor structure 1100 after deposition of a low-k dielectric material 111 according to an embodiment of the present invention. As shown, Figure 11 includes the elements of Figure 10, as well as the low-k dielectric material 111 deposited to cover the dielectric layer 20, the oxide 90, and the exposed surface of the hard mask 42. The layer of low-k dielectric material 111 extends above the top surface of the hard mask 42. As shown, the low-k dielectric material 111 is void-free. In various embodiments, the low-k dielectric material 111 fills small recesses or depressions in the oxide 90 between MRAM pillars. These small depressions in the oxide 90 may be adjacent to the top portion of the MRAM pillars (e.g., adjacent to the HM42). After deposition of the low-k dielectric material 111 using a known deposition process such as CVD or PVD, the top surface of the low-k dielectric material 111 can be planarized by CMP without exposing the hard mask 42.

[0068] Figure 12 shows a cross-sectional view of the semiconductor structure 1200 after the upper electrode 120 has been formed according to an embodiment of the present invention. As shown, Figure 12 includes the ILD8, metal liner 9, Mx10, dielectric layer 20, metal liner 39, lower electrode 30, material layer stack 41, HM42, spacer 77, oxide 90, low-k dielectric material 111, upper electrode 120, logic region A, memory region B, H1 indicating the distance from the top of the dielectric layer 20 to the top of the HM42, and H2 indicating the distance from the top surface of the lowest point of the oxide 90 surface between HM42 to the top of the HM42. As previously mentioned, reducing H2 improves the gap-fill of the low-k dielectric material 111 by reducing the portion of the gap between the MRAM pillars that is filled by the low-k dielectric material 111. In this way, the low-k dielectric material 111, which has lower conformability and gap-filling ability than the oxide 90, does not create voids or seams between or near the upper electrodes 120 during the formation of a narrow-pitch MRAM device.

[0069] In conventional MRAM device formation processes that do not use oxide 90, the aspect ratio of H1 to H2 is approximately 1. In narrow-pitch MRAM devices formed without oxide 90, the gap, or distance H2, that the low-k dielectric material 111 must fill is typically from the top of the dielectric material, such as the dielectric layer 20, to the top of HM42 below the upper electrode 120. In this case, H2 is approximately the same as H1. In embodiments of the present invention, the deposition and patterning of oxide 90 gives the semiconductor structure 1200 an H2 that is significantly smaller than that of MRAM devices formed in the conventional way.

[0070] As shown in Figure 12, the region or portion of the gap filled by the low-k dielectric material 111 is smaller than the region or portion of the gap filled by the oxide 90. Using the process described with respect to Figures 1 to 12, the aspect ratio of H1 to H2 is reduced, and the depth of the gap or recess filled by the low-k dielectric material 111 is reduced. Using oxide 90, which has excellent conformality and gap-filling properties, H2 is reduced because the oxide 90 fills most, if not all, of the gap between the MRAM pillars formed on the lower electrode 30.

[0071] In various embodiments, the upper electrode 120 is formed on HM42. Using known electrode formation processes, a portion of the HM42 on each MRAM pillar is exposed by etching the low-k dielectric material 111. Using previously described processes and metal liner materials, a metal liner 129 can be deposited on the exposed surface of the low-k dielectric material 111, HM42, and a small portion of the oxide 90 that were exposed after the etching process. Layers of electrode metals such as Cu, TiN, and W can be deposited on the metal liner 129, but are not limited to these. CMP may be performed to remove the top portion of the metal liner 129 and the top portion of the electrode material layer on the low-k dielectric material 111, thereby forming the upper electrode 120. In some embodiments, the upper electrode 120 is a bit line.

[0072] As shown, each of the two MRAM devices shown in Figure 12 includes an MRAM pillar consisting of a stack 41 of material layers covered by HM 42, on the lower electrode 30. Each MRAM pillar has vertical sides covered by spacers 77, and one of the upper electrodes 120 resides on the MRAM pillar. The two MRAM devices shown in Figure 12 each include an MRAM pillar, a lower electrode 30, and an upper electrode 120.

[0073] Figure 12 shows two MRAM devices, but any number of MRAM devices may be present in memory region B. Figure 12 also includes Mx10 in logic region A. In some examples (not shown), metal lines, contacts, vias, or other semiconductor devices may be formed above Mx10 in logic region A. The process for forming the semiconductor structure 1100 described with respect to Figures 9 to 11 can prevent the formation of voids or seams in either the oxide 90 or the low-k material in the region of the semiconductor structure 1100 adjacent to the upper electrode 120. In one embodiment, voids in the oxide 90 may occur below the region adjacent to the upper electrode 120.

[0074] Figure 13 shows a cross-sectional view of a semiconductor structure 1300 according to an embodiment of the present invention, in which a void 90V is formed during the deposition of oxide 90. Figure 13 is essentially the same as Figure 12, except that a void 90V exists between adjacent narrow-pitch MRAM pillars, between the uppermost portion of the lower electrode 30 and the lower portion of the material layer stack 41. The void 90V may form in the lower portion of the gap between two MRAM pillars. As shown in Figure 13, the void 90V is formed in the oxide 90 adjacent to the spacer 77 and below the HM 42. For example, the void 90V occurs adjacent to or below the lower portion or lower half of the material layer stack 41.

[0075] Voids 90V initially occur during the oxide deposition process described with respect to Figure 9. As shown, voids 90V do not occur near the upper electrode 120 (e.g., voids 90V are below the bottom surface of the upper electrode 120). In this way, voids 90V do not affect the functionality of the MRAM device or the reliability of the finished semiconductor device (e.g., voids 90V do not cause short circuits, either initially or over time, due to metallic contact or trapped fluid between the upper electrodes 120 or between bit lines). In Figure 13, voids 90V occur in the oxide 90 adjacent to the lower electrode 30 and the lower half or lower portion of the material layer stack 41, but in other examples, voids 90V may be smaller and located in different positions below the top portion of the material layer stack 41 (e.g., not near the upper electrode 120). In one embodiment, voids 90V are located below the bottom surface of HM42.

[0076] Figure 14 shows a cross-sectional view of a semiconductor structure 1400 after partial spacer etching according to another embodiment of the present invention. As shown, Figure 14 includes ILD8, Mx10, metal liner 9, dielectric layer 20, metal liner 39, lower electrode 30, material layer stack 41, HM42, and spacer material 85. In some embodiments, partial etching of the spacer material 85 is performed as shown in Figure 14. In Figure 14, the semiconductor structure 700 of Figure 7 is used, with spacer material 85 instead of spacer material 77, to perform partial spacer etching of the spacer material 85. Spacer material 85 may be the same material as spacer material 77 in Figure 7, but spacer material 85 is not limited to spacer material 77 and may be any dielectric material used for spacer formation in semiconductor devices.

[0077] As shown in Figure 14, partial spacer etching of the spacer material 85 can be performed. For example, directional etching, i.e., RIE, can remove the uppermost portion of the spacer material 85 that forms a spacer around the MRAM pillar, leaving a thin layer of spacer material 85 covering the dielectric layer 20 and HM42. After partial spacer etching, the spacer material 85 remains in contact with the upper portion of the metal liner 39 and the stack of material layers 41 to form a spacer, and also remains as a thin layer of spacer material 85 above the exposed surfaces of HM42 and dielectric layer 20. As shown, the spacer material 85 in contact with HM42 is thinned near the top surface of HM42 like a typical spacer, but is also followed by a thin layer covering the top surface of HM42. After partial spacer etching, the spacer material 85 remains in contact with the metal liner 39, the stack of material layers 41, and the vertical surfaces i.e., sides of HM42 to form a conventional spacer. A thin layer of spacer material 85 also remains on the horizontal surface of the semiconductor structure 1400. RIE etching is controlled by processing time, intentionally leaving a portion of the spacer material 85 (e.g., SiN) intact. The intention here is to ensure that the metal 10 is never exposed and diffused during or after the RIE process.

[0078] Figure 15 shows a cross-sectional view of a semiconductor structure 1500 after deposition of oxide 95 according to an embodiment of the present invention. As shown, Figure 15 includes the elements of Figure 14 and a layer of oxide 95. Oxide 95 is essentially the same as oxide 90, except that oxide 95 covers the spacer material 85. As previously mentioned, oxide 95 can be an oxide material such as SiO2 or SOD, or an insulating material such as spin-on-glass or TEOS. Oxide 95 can be deposited using processes and materials previously described in detail with respect to Figure 10. For example, oxide 95 can be deposited using PECVD, PVD, CVD, SOD, ALD, or FCVD. As shown, oxide 95 covers the spacer material 85. Oxide 95 fills the gaps between MRAM pillars and extends upward a certain distance from the uppermost surface of oxide 95 on the MRAM pillars.

[0079] Figure 16 shows a cross-sectional view of the semiconductor structure 1600 after etching a portion of the oxide 95 according to an embodiment of the present invention. In various embodiments, the directional self-alignment process etches portions of the oxide 95 that are present on the horizontal plane of the spacer material 85 and not between the MRAM pillars. As previously described in detail with respect to Figure 10, directional etching, or RIE, leaves most of the oxide 95 behind between the narrow-pitch MRAM pillars (i.e., above the spacer material 85) and on the vertical surfaces of the MRAM pillars covered by the spacer material 85. More specifically, as shown in Figure 16, the oxide 95 remains above the spacer material 85 between the lower electrodes 30, and in contact with the vertical portions of the spacer material 85 that are in contact with the vertical surfaces of the HM 42, the stack of material layers 41, and the uppermost portion of the metal liner 39. The height to which the oxide 95 extends above the spacer material 85 between the MRAM pillars can vary. For example, the height of the oxide 95 above the spacer material 85 between MRAM pillars can range from approximately the same level as the top surface of the spacer material 85 on the HM42 (e.g., slightly below the top surface of the HM42) to the same level as the top portion of the material layer stack 41. After directional etching (e.g., RIE), the top surface of the oxide 95 between the two MRAM pillars is continuous, and in some cases may have slight recesses. There are no voids, cracks, or seams extending from the top surface of the oxide 95 into the top portion of the oxide 95.

[0080] Figure 17 shows a cross-sectional view of a semiconductor structure 1700 after deposition of low-k dielectric material 115 according to an embodiment of the present invention. As shown, Figure 17 includes the elements of Figure 16 and the low-k dielectric material 115. The low-k dielectric material 115 is essentially the same as the low-k dielectric material 111. The layer of low-k dielectric material 115 is deposited above the spacer material 85 and covering the periphery and top of the oxide 95. As shown, no voids are present in the low-k dielectric material 115 in Figure 17.

[0081] Figure 18 shows a cross-sectional view of the semiconductor structure 1800 after the formation of the upper electrode 181 according to an embodiment of the present invention. For example, the upper electrode 181 with a metal liner 189 can be formed using known electrode formation processes and metal etching processes, as previously described in detail with respect to Figure 12. As shown, Figure 18 includes ILD8, Mx10, dielectric layer 20, metal liner 39, lower electrode 30, material layer stack 41, HM42, spacer material 85, oxide 95, low-k dielectric material 115, metal liner 189, and upper electrode 181. The upper electrode 181 with the metal liner 189 is formed in the low-k dielectric material 115 on the HM42. In some examples, the upper electrode 181 may cover a small portion of oxide 95 near the top of the HM42. As previously described with respect to Figure 12, in other examples, lines, contacts, vias, and other semiconductor devices may be formed in the logic region (not shown). As shown, there are no voids near the upper electrode 181 or the metal liner 189.

[0082] Figure 19 shows a cross-sectional view of a semiconductor structure 1900 having a void 90V in the oxide 95 according to an embodiment of the present invention. As shown, Figure 19 includes the elements and void 90V of Figure 18. The void 90V in Figure 19 is essentially the same as the void 90V in Figure 13. As shown, Figure 19 is formed with the materials and processes described in Figures 14-18, except for 90V, which is a small void that occurred during oxide 95 deposition in Figure 15. As detailed with respect to Figures 9 and 13, the void 90V is formed below the upper electrode 181. When the void 90V occurs during oxide 95 deposition, the uppermost surface of the oxide 95 between the HM42 and the uppermost parts of the material layer stack 41 remains continuous (for example, the void 90V does not extend to the uppermost surface of the oxide 95 and is not in the vicinity of the upper electrode 181). As shown, 90V is formed in the portion of oxide 95 below HM42, adjacent to the lower half of the metal liner 39 and the stack 41 of the material layers. In other examples, the void 90V may be smaller, or located at a different position below HM42, or both.

[0083] While the present invention has been shown and described with reference to certain exemplary embodiments, it will be understood by those skilled in the art that various modifications in form and detail can be made without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

[0084] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from their scope and the embodiments described. The terms used herein have been selected to best describe the principles of one or more embodiments, practical applications or technical improvements to technologies available on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, Located within the first dielectric material layer, with two adjacent lower electrodes above the metal layer, Two adjacent pillars, each located on one of the two adjacent lower electrodes, wherein each of the two adjacent pillars comprises a stack of memory device material, Spacers around the vertical sides of each of the two adjacent pillars and each of the two adjacent lower electrodes or the portion of the metal liner surrounding each lower electrode that is exposed on the layer of the first dielectric material, A second dielectric material is in contact with the spacers around the vertical sides of each of the two adjacent pillars and around the exposed portion of each of the two adjacent lower electrodes or the metal liner surrounding each of the lower electrodes, and is located on the layer of the first dielectric material between the two adjacent lower electrodes, filling a first portion of the gap between the two adjacent pillars and between the two adjacent lower electrodes from the top of the layer of the first dielectric material to at least the top level of the stack, between the two adjacent pillars, A low-k dielectric material formed on the layers of the second dielectric material and the first dielectric material. A semiconductor structure comprising the following features.

2. The semiconductor structure according to claim 1, further comprising an upper electrode on the uppermost part of each of the two adjacent pillars in the low-k dielectric material.

3. The semiconductor structure according to claim 1, wherein each of the two adjacent pillars is composed of a stack of magnetoresistive random-access memory device material.

4. The semiconductor structure according to claim 1, wherein the low-k dielectric material covering the second dielectric material fills the second portion of the gap between the two adjacent pillars.

5. The semiconductor structure according to claim 2, wherein the low-k dielectric material covering the second dielectric material is void-free between the upper electrodes on the uppermost parts of each of the two adjacent pillars.

6. The semiconductor structure according to claim 1, wherein the second dielectric material is void-free.

7. The semiconductor structure according to claim 4, wherein the second portion of the gap between the two adjacent pillars is smaller than at least the first portion of the gap between the two adjacent pillars.

8. The semiconductor structure according to claim 1, wherein at least the first portion of the gap between the two adjacent pillars extends from the top of the layer of the first dielectric material to a portion of the hard mask on the stack in the two adjacent pillars.

9. The semiconductor structure according to claim 4, wherein the second portion of the gap between the two adjacent pillars extends from the lowest point of the uppermost surface of the second dielectric material between the two adjacent pillars to the uppermost part of the hard mask on the stack in the two adjacent pillars.

10. The semiconductor structure according to claim 1, wherein the two adjacent pillars comprising the stack of the memory device material are two vertical structures for forming a resistive random-access memory device.

11. The semiconductor structure according to claim 1, wherein the second dielectric material provides improved gap-fill capability compared to that of the low-k dielectric material.

12. The semiconductor structure according to claim 1, wherein the second dielectric material filling at least the first portion of the gap between the two adjacent pillars further comprises the second dielectric material filling the gap between each spacer of the spacers around the vertical side surface of each of the two adjacent pillars.

13. The semiconductor structure according to claim 1, wherein the two adjacent lower electrodes located within the layer of the first dielectric material and above the metal layer are in a matrix of a plurality of lower electrodes.

14. The semiconductor structure according to claim 1, wherein the second dielectric material is one of an oxide material, a nitride material, or spin-on glass.

15. A void in the lower half of the stack of the second dielectric material or in the portion of the second dielectric material adjacent to one or more of the two adjacent lower electrodes, The two upper electrodes on the two adjacent pillars and The semiconductor structure according to claim 1, further comprising the low-k dielectric material surrounding the two upper electrodes.

16. The semiconductor structure according to claim 15, wherein the low-k dielectric material is void-free.

17. The semiconductor structure according to claim 15, wherein the void in the second dielectric material is not adjacent to the two upper electrodes.

18. A method for forming at least two adjacent memory devices with a narrow pitch, wherein the method is To form at least two adjacent pillars on at least two adjacent lower electrodes of the first dielectric layer, each comprising a stack of memory device material, To form a spacer in contact with each of the two adjacent pillars and each of the two adjacent lower electrodes, or the portion of the metal liner surrounding each lower electrode that is exposed on the first dielectric layer, The second dielectric material is deposited on the first dielectric layer so as to cover the exposed portion of each of the at least two adjacent pillars and the two adjacent lower electrodes or the metal liner surrounding each lower electrode, The etching of the second dielectric material is performed such that the etching leaves the second dielectric material on the vertical surface of the spacer in contact with each of the at least two adjacent pillars and each of the two adjacent lower electrodes or the exposed portion of the metal liner surrounding each of the lower electrodes, and on the first dielectric layer between the at least two adjacent lower electrodes, with the first portion of the gap between the two adjacent pillars and between the two adjacent lower electrodes filling the gap between the at least two adjacent pillars from the top of the first dielectric layer to at least the top of the stack, Depositing a low-k dielectric material so as to cover the second dielectric material and on the first dielectric layer, After depositing the low-k dielectric material, upper electrodes are formed on each of the at least two adjacent pillars. A method that includes this.

19. The method according to claim 18, wherein the deposition of the second dielectric material includes using one of plasma-enhanced chemical vapor deposition, physical vapor deposition, chemical vapor deposition, spin-on oxide, or spin-on glass deposition, and the second dielectric material is one of oxide material, spin-on glass material, silane material, or tetraethoxysilane material.

20. The method according to claim 19, wherein the etching of the second dielectric material is performed by using photolithography and reactive ion etching.

21. The method according to claim 18, wherein a void-free gap fill is provided between each upper electrode by depositing the low-k dielectric material.

22. The method according to claim 18, wherein the pillar is a pillar for a magnetoresistive random-access memory device.

23. Depositing the aforementioned second dielectric material is A fluid dielectric material is deposited on the first dielectric layer so as to cover the at least two adjacent pillars on the at least two adjacent lower electrodes, The process of curing the aforementioned fluid dielectric material, Performing chemical mechanical polishing on the aforementioned fluid dielectric material Including the above etching, Patterning the aforementioned fluid dielectric material, Etching the fluid dielectric material such that a portion of the fluid dielectric material between the spacers covering each of the at least two adjacent pillars and a small portion of the fluid dielectric material adjacent to the spacers remain. The method according to claim 18, including the method described in claim 18.

24. The method according to claim 23, wherein the deposition of the fluid dielectric material is performed using either a spin-on process or fluid chemical vapor deposition.

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