Phase change memory gap

Abstract

The PCM cell includes a first electrode, a heater / PCM portion electrically connected to the first electrode, the heater / PCM portion including a PCM material, a second electrode electrically connected to the PCM material, and an electrical insulator stack surrounding the protruding liner, the stack including a plurality of first layers having a plurality of first inner surfaces facing the protruding liner, the plurality of first layers being composed of a first material, and a plurality of second layers alternating with the plurality of first layers, the plurality of second layers being composed of a second material different from the first material, the plurality of second layers having a plurality of second inner surfaces facing the protruding liner, the plurality of second inner surfaces offset from the plurality of first inner surfaces forming a plurality of gaps.

Description

Technical Field

[0001] The present invention relates to computer memory, and more particularly to a phase change material memory device including voids.

Background Art

[0002] Phase change memory (PCM) can be used for both training and inference in analog computing with respect to artificial intelligence. A PCM structure can include a phase change memory cell device having a high retention force for minimizing energy consumption, an adjustable conductivity, and an overall high device resistance. This adjustment can be achieved by forming different structural states in which the ratio of the crystalline phase and the amorphous phase of the PCM material changes. The formation of these phases can occur by heating the PCM material in various amounts in a controlled manner.

Summary of the Invention

[0003] According to an embodiment of the present invention, a PCM cell includes a first electrode, a heater / PCM portion electrically connected to the first electrode and including a PCM material, a second electrode electrically connected to the PCM material, and an electrical insulator stack surrounding a protrusion liner. The stack includes a plurality of first layers having a plurality of first inner surfaces facing the protrusion liner and composed of a first material, and a plurality of second layers alternating with the plurality of first layers, the plurality of second layers being composed of a second material different from the first material and having a plurality of second inner surfaces facing the protrusion liner. A plurality of second inner surfaces offset from the plurality of first inner surfaces form a plurality of voids.

[0004] According to embodiments of the present invention, a method for manufacturing a PCM cell includes forming a first electrode and forming an electrical insulator stack on the first electrode. The stack includes a plurality of first layers made of a first material and a plurality of second layers staggered with the plurality of first layers, wherein the plurality of second layers are made of a second material different from the first material. The method also includes forming vias in the stack, removing portions of the plurality of second layers from the vias while leaving the plurality of first layers intact, forming walls in the plurality of first layers within the vias to create a plurality of gaps, forming heater / PCM portions inside the walls, and forming second electrodes on the heater / PCM portions.

[0005] According to embodiments of the present invention, the PCM cell includes a first electrode, a heater / PCM portion electrically connected to the first electrode and containing PCM material, a second electrode electrically connected to the PCM material, and an electrical insulator stack surrounding a projection liner, the stack defining a plurality of gaps. Each of the gaps has a toroidal shape, is axially spaced apart from one or more other gaps, and surrounds a portion of the PCM material. [Brief explanation of the drawing]

[0006] [Figure 1A] This is a cross-sectional view of a PCM cell containing voids according to an embodiment of the present invention. [Figure 1B] Figure 1A is a cross-sectional view of a PCM cell containing an amorphous zone according to an embodiment of the present invention. [Figure 2] This is a flowchart illustrating a method for manufacturing the PCM cell shown in Figure 1A, according to an embodiment of the present invention. [Figure 3A] Figure 2 is a cross-sectional view of a method for manufacturing a PCM cell according to an embodiment of the present invention. [Figure 3B] Figure 2 is a cross-sectional view of a method for manufacturing a PCM cell according to an embodiment of the present invention. [Figure 3C]Figure 2 is a cross-sectional view of a method for manufacturing a PCM cell according to an embodiment of the present invention. [Figure 3D] Figure 2 is a cross-sectional view of a method for manufacturing a PCM cell according to an embodiment of the present invention. [Figure 3E] Figure 2 is a cross-sectional view of a method for manufacturing a PCM cell according to an embodiment of the present invention. [Figure 3F] Figure 2 is a cross-sectional view of a method for manufacturing a PCM cell according to an embodiment of the present invention. [Figure 3G] Figure 2 is a cross-sectional view of a method for manufacturing a PCM cell according to an embodiment of the present invention. [Figure 3H] Figure 2 is a cross-sectional view of a method for manufacturing a PCM cell according to an embodiment of the present invention. [Figure 3I] Figure 2 is a cross-sectional view of a method for manufacturing a PCM cell according to an embodiment of the present invention. [Figure 4] This is a flowchart illustrating an alternative method for manufacturing an alternative PCM cell according to an embodiment of the present invention. [Figure 5A] Figure 4 is a cross-sectional view of an alternative method for manufacturing an alternative PCM cell according to an embodiment of the present invention. [Figure 5B] Figure 4 is a cross-sectional view of an alternative method for manufacturing an alternative PCM cell according to an embodiment of the present invention. [Figure 5C] Figure 4 is a cross-sectional view of an alternative method for manufacturing an alternative PCM cell according to an embodiment of the present invention. [Figure 5D] Figure 4 is a cross-sectional view of an alternative method for manufacturing an alternative PCM cell according to an embodiment of the present invention. [Figure 5E] Figure 4 is a cross-sectional view of an alternative method for manufacturing an alternative PCM cell according to an embodiment of the present invention. [Figure 5F] Figure 4 is a cross-sectional view of an alternative method for manufacturing an alternative PCM cell according to an embodiment of the present invention. [Figure 5G] Figure 4 is a cross-sectional view of an alternative method for manufacturing an alternative PCM cell according to an embodiment of the present invention. [Modes for carrying out the invention]

[0007] This specification describes various embodiments of the present invention with reference to the relevant drawings. Alternative embodiments may be devised without departing from the scope of the present invention. Note that in the following description and drawings, various connections and positional relationships between elements (e.g., above, below, adjacent, etc.) are shown. These connections or positional relationships, or both, may be direct or indirect unless otherwise specified, and this disclosure is not intended to limit in this respect. Thus, the joining of entities may refer to direct or indirect joining, and the positional relationship between entities may be direct or indirect positional relationship. As an example of an indirect positional relationship, the reference in this description to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C" and layer "D") are between layer "A" and layer "B", unless the relevant properties and functions of layer "A" and layer "B" are substantially altered by the intermediate layers.

[0008] The following definitions and abbreviations are used in the claims and interpretation of this specification. When used herein, the terms “equipped,” “having,” “containing,” “including,” “having,” “having,” “containing,” “having,” or any other variation thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus containing a list of elements is not necessarily limited to those elements alone, and may include other elements that are not expressly included or are specific to such composition, mixture, process, method, article, or apparatus. In addition, any numerical ranges included herein include the boundaries of those numerical ranges unless otherwise expressly stated.

[0009] In the following, for explanatory purposes, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “upper,” and “lower,” and their derivatives, are used in relation to the structures and methods described, as they are oriented in the diagrams. The terms “covering,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is located on top of a second element, such as a second structure, and an intervening element, such as an interface structure, may be located between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconductor layer present at the interface between these two elements. It should be noted that the term “selective to ~,” such as “first element selective to second element,” means that the first element can be etched and the second element can function as an etching stop.

[0010] For the sake of brevity, prior art related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, various operations and process steps described herein may be incorporated into more comprehensive procedures or processes that include additional steps or functions not described in detail herein. Specifically, since the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps are described only briefly or omitted entirely herein without providing details of the well-known process.

[0011] Generally, the various processes used to form microchips that are packaged into ICs can be classified into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0012] Film deposition can be any process that grows a material on a wafer, covers the wafer with a material, or transfers the material to the wafer in some other way. The techniques available include, among others, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). Another film deposition technique is plasma enhanced chemical vapor deposition (PECVD), which is a process that uses energy within a plasma to cause reactions at the wafer surface. This reaction otherwise requires higher temperatures associated with conventional CVD. The energetic ion bombardment during PECVD film deposition can also improve the electrical and mechanical properties of the film.

[0013] Removal / etching can be any process that removes material from a wafer. Examples include etching processes (either wet or dry) and chemical-mechanical planarization (CMP). One example of a removal process is ion beam etching (IBE). Generally, IBE (or milling) refers to a dry plasma etching method that uses a remote, wide beam ion / plasma source to remove substrate material by means of a physically inert gas, a chemically reactive gas, or both. Like other dry plasma etching techniques, IBE has advantages such as etching rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). Generally, RIE uses a chemically reactive plasma to remove material deposited on a wafer. In RIE, the plasma is generated by an electromagnetic field under low pressure (vacuum). High-energy ions from the RIE plasma attack the wafer surface, reacting with it and removing the material.

[0014] Semiconductor doping can generally be an electrical property modification, for example, by doping the source and drain of a transistor, by diffusion, or by ion implantation, or by both. After these doping processes, furnace annealing or rapid thermal annealing (RTA) follows. Annealing helps activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and separate transistors and their components. Selective doping of different regions of a semiconductor substrate enables the conductivity of the substrate to be changed by the application of a voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices.

[0015] Semiconductor lithography can be the formation of a three-dimensional relief image or pattern on a semiconductor substrate for subsequent pattern transfer to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist. To construct the complex structures that make up the transistors of a circuit and the many wires that connect millions of transistors, the steps of lithography and etching pattern transfer are repeated multiple times. Each pattern printed on the wafer is aligned to the patterns already formed, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0016] FIG. 1A and FIG. 1B are cross-sectional views of a PCM cell 100 for use, for example, in an integrated circuit (not shown). In the illustrated embodiment, the PCM cell 100 includes a lower wire 102, an insulator 104, a lower electrode 106, an insulator 108, a wall 110, a protrusion liner 112, a PCM material 114, a stack 116, a gap 118, an insulator 120, an upper electrode 122, and an upper wire 124.

[0017] In the illustrated embodiment, the lower part of the lower electrode 106 is in direct contact with and electrically connected to the upper part of the lower wire 102, and the lower wire 102 can receive electrical signals from other components of the integrated circuit (not shown). The lower part of the projection liner 112 is in direct contact with and electrically connected to the upper part of the lower electrode 106. The lower and sides of the PCM material 114 are in direct contact with and electrically and thermally connected to the inner surface of the projection liner 112. The lower part of the upper electrode 122 is in direct contact with and electrically connected to the upper part of the PCM material 114. The lower part of the upper wire 124 is in direct contact with and electrically connected to the upper part of the upper electrode 122, and the upper wire 124 can deliver electrical signals from the PCM cell 100 to other components of the integrated circuit (not shown).

[0018] In the embodiments shown, the wall 110 is in direct contact with the outside of the projection liner 112 and surrounds it laterally. Thus, the wall 110 surrounds the projection liner 112 on all parallel sides (e.g., sides extending vertically, as shown in Figure 1A) in at least one direction. The stack 116 generally surrounds the outside of the wall 110 laterally and is in selective direct contact with it. More specifically, the stack 116 is an electrical insulator having a two-layer configuration including alternately overlapping layers A 128 and B 130. The inner surface 129 of layer A 128 is in direct contact with the wall 110 and surrounds its corresponding axial cross-section laterally, while the inner surface 131 of layer B 130 is laterally spaced away from the wall 110. This forms a series of axially spaced toroidal gaps 118 that surround the wall 110, the projection liner 112, and a portion of the PCM material 114, respectively, with each gap 118 being surrounded by two A layers 128, a B layer, and the wall 110. Since the gaps 118 are cavities within the stack 116, the outside of the wall 110 does not come into contact with the solid material in the gaps 118. The lower and upper parts of the stack 116 are formed by two A layers 128 that are in direct contact with the insulator 108, the lower electrode 106, the insulator 120, and the upper electrode 122, respectively. The upper electrode 122 is also in direct contact with the insulator 120 and surrounded by the insulator 120 laterally on the outside and axially on a portion of its top surface, and the outside of the upper wire 124 is in direct contact with the insulator 120 and surrounded by the insulator 120 laterally.

[0019] Figure 1A shows nine layers (i.e., five A layers 128 and four B layers 130), but there may be fewer (e.g., three) or more (e.g., 21) layers. In addition, the A layers 128 and B layers 130 may have thicknesses ranging from, for example, 2 nanometers (nm) to 20 nm. Furthermore, the thickness of the A layers 128 may be the same as or different from the thickness of the B layers 130.

[0020] In the embodiments shown, layers A 128 and B 130 are, for example, NBLoK, silicon nitride (SiN), aluminum oxide (Al2O3), aluminum nitride (AlN), silicon oxide (SiO2), or silicon oxycarbide (SiO2). X C Y It is composed of dielectric (electrically insulating) materials such as ). Layers A 128 and B 130 are composed of different materials so that a portion of layer B 130 can be selectively removed without significantly removing layer A 128 (thereby forming a gap 118). For example, layer A 128 may be composed of SiN and layer B 130 may be composed of AIN. The difference in materials between layer A 128 and layer B 130 can be utilized during the manufacturing of the PCM cell 100. For example, there is significant selectivity with respect to the removal of AIN and SiN by some reactant or process or both, with etching rate ratios such as 5:1, 10:1, or even larger (e.g., AIN:SiN or SiN:AIN). More specifically, SiN is easily removed using the RIE process, while AIN is resistant to the RIE process, so that SiN can be removed without significantly removing AIN. On the other hand, AIN is easily removed using certain wet etching processes and chemicals, while SiN is resistant to such processes, so AIN can be removed without significantly removing SiN. In another example, layer A 128 may be composed of SiO2 and layer B 130 may be composed of Al2O3. Al2O3 has higher selectivity for chlorine gas (Cl2), argon (Ar), and argon-boron-chlorine (Ar / B / Cl2) mixtures. Furthermore, the etching rates of SiO2 and SiN are higher than those of carbon tetrafluoride (CF4). 4) The etching rate of Al2O3 is related to aluminum chloride (AlCl3) or chlorine-boron trichloride (Cl2 / BCl3) mixtures. Therefore, fluorine (F), Cl2, sulfur hexafluoride (SF6), and carbon fluoride (C) are also involved. x F y Gases such as , Ar, and hydrogen (H2) can contribute to the selectivity of RIE between Al2O3 and SiN or SiO2.

[0021] In the embodiment shown, the insulators 104, 108, 120, and the stack 116 structurally support, selectively electrically insulate, and fill the spaces between the other components of the PCM cell 100 as needed. Thus, the outside of the lower wire 102 is in direct contact with the insulator 104 and is laterally surrounded by the insulator 104, and the outside of the lower electrode 106 is in direct contact with the insulator 108 and is laterally surrounded by the insulator 108. Furthermore, the top surface of the stack 116, the outside and part of the top surface of the upper electrode 122, and the outside of the upper wire 124 are in direct contact with the insulator 120.

[0022] In the embodiments shown, the cross-sections of various components or the entire PCM cell 100 or both (into the page of Figure 1) can be circular, but in other embodiments they can be rectangular, square, elliptical, or any other suitable shape. In addition, the width of the PCM material 114 is smaller than the width of the lower electrode 106 and the upper electrode 122, while the axial length of the PCM material 114 is significantly longer than its width. Thus, the PCM cell 100 can be said to have a confined cell configuration, in which electrical signals (i.e., current) can flow from the lower electrode 106 to the upper electrode 122 through the projection liner 112 and the PCM material 114. In some embodiments, the PCM material 114 may have a width of 20 nm to 50 nm and a thickness (i.e., height) of 30 nm to 100 nm.

[0023] In the embodiments shown, the lower electrode 106 and the upper electrode 122 are made of a highly conductive material, such as a metal or metallic compound, for example, titanium nitride (TiN) or tungsten (W). The wall 110 includes a high electrical resistance component made of a dielectric (e.g., SiN) or a higher-resistance metal, for example, tantalum nitride (TaN). The wall 110 may have a thickness in the range of, for example, 5 nm to 50 nm. In addition, the projection liner 112 is made of a higher-resistance metal, for example, TaN. The projection liner 112 may have a thickness in the range of, for example, 2 nm to 10 nm.

[0024] In the embodiments shown, the insulators 104, 108, and 120 are composed of dielectric (electrically insulating) materials such as SiN, SiO2, silicon carbide nitride (SiNC), or tetraethyl orthosilicate (TEOS). In some embodiments, all of the insulators 104, 108, and 120 are made of the same material, while in other embodiments, different materials are used for some or all of the insulators 104, 108, and 120. In some embodiments, the insulator 108 (and the lower electrode 106) has a thickness in the range of 10 nm to 100 nm.

[0025] In the embodiments shown, the PCM material 114 is basically composed of a phase-change material such as germanium-antimony-tellurium (GST) material, gallium-antimony-tellurium (GaST) material, or silver-iridium-antimony-telluride (AIST) material, but other materials may be used as needed. Other examples of PCM materials include, but are not limited to, germanium-tellurium composites (GeTe), silicon-antimony-tellurium (Si-Sb-Te) alloys, gallium-antimony-tellurium (Ga-Sb-Te) alloys, germanium-bismuth-tellurium (Ge-Bi-Te) alloys, indium-tellurium (In-Se) alloys, arsenic-antimony-tellurium (As-Sb-Te) alloys, silver-indium-antimony-tellurium (Ag-In-Sb-Te) alloys, Ge-In-Sb-Te alloys, Ge-Sb alloys, Sb-Te alloys, Si-Sb alloys, Ge-Te alloys, and combinations thereof. PCM material 114 may be undoped or doped (for example, doped with one or more of oxygen (O), nitrogen (N), silicon (Si), or titanium (Ti)). The terms "composed essentially" and "consist essentially," when used herein in reference to materials of various layers, indicate that, if other materials are present, those other materials do not substantially alter the fundamental properties of the enumerated material. For example, PCM material 114, which is essentially composed of GST material, does not contain any other materials that substantially alter the fundamental properties of the GST material.

[0026] In the embodiment shown, the PCM cell 100 can be operated as a memory cell by programming it by passing a current pulse from the lower electrode 106 to the upper electrode 122. This operation can be performed at various voltages and / or for various durations to read or write values ​​to the PCM cell 100. For example, a high voltage (e.g., 1 volt (V) to 4 V) can be used for a short duration to write, which can cause the PCM material 114 to heat itself above its melting point (by resistive heating). Thereafter, the PCM material 114 performs the functions of both a heater and a memory. After the current flow stops, the PCM material 114 can cool rapidly, thereby forming an amorphous zone 126 in a process called "resetting". The amorphous zone 126 is a dome-shaped region of the PCM material 114 having an amorphous structure, while the rest of the PCM material 114 still has a polycrystalline structure. Generally, this amorphous configuration lacks a distinct structure. However, localized, disorganized crystalline nuclei (i.e., small crystallized regions of the phase-change material 114) may exist in the amorphous zones 126. The generation of amorphous zones 126 can increase the overall electrical resistance of the PCM cell 100 compared to a purely polycrystalline configuration (such as the PCM cell 100 in Figure 1A). These resistance values ​​of the PCM cell 100 can be read, for example, by sending a current pulse from the lower electrode 106 to the upper electrode 122 at a low voltage (e.g., 0.2V), without changing the state of the PCM material 114 (including the state of the amorphous zones 126) or the resistance values ​​of the PCM cell 100.

[0027] In addition, the PCM material 114 can be rewritten and returned to a polycrystalline configuration by "setting" the PCM cell 100. One method for setting the PCM material 114 is to use a high-voltage (e.g., 1V-4V) electrical pulse for a short period (e.g., 10 nanoseconds (ns)), thereby heating the PCM material 114 above its crystallization point but not reaching its melting point. Since the crystallization temperature is lower than the melting temperature, the PCM material 114 can anneal and form crystals after the current flow stops. Another method for setting the PCM material 114 is to use an electrical pulse with a relatively long (e.g., 1 microsecond) falling edge (as opposed to a square pulse with a relatively short trailing edge on the order of a few nanoseconds), strong enough to heat the PCM material 114 above its melting point, and then allow the PCM material 114 to cool slowly and form crystals. Either of these processes causes the overall electrical resistance of a polycrystalline PCM cell 100 to decrease compared to a PCM cell 100 that includes an amorphous zone 126 (like PCM cell 100 in Figure 1B). This new resistance can then be read using a current at a low voltage (e.g., 0.2V) without changing the state of the PCM material 114 or the resistance of the PCM cell 100.

[0028] In some embodiments, the melting temperature of the PCM material 114 is approximately 600°C. In some embodiments, the crystallization temperature of the PCM material 114 is approximately 180°C. In addition, the process of setting and resetting the PCM cell 100 can occur repeatedly, and in some embodiments, different amorphous zones 126 with different resistances can be generated within the PCM material 114 (for example, due to containing amorphous zones 126 of different sizes or different amounts of crystallization nuclei within the amorphous zones 126, or both). This makes it possible for the PCM cell 100 to have a variety of different resistances, which can be generated by changing the resetting parameters. Thus, if the PCM cell 100 is considered to represent an information digit, these digits may be non-binary numbers (as opposed to conventional bits). However, in some embodiments, the PCM cell 100 can be used as a bit by including or not including uniform amorphous zones 126 in the PCM material 114. In such embodiments, the PCM cell 100 may have high resistance (also known as low voltage output or "0") or low resistance (also known as high voltage output or "1").

[0029] The components and configuration of the PCM cell 100 allow the gap 118 to be separated from the PCM material 114, reducing heat conduction. This is because the gap 118 has a lower thermal conductivity than the B layer 130. This allows more of the heat generated within the PCM material 114 to be retained within the PCM material 114, thereby improving the speed and efficiency of the PCM cell 100 and reducing the amount of energy required to tune / program the PCM cell 100. Furthermore, the degradation of the PCM cell 100's performance is also mitigated, with the lower wire 102 and upper wire 124 being heated less than if there were no gap 118. In addition, the protruding liner 112 thermally insulates the lower electrode 106 from the PCM material 114, further improving the efficiency of the PCM cell 100.

[0030] Figure 2 is a flowchart of method 200 for manufacturing PCM cell 100. Figures 3A to 3I are a series of diagrams of method 200 for manufacturing PCM cell 100. Here, Figures 2 and 3A to 3I are used in conjunction with each other for explanation, and each operation of method 200 is illustrated by one of Figures 3A to 3I. In addition, references to the features of PCM cell 100 shown in Figure 1A or 1B or both may be made during this explanation.

[0031] In the embodiment shown, method 200 begins in operation 202, in which a two-layer dielectric block 332 is formed on a lower electrode 106 and an insulator 108. In operation 204, a mask 334 is formed on the block 332. The mask 334 consists of an organic planarization layer (OPL) 336, silicon with anti-reflective coating (SiARC) 338, and a photoresist layer 340. The photoresist layer 340 includes a gap 342 for the formation of vias 344 during operation 206. More specifically, the vias 344 have a width smaller than the width of the lower electrode 106, for example, 20 nm. The vias 344 are formed by etching each layer of the block 332 in the same manner, and then the mask 334 is removed.

[0032] In operation 208, for example, using a wet process or RIE process, block 332 is selectively etched to remove a portion of one type of the two-layer dielectric material within via 344, while leaving the other type of the two-layer dielectric material intact. This creates pores 346 in operation 208, such as in stack 116 (containing layer A 128 and layer B 130), with the inner surface 131 of layer B 130 offset from the inner surface 129 of layer A 128. In operation 210, a TaN layer 348 is formed on top of stack 116 using a CVD or PVD process. This ensures that the TaN layer 348 follows the inner edge of layer A 128, avoiding contact with layer B 130 and separating the pores 346 into cavities 350 and gaps 118. The formation of gaps 118 occurs under CVD or PVD process conditions where a vacuum exists between them. This vacuum may be at a pressure of, for example, 10 milliliters (mTorr) or less, which keeps some fluid (e.g., air) sealed within the gap 118. In some embodiments, an ALD process is used in operation 210 instead of CVD or PVD. However, when ALD is used, the resulting TaN layer 348 may penetrate further into the pores 346 toward the B layer 130, making the gap 118 smaller. Since air has a lower thermal conductivity than the dielectric material, this can reduce the thermal insulation of the stack 116.

[0033] In operation 212, for example, the TaN layer 348 is etched using the RIE process to remove its horizontal portion, thereby forming the wall 110, in addition to exposing the lower electrode 106 and stack 116. In operation 214, the protrusion layer 352 and PCM layer 354 are deposited inside the wall 110. More specifically, the protrusion layer 352 is formed on the stack 116, wall 110, and lower electrode 106, and the PCM layer 354 is formed on top of the protrusion layer 352. In operation 216, chemical mechanical polishing (CMP) is performed to remove excess material from the protrusion layer 352 and PCM layer 354 to form the stack 116 and the adjacent protrusion liner 112 and PCM material 114, respectively. In operation 218, the insulator 120, upper electrode 122, and upper wire 124 are formed on the stack 116, wall 110, projection liner 112, and PCM material 114, respectively.

[0034] The components, configuration, and operation of the PCM cell 100 and method 200 allow for the formation of a gap 118 around the PCM material 114. This can occur because layer B 130 is susceptible to at least one material removal process, while layer A 128 is resistant to this material removal process.

[0035] Figure 4 is a flowchart of method 400 for manufacturing PCM cell 500. Figures 5A to 5G are a series of cross-sectional views of method 400 for manufacturing PCM cell 500. Here, Figures 4 and 5A to 5G are used in conjunction with each other for illustrative purposes, and each operation of method 400 is illustrated by one of Figures 5A to 5G. During this explanation, references to features of PCM cell 100 (shown in Figure 1) and PCM cell 500 (shown in Figure 5G) may be made. Features in PCM cell 500 that are the same as those in PCM cell 100 may have the same reference number, and features in PCM cell 500 that are similar to features in PCM cell 100 may have a reference number 400 greater.

[0036] In some embodiments, method 400 begins with operation 210 of method 200 (shown in Figure 3E), and in other embodiments, method 400 begins after operation 212 of method 200 (shown in Figure 3F). Figures 5A–5I illustrate the latter embodiments. In operation 414, a TiN layer 556 and a high-resistance layer 558 are deposited on the inside of the wall 110. More specifically, the TiN layer 556 is formed on the stack 116, the wall 110, and the lower electrode 106, and the high-resistance layer 558 is formed on top of the TiN layer 556 and may consist of, for example, SiN or high-resistance TaN. In operation 416, chemical mechanical polishing (CMP) is performed to remove excess material from the TiN layer 556 and the high-resistance layer 558 to form the stack 116 and the adjacent heater 560. In operation 418, the PCM layer 562, the TiN layer 564, and the SiN layer 566 are formed on the stack 116 and the heater 560. In some embodiments, the thickness of the PCM layer 562 is approximately 80 nm, the thickness of the TiN layer 564 is approximately 75 nm, and the thickness of the SiN layer 566 is approximately 220 nm. In some embodiments, prior to operation 418, a projection liner 568 (shown in perspective as it is not included in the subsequent steps of method 400) is formed on the stack 116 and the heater 560.

[0037] In operation 420, masking and etching are performed to form the PCM material 514, the upper electrode 522, and the hard mask 570, which expose the stack 116. In the shown embodiment, the lateral widths of the PCM material 514 and the upper electrode 522 are the same, while the width of the heater 560 is reduced relatively significantly (e.g., to 1 / 3 to 1 / 7 or about 1 / 5). Thus, it can be said that the PCM cell 500 has a mushroom-shaped configuration, where electrical signals (i.e., current) can flow from the lower electrode 104 to the upper electrode 522 through the heater 560 and the PCM material 114. In contrast to the PCM cell 100, the PCM cell 500 includes a heater / PCM portion consisting of two parts: the heater 560 and the separated PCM material 114. However, instead of relying on the PCM material 514 itself to heat the PCM material 514, the heater 560 is used to program the PCM material 514, but the memory function can be operated in the same way as the PCM cell 100.

[0038] In operation 422, an encapsulation layer 572 is formed on the stack 116, PCM material 514, upper electrode 522, and hard mask 570. The encapsulation layer 572 may be composed of, for example, SiN or silicon carbonitride (SiCN). In operation 424, etching is performed to expose the insulator 108 in order to form the encapsulator 574 and cap 576. In operation 426, the insulator 520 and upper wire 524 are formed on the insulator 108, stack 116, upper electrode 522, encapsulator 574, and cap 576, respectively, completing the PCM cell 500.

[0039] The components, configuration, and operation of the PCM cell 500 and method 400 allow for the formation of a gap 118 around the heater 560. This can occur because layer B 130 is susceptible to at least one material removal process, while layer A 128 is resistant to this material removal process.

[0040] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive, nor are they limited to the embodiments disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the embodiments described. The terms used herein have been selected to best describe the principles of the embodiments, their practical applications, or any technical improvements beyond the technology available on the market, or to enable other those skilled in the art to understand the embodiments disclosed herein.

[0041] In preferred embodiments of the present invention as described herein, a phase-change memory (PCM) cell is provided comprising a heater / PCM portion electrically connected to the first electrode and containing PCM material, a second electrode electrically connected to the PCM material, and an electrical insulating stack surrounding a protruding liner, wherein the stack defines a plurality of gaps, each having a toroidal shape, axially spaced apart from one or more other gaps, and surrounding a portion of the heater / PCM portion. The stack preferably comprises a plurality of first layers and a plurality of second layers staggered with the plurality of first layers, with each gap being surrounded by two of the plurality of first layers and one of the plurality of second layers. The PCM cell may further comprise a protruding liner in direct contact with the first electrode, the second electrode, and the PCM material. The PCM cell may further comprise walls in direct contact with the protruding liner and the stack. Each gap may further be surrounded by walls. Each gap may enclose a portion of the wall. The heater / PCM section may further include a heater made of a high electrical resistance material, which is separated from the PCM material.

Claims

1. A phase-change memory (PCM) cell, The first electrode and A heater / PCM portion electrically connected to a first electrode, comprising a PCM material, A second electrode electrically connected to the PCM material, An electrical insulator stack surrounding at least a portion of the heater / PCM portion and The stack is equipped with, A plurality of first layers, each composed of a first material and having a plurality of first inner surfaces facing the heater / PCM portion, The material comprises a plurality of second layers that are staggered with the plurality of first layers, the plurality of second layers being made of a second material different from the first material, and the plurality of second layers having a plurality of second inner surfaces facing the heater / PCM portion. The plurality of second inner surfaces, which are offset from the plurality of first inner surfaces, form a plurality of gaps. A PCM cell having a wall between the plurality of gaps and the PCM material.

2. The PCM cell according to claim 1, further comprising the first electrode, the second electrode, and a protruding liner in direct contact with the PCM material.

3. The PCM cell according to claim 2, wherein the wall is in direct contact with the projection liner and the stack.

4. The PCM cell according to claim 3, wherein each of the plurality of gaps is surrounded by two of the plurality of first layers, one of the plurality of second layers, and the wall.

5. The plurality of first layers are in direct contact with the wall, The PCM cell according to claim 3, wherein the plurality of second layers are spaced apart from the wall.

6. The PCM cell according to claim 3, wherein each gap is further surrounded by the wall.

7. The first material is resistant to the material removal process, The PCM cell according to claim 1, wherein the second material is susceptible to the effects of the material removal process.

8. The PCM cell according to claim 1, further comprising a heater made of a high electrical resistance material, wherein the heater / PCM portion is separated from the PCM material.

9. A method for manufacturing a phase-change memory (PCM) cell, To form the first electrode, Forming an electrical insulator stack on the first electrode, wherein the stack is A plurality of first layers made of a first material, and The formation comprises a plurality of second layers that are staggered with the plurality of first layers, wherein the plurality of second layers are made of a second material different from the first material. Forming vias within the aforementioned stack, Removing a portion of the multiple second layers from the via while leaving the multiple first layers intact, The process involves forming walls in the multiple first layers within the via and creating multiple gaps. The heater / PCM portion is formed on the inside of the aforementioned wall, A second electrode is formed on the heater / PCM portion. Methods that include...

10. The method according to claim 9, wherein each of the plurality of gaps is surrounded by two of the plurality of first layers, one of the plurality of second layers, and the wall.

11. The method according to claim 9, further comprising forming a projection liner on the first electrode and the wall before forming the heater / PCM portion, such that the projection liner is positioned between the wall and the heater / PCM portion.

12. The method according to claim 9, wherein forming the heater / PCM portion on the inside of the wall includes forming a PCM material film on the inside of the wall and on the stack.

13. The heater / PCM portion is formed on the inside of the wall. A heater is formed by depositing a high electrical resistance material on the inside of the wall and on the stack, The PCM material is deposited on the heater and on the stack. The method according to claim 9, including the method described in claim 9.

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