Stacked complementary transistor structure for three-dimensional integration

Abstract

The device includes a first interconnect structure, a second interconnect structure, a stacked complementary transistor structure, a first contact, and a second contact. The stacked complementary transistor structure is disposed between the first interconnect structure and the second interconnect structure. The stacked complementary transistor structure includes a first transistor of a first type and a second transistor of a second type opposite to the first type. The first contact connects a first source / drain element of the first transistor to the first interconnect structure. The second contact connects a first source / drain element of the second transistor to the second interconnect structure. The first and second contacts are disposed in alignment with one another.

Description

[Technical Field]

[0001] This disclosure generally relates to monolithic three-dimensional (3D) integration technology, and more particularly to technology for manufacturing monolithic 3D semiconductor integrated circuit devices, including stacked CMOS (complementary metal-oxide-semiconductor) transistor structures. [Background technology]

[0002] Continuous innovation in semiconductor process technology enables higher integration density and device scaling. In particular, the latest 3D integration technology is poised to become a crucial technological driver for providing extremely high-density integrated circuits. 3D monolithic design involves stacked layers of field-effect transistor (FET) devices to reduce the device footprint. For example, the FET-over-FET integration scheme is one form of 3D monolithic integration scheme in which p-type FETs (PFETs) and n-type FETs (NFETs) are formed in different device layers on a single substrate.

[0003] While stacked CMOS structures increase transistor density by stacking PFET and NFET devices vertically on top of each other, the integration density of a stacked CMOS structure is limited, for example, by the space required for source / drain contacts. In particular, in the case of a 3D semiconductor integrated circuit device where the source / drain elements of a stacked CMOS structure are connected to a back-end-of-line (BEOL) interconnect structure located on top of the stacked CMOS structure, at least one lower source / drain region of the lower FET device must be formed to extend laterally beyond the upper source / drain region of the corresponding upper FET device to provide the lateral space required to form a source / drain contact from the lower source / drain region to the BEOL interconnect structure. This extra lateral space required for the source / drain contact increases the cell size of the stacked CMOS structure, which is undesirable.

[0004] Furthermore, another issue with stacked CMOS technology is the ability to effectively isolate the stacked NFET / PFET structure from the underlying semiconductor substrate. For example, insufficient isolation leads to decreased device performance as a result of increased source / drain leakage to the underlying substrate and increased parasitic capacitance and leakage between the metal gate structure and the underlying substrate. Conventional isolation techniques can be used to form structures / layers to isolate the stacked NFET / PFET structure from the underlying semiconductor substrate. Such techniques require dedicated process modules to form such isolation structures or layers, or both, which introduces additional complexity and cost to the semiconductor manufacturing process. [Overview of the project]

[0005] Here, exemplary embodiments relating to semiconductor integrated circuit devices including stacked complementary transistor structures and methods for manufacturing such semiconductor integrated circuit devices will be described in further detail.

[0006] An exemplary embodiment includes a device comprising a first interconnect structure, a second interconnect structure, a stacked complementary transistor structure, a first contact, and a second contact. The stacked complementary transistor structure is positioned between the first interconnect structure and the second interconnect structure. The stacked complementary transistor structure includes a first transistor of the first type and a second transistor of the second type, which is the opposite of the first type. The first contact connects the first source / drain element of the first transistor to the first interconnect structure. The second contact connects the first source / drain element of the second transistor to the second interconnect structure. The first and second contacts are positioned aligned with each other.

[0007] Advantageously, implementing a second interconnect structure and connecting the second contact to the second interconnect structure reduces the cell size of the stacked complementary transistor structure. This is because the first and second contacts can be formed aligned longitudinally with each other. This eliminates the need to connect both the first and second contacts to the same interconnect structure (e.g., the first interconnect structure), which would require the first and second contacts to be placed adjacent to each other, thereby requiring additional lateral space and thus increasing the cell size of the stacked complementary transistor structure.

[0008] Another exemplary embodiment includes a device comprising a first interconnect structure, a second interconnect structure, a multilayer complementary transistor structure, an insulating layer, a first contact, and a second contact. The multilayer complementary transistor structure is located between the first interconnect structure and the second interconnect structure. The multilayer complementary transistor structure includes a first transistor of the first type and a second transistor of the second type, which is the opposite of the first type. The insulating layer is located between the multilayer complementary transistor structure and the second interconnect structure and includes extensions of the first and second source / drain elements of the second transistor, respectively, extending into the second insulating layer. The first contact connects the first source / drain element of the first transistor to the first interconnect structure. The second contact is coupled to the extension of the first source / drain element of the second transistor to connect the first source / drain element of the second transistor to the second interconnect structure. The first and second contacts are positioned aligned with each other.

[0009] Advantageously, by implementing the extensions of the first and second source / drain elements of the second transistor, the first and second source / drain elements can apply strain (e.g., compressive or tensile strain) to the active channel of the second transistor at the same point in time during the manufacturing of the device before the extensions are released from the semiconductor substrate before being placed on the second insulating layer.

[0010] Another embodiment includes a device comprising a first interconnect structure, a second interconnect structure, a complementary inverter, a first contact, a second contact, and a third contact. The complementary inverter includes a stacked complementary transistor structure positioned between the first interconnect structure and the second interconnect structure. The stacked complementary transistor structure includes a first transistor of the first type and a second transistor of the second type, which is the opposite of the first type. The first transistor includes a source element and a drain element, and the second transistor also includes a source element and a drain element. The first contact connects the drain elements of the first and second transistors to the first interconnect structure in common. The second contact connects the source element of the first transistor to the first interconnect structure. The third contact connects the source element of the second transistor to the second interconnect structure. The second and third contacts are positioned aligned with each other.

[0011] Another embodiment includes a method for manufacturing a semiconductor device. A stacked complementary transistor structure is formed on a semiconductor substrate. The stacked complementary transistor structure includes a first transistor of a first type and a second transistor of a second type, which is the opposite of the first type. A first contact is formed connected to the first source / drain element of the first transistor. A first interconnect structure is formed connected to the first contact. A portion of the semiconductor substrate is removed to expose the bottom surface of the stacked complementary transistor structure. An insulating layer is formed to cover the exposed bottom surface of the stacked complementary transistor structure. A second contact is formed in the insulating layer connected to the first source / drain element of the second transistor, and the second contact is formed aligned with the first contact. A second interconnect structure is formed on the insulating layer, and the second interconnect structure is connected to the second contact.

[0012] Advantageously, the process of replacing the removed portion of the semiconductor substrate with an insulating layer to cover the exposed bottom surface of the stacked complementary transistor structure and the first and second source / drain elements of the second transistor works to provide isolation from the semiconductor substrate without requiring the implementation of a dedicated process module to achieve such isolation.

[0013] Another embodiment includes a method for manufacturing a semiconductor device. A stacked complementary transistor structure is formed on a semiconductor substrate. The stacked complementary transistor structure includes a first transistor of a first type and a second transistor of a second type, which is the opposite of the first type. The first transistor includes a first source / drain element and a second source / drain element. The second transistor includes a first source / drain element and a second source / drain element, and the first and second source / drain elements of the second transistor each include extensions that extend into the semiconductor substrate. A first contact is formed connected to the first source / drain element of the first transistor. A first interconnect structure is formed connected to the first contact. A portion of the semiconductor substrate is removed to expose the bottom surface of the stacked complementary transistor structure and free the extensions of the first and second source / drain elements of the second transistor. An insulating layer is formed to cover the exposed bottom surface of the stacked complementary transistor structure and the extended portions of the first and second source / drain elements of the second transistor. A second contact is formed in the insulating layer so as to contact the extended portions of the first source / drain elements of the second transistor, and the second contact is formed in alignment with the first contact. A second interconnect structure is formed on the insulating layer, and the second interconnect structure is connected to the second contact.

[0014] Advantageously, by removing portions of the semiconductor substrate, the extensions of the first and second source / drain elements of the second transistor are freed, allowing the first and second source / drain elements to apply strain (e.g., compressive or tensile strain) to the active channel of the second transistor before the second insulating layer is formed. This strain enhances the performance of the second transistor and the stacked complementary transistor structure.

[0015] Other embodiments are described in the following detailed description of the embodiments, which are to be read in conjunction with the accompanying drawings. Figures 2 to 17 schematically illustrate a method for manufacturing a semiconductor integrated circuit device including a stacked complementary transistor structure containing first and second transistors, according to embodiments of the present invention. [Brief explanation of the drawing]

[0016] [Figure 1] This is a schematic vertical cross-sectional view of a semiconductor integrated circuit device including a stacked complementary transistor structure according to an exemplary embodiment of the present disclosure. [Figure 2] This is a schematic vertical cross-sectional view of the initial structure of a semiconductor integrated circuit device in the early stages of manufacturing, including a semiconductor substrate and a nanosheet laminate structure formed on the semiconductor substrate. [Figure 3A] This is a schematic diagram of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by patterning the nanosheet stack structure of Figure 2 to form a patterned nanosheet stack structure and forming a shallow trench isolation layer on a semiconductor substrate, according to exemplary embodiments of the present disclosure. [Figure 3B] This is a schematic diagram of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by patterning the nanosheet stack structure of Figure 2 to form a patterned nanosheet stack structure and forming a shallow trench isolation layer on a semiconductor substrate, according to exemplary embodiments of the present disclosure. [Figure 3C]This is a schematic diagram of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by patterning the nanosheet stack structure of Figure 2 to form a patterned nanosheet stack structure and forming a shallow trench isolation layer on a semiconductor substrate, according to exemplary embodiments of the present disclosure. [Figure 4A] A schematic diagram of the following intermediate structure of a semiconductor integrated circuit device, comprising forming a dummy gate structure that overlaps a portion of the patterned nanosheet stack structure shown in Figures 3A-3C according to an exemplary embodiment of the present disclosure, and patterning the exposed portion of the patterned nanosheet stack structure in the source / drain region adjacent to the dummy gate structure to form the first and second nanosheet channel structures of the first and second transistors, respectively. [Figure 4B] A schematic diagram of the following intermediate structure of a semiconductor integrated circuit device, comprising forming a dummy gate structure that overlaps a portion of the patterned nanosheet stack structure shown in Figures 3A-3C according to an exemplary embodiment of the present disclosure, and patterning the exposed portion of the patterned nanosheet stack structure in the source / drain region adjacent to the dummy gate structure to form the first and second nanosheet channel structures of the first and second transistors, respectively. [Figure 4C] A schematic diagram of the following intermediate structure of a semiconductor integrated circuit device, comprising forming a dummy gate structure that overlaps a portion of the patterned nanosheet stack structure shown in Figures 3A-3C according to an exemplary embodiment of the present disclosure, and patterning the exposed portion of the patterned nanosheet stack structure in the source / drain region adjacent to the dummy gate structure to form the first and second nanosheet channel structures of the first and second transistors, respectively. [Figure 5] This is a schematic vertical cross-sectional view of the following intermediate structure of a semiconductor integrated circuit device structure, which is constructed by replacing the remainder of the sacrificial nanosheet layer with a dielectric isolation layer that isolates the stacked first and second transistors, according to an exemplary embodiment of the present disclosure. [Figure 6] A schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, configured by forming recesses in the sidewalls of the first and second nanosheet-channel structures by laterally indenting the exposed sidewall surfaces of the sacrificial nanosheet layers of the first and second nanosheet-channel structures in FIG. 5, according to an exemplary embodiment of the present disclosure. [Figure 7] A schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, configured by forming gate sidewall spacers embedded in the recesses in the sidewalls of the first and second nanosheet-channel structures, according to an exemplary embodiment of the present disclosure. [Figure 8] A schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, configured by indenting the exposed portions of the semiconductor substrate in the source / drain regions to form the first and second trenches in the semiconductor substrate, according to an exemplary embodiment of the present disclosure. [Figure 9] A schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, configured by epitaxially growing the first and second source / drain elements of the first transistor starting from the bottom surfaces of the first and second trenches in the semiconductor substrate, according to an exemplary embodiment of the present disclosure. [Figure 10] A schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, configured by depositing and patterning a conformal layer of a dielectric material to form a protective liner on the first and second source / drain elements of the first transistor, according to an exemplary embodiment of the present disclosure. [Figure 11] A schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, configured by epitaxially growing the first and second source / drain elements of the second transistor and forming a first insulating layer to seal the stacked complementary transistor structure, according to an exemplary embodiment of the present disclosure. [Figure 12A]A schematic vertical cross-sectional view of a next intermediate structure of a semiconductor integrated circuit device, which is configured by removing a dummy gate structure and a sacrificial nanosheet layer to release active nanosheet channel layers of first and second nanosheet channel structures of first and second transistors, thereby forming an open gate region, according to an exemplary embodiment of the present disclosure. [Figure 12B] A schematic vertical cross-sectional view of a next intermediate structure of a semiconductor integrated circuit device, which is configured by removing a dummy gate structure and a sacrificial nanosheet layer to release active nanosheet channel layers of first and second nanosheet channel structures of first and second transistors, thereby forming an open gate region, according to an exemplary embodiment of the present disclosure. [Figure 13A] A schematic vertical cross-sectional view of a next intermediate structure of a semiconductor integrated circuit device, which is formed by forming a metal gate structure and forming a second insulating layer on the first insulating layer and the metal gate structure, according to an exemplary embodiment of the present disclosure. [Figure 13B] A schematic vertical cross-sectional view of a next intermediate structure of a semiconductor integrated circuit device, which is formed by forming a metal gate structure and forming a second insulating layer on the first insulating layer and the metal gate structure, according to an exemplary embodiment of the present disclosure. [Figure 14] A schematic vertical cross-sectional view of a next intermediate structure of a semiconductor integrated circuit device, which is configured by forming gates and source / drain contacts in a stacked FET structure, according to an exemplary embodiment of the present disclosure. [Figure 15] A schematic vertical cross-sectional view of a next intermediate structure of a semiconductor integrated circuit device, which is configured by forming a first interconnect structure on a front side of the intermediate structure of FIG. 14 and coupling a handler substrate to the first interconnect structure. [Figure 16]This is a schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, which is formed by back-side machining the intermediate structure of Figure 14 to remove a portion of the semiconductor substrate according to an exemplary embodiment of the present disclosure. [Figure 17] This is a schematic vertical cross-sectional view of the following intermediate structure of a semiconductor integrated circuit device, which is formed by back-facing the intermediate structure of Figure 16 to form a dielectric layer, back-side contacts, and back-side interconnect structure according to an exemplary embodiment of the present disclosure. [Figure 18] This is a schematic vertical cross-sectional view of a semiconductor integrated circuit device including a stacked complementary transistor structure, according to another exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0017] Here, exemplary embodiments relating to semiconductor integrated circuit devices including stacked CMOS device structures (alternatively, stacked complementary transistor structures) with reduced CMOS cell size, and methods for manufacturing such semiconductor integrated circuit devices, will be described in further detail. As will be described in further detail below, the reduction in CMOS cell size of a stacked CMOS device structure is achieved by forming backside source / drain contacts in a backside interconnect structure (e.g., a backside power distribution network), thereby allowing (i) longitudinal alignment of the drain contacts with respect to the drain elements of a stacked complementary transistor structure, and (ii) longitudinal alignment of the source contacts with respect to the source elements of a stacked complementary transistor structure.

[0018] As will be described in more detail below, exemplary embodiments of the present disclosure further include techniques for providing isolation from the semiconductor substrate, thereby enabling backside removal of portions of the semiconductor substrate in contact with the stacked complementary transistor structure, in order to eliminate the need to implement a dedicated process module to achieve such isolation. Furthermore, as will be described in more detail below, techniques are provided for improving the performance of the stacked complementary transistor structure by growing deep, high-quality epitaxial source / drain elements directly from a crystalline semiconductor substrate in relation to the increased strain when backside removal of portions of the semiconductor substrate between epitaxial source / drain elements.

[0019] For illustrative purposes, exemplary embodiments of the invention are described in relation to stacked complementary transistor structures, including nanosheet FET devices. However, it should be understood that the exemplary embodiments described herein are readily applicable to various types of gate-all-around (GAA) FET devices, such as nanowire FETs, or other types of GAA FET devices having gate structures formed on all sides of the active channel layer. Furthermore, the exemplary techniques disclosed herein can be implemented by stacked fin-type FET (FinFET) devices.

[0020] Please understand that the various layers, structures, and regions shown in the attached drawings are schematic examples and not to scale. In addition, for the sake of clarity, one or more layers, structures, and regions of types commonly used to form semiconductor devices or structures may not be explicitly shown in the given drawings. This does not imply that all layers, structures, and regions not explicitly shown are omitted from actual semiconductor structures. Furthermore, please understand that the embodiments described herein are not limited to the specific materials, features, and processing steps illustrated and described herein. In particular, with respect to semiconductor processing steps, the description provided herein is not intended to encompass all processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, are intentionally omitted herein for the sake of brevity.

[0021] The same or similar reference numbers are used throughout the drawings to indicate the same or similar features, elements, or structures, and it should be understood that a detailed description of the same or similar features, elements, or structures is not repeated for each drawing. Furthermore, the terms “about” or “substantially” used herein with respect to thickness, width, proportion, range, etc., are intended to indicate that they are close or approximate, not exact. For example, the terms “about” or “substantially” used herein imply that there is a small error, such as less than 1% of the amount mentioned. The term “on” used herein to describe the formation of a feature (e.g., a layer) that is “on” a side or surface means that the feature (e.g., a layer) may be formed “directly on” (i.e., in direct contact) the implied side or surface, or that the feature (e.g., a layer) may be formed “indirectly on” the implied side or surface, together with one or more additional layers positioned between the feature (e.g., a layer) and the implied side or surface.

[0022] To provide spatial context regarding different structural orientations of semiconductor structures shown in the drawings, each drawing is shown in an XYZ Cartesian coordinate system. As used herein, the terms “vertical,” “vertical direction,” or “vertical height” mean the Z direction in the Cartesian coordinate system shown in the drawings, and as used herein, the terms “horizontal,” “horizontal direction,” or “lateral direction” mean the X direction, the Y direction, or both in the Cartesian coordinate system shown in the drawings.

[0023] Figure 1 is a schematic vertical cross-sectional view of a semiconductor integrated circuit device including a stacked complementary transistor structure according to an exemplary embodiment of the present disclosure. In particular, Figure 1 is a schematic vertical cross-sectional view (XZ plane) of a semiconductor integrated circuit device 100 including a stacked complementary transistor structure (e.g., a stacked complementary FET structure) including a first transistor 101 (e.g., a first FET device) and a second transistor (e.g., a second FET device) positioned on the first transistor 101. In some embodiments, the first transistor 101 includes a PFET device, and the second transistor 102 includes an NFET device. In some embodiments, as shown in Figure 1, the first and second transistors 101 and 102 include nanosheet FET devices.

[0024] In particular, in the exemplary embodiment shown in Figure 1, the first transistor 101 includes a nanosheet FET device comprising a plurality of active nanosheet channel layers 112 and 114, a first source / drain element 160-1, and a second source / drain element 160-2. The second transistor 102 includes a nanosheet FET device comprising a plurality of active nanosheet channel layers 122 and 124, a first source / drain element 162-1, and a second source / drain element 162-2. The term “source / drain element” as used herein should be understood to mean that a given source / drain element can be either the source element or the drain element of a given FET device, depending on the application or circuit configuration.

[0025] In addition, the first and second transistors 101 and 102 include a common gate structure including gate sidewall spacers 135 and 136 and a metal gate 180. In some embodiments, the metal gate 180 includes a high-k metal gate (HKMG) structure. The gate sidewall spacers 134 and 136 define a common gate region of the first and second transistors 101 and 102 that surrounds / accompanies the metal gate 180. The gate sidewall spacer 134 acts to electrically isolate the metal gate 180 from surrounding elements, and the gate sidewall spacer 136 includes an embedded gate sidewall spacer (or internal spacer) formed between the edges of the active nanosheet channel layers 112, 114, 122 and 124, and acts to isolate the metal gate 180 from the source / drain elements 160-1, 160-2, 162-1 and 162-2. The metal gate 180 provides the gate length (L) of the first and second transistors 101 and 102. G The active nanosheet channel layers 112, 114, 122, and 124 define the gate length L, which seals the active nanosheet channel layers 112, 114, 122, and 124. G It is physically longer (length L) than [the other transistor]. The first and second transistors 101 and 102 are isolated by a dielectric isolation layer 150.

[0026] The semiconductor integrated circuit device 100 further includes a shallow trench isolation (STI) layer 140, a dielectric liner layer 170, a first insulating layer 175 (or a first interlayer insulation (ILD) layer), a second insulating layer 176 (or a second ILD layer), a gate contact 190, source / drain contacts 191, 192 and 193, a first interconnect structure 200 (e.g., a BEOL interconnect structure), a backside insulating layer 205, and a second interconnect structure 210 (e.g., a backside power distribution network). The gate contact 190 provides a connection between the metal gate 180 and the first interconnect 200. Source / drain contact 191 is commonly connected to the first source / drain elements 160-1 and 162-1 of the first and second transistors 101 and 102, providing a common connection between the first interconnect structure 200 and the source / drain elements 160-1 and 162-1 of the first and second transistors 101 and 102. Source / drain contact 192 provides a connection between the first interconnect structure 200 and the second source / drain element 162-2 of the second transistor 102. Source / drain contact 193 provides a connection between the second source / drain element 160-2 of the first transistor 101 and the second interconnect structure 210. In some embodiments, the first interconnect structure 200 includes a BEOL interconnect structure that includes a front-side I / O signaling network and a power distribution network. In some embodiments, the second interconnect structure 210 includes a backside power distribution network. In some embodiments, the second interconnect structure 210 includes both a backside I / O signaling network and a power distribution network.

[0027] In an exemplary embodiment, Figure 1 schematically shows a complementary inverter cell (alternatively, a CMOS inverter cell). For example, assuming that the first transistor 101 is a PFET and the second transistor 102 is an NFET, the first source / drain elements 160-1 and 162-1 are the drain elements for the first and second transistors 101 and 102, and the second source / drain elements 160-2 and 162-2 are the source elements for the first and second transistors 101 and 102. In this example, the gate contact 190 provides an input terminal to the CMOS inverter, and the source / drain contact 191 provides an output terminal of the CMOS inverter that is commonly connected to the source / drain elements 160-1 and 162-1 (e.g., the drain terminals), forming the output node of the CMOS inverter. Furthermore, the source / drain contact 192 connects the second source / drain element 162-2 (e.g., source terminal) of the second transistor 102 to the negative power supply voltage VSS (e.g., ground (GND) voltage) supplied by the power distribution network of the first interconnect structure 200, and the backside source / drain contact 193 connects the second source / drain element 160-2 (e.g., source terminal) of the first transistor 101 to the positive power supply voltage VDD supplied by the power distribution network of the second interconnect structure 210.

[0028] In another embodiment of the CMOS inverter cell, the first transistor 101 is an NFET and the second transistor 102 is a PFET. In this example, the source / drain contact 192 connects the second source / drain element 162-2 (e.g., source terminal) of the second transistor 102 to the positive power supply voltage VDD supplied by the power distribution network of the first interconnect structure 200, and the backside source / drain contact 193 connects the second source / drain element 160-2 (e.g., source terminal) of the first transistor 101 to the negative power supply voltage VSS (e.g., GND) supplied by the backside power distribution network of the second interconnect structure 210.

[0029] The exemplary stacked complementary transistor architecture shown in Figure 1 offers several advantages over conventional structures. For example, the exemplary stacked complementary transistor structure shown in Figure 1 provides a reduction in CMOS cell size by forming a backside source / drain contact (e.g., source / drain contact 193) to the source / drain element of the first transistor 101 for connection to the second interconnect structure 210, and a frontside source / drain contact to the source / drain element of the second transistor 102 for connection to the first interconnect structure 200. This configuration allows for longitudinal alignment of separate source / drain contacts for the respective first source / drain elements 160-1 and 162-1 of the stacked first and second transistors 101 and 102, or for the respective second source / drain elements 160-2 and 162-2 of the stacked first and second transistors 101 and 102, or both. For example, in the exemplary embodiment shown in Figure 1, the second source / drain element 160-2 of the first transistor 101 is connected to the second interconnect structure 210 by a source / drain contact 193, thereby allowing the source / drain contact 193 to be aligned longitudinally with the source / drain contact 192 (for example, vertically aligned in the Z direction). For illustrative purposes, dashed lines are shown in Figure 1 to represent an exemplary state of longitudinal alignment of the source / drain contacts 192 and 193.

[0030] In contrast, in conventional stacked CMOS cells that do not implement the second (backside) interconnect structure 210, the lateral size of the second source / drain element 160-2 of the first transistor 101 must be increased (in the X direction) to provide a landing area to enable the connection of source / drain contacts extending from the first interconnect structure 200 to the second source / drain element 160-2. This conventional configuration increases the CMOS cell size as a result of the increased lateral size of the second source / drain element 160-2, which is required to (i) provide sufficient contact area for source / drain contacts extending from the first interconnect structure 200, and (ii) ensure that there is sufficient lateral spacing between adjacent source / drain contacts that extend downward from the first interconnect structure 200 and connect to the respective second source / drain elements 160-2 and 162-2 of the stacked first and second transistors 101 and 102.

[0031] Another advantage provided by the exemplary multilayer complementary transistor architecture in Figure 1 is that the formation of the backside insulating layer 205 eliminates the need to implement a dedicated fabrication module to isolate the multilayer complementary transistor structure from the semiconductor substrate. As will be described in more detail below, the fabrication module for forming the backside insulating layer 205 and the second interconnect structure 210 involves backside removal of the portion of the semiconductor substrate that is in contact with the multilayer complementary transistor structure, thereby naturally obtaining isolation between the semiconductor substrate and the multilayer complementary transistor structure.

[0032] Furthermore, the exemplary architecture of the stacked complementary transistor structure shown in Figure 1 provides enhanced device performance due to the extension portions 160E of the first and second source / drain elements 160-1 and 160-2 of the first transistor 101, which extend below the lower surface of the gate structure. In some embodiments, as will be described in more detail below, the first and second source / drain elements 160-1 and 160-2 of the first transistor 101 include epitaxial source / drain elements that are epitaxially grown bottom-up, starting at the bottom of a trench formed in a crystalline semiconductor substrate. Subsequently, when the crystalline semiconductor substrate is removed, the extension portions 160E are essentially freed from the semiconductor substrate, thereby allowing the first and second source / drain elements 160-1 and 160-2 to strain the active nanosheet channel layers 112 and 114 of the first transistor 101.

[0033] For example, in the case of an NFET device, the first and second source / drain elements 160-1 and 160-2 apply tensile strain to the active nanosheet channel layers 112 and 114 of the first transistor 101, which enhances the performance of the NFET. Furthermore, in the case of a PFET device, the first and second source / drain elements 160-1 and 160-2 apply compressive strain to the active nanosheet channel layers 112 and 114 of the first transistor 101, which enhances the performance of the PFET device. In this regard, the extension portion 160E of the first and second source / drain elements 160-1 and 160-2 of the first transistor 101 allows for an increased size of the first and second source / drain elements 160-1 and 160-2 to enable increased strain without increasing the CMOS cell size.

[0034] Figures 2 to 17 schematically illustrate a method for manufacturing a semiconductor integrated circuit device including a stacked complementary transistor structure according to embodiments of the present invention. In particular, for illustrative purposes, Figures 2 to 16 schematically illustrate a method for manufacturing the semiconductor integrated circuit device 100 of Figure 1. First, Figure 2 is a schematic vertical cross-sectional view (XZ plane) of the initial device structure of a semiconductor integrated circuit device in the early stages of manufacturing, including a semiconductor substrate 105 and a nanosheet stacked structure 106 formed on the semiconductor substrate 105. The nanosheet stacked structure 106 includes a stack of epitaxial semiconductor layers, comprising a first nanosheet stack 110, a sacrificial nanosheet layer 116, and a second nanosheet stack 120.

[0035] While the semiconductor substrate 105 is shown as a general substrate layer, it should be understood that the semiconductor substrate 105 may include one of several different types of semiconductor substrate structures and materials. For example, in some embodiments, the semiconductor substrate 105 is a bulk semiconductor substrate (e.g., a wafer) formed from a crystalline semiconductor material, including, but not limited to, silicon (Si), germanium (Ge), or other types of semiconductor substrate materials commonly used in bulk semiconductor manufacturing processes, such as silicon (Si), germanium (Ge), or silicon-germanium alloys, compound semiconductor materials (e.g., Group III-V). In other embodiments, the semiconductor substrate 105 may be an SOI (silicon-on-insulator) substrate, a GeOI (germanium-on-insulator) substrate, or other types of semiconductor-on-insulator substrate, which includes an insulating layer (e.g., an oxide layer) placed between a base substrate layer (e.g., a silicon substrate) and an active semiconductor layer (e.g., Si, Ge, etc.) on which active circuit components are formed as part of a front-end-of-line (FEOL) structure. Note that in each figure, the XY plane represents a plane parallel to the plane of the semiconductor substrate 105 (e.g., wafer) being processed.

[0036] In an exemplary embodiment shown in Figure 2, the first nanosheet stack 110 includes a stack of alternately located epitaxial semiconductor layers 111, 112, 113, 114, and 115, which are used to form the first transistor 101 in Figure 1. The second nanosheet stack 120 includes a stack of alternately located epitaxial semiconductor layers 121, 122, 123, 124, and 125, which are used to form the second transistor 102 in Figure 1. A sacrificial nanosheet layer 116 includes a sacrificial layer that acts as a placeholder to enable the epitaxial growth of the second nanosheet stack 120 on the first nanosheet stack 110, but the sacrificial nanosheet layer 116 is later replaced with a dielectric material to form a dielectric isolation layer 150 between the first transistor 101 and the second transistor 102.

[0037] The laminate of alternating epitaxial semiconductor layers 111-115 of the first nanosheet laminate 110 includes sacrificial nanosheet layers 111, 113, and 115 and active nanosheet channel layers 112 and 114, each active nanosheet channel layer 112 and 114 positioned between the sacrificial nanosheet layers in the first nanosheet laminate 110. The laminate of alternating epitaxial semiconductor layers 121-125 of the second nanosheet laminate 120 includes sacrificial nanosheet layers 121, 123, and 125 and active nanosheet channel layers 122 and 124, each active nanosheet channel layer 122 and 124 positioned between the sacrificial nanosheet layers in the second nanosheet laminate 120. The epitaxial semiconductor layers of the nanosheet laminate structure 106 are then grown.

[0038] For example, the first nanosheet laminate 110 is formed by the following steps: a sacrificial nanosheet layer 111 is epitaxially grown on the surface of a semiconductor substrate 105; an active nanosheet channel layer 112 is epitaxially grown on the sacrificial nanosheet layer 111; a sacrificial nanosheet layer 113 is epitaxially grown on the active nanosheet channel layer 112; an active nanosheet channel layer 114 is epitaxially grown on the sacrificial nanosheet layer 113; and a sacrificial nanosheet layer 115 is epitaxially grown on the active nanosheet channel layer 114. Next, a sacrificial nanosheet layer 116 is epitaxially grown on the sacrificial nanosheet layer 115. The second nanosheet laminate 120 is formed by a process in which a sacrificial nanosheet layer 121 is epitaxially grown on a sacrificial nanosheet layer 116, an active nanosheet channel layer 122 is epitaxially grown on a sacrificial nanosheet layer 121, a sacrificial nanosheet layer 123 is epitaxially grown on an active nanosheet channel layer 122, an active nanosheet channel layer 124 is epitaxially grown on a sacrificial nanosheet layer 123, and a sacrificial nanosheet layer 125 is epitaxially grown on an active nanosheet channel layer 124.

[0039] In some embodiments, the epitaxial semiconductor layer of the nanosheet stacked structure 106 includes a single-crystal semiconductor material that is epitaxially grown using known methods such as chemical vapor deposition (CVD), metal-organic vapor deposition (MOCVD), reduced-pressure chemical vapor deposition (LPCVD), molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), metal-organic molecular beam epitaxy (MOMBE), rapid thermochemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), or other known epitaxial growth techniques suitable for a given process.

[0040] The type of material used to form the epitaxial semiconductor layers 111-115 of the first nanosheet stack 110 and the epitaxial semiconductor layers 121-125 of the second nanosheet stack 120 depends on various factors, such as the type of nanosheet FET device (p-type or n-type), the desired level of etch selectivity between the semiconductor layers, and providing sufficient lattice matching between the semiconductor layer materials to ensure proper (e.g., defect-free) epitaxial growth of the crystalline semiconductor layer.

[0041] For example, in some embodiments, the active nanosheet channel layers 112 and 114 of the first nanosheet laminate 110 and the active nanosheet channel layers 122 and 124 of the second nanosheet laminate 120 are formed from epitaxial silicon (or crystalline Si). In some embodiments, the active nanosheet channel layers 112 and 114 of the first nanosheet laminate 110 can be doped to adjust a desired threshold voltage of the first transistor 101, and the active nanosheet channel layers 122 and 124 of the second nanosheet laminate 120 can be doped to adjust a desired threshold voltage of the second transistor 102.

[0042] When the active nanosheet channel layers 112, 114, 122, and 124 are formed from crystalline Si, the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 (which function as sacrificial layers that are later etched away to "release" the active nanosheet channel layers 112, 114, 122, and 124) can be formed from an epitaxial silicon-germanium (SiGe) alloy. This allows the epitaxial SiGe material of the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 to be selectively etched against the epitaxial Si material of the active nanosheet channel layers 112, 114, 122, and 124 in subsequent steps to "release" the active nanosheet channel layers 112, 114, 122, and 124. In other embodiments, the active nanosheet channel layers 112, 114, 122, and 124 can be formed from an epitaxial SiGe material at a desired Ge concentration (optimized for device performance), and the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 can be formed from a sacrificial semiconductor material (e.g., Si) that can be selectively etched relative to the active nanosheet channel layers 112, 114, 122, and 124. While the first and second nanosheet stacks 110 and 120 are shown to include two active nanosheet channel layers 112 and 114, as well as 122 and 124, in other embodiments of the present invention, the first and second nanosheet stacks 110 and 120 can be manufactured using three or more active nanosheet channel layers.

[0043] The sacrificial nanosheet layer 116 is formed from an epitaxial semiconductor material that can be selectively etched against the epitaxial semiconductor material of the active nanosheet channel layers 112, 114, 122, and 124, as well as the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125. For example, in an embodiment in which the active nanosheet channel layers 112, 114, 122, and 124 are formed from an epitaxial silicon material and the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 are formed from an epitaxial SiGe alloy, the sacrificial nanosheet layer 116 can be formed from an epitaxial SiGe alloy material having a Ge concentration different from that of the epitaxial SiGe alloy material of the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125. For example, the epitaxial SiGe alloy material of sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 can have a Ge concentration of 25%, while the epitaxial SiGe alloy material of sacrificial nanosheet layer 116 can have a Ge concentration of 50%, which provides etch selectivity for sacrificial nanosheet layer 116 with respect to sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125.

[0044] The thickness of the sacrificial nanosheet layer 116 is selected based on the desired target thickness for the dielectric isolation layer 150 between the first transistor 101 and the second transistor 102, which is formed later to replace the sacrificial nanosheet layer 116. Furthermore, the thicknesses of the sacrificial nanosheet layers 111, 113, and 115 of the first nanosheet laminate 110 define the spacing (or channel spacing) above and below the active nanosheet channel layers 112 and 114, on which the high-k dielectric material and work function metal are later formed. Similarly, the thicknesses of the sacrificial nanosheet layers 121, 123, and 125 of the second nanosheet laminate 120 define the spacing (or channel spacing) above and below the active nanosheet channel layers 122 and 124, on which the high-k dielectric material and work function metal are later formed. The spacing size and type of the work function material placed in the spaces above and below the active nanosheet channel layers 112 and 114, as well as 122 and 124, partially define the threshold voltage (Vt) of the first and second (nanosheet FET) transistors 101 and 102. In some embodiments, the thicknesses of the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 are in the range of about 6 nm to about 10 nm.

[0045] Next, Figures 3A, 3B, and 3C are schematic diagrams of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by patterning the nanosheet laminate structure 106 of Figure 2 to form a patterned nanosheet laminate structure according to an exemplary embodiment of the present disclosure, and by forming a shallow trench isolation (STI) layer on a semiconductor substrate 105. More specifically, Figures 3A, 3B, and 3C show the gate widths W of the first and second transistors 101 and 102. GFigure 3A schematically shows the next step in the manufacturing process in which the nanosheet laminate structure 106 of Figure 2 is patterned to form a patterned nanosheet laminate structure 106-1 that defines the STI layer 140 formed on the semiconductor substrate 105. Figure 3A is a schematic plan view (XY plane) of the intermediate semiconductor structure, Figure 3B is a schematic vertical cross-sectional view (XZ plane) of the intermediate semiconductor structure along the line 3B-3B shown in Figure 3A, and Figure 3C is a schematic vertical cross-sectional view (YZ plane) of the intermediate semiconductor structure along the line 3C-3C shown in Figure 3A.

[0046] As shown in Figures 3A, 3B, and 3C, the patterning of the nanosheet stack structure 106 (Figure 2) is such that the gate width W of the active nanosheet channel layers 112, 114, 122, and 124 of the first and second transistors 101 and 102 G The width that defines the gate structure and the laminate length L that defines the overall target length of the gate structure and the source / drain (S / D) region formed on opposite sides of the gate structure. S This results in the formation of a patterned nanosheet laminate structure 106-1 having the gate width W. G The thickness of the active nanosheet channel layers 112, 114, 122, and 124 of the first and second transistors 101 and 102 is greater (e.g., more than twice as much).

[0047] In some embodiments, the patterning process is performed by forming an etch mask (e.g., a lithography mask or a hard mask) on the nanosheet laminate structure 106 (Figure 2), the etch mask containing an image of the patterned nanosheet laminate structure 106-1 and STI trenches formed on the upper surface of the semiconductor substrate 105. The nanosheet laminate structure 106 and the semiconductor substrate 105 are then etched using one or more dry etching (e.g., reactive ion etching (RIE)) sequences to completely etch the layers of the nanosheet laminate structure 106 (to form the patterned nanosheet laminate structure 106-1) and then etch into the semiconductor substrate 105 to form STI trenches around the patterned nanosheet laminate structure 106-1. The etch mask can be formed using any suitable patterning process, including, but not limited to, photolithography processes, or multi-patterning processes such as sidewall image transfer (SIT), self-aligning double patterning (SADP), and self-aligning quadruple patterning (SAQP). Etching can be performed using one or more consecutive dry etch processes with etch chemicals suitable for etching the materials of the epitaxial semiconductor layer of the nanosheet laminate structure 106 and the semiconductor substrate 105.

[0048] As shown in Figures 3B and 3C, the etch process results in the formation of STI trenches to a depth D on the upper surfaces of the patterned nanosheet laminate 106-1 and the semiconductor substrate 105. The STI trenches are filled with insulating material to form an STI layer 140. For example, in some embodiments, the STI layer 140 is formed by a process that includes depositing a layer of insulating material on the surface of the semiconductor structure to cover the patterned nanosheet laminate 106-1, planarizing the surface of the semiconductor structure (by chemical mechanical polishing (CMP)) up to the upper surface of the patterned nanosheet laminate 106-1 to remove excess insulating material, and then performing an etch-back (or recess) process to recess the remaining layer of insulating material up to the upper surface of the semiconductor substrate 105 to form the STI layer 140. The STI layer 140 can be formed from any type of insulating material, such as silicon oxide material, or a combination of multiple insulating materials, such as forming a silicon oxide fill after forming a silicon nitride liner. The insulating material is deposited and patterned using known techniques.

[0049] Figures 4A, 4B, and 4C are schematic diagrams of the next intermediate structure of a semiconductor integrated circuit device, comprising forming a dummy gate structure covering a portion of a patterned nanosheet stack structure 106-1 according to exemplary embodiments of the present disclosure, and patterning the exposed portion of the patterned nanosheet stack structure 106-1 in the source / drain region adjacent to the dummy gate structure to form first and second nanosheet channel structures 110-1 and 120-1, respectively, for first and second transistors 101 and 102. Specifically, Figure 4A is a schematic plan view (XY plane) of the intermediate device structure, Figure 4B is a schematic vertical cross-sectional view (XZ plane) of the intermediate device structure along line 4B-4B shown in Figure 4A, and Figure 4C is a schematic vertical cross-sectional view (YZ plane) of the resulting semiconductor structure along line 4C-4C shown in Figure 4A.

[0050] As shown in Figures 4A, 4B, and 4C, the gate structure includes a dummy gate 130 (e.g., a conformal oxide layer) and a dummy gate electrode layer (e.g., a sacrificial polysilicon or amorphous silicon material). In addition, the gate structure includes a gate capping layer 132 and a gate sidewall spacer 134. In some embodiments, the dummy gate 130 includes a conformal dummy gate oxide layer and a dummy gate electrode layer (e.g., a sacrificial polysilicon or amorphous silicon material). As will be described in more detail below, the dummy gate 130 is then removed as part of a substitution metal gate (RMG) process and replaced with a high-k gate dielectric material and a metallic material to form a common HKMG gate structure for the first and second transistors 101 and 102.

[0051] The semiconductor device structures shown in Figures 4A, 4B, and 4C are manufactured using known methods. For example, a thin conformal layer of silicon oxide is deposited across the entire surface of the semiconductor structures shown in Figures 3A, 3B, and 3C, and a layer of polysilicon (or alternatively, amorphous silicon) is blanket-deposited on the conformal layer of silicon oxide and then planarized using known techniques. A hard mask layer is formed on the planarized surface of the polysilicon layer by depositing one layer or multiple layers of dielectric material (e.g., SiN, SiOCN, SiBCN). The hard mask layer is then patterned to form a gate-capping layer 132 that defines the image of the gate structure. The gate-capping layer 132 is then used as an etch hard mask to anisotropically etch (e.g., RIE) the sacrificial polysilicon and oxide layers, thereby forming a dummy gate 130.

[0052] Next, the gate sidewall spacer 134 is formed by depositing a conformal layer of dielectric material onto the entire surface of the semiconductor structure. The conformal layer of dielectric material is formed from SiN, SiBCN, SiOCN, or any other type of low-k dielectric material commonly used to form insulating gate sidewall spacers in FET devices, and can be deposited using known techniques such as atomic layer deposition (ALD), CVD, and PVD. The conformal layer of dielectric material is then patterned by performing an anisotropic dry etch process such as RIE to etch the conformal layer of dielectric material in the perpendicular direction (Z direction). This etch process is performed selectively on the semiconductor material of the patterned nanosheet laminate structure 106-1 and the STI layer 140. The etch process results in the formation of a gate sidewall spacer surrounding the dummy gate 130 and the gate capping layer 132, as shown in Figures 4A-4C. The gate sidewall spacer 134 defines the gate region of the nanosheet FET device.

[0053] After forming the gate sidewall spacer 134, an anisotropic dry etch process (e.g., RIE) is performed to etch the exposed portion of the patterned nanosheet stack structure 106-1 in the source / drain region adjacent to the gate structure up to the upper surface of the semiconductor substrate 105 and the STI layer 140. As shown in Figures 4A and 4B, the etch process results in (i) the formation of the first and second nanosheet channel structures 110-1 and 120-1 of the first and second transistors 101 and 102, respectively, and (ii) the exposure of a portion of the semiconductor substrate 105 in the S / D region. The first and second nanosheet channel structures 110-1 and 120-1 are formed with a predetermined length L in the X direction (see Figures 4A and 4B). The gate width W in the Y direction of the resulting first and second nanosheet channel structures 110-1 and 120-1 G (See Figures 4A and 4C) is maintained because the gate width W GThis is because the sidewalls of the patterned nanosheet laminate structure 106-1 that defines the structure are covered with dummy gates 130 and gate sidewall spacers 134 (see, for example, Figure 4C) during the etching process.

[0054] The next step in the manufacturing process involves replacing the remainder of the sacrificial nanosheet layer 116, which is positioned between the first nanosheet channel structure 110-1 and the second nanosheet channel structure 120-1 (see Figures 4B and 4C), with a dielectric isolation layer 150 that isolates the first and second transistors 101 and 102. In particular, Figure 5 is a schematic vertical cross-sectional view of the next intermediate structure of the semiconductor integrated circuit device structure, which is constructed by replacing the remainder of the sacrificial nanosheet layer 116 with a dielectric isolation layer 150 that isolates the stacked first and second transistors 101 and 102, according to an exemplary embodiment of the present disclosure.

[0055] In some embodiments, the remainder of the sacrificial nanosheet layer 116 is removed by performing an etching process configured to be selective to the materials of the surrounding structures / elements, including the semiconductor substrate 105, the STI layer 140, the gate capping layer 132, the gate sidewall spacer 134, and the epitaxial semiconductor layers of the first and second nanosheet channel structures 110-1 and 120-1. As described above, in some embodiments, the sacrificial nanosheet layer 116 is formed from a SiGe alloy having a Ge concentration of 50% Ge, which can be etched very selectively to the epitaxial semiconductor material of the first and second nanosheet channel structures 110-1 and 120-1, for example. In some embodiments, the sacrificial nanosheet layer 116 is removed using a dry etching process that uses an appropriate etching gas to selectively etch the material of the sacrificial nanosheet layer 116. Next, the dielectric isolation layer 150 is formed by depositing a conformal layer of a dielectric material such as silicon nitride to fill the space between the first nanosheet channel structure 110-1 and the second nanosheet channel structure 120-1, and then performing an etch-back process to remove excess dielectric material.

[0056] Next, Figure 6 is a schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by laterally recessing the exposed sidewall surfaces of the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 of the first and second nanosheet channel structures 110-1 and 120-1 to form recesses R in the sidewalls of the first and second nanosheet channel structures 110-1 and 120-1. As shown in Figure 6, the exposed sidewall surfaces of the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 are recessed (in the X direction) to a recess depth R. In some embodiments, the depth of the lateral recess R is controlled by timed etching. For example, in some embodiments, the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 are recessed to a depth defined by the thickness of the gate sidewall spacer 134.

[0057] In some embodiments, the lateral etching process can be performed using an isotropic wet etching process with an etching solution suitable for selectively etching the semiconductor material (e.g., SiGe) of the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 with respect to the semiconductor material (e.g., Si) of the active nanosheet channel layers 112, 114, 122, and 124 and other exposed elements. In some embodiments, an isotropic dry plasma etching process can be performed to selectively laterally etch the exposed sidewalls of the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 with respect to the active nanosheet channel layers 112, 114, 122, and 124 and other exposed elements.

[0058] The next step in the manufacturing process includes forming embedded gate sidewall spacers 136 within recesses R in the sidewalls of the first and second nanosheet channel structures 110-1 and 120-1. For example, Figure 7 is a schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, configured by forming embedded gate sidewall spacers 136 within recesses R in the sidewalls of the first and second nanosheet channel structures, according to an exemplary embodiment of the present disclosure. In some embodiments, the embedded gate sidewall spacers 136 are formed from the same dielectric material used to form the gate sidewall spacers 134. For example, the embedded gate sidewall spacers 136 can be formed from SiN, SiBCN, SiCO, SiCON, or any other type of dielectric material used to form the gate sidewall spacers 134 of the gate structure (e.g., a low-k dielectric material having k less than 5, where k is the relative permittivity).

[0059] In some embodiments, the embedded gate sidewall spacer 136 is formed by depositing a conformal layer of dielectric material onto the intermediate device structure in Figure 6 until the recess R is filled with dielectric material, and then etching back to remove excess dielectric material from the gate structure and substrate. The dielectric material is deposited using a highly conformal deposition process such as ALD to ensure that the recess R is sufficiently filled with dielectric material. The conformal layer of dielectric material can be etched back using an isotropic (wet or dry) etch process to remove excess dielectric material while leaving dielectric material in the recess R to form the embedded gate sidewall spacer 136. The wet etch process may include, but is not limited to, buffered hydrofluoric acid (BHF), diluted hydrofluoric acid (DHF), nitrohydrofluoric acid (HNA), phosphoric acid, HF diluted with ethylene glycol, hydrochloric acid (HCl), or any combination thereof.

[0060] Next, Figure 8 is a schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by recessing an exposed portion of the semiconductor substrate 105 in the S / D region to form a first trench 105-1 and a second trench 105-2 in the semiconductor substrate 105, according to an exemplary embodiment of the present disclosure. The first and second trenches 105-1 and 105-2 are formed to allow the formation of extensions (Figure 1) of the first and second source / drain elements 160-1 and 160-2 of the first transistor 101 that extend below the bottom surface of the gate structure. As shown in Figure 8, the bottom surfaces of the first and second trenches 105-1 and 105-2 are formed to allow epitaxial growth of the first and second source / drain elements 160-1 and 160-2 of the first transistor 101, for example, as schematically shown in Figure 9. <100> A crystalline silicon surface is provided.

[0061] In particular, Figure 9 is a schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by epitaxially growing the first and second source / drain elements 160-1 and 160-2 of the first transistor 101, starting from the bottom of the first and second trenches in a semiconductor substrate 105, according to an exemplary embodiment of the present disclosure. The first and second source / drain elements 160-1 and 160-2 of the first transistor 101 are exposed at the bottom of the first and second trenches 105-1 and 105-2. <100> It is formed by epitaxial growth of semiconductor material from a bottom-up approach starting on a crystalline semiconductor surface. In this process, the epitaxial process is <100> The growth rate of the epitaxial material on the surface of the crystal plane (starting from the bottom of the first and second trenches 105-1 and 105-2 of the semiconductor substrate 105) is <110> The growth rate of epitaxial material on the exposed sides of the crystal-plane-oriented active nanosheet channel layers 112, 114, 122, and 124 is configured to be greater than the growth rate of epitaxial material on the exposed sides of the crystal-plane-oriented active nanosheet channel layers 112, 114, 122, and 124. In this process, the recessed substrate surface at the bottom of the first and second trenches 105-1 and 105-2 is used to seed the growth of epitaxial material forming the first and second source / drain elements 160-1 and 160-2. <110> The epitaxial semiconductor material that provides the semiconductor surface and onto which it is deposited adopts the same lattice structure and orientation as the crystalline seed plane.

[0062] The first and second source / drain elements 160-1 and 160-2 can be epitaxially grown using known methods such as CVD, MOCVD, LPCVD, MBE, VPE, LPE, MOMBE, RTCVD, LEPD, UHVCVD, APCVD, or other known epitaxial growth techniques suitable for a given process. The type of epitaxial semiconductor material used to form the first and second source / drain elements 160-1 and 160-2 depends on whether the first transistor 101 is an NFET or a PFET. For example, if the first transistor 101 is a P-type FET device, and the active nanosheet channel layers 112 and 114 are formed from epitaxial Si, then the first and second source / drain elements 160-1 and 160-2 can be formed from epitaxial SiGe material (having a relatively high Ge concentration), boron-doped SiGe (B:SiGe), or other suitable epitaxial material. On the other hand, if the first transistor 101 is an N-type FET device, and the active nanosheet channel layers 112 and 114 are formed from epitaxial Si, then the first and second source / drain elements 160-1 and 160-2 can be formed from carbon-doped silicon (Si:C) epitaxial material, phosphorus-doped silicon (Si:P) epitaxial material, or other suitable epitaxial material.

[0063] The first and second source / drain elements 160-1 and 160-2 can be doped using known techniques. For example, in some embodiments, the first and second source / drain elements 160-1 and 160-2 are doped "in situ" during the epitaxial growth process by adding a dopant gas to the source deposition gas (i.e., a Si-containing or Ge-containing or both source gas). Exemplary dopant gases may include boron (B) or gallium (Ge)-containing gases for P-type FETs, or phosphorus (P) or arsenic (As)-containing gases for N-type FETs (e.g., PH3 or AsH3), where the concentration of the impurity in the gas phase determines its concentration in the semiconductor material being epitaxially grown. In other embodiments, an "ex-situ" process may be performed to add the dopant to the first and second source / drain elements 160-1 and 160-2. For example, “extra-in-situ” processes can be carried out by ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid-phase doping, solid-phase doping, or any suitable combination of these techniques.

[0064] Furthermore, in some embodiments, a thermal annealing process is performed after the epitaxial growth and doping of the first and second source / drain elements 160-1 and 160-2 to inject dopants into the edges of the active nanosheet channel layers 112 and 114 that contact the epitaxial semiconductor material of the first and second source / drain elements 160-1 and 160-2. As a result of the annealing process, the first and second source / drain elements 160-1 and 160-2 are effectively extended into the semiconductor material at the edges of the active nanosheet channel layers 112 and 114, thereby reducing the parasitic resistance of the nanosheet FET device. In other embodiments, the thermal annealing process is performed at a later stage (e.g., after the formation of the high-k dielectric layer) so that the same annealing process can serve two purposes simultaneously, namely, to drive dopants into the nanosheet layer and to improve the reliability of the high-k gate dielectric.

[0065] Next, Figure 10 is a schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by depositing and patterning conformal layers of dielectric material to form a dielectric liner layer 170 on the first and second source / drain elements 160-1 and 16-2 of the first transistor 101, according to an exemplary embodiment of the present disclosure. The dielectric liner layer 170 is formed to protect the first and second source / drain elements 160-1 and 160-2 of the first transistor 101 during a subsequent epitaxial process for growing the first and second source / drain elements 162-1 and 162-1 of the second transistor 102. In some embodiments, the dielectric liner layer 170 is formed by a process that includes depositing a conformal layer of dielectric material on the intermediate structure shown in Figure 9, and patterning the conformal layer of dielectric material to remove the dielectric material from the sidewalls of the second nanosheet channel structure 120-2, thereby exposing the edges of the active nanosheet channel layers 122 and 124.

[0066] In some embodiments, the dielectric liner layer 170 is formed from a dielectric material such as SiOC, SiCN, SiN, or SiBCN, which has etch selectivity for the dielectric material of the gate capping layer 132 and gate sidewall spacer 134, for example. The conformal layer of the dielectric material is deposited using any suitable deposition method. Following the conformal deposition process, a planarization layer 172 (e.g., an organic planarization layer (OPL)) is deposited and then recessed to a level between the upper and lower surfaces of the dielectric isolation layer 150, as shown in Figure 10, in order to expose the conformal dielectric layer on the recessed surface 172-1 of the planarization layer 172. Next, an etching process is performed to selectively etch the exposed portion of the conformal dielectric layer, thereby forming a patterned dielectric liner layer 170 and exposing the edges of the active nanosheet channel layers 122 and 124 of the second nanosheet channel structure 120-2.

[0067] Figure 11 is a schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, comprising epitaxial growth of first and second source / drain elements 162-1 and 162-2 of a second transistor 102 and the formation of a first insulating layer 175 (e.g., a first ILD layer 175) to encapsulate the stacked complementary transistor structure, according to exemplary embodiments of the present disclosure. In some embodiments, the planarization layer 172 is removed before epitaxial growth of the first and second source / drain elements 162-1 and 162-2. The first and second source / drain elements 162-1 and 162-2 are formed by epitaxially growing a semiconductor material (e.g., epitaxial Si material, SiGe material, carbon-doped silicon (Si:C) material, etc.) on the exposed sidewalls of the active nanosheet channel layers 122 and 124 using the same or similar materials and techniques described above for forming the first and second source / drain elements 160-1 and 160-2 of the first transistor 101. In this process, the exposed sidewalls of the active nanosheet channel layers 122 and 124 provide a surface area for seeding the epitaxial growth of the source / drain elements 162-1 and 162-2. As described above, the type of epitaxial semiconductor material used to form the source / drain elements 162-1 and 162-2 varies, for example, depending on the device type of the second transistor 102 (e.g., N-type or P-type). In some embodiments, the epitaxial growth of the semiconductor material is carried out so that the epitaxial material fuses (in the Z direction) to form source / drain elements 162-1 and 162-2.

[0068] After the formation of the first and second source / drain elements 162-1 and 162-2 of the second transistor 102, the process continues by forming a first ILD layer 175 in dielectric / insulating material to seal the stacked complementary transistor structure before initiating the substitution metal gate process. In some embodiments, the ILD layer 175 is formed by depositing a blanket layer of dielectric / insulating material on the semiconductor structure and planarizing the layer of dielectric / insulating material up to the gate capping layer 132 to form the first ILD layer 175, as schematically shown in Figure 11.

[0069] The first ILD layer 175 may include, but is not limited to, any suitable insulating / dielectric material commonly used in semiconductor process technology, including silicon oxide, silicon nitride, silicon oxynitride, SiCOH, SiCH, SiCNH, or other types of silicon-based low-k dielectrics (e.g., less than about 4.0 k), porous dielectrics, known ULK (ultra-low-k) dielectric materials (having less than about 2.5 k), or any suitable combination of these materials. The dielectric / dielectric material of the ILD layer 175 is deposited using known deposition techniques such as ALD, CVD, PECVD, PVD, or spin-on deposition. In some embodiments, the dielectric / dielectric material layer is planarized using a standard planarization process such as CMP to remove excess dielectric / dielectric material up to the top surface of the gate capping layer 132. In some embodiments, a conformal layer of dielectric material (e.g., SiN) is deposited (before the insulating material of the ILD layer 175) to form a protective liner layer covering the first and second source / drain elements 162-1 and 162-2, before the insulating material of the ILD layer 175 is blanket-deposited.

[0070] After the formation of the ILD layer 175, a substitution metal gate process is performed to replace the dummy gate 130 with a metal gate 180 (e.g., an HKMG structure) using steps schematically shown in Figures 12A, 12B, 13A, and 13B. For example, Figures 12A and 12B are schematic vertical cross-sectional views of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by removing the dummy gate 130 and removing the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 to free the active nanosheet channel layers 112, 114, 122, and 124 and form an open gate region 130-1, according to exemplary embodiments of the present disclosure. Figure 12A is a schematic vertical cross-sectional view (XZ plane) of the resulting intermediate structure, and Figure 12B is a schematic vertical cross-sectional view (YZ plane) of the resulting semiconductor structure along the line 12B-12B shown in Figure 12A.

[0071] In some embodiments, the dummy gate 130 is removed using a process that includes removing the gate capping layer 132 to expose the dummy gate 130 and performing a plurality of etch processes to remove the dummy gate 130. More specifically, in some embodiments, the gate capping layer 132 is removed by planarizing the surface of the semiconductor structure up to the top surface of the dummy gate 130 (e.g., by CMP). In other embodiments, the dielectric material of the gate capping layer 132 (e.g., SiN) can be selectively etched against the material of the gate sidewall spacer 134 (e.g., SiBCN) and the material of the ILD layer 175 (e.g., silicon oxide) to expose the underlying dummy gate 130. As described above, in some embodiments in which the dummy gate 130 includes a dummy gate electrode layer (e.g., a sacrificial polysilicon layer or an amorphous silicon layer) and a dummy gate oxide layer, the dummy gate electrode and gate oxide layer are etched using known etching techniques and etch chemicals.

[0072] For example, the sacrificial polysilicon material of the gate electrode layer can be removed using a selective dry-etch or wet-etch process with a suitable etch chemical including ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), or SF6 plasma. Etching of the dummy poly-gate layer is selective to, for example, the dummy gate oxide layer, thereby protecting the active nanosheet channel layers 112, 114, 122, and 124 from etching during the poly-etch process. After the polysilicon material has been removed, an oxide-etch process is performed to etch the dummy gate oxide layer selectively to the active nanosheet channel layers 112, 114, 122, and 124. In this way, the sacrificial material of the dummy gate 130 (e.g., dummy polysilicon and oxide layers) can be etched without damaging the active nanosheet channel layers 112, 114, 122, and 124.

[0073] After removing the dummy gate 130, an etching process is performed to selectively etch the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125, freeing the active nanosheet channel layers 112, 114, 122, and 124 of the first and second nanosheet channel structures 110-1 and 120-1, thereby extending the open gate region 130-1 into the space between and adjacent to the active nanosheet channel layers 112, 114, 122, and 124. The sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 (e.g., epitaxial SiGe layers) can be selectively etched relative to the active nanosheet channel layers 112, 114, 122, and 124 (e.g., epitaxial Si layers). In some embodiments, the SiGe material of the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 is selectively etched (by high etch selectivity) using a wet etching solution containing gas-phase HCl (hydrochloric acid) or hydrogen peroxide (H2O2), thereby selectively etching the SiGe material of the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125 relative to the Si material of the active nanosheet channel layers 112, 114, 122, and 124. For example, if the active nanosheet channel layers 112, 114, 122, and 124 are formed from epitaxial Si or epitaxial SiGe having a lower Ge concentration than the epitaxial SiGe material of the sacrificial nanosheet layers 111, 113, 115, 121, 123, and 125, gas-phase HCl (hydrochloric acid) provides high etch selectivity.

[0074] Next, Figures 13A and 13B are schematic vertical cross-sectional views of the next intermediate structure of a semiconductor integrated circuit device, formed by forming a metal gate 180 and a second ILD layer 176, according to exemplary embodiments of the present disclosure. Figure 13A is a schematic vertical cross-sectional view (XZ plane) of the resulting intermediate structure, and Figure 13B is a schematic vertical cross-sectional view (YZ plane) of the resulting semiconductor structure along the line 13B-13B shown in Figure 13A. In some embodiments, the metal gate 180 includes an HKMG structure formed by a process comprising: (i) depositing one or more conformal layers of high-k gate dielectric material on an exposed surface of a semiconductor structure to conformally cover the surfaces of active nanosheet channel layers 112, 114, 122, and 124; and (ii) depositing one or more layers of work function metal to cover the high-k dielectric, fill the reaming space in the open gate region 130-1, and form a metal gate electrode layer.

[0075] In some embodiments, the high-k dielectric layer is preferably formed from a high-k dielectric material having a dielectric constant of about 3.9 or higher. For example, the gate dielectric material may include, but is not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconium oxide, and nitride films thereof. In other embodiments, the high-k dielectric may include lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k dielectric material may further include dopants such as lanthanum and aluminum. In one embodiment of the present invention, the conformal high-k gate dielectric layer is formed with a thickness in the range of about 0.5 nm to about 2.0 nm, but this range varies depending on the target application. The conformal layer of the high-k gate dielectric material is deposited using known methods such as ALD, which enable the high conformability of the gate dielectric material.

[0076] As is known in the art, the use of high-k gate dielectric materials can be problematic in that such dielectric materials generally do not bond well with silicon layers. For example, high-k gate dielectric materials do not passivate the silicon surface, resulting in numerous interfacial traps, charges, and other problems that can degrade device performance. Thus, in one exemplary embodiment, a channel pre-cleaning process is performed to clean the exposed silicon surfaces of the active nanosheet channel layers 112, 114, 122, and 124 before depositing the high-k dielectric material to form the high-k gate dielectric layer, and then an oxidation process is performed to grow an ultrathin interfacial silicon oxide layer on the exposed surfaces of the active nanosheet channel layers 112, 114, 122, and 124. The formation of the interfacial silicon oxide layer is a selective step, and in other embodiments of the present invention, the high-k dielectric material of the HKMG structure can be formed on the exposed silicon surface of the active nanosheet channel layer without first forming a thin interfacial oxide layer.

[0077] In some embodiments, the interfacial silicon oxide layer is formed using a chemical oxidation process in ozonated deionized water containing ozone, an appropriate oxidation temperature, an ozone concentration in the deionized water, and a chemical oxidation process time for forming a thin interfacial silicon oxide layer. The interfacial layer is formed by oxidizing the exposed silicon surfaces of active nanosheet channel layers 112, 114, 122, and 124 to form a thin interfacial silicon oxide layer with a thickness ranging from about 5 angstroms to about 10 angstroms (i.e., about 0.5 nm to about 1 nm).

[0078] In some embodiments, the metal gate electrode includes one or more work function metal layers conformally deposited on the high-k gate dielectric layer. The work function metal layer may include one or more types of metal materials including, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), and Al-containing alloys (e.g., TiAlC, TiAl and AlC, or their nitrided alloys). In other embodiments, the work function metal layer may include metal materials including compositions or alloys of Zr, W, Hf, Ti, Al, Ru, Pa, ZrAl, WAl, TaAl, HfAl, TaC, TiC, TaMgC, and other types, compositions or alloys of work function metals commonly used to obtain the target work function for FET devices. The work function metal layer is conformally deposited using known methods such as ALD, CVD, etc. that enable high conformality of the deposited work function metal layer.

[0079] In some embodiments, the work function metal layer completely fills the spaces above and below the active nanosheet channel layers 112, 114, 122, and 124. In fact, when the initial spacing between the active nanosheet channel layers 112, 114, 122, and 124 is relatively small (e.g., 7 nm to 10 nm), after the formation of the high-k dielectric layer, the conformal deposition of a stack of two or more work function metal layers can result in filling (i.e., pinching off) the spaces above and below the active nanosheet channel layers 112, 114, 122, and 124, whereby those spaces are filled with the gate dielectric material and the work function metal. This is sufficient for short-channel length nanosheet FET devices with L G of about 15 nm or less.

[0080] Furthermore, in some embodiments, the remainder of the open gate region 130-1 on the active nanosheet channel layer 124 can be filled with work function metal by continuing the deposition process for the last deposited work function metal layer until the open gate region 130-1 on the active nanosheet channel layer 124 is completely filled with work function metal. In other embodiments, the remainder of the open gate region 130-1 can be filled with a low-resistance metallic material such as tungsten, ruthenium, cobalt, copper, or aluminum to form a metallic gate electrode away from the work function metal.

[0081] After deposition of dielectric and metallic materials to form the metal gate 180 (e.g., HKMG structure), a CMP process is performed to polish the surface of the semiconductor structure down to the ILD layer 175, thereby removing excess portions of the gate dielectric, work function, and gate electrode layer on the ILD layer 175. After the formation of the metal gate 180, a second ILD layer is formed on the first ILD layer 175 to cover the exposed upper surface of the metal gate 180. In some embodiments, the second ILD layer 176 is formed from the same or similar material as the first ILD layer 175.

[0082] In some embodiments, a gate-capping layer can be formed before the second ILD layer is formed, and the gate-capping layer covers the upper surface of the metal gate 180. For example, after the formation of the metal gate 180, an etching process can be performed to recess the upper surface of the metal gate 180 to a target level below the upper surface of the ILD layer 175. Then, a layer of dielectric material is deposited on the surface of the semiconductor device structure to fill the area above the recessed surface of the metal gate 180 with dielectric material, and the semiconductor device structure is planarized to the surface of the ILD layer 175, removing excess dielectric material, thereby forming the gate-capping layer. The gate-capping layer can be formed from a dielectric material such as SiN or SiBCN. Next, a second ILD layer 176 is formed to cover the first ILD layer 175 and the gate-capping layer.

[0083] Next, Figure 14 is a schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by forming a front-side gate and source / drain contacts on a stacked complementary FET structure according to an exemplary embodiment of the present disclosure. More specifically, Figure 14 schematicly illustrates the next step of the manufacturing process, in which the gate contact 190 is formed in contact with the metal gate 180, the source / drain contact 191 is formed in contact with the first source / drain elements 160-1 and 162-1 of the first and second transistors 101 and 102, and the source / drain contact 192 is formed in contact with the second source / drain element 162-1 of the second transistor 102. In some embodiments, the contacts 190, 191 and 192 are formed using any suitable middle-of-line (MOL) process module and material for forming MOL contacts.

[0084] For example, contacts 190, 191, and 192 are formed by a process that includes patterning / etching the first and second ILD layers 175 and 176 to (i) form via openings in the ILD layer 176 up to the metal gate 180, (ii) form via openings in the ILD layers 175 and 176 to expose portions of the first source / drain elements 160-1 and 160-2 of the first and second transistors 101 and 102, and (iii) form via openings in the ILD layers 175 and 176 to expose portions of the second source / drain element 162-2 of the second transistor 102, and then filling the via openings with a metallic material to form the gate contact 190 and the source / drain contacts 191 and 192. In some embodiments, the etching process includes a first etching process for selectively etching the ILD layers 175 and 176 with respect to the material of the metal gate 180 and the epitaxial source / drain region to form via openings, and a second etching process for selectively etching the portion of the dielectric liner layer (e.g., dielectric liner layer 170) exposed to the via openings previously formed in the epitaxial source / drain element.

[0085] In some embodiments, a salicide process is performed before forming contacts 190, 191, and 192 to form a silicide contact layer on the exposed surface of the epitaxial source / drain element in the via opening before filling the via opening with metallic material. Generally, the salicide process involves the reaction of a thin metal film with the epitaxial material of the source / drain element to form metallic silicide contacts by an annealing process.

[0086] In some embodiments, contacts 190, 191, and 192 are formed by depositing a thin conformal diffusion barrier layer so as to be aligned with the surface of the via openings, and then depositing a metallic material on the diffusion barrier layer to fill the via openings. In some embodiments, the metallic material includes, but is not limited to, tungsten or cobalt, and includes any suitable material for forming the MOL contacts. The diffusion barrier layer prevents the diffusion of the metallic material of the contacts into the material surrounding the ILD layers 175 and 176 and prevents the diffusion of, for example, oxygen from the ILD layers 175 and 176, which could oxidize the metallic material used to form contacts 190, 191, and 192. For example, the diffusion barrier layer can be a thin conformal layer of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or any other material suitable for use as a diffusion barrier to prevent the diffusion of the metallic material forming the MOL.

[0087] Next, Figure 15 is a schematic vertical cross-sectional view of a next intermediate structure of a semiconductor integrated circuit device, which is constructed by forming a first interconnect structure (e.g., a BEOL interconnect structure) on the front side of the intermediate structure of Figure 14 and coupling a handler substrate to the first interconnect structure, according to an exemplary embodiment of the present disclosure. More specifically, Figure 15 schematicly shows the next step of the manufacturing process in which the first interconnect structure 200 is formed on the ILD layer 175 and the handler substrate 202 is temporarily coupled to the first interconnect structure 200.

[0088] As described above, in some embodiments, the first interconnect structure 200 includes a BEOL interconnect structure comprising multiple levels of metal lines and interlevel metal vias embedded in multiple layers of dielectric material, forming a network of interconnect structures and wiring configured to (i) connect various integrated circuit components and devices manufactured as part of the front-end (FEOL) layer of a semiconductor integrated circuit, (ii) provide I / O connections between FEOL devices and external components, and (iii) provide a power distribution network for distributing positive and negative power supply voltages to active components. BEOL metallization includes horizontal wiring, interconnects, pads, etc., and vertical wiring in the form of conductive vias that form connections between different interconnect levels of the BEOL interconnect structure. The BEOL interconnect structure provides MOL contacts and connections to / between other active or passive devices formed as part of the FEOL layer. The BEOL interconnect structure can be manufactured using any suitable BEOL process module, the details of which are well known to those skilled in the art.

[0089] The handler substrate 202 (e.g., handler wafer) is bonded to the first interconnect structure 200 to facilitate backside processing, as will be further described below with reference to Figures 16 and 17. The handler substrate 202 is temporarily bonded to the first interconnect structure 200 using polymer bonding techniques (e.g., contact bonding or thermal compression bonding) or other suitable techniques. The handler substrate 202 may include a semiconductor substrate or a glass substrate, or any type of substrate material suitable for a given application.

[0090] Next, Figure 16 is a schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by back-side machining the intermediate structure of Figure 14 to remove the semiconductor substrate 105, according to an exemplary embodiment of the present disclosure. More specifically, Figure 16 schematicly illustrates the next step of the manufacturing process in which the semiconductor substrate 105 is removed to expose the bottom side of the first transistor 101 and the extensions 160E of the first and second source / drain elements 160-1 and 160-2 of the first transistor 101. The semiconductor substrate 105 is removed using known techniques such as mechanical grinding, polishing, etching, or any combination of grinding, polishing and etching.

[0091] For example, a backside grinding / polishing process is first performed to remove the bulk of the semiconductor substrate 105 down to the STI layer 140. Then, an etching process is performed to selectively etch the remaining portion of the semiconductor substrate 105, exposing the bottom side of the first transistor 101 and the extended portions 160E of the first and second source / drain elements 160-1 and 160-2. The backside etching process for removing the semiconductor substrate 105 is configured to be selective to the STI layer 140, the epitaxial material of the source / drain elements 160-1 and 160-2 of the first transistor 101, and the material of the metal gate 180. In some embodiments, the backside selective etching process is performed using an aqueous ammonia etching solution.

[0092] As schematically shown in Figure 16, etching the semiconductor substrate 105 works to release the extensions 160E of the first and second source / drain elements 160-1 and 160-2 of the first transistor 101, and as a result of releasing the extensions 160E of the first and second source / drain elements 160-1 and 160-2, strain is applied to the active nanosheet channel layers 112 and 114 of the first transistor 101. In some embodiments, as schematically shown in Figure 16, the first transistor 101 is a PFET, and the source / drain elements 160-1 and 160-2 are formed from, for example, epitaxial SiGe, and the release of the extension portion 160E causes the epitaxial material of the source / drain elements 160-1 and 160-2 to further relax (e.g., expand), resulting in compressive strain being applied to the active nanosheet channel layers 112 and 114 of the first transistor 101 (as schematically shown by the direction of the arrows in Figure 16). The compressive strain applied to the active nanosheet channel layers 112 and 114 of the first transistor 101 works to improve the performance of the first transistor 101 if the first transistor 101 is a PFET.

[0093] On the other hand, if the first transistor 101 is an NFET and the first and second source / drain elements 160-1 and 160-2 are formed from, for example, an epitaxial SiP material, then the release of the extension portion 160E causes the epitaxial material of the first and second source / drain elements 160-1 and 160-2 to further relax (e.g., contract), resulting in tensile strain being applied to the active nanosheet channel layers 112 and 114 of the first transistor 101 (in the opposite direction to the arrows shown in Figure 16). The tensile strain applied to the active nanosheet channel layers 112 and 114 of the first transistor 101 works to improve the performance of the first transistor 101 if the first transistor 101 is an NFET.

[0094] Next, Figure 17 is a schematic vertical cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, which is constructed by back-facing the intermediate structure of Figure 16 to form a dielectric layer, back-side contacts, and a back-side interconnect structure, according to an exemplary embodiment of the present disclosure, for removing the semiconductor substrate 105, according to an exemplary embodiment of the present disclosure. More specifically, Figure 17 schematicly illustrates the next steps of the manufacturing process, which include forming a back-side insulating layer 205, forming source / drain contacts 193, and forming a second (back-side) interconnect structure 210. In some embodiments, the back-side insulating layer 205 is formed by a process which includes (i) depositing conformal layers of dielectric material (e.g., SiN) to form a dielectric liner on the exposed surfaces of the source / drain elements 160-1 and 160-2 of the first transistor 101 and the exposed bottom surface of the metal gate 180, and (ii) depositing and planarizing layers of insulating material, thereby forming the back-side insulating layer 205. In some embodiments, the backside insulating layer 205 is formed from the same or similar material as the ILD layers 175 and 176 (e.g., silicon oxide, low-k dielectric material, etc.).

[0095] Next, source / drain contacts 193 are formed on the backside insulating layer 205 using the same or similar techniques and materials as the MOL fabrication techniques described above to manufacture the frontside contacts 190, 191, and 192. The second interconnect structure 210 is formed on the backside insulating layer 205, for example, using BEOL fabrication techniques. In some embodiments, the second interconnect structure 210 is configured to distribute the positive or negative or both of the power supply voltage active components of the FEOL layer. In some embodiments, the second interconnect structure 210 is further configured to enable backside signal I / O to the device in the FEOL layer in addition to the signal I / O provided by the first (BEOL) interconnect structure 200. After the formation of the second interconnect structure 210, the handler substrate 202 is removed using known techniques, resulting in the semiconductor integrated circuit device 100 shown in Figure 1.

[0096] Figure 18 is a schematic vertical cross-sectional view of a semiconductor integrated circuit device including a stacked complementary transistor structure according to another exemplary embodiment of the present disclosure. In particular, Figure 18 is a schematic vertical cross-sectional view of a semiconductor integrated circuit device 100-1 similar to the semiconductor integrated circuit device 100 of Figure 1, except that the first transistor 101 in Figure 18 includes first and second source / drain elements 260-1 and 260-2 which do not have extensions extending into the backside insulating layer 205. The process for manufacturing the semiconductor integrated circuit device 100-1 is similar to the processes shown in Figures 2 to 17, except that the modified process omits the trench formation process shown in Figure 8, and the epitaxial process shown in Figure 9 begins on an exposed, but not recessed, surface of the semiconductor substrate 105 in the S / D region to grow the first and second source / drain elements 260-1 and 260-2 shown in Figure 18.

[0097] It should be understood that the techniques disclosed herein may be implemented for other stacked complementary transistor structures. For example, while the exemplary embodiments disclosed herein show a stacked complementary transistor structure having a common metal gate structure, the techniques disclosed herein may be implemented in relation to a stacked complementary transistor structure in which the first and second transistors have separate gate structures to enable independent gate control of the first and second transistors.

[0098] Furthermore, exemplary embodiments described herein disclose the use of a sacrificial nanosheet layer 116 (e.g., Figure 2) formed from, for example, epitaxial SiGe (having a Ge concentration of 50%) as a placeholder to enable the epitaxy growth of a second nanosheet laminate 120 for a second transistor 102, the sacrificial nanosheet layer 116 is later replaced with a dielectric to form a dielectric isolation layer 150 between the first transistor 101 and the second transistor 102. In alternative embodiments, the first nanosheet laminate 110 can be epitaxially grown on a first semiconductor substrate, and the second nanosheet laminate 120 can be epitaxially grown on a second semiconductor substrate. A layer of dielectric material can be deposited on either the first nanosheet stack 110 or the second nanosheet stack 120, after which a wafer coupling and thinning process module is performed to form the first and second nanosheet stack structures 110 and 120 such that the dielectric layer is positioned between the first and second nanosheet stacks 110 and 120. This alternative process eliminates the need to perform a process as schematically shown in Figures 4B and 5, in which the remainder of the sacrificial nanosheet layer 116 between the first nanosheet channel structure 110-1 and the second nanosheet channel structure 120-2 is etched (as shown in Figure 4B) and replaced with a dielectric isolation layer 150 (as shown in Figure 5).

[0099] It should be understood that the exemplary methods described herein for manufacturing stacked complementary transistor structures can be readily incorporated into integrated circuits comprising semiconductor processing flows, semiconductor devices, and various analog and digital or mixed-signal circuits. In particular, integrated circuit dies can be manufactured from various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, and inductors. The integrated circuits disclosed herein can be employed in applications, hardware, or electronic systems or combinations thereof. Suitable hardware and systems for carrying out the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., mobile phones), solid-state media storage devices, and functional circuits. Systems and hardware incorporating such integrated circuits are considered parts of the exemplary embodiments described herein. With regard to the teachings of the invention provided herein, those skilled in the art will be able to consider other implementations and applications of the exemplary techniques disclosed herein.

[0100] While exemplary embodiments are described herein with reference to the accompanying drawings, it should be understood that the present invention is not limited to these exact embodiments, and various other changes and modifications can be made by those skilled in the art without departing from the scope of the appended claims.

Claims

1. The first interconnect structure, The second interconnect structure, A stacked complementary transistor structure disposed between the first interconnect structure and the second interconnect structure, wherein the stacked complementary transistor structure includes a first transistor of the first type and a second transistor of the second type which is the opposite of the first type, A first contact connects the first source / drain elements of the first transistor to the first interconnect structure, A second contact connects the first source / drain element of the second transistor to the second interconnect structure, Equipped with, The first and second contacts are arranged in alignment with each other. The first source / drain element of the second transistor includes an extension that extends below the gate of the second transistor toward the second interconnect structure. device.

2. The device according to claim 1, further comprising a third contact that connects the source / drain elements of the first and second transistors to the first interconnect structure in common.

3. The device according to claim 1, wherein the stacked complementary transistor structure includes a common metal gate structure shared by the first and second transistors.

4. The device according to claim 1, wherein the first and second transistors include gate-all-around field-effect transistors.

5. The device according to claim 1, wherein the stacked complementary transistor structure includes a complementary inverter cell.

6. The device according to claim 1, wherein the first interconnect structure includes a signaling network and a power distribution network.

7. The device according to claim 1, wherein the second interconnect structure includes a power distribution network.

8. The device according to claim 1, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor, or the first transistor is an N-type transistor and the second transistor is a P-type transistor.

9. The first interconnect structure, The second interconnect structure, A stacked complementary transistor structure disposed between the first interconnect structure and the second interconnect structure, wherein the stacked complementary transistor structure includes a first transistor of the first type and a second transistor of the second type which is the opposite of the first type, An insulating layer disposed between the stacked complementary transistor structure and the second interconnect structure, wherein the first and second source / drain elements of the second transistor each include an extension portion that extends into the insulating layer below the gate of the second transistor, A first contact connects the first source / drain elements of the first transistor to the first interconnect structure, A second contact coupled to the extension portion of the first source / drain element of the second transistor in order to connect the first source / drain element of the second transistor to the second interconnect structure, Equipped with, The first and second contacts are arranged in alignment with each other. device.

10. The second transistor is a P-type transistor, The device according to claim 9, wherein the first and second source / drain elements of the second transistor include an epitaxial semiconductor material configured to apply compressive strain to the active channel of the second transistor.

11. The second transistor is an N-type transistor, The device according to claim 9, wherein the first and second source / drain elements of the second transistor include an epitaxial semiconductor material configured to apply tensile strain to the active channel of the second transistor.

12. The device according to claim 9, wherein the stacked complementary transistor structure includes a common metal gate structure shared by the first and second transistors.

13. The device according to claim 9, wherein the first and second transistors include gate-all-around field-effect transistors.

14. The device according to claim 9, wherein the stacked complementary transistor structure includes a complementary inverter cell.

15. The device according to claim 9, wherein the first interconnect structure includes a signaling network and a power distribution network.

16. The device according to claim 9, wherein the second interconnect structure includes a power distribution network.

17. The first interconnect structure, The second interconnect structure, A complementary inverter comprising a stacked complementary transistor structure disposed between the first interconnect structure and the second interconnect structure, wherein the stacked complementary transistor structure comprises a first transistor of a first type and a second transistor of a second type opposite to the first type, the first transistor comprising a source element and a drain element, and the second transistor comprising a source element and a drain element, A first contact that connects the drain elements of the first and second transistors to the first interconnect structure in common, A second contact connects the source element of the first transistor to the first interconnect structure, A third contact connects the source element of the second transistor to the second interconnect structure, An insulating layer disposed between the stacked complementary transistor structure and the second interconnect structure, Equipped with, The second and third contacts are arranged in alignment with each other. The source element and the drain element of the second transistor each include an extension portion that extends into the insulating layer below the gate of the second transistor. device.

18. The device according to claim 17, further comprising an insulating layer disposed between the stacked complementary transistor structure and the second interconnect structure, wherein the source element and the drain element of the second transistor each include an extended portion extending into the insulating layer.

19. The device according to claim 17, wherein the first and second transistors include gate-all-around field-effect transistors.

20. A method for manufacturing semiconductor devices, Forming a stacked complementary transistor structure on a semiconductor substrate, wherein the stacked complementary transistor structure includes a first transistor of a first type and a second transistor of a second type opposite to the first type, and the first source / drain element of the second transistor includes an extension portion that extends into the semiconductor substrate below the gate of the second transistor. To form a first contact connected to the first source / drain element of the first transistor, To form a first interconnect structure connected to the first contact, By removing a portion of the semiconductor substrate, the bottom surface of the stacked complementary transistor structure is exposed. To form an insulating layer that covers the exposed bottom surface of the stacked complementary transistor structure, Forming a second contact connected to the first source / drain element of the second transistor in the insulating layer, wherein the second contact is formed in alignment with the first contact. The method involves forming a second interconnect structure in the insulating layer, wherein the second interconnect structure is connected to the second contact. Methods that include...

21. The method according to claim 20, further comprising forming a second source / drain element of the first transistor and a third contact commonly connected to the second source / drain element of the second transistor, wherein the first interconnect structure is connected to the third contact.

22. A method for manufacturing semiconductor devices, The present invention relates to forming a stacked complementary transistor structure on a semiconductor substrate, wherein the stacked complementary transistor structure includes a first transistor of a first type and a second transistor of a second type opposite to the first type, the first transistor includes a first source / drain element and a second source / drain element, the second transistor includes a first source / drain element and a second source / drain element, and the first and second source / drain elements of the second transistor each include an extension portion that extends into the semiconductor substrate below the gate of the second transistor. To form a first contact connected to the first source / drain element of the first transistor, To form a first interconnect structure connected to the first contact, By removing a portion of the semiconductor substrate, exposing the bottom surface of the stacked complementary transistor structure, and freeing the extended portions of the first and second source / drain elements of the second transistor, To form an insulating layer that covers the exposed bottom surface of the stacked complementary transistor structure and the extended portions of the first and second source / drain elements of the second transistor, Forming a second contact in the insulating layer so as to contact the extended portion of the first source / drain element of the second transistor, wherein the second contact is formed in alignment with the first contact, The method involves forming a second interconnect structure on the insulating layer, wherein the second interconnect structure is connected to the second contact. Methods that include...

23. The method according to claim 22, further comprising forming a second source / drain element of the first transistor and a third contact commonly connected to the second source / drain element of the second transistor, wherein the first interconnect structure is connected to the third contact.

24. The method according to claim 22, wherein strain is applied to the active channel of the second transistor by releasing the extensions of the first and second source / drain elements of the second transistor.

25. The method according to claim 22, wherein the first and second source / drain elements of the second transistor include an epitaxial semiconductor material configured to apply either (i) a compressive strain to the active channel of the second transistor when the second transistor includes a P-type transistor, and (ii) a tensile strain to the active channel of the second transistor when the second transistor includes an N-type transistor.

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