Electrical margin testing method and margin tester

Abstract

To determine a case in which electric characteristics are changed to the extent that they affect operation by screening a large number of prototypes and production components.SOLUTION: A margin tester 102 is at a lower cost, easier to use, and faster than a conventional BERT and oscilloscope, and can be operated for a full multi-lane I / O link in a standard operation state accompanying complete loading and crosstalk. The margin tester 102 evaluates an electric margin of a receiver in a multi-lane high-speed I / O link that can be normally used by using a device 104 to be tested simultaneously in one direction or in both directions. In a form for a specific technique, an embodiment of the margin tester 102 may be realized as an add-in card margin tester for testing a mother board slot of a mother board to be tested, or may be realized as a mother board having a slot for testing an add-in card.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The disclosed technology relates to a test measurement system, and particularly to a high-speed electrical margin test for an electrical device under test (DUT). Method and margin tester It relates to.

Background Art

[0002] Designers and manufacturers of electrical devices require test measurement equipment and appropriate test procedures to confirm that the devices function properly. Such tests may be performed, for example, at the engineering characterization stage of designing a new device to compare the actual electrical performance of the device with the simulated performance to confirm that the device is operating as designed. Also, such tests may be performed in a production manufacturing environment after the engineering design is completed to detect manufacturing defects in each manufactured device.

[0003] Many electrical devices are designed to include high-speed I / O signal paths or buses. For example, the motherboards of modern personal computers (PCs), like other types of electrical devices, often have a high-speed serial PCI Express (PCIe or PCI-e) bus, which is a bus that operates in accordance with the PCI Express high-speed serial computer expansion bus standard. The PCI Express standard format specification is maintained and developed by PCI-SIG (PCI Special Interest Group). These buses are typically used for communication between the motherboard and add-in cards / daughter cards, which are inserted into PCIe connector slots or ports on the motherboard. Many electrical devices other than motherboards also employ PCIe buses and connectors for high-speed I / O. PCIe Gen 4 (or version 4) devices can achieve bandwidths of up to 16 gigabytes per second (GT / s). PCIe Gen 5 (or version 5) devices can achieve bandwidths of up to 32 GT / s.

[0004] PCIe devices communicate via logical connections called interconnects or links. A link is a point-to-point communication channel between two PCIe ports, enabling simultaneous bidirectional traffic. At the physical level, a link consists of one or more lanes. Low-speed PCIe devices use single-lane (x1) links, while high-speed PCIe devices, such as graphics adapters, typically use wider and faster 16-lane (x16) links. Each lane consists of two differential signaling pairs, one for receiving data and the other for transmitting. Thus, each lane consists of four wires or signal traces. Traditionally, the performance of PCIe device lanes has been tested using bit error rate testers (BERTs), high-speed signal generators, and oscilloscopes.

[0005] In the engineering bench testing and engineering characterization phases of printed circuit board (PCB) development, high-speed routes of the board design (such as PCIe interconnects) are simulated; that is, a design "recipe" or baseline design is followed. However, testing every sample and every lane of a board for all high-speed I / O with bit error rate testers (BERTs) and oscilloscopes is impractical due to cost, time, and complexity constraints. In particular, traditional BERTs and oscilloscopes for testing high-speed I / O standards like PCIe continue to increase in cost and complexity with increasing data rates. A single Tx and Rx test station for testing one PCIe lane at a time can cost over $1 million. Furthermore, these devices are difficult to use for traditional Tx and Rx testing and calibration, and ensuring accurate measurements and maintaining the device in good working order requires expert (PhD level) users and a considerable amount of time. As a result of these constraints, conventional BERT and oscilloscopes are not widely used for large-scale electrical testing of prototype silicon, boards, PCBs, and cables, and are typically not used at all in production testing. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2008 / 0192814 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] However, as I / O link data rates increase, such as 32.0 GT / s for PCI Express 5.0, the risk of even small or subtle issues significantly impacting the performance of these I / O links increases. Therefore, it is becoming increasingly important to flag electrical performance issues for all prototype samples, ports, and lanes before production, and to test the electrical performance of all units on the production line to catch production-related issues (defective parts, etc.) and prevent these issues from leading to customer problems and returns. Furthermore, conventional BERT and oscilloscopes can only test one lane at a time, meaning this testing takes place in an environment different from the actual operation of these I / O links. In other words, during actual operation, multi-lane links are typically formed, creating an environment where serious crosstalk and loading problems can occur, and conventional BERT and oscilloscope testing cannot handle this environment, even if tested. Similarly, in manufacturing test environments, when assembling and testing multiple PCBs of a given design, production lines typically do not use BERT and oscilloscopes for high-speed I / O testing due to cost, time, and complexity constraints.

[0008] Therefore, there is a growing need for a new type of instrument that can screen large quantities of prototypes and production parts and identify when electrical characteristics change to a degree that affects operation. Compared to conventional BERT and oscilloscopes, this instrument offers the highest value in terms of low cost, ease of use, and high speed, and can operate on full-fledged multi-lane I / O links under standard operating conditions with full loading and crosstalk. Overall, knowing the electrical margin (statistically effective operating margin) for each high-speed I / O lane in each direction is valuable in that it increases the likelihood of finding both design (e.g., for every production sample, lane by lane) and assembly (e.g., the cause of a particular board / lane) problems across all production samples.

[0009] Some conventional solutions rely solely on functional testing as an optimal approximation (for example, simply inserting a "golden" device, i.e., a reference device, and testing the link at full speed). Other companies utilize on-die electrical margining on the silicon (semiconductor) for their boards, but this provides only one-way information and is not calibrated / characterized like test equipment, leaving the significant task of dealing with and understanding the individual differences of each add-in card selected for that purpose.

[0010] This application discloses a system, device, and method for high-speed input / output (I / O) margin testing to solve the above-mentioned technical problems.

[0011] Components in a drawing do not necessarily have the same scale relative to each other. Similar reference numbers indicate corresponding parts across multiple drawings. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is a schematic block diagram showing an example of an environment in which an embodiment of a system, apparatus, and method for high-speed input / output (I / O) margin testing according to an exemplary embodiment may be implemented. [Figure 2] Figure 2 is a block diagram showing an example of an add-in card margin tester for specific technologies compliant with the PCI Express High-Speed ​​Serial Computer Expansion Bus standard for margin testing PCI Express motherboard slots, according to an exemplary embodiment. [Figure 3] Figure 3 is a block diagram showing an example of a motherboard margin tester having a slot compliant with the PCI Express high-speed serial computer expansion bus standard for margin testing a PCI Express add-in card according to an example embodiment. [Figure 4]Figure 4 is a diagram illustrating the results of an exemplary margin test of a device under test (DUT) performed by a high-speed I / O margin tester, and an example of an embodiment showing potential assembly or production problems of the DUT identified based on the results of this margin test. [Figure 5] Figure 5 shows the results of another exemplary margin test of a device under test (DUT) performed by a high-speed I / O margin tester, and an example of an embodiment illustrating potential assembly or production problems of the DUT identified based on the results of this margin test. [Figure 6] Figure 6 is a block diagram showing a general-purpose margin tester according to an exemplary embodiment, in which multiple interfaces are configured to be cabled to at least one test fixture to evaluate the electrical margin of the DUT's multi-lane high-speed I / O links in both the transmit (Tx) and receive (Rx) directions. [Figure 7] Figure 7 is a lower-level block diagram of a margin tester according to an exemplary embodiment for testing the electrical margin of a multi-lane high-speed I / O link of a DUT in both the Tx and Rx directions. [Figure 8] Figure 8 is a block diagram of an example field-programmable gate array (FPGA) configured according to an embodiment, which can be used in a margin tester controller to test the electrical margin of the DUT's multi-lane high-speed I / O links in one or both directions, Tx and Rx. [Figure 9] Figure 9 is a block diagram of an example of FPGA output drive options according to an exemplary embodiment, which may be used with a margin tester controller to test the electrical margin of the DUT's multi-lane high-speed I / O links in the Tx direction. [Figure 10] Figure 10 is a flowchart of an exemplary method 1000 for margin testing a DUT according to one embodiment. [Figure 11]FIG. 11 is a flowchart of an exemplary method for identifying potential DUT assembly or production problems based on a process of margin testing the electrical margins of a multi-lane high-speed I / O link of a DUT in one or both of the Tx and Rx directions. [Figure 12] FIG. 12 is a flowchart of an exemplary method for a margin tester to initiate an electrical margin evaluation based on user-selectable options according to an example of an embodiment. [Figure 13] FIG. 13 is a flowchart of an exemplary method 1300 for providing a calibrated margin tester according to an example of an embodiment. [Figure 14] FIG. 14 is a flowchart of an exemplary method for setting up a DUT to perform a margin test according to an example of an embodiment. [Figure 15] FIG. 15 is another lower-level block diagram of a margin tester according to an exemplary embodiment for testing the electrical margins of a multi-lane high-speed I / O link of a DUT in both the Tx and Rx directions. [Figure 16A] FIG. 16A shows a plot of margin versus link training state in the transmit direction. [Figure 16B] FIG. 16B shows a plot of margin versus link training state in the receive direction. BEST MODE FOR CARRYING OUT THE INVENTION

[0013] FIG. 1 is a schematic block diagram showing an exemplary environment in which a system, device, and method for high-speed I / O margin testing according to an exemplary embodiment may be implemented. In one embodiment, the illustrated margin tester 102 evaluates the electrical receiver margins of the operation for one or both of the Tx and Rx directions of the multi-lane high-speed I / O link 110 of an exemplary DUT 104. The margin tester 102 of FIG. 1 represents one or more embodiments of the margin tester disclosed in the present application.

[0014] The margin tester 102 may be coupled to a test station, PC, terminal, or other display device 106 capable of processing, replicating, or displaying eye pattern displays or data eye diagrams 108 representing various aspects of the multi-lane high-speed I / O link 110. In some embodiments, the test station, PC, terminal, or other display device 106 may be integrated with the margin tester 102 or integrated as part of the margin tester 102. The eye pattern display or data eye diagram 108 is a high-speed digital signal representation that enables rapid visualization and determination of key parameters of the electrical quality of the signal, and thus the statistically effective operating margin of the DUT can be determined using the data obtained therefrom. The eye pattern display or data eye diagram 108 consists of a digital waveform, where the vertical axis is signal amplitude and the horizontal axis is time, and the waveform portion corresponding to each individual bit is folded into a single graph. By repeating this configuration for a large number of waveform samples, the resulting graph represents the average statistics of the signal and resembles an eye. The eye aperture corresponds to one bit period and is usually called the unit interval (UI) width of the eye pattern display or data eye diagram. The bit period is the size of the horizontal aperture of the eye diagram at the eye intersection and is usually measured in picoseconds for high-speed digital signals (i.e., 200 picoseconds are used for a 5Gbps signal). Its data rate is the reciprocal of the bit period (1 / bit period). The bit period is generally called the unit interval (UI) when describing eye diagrams. The advantage of using UI rather than actual time on the horizontal axis is that it is normalized and makes it easy to compare eye diagrams of different data rates. The eye width is the size of the horizontal aperture of the eye diagram. This is calculated by measuring the difference in the statistical mean of the eye intersections. Rise time is the magnitude of the average transition time for the upward slope of the data in the eye diagram. It is typically measured at the 20% and 80% levels of the slope, or at the 10% and 90% levels.The fall time is the magnitude of the average transition time of the downward slope of the eye diagram data. Its measurement is usually performed at the 20% and 80% levels or the 10% and 90% levels of the slope. Jitter is the time deviation from the ideal timing of data bit events and is an important characteristic of high-speed digital data signals. To calculate jitter, the time deviation at the intersection of the rising edge and falling edge transitions of the eye diagram is measured. Fluctuation can be random or deterministic. By analyzing the time histogram of the deviation, the amount of jitter can be obtained. Peak-to-peak (p-p) jitter is defined as the full width of the histogram that represents the presence of all data points. Root mean square (RMS) jitter is defined as the standard deviation of the histogram. The unit of jitter measurement in high-speed digital signals is usually picoseconds.

[0015] Embodiments of the margin tester 102 can take at least two forms: "technology-specific and general-purpose". The margin tester 102 can be used with any high-speed I / O protocol link of any link width (number of lanes) and, without limitation, can be used with any form of high-speed differential signaling such as non-return-to-zero (NRZ), pulse amplitude modulation 3 (PAM-3), pulse amplitude modulation 4 (PAM-4), etc. As an example of a specific embodiment regarding the test, PCI Express is used, but different high-speed serial bus standards, hardware, and protocols may also be used.

[0016] FIG. 2 is a block diagram showing an exemplary technology-specific add-in card margin tester 202 for margin testing a PCI Express motherboard slot 206 in accordance with the PCI Express high-speed serial computer expansion bus standard according to an example of an embodiment.

[0017] In one embodiment for a specific technology, the margin tester embodiment is implemented as a PCI Express add-in card margin tester 202 to test the PCI Express motherboard slot 206 of the motherboard under test 204. For example, the PCI Express add-in card margin tester 202 may be a PCI Express x16 CEM (card electromechanical specification) form factor add-in card. In another embodiment for a specific technology, the margin tester embodiment is implemented as a motherboard having a PCI Express slot to test a PCI Express add-in card (as shown in Figure 3).

[0018] The PCI Express add-in card margin tester 202 may be a standard PCI Express compliant add-in card form factor for a specific PCI Express form factor (e.g., CEM or M.2 (formerly known as Next Generation Form Factor (NGFF)) or U.2 (formerly known as SFF-8639)). The PCI Express add-in card margin tester 202 may have a PCB 212 and one or more components for each lane, implementing the compliant PCI Express physical and logical link layers. The PCI Express add-in card margin tester 202 may have multiple interfaces (such as connector 208) coupled to the PCB 212 and the controller 210. As will be apparent to those skilled in the art, the controller 210 is not limited to one controller, but may consist of two or more controllers working together. Such an interface includes a number of connectors 208 connected to a motherboard slot 206 and a margin tester transmitter, which optionally has the ability to introduce controlled noise (e.g., voltage oscillations and sinusoidal jitter) under the control of a controller 210, thereby changing the expected eye margin at the receiver of the motherboard 204 under test to a specific target in terms of timing or voltage margin without requiring software to be executed on the motherboard 204 under test. The controller 210 may also be connected to a memory 214, which can store instructions and other data that the controller 210 may read, use, or execute in order to perform the functions described herein.

[0019] Various embodiments of the margin tester 102 (such as the PCI Express add-in card margin tester 202 for specific technologies, the motherboard margin tester 302 for specific technologies, and the general-purpose margin tester 602) may or may not have noise introduction capabilities. For cost-conscious production testing, the absence of noise introduction capabilities may be more attractive. The margin tester receiver in a compliant physical layer embodiment may have the ability to provide margins to links as defined in the PCI Express 4.0 / 5.0 lane margin specification, but may also have additional, more sophisticated on-die margin setting capabilities. In one embodiment, the margin tester receiver may measure eye margins by operating an independent error detector and comparing mismatches using a data sampler. In one embodiment, the controller 210 that causes the margin tester 102 (such as the PCI Express add-in card margin tester 202 for specific technologies, the motherboard margin tester 302 for specific technologies, and the general-purpose margin tester 602) to perform the functions described herein may be implemented using a field-programmable gate array (FPGA) and FPGA I / O, which are shown in more detail in Figures 7 to 9. However, other combinations of configurable controller hardware, firmware, and software may be used.

[0020] Figure 3 is a block diagram showing an exemplary motherboard margin tester 302 for specific technologies, having a slot compliant with the PCI Express high-speed serial computer expansion bus standard, for margin testing a PCI Express add-in card according to an example of an embodiment.

[0021] Motherboard margin tester 302 is another example of an embodiment for a particular art of margin tester 102 disclosed herein, and is implemented as a motherboard margin tester 302 having one or more PCI Express slots 306 for testing PCI Express add-in cards such as the PCIe x16 add-in card DUT304 shown in Figure 3. Motherboard margin tester 302 may have multiple interfaces (e.g., one or more PCI Express slots 306) coupled to PCB 312 and controller 210. For example, such interfaces may have one or more PCI Express slots 306 into which the PCIe x16 add-in card DUT304 may be inserted for testing. The margin test transmitter optionally has the ability to introduce controlled noise, for example, voltage oscillations and sinusoidal jitter (further described later with respect to Figures 8 and 9), under the control of the controller 210, thereby allowing the expected eye margin at the PCIe x16 add-in card DUT304 to be changed to a specific target in terms of timing or voltage margin without requiring software to be run on the PCIe x16 add-in card DUT304. For example, the controller 210 may be configured to evaluate the electrical margin of a single-lane or multi-lane high-speed I / O link by introducing a reduction in eye width aperture by introducing jitter on at least the margin test transmitter (or by implementing other eye width reduction methods), in which case the introduction of jitter can be applied simultaneously to all lanes of the single-lane or multi-lane high-speed I / O link, or independently to each lane of the single-lane or multi-lane high-speed I / O link.Furthermore, the controller 210 may be configured to evaluate the electrical margin of a single-lane or multi-lane high-speed I / O link by introducing a reduction in eye height opening by introducing jitter on at least a margin test transmitter (or by implementing other eye height reduction methods), in which case the introduction of jitter can be applied simultaneously to all lanes of the single-lane or multi-lane high-speed I / O link, or independently to each lane of the single-lane or multi-lane high-speed I / O link. The controller 210 may be further configured to evaluate the electrical margin of a single-lane or multi-lane high-speed I / O link by varying at least the amount of skew for each lane across multiple lanes.

[0022] The controller 210 may be connected to a memory 214, which can store instructions and other data that the controller 210 may read, use, or execute in order to perform the functions described in this application.

[0023] Durability and insertion cycles are important considerations for specific-technical embodiments of the margin tester 102 (such as the PCI Express add-in card margin tester 202 and the motherboard margin tester 302). Therefore, PCBs 212 and 312 may be designed to measure margin characteristics using adapters configured to be replaced at low cost when worn out, without replacing the rest of the margin test unit. For example, a replaceable adapter may be coupled to one or more PCI Express slots 306 or connectors 208 and configured to wear out after a certain amount of use. In this case, only the adapter needs to be replaced when it wears out, without replacing the rest of the PCI Express add-in card margin tester 202 or motherboard margin tester 302.

[0024] Figure 4 shows the results of exemplary margin tests performed on several DUTs by the high-speed I / O margin tester 102, and Figure 402 shows an example of an embodiment illustrating potential assembly or production problems of the DUTs identified based on the results of these margin tests.

[0025] In one embodiment, the margin test may include a process in which the margin tester 102 evaluates the timing of the eye width margin for each DUT among a plurality of devices under test (DUTs) in one or both directions, Tx and Rx, for each high-speed input / output (I / O) lane of the DUT's multi-lane high-speed I / O link. The margin tester 102 may then detect, for some of the DUTs, eye width margin timing measurements that fall below a predetermined threshold for different lanes across these DUTs. Potential assembly or production problems of the DUTs may then be detected (visually or automatically by the margin tester 102) based on the detection of eye width margin timing measurements that fall below a predetermined threshold for different lanes across these DUTs.

[0026] In one embodiment, an add-in card margin tester, such as the add-in card margin tester 202 shown in Figure 2, may be used for bench testing / characterization of a prototype sample of a motherboard having PCIe x8 slots. The following exemplary test procedure may be performed using the add-in card margin tester 202, measuring the E-6 timing eye width margin (left + right) with respect to the slot for several milliseconds simultaneously for each lane. For simplicity, this example only measures time, but other embodiments may include other measurements. Each measurement in this example is performed three times, however, this may be user-programmable in various embodiments. The measurements shown in Figure 402 are performed on the margin tester receiver in addition to the motherboard DUT receiver. The measurements are performed on the motherboard DUT receiver and can be done in two ways. The first method may utilize the jitter (Sj) and voltage swing sweep of the margin tester. A second method may utilize on-die margin testing at the motherboard receiver. For example, on-die margin testing at the motherboard receiver may be performed by software on a bootable drive connected to the motherboard DUT, under the control of the controller 210 of the add-in card margin tester 202, or by BIOS (basic input / output system) software on the motherboard DUT to support the speed. In this example, the measurement is performed at 16 GT / s, but this may be changed and may be user-configurable.

[0027] The above example test procedure yields exemplary results regarding the average margin in the test receiver, as shown in Figure 402. As shown in Figure 402, consistently low margins on lane 2 across all five DUTs from DUT#1 to DUT#5 may indicate a potential design problem. In contrast, low margins on lane 4 of DUT#1, lane 0 of DUT#3, and lane 6 of DUT#4 may indicate a potential assembly or production problem related to specific lanes on those particular DUTs.

[0028] Figure 5 shows the results of another exemplary margin test of a DUT performed by a high-speed I / O margin tester, and an example of an embodiment illustrating potential assembly or production problems of the DUT identified based on the results of this margin test.

[0029] Similar indicators of potential design or assembly problems can be seen in the example results shown in Figure 502 of Figure 5 regarding voltage swing and average Sj margin in the DUT receiver. As shown in Figure 502, a consistently low margin on lane 1 across all five DUTs from DUT#1 to DUT#5 may be an indicator of a potential design problem. In contrast, low margins on lane 0 of DUT#1, lane 5 of DUT#1, and lane 7 of DUT#2 may be indicators of potential assembly or production problems related to specific lanes on those particular DUTs.

[0030] Further features of embodiments of the disclosed technology may include the following functions, which may be performed under the control of the controller 210 (e.g., by executing instructions according to a configured FPGA or by reading from another non-temporary computer-readable storage medium): the ability to select one or more different high-speed I / O protocols and use them to perform margin testing on the multi-lane high-speed I / O links of the DUT; the ability to test multiple ports of the DUT using miscellaneous protocols simultaneously; the ability to output the margin variation per execution during any number of executions of the margin test of the margin tester for the multi-lane high-speed I / O links; the ability to implement fixed equalization (EQ) of Tx for the DUT to test how much the margin varies due to equalization (EQ) training of Tx; and the ability to test the effect of receiver equalization on the margin of the multi-lane high-speed I / O links of the DUT using fixed continuous-time linear equalization (CTLE) in the receiver of the margin tester. This function allows you to test the effect of the receiver's equalization process on the margin of the DUT's multi-lane high-speed I / O link by using decision feedback equalization (DFE) in the margin tester receiver. It also allows you to calculate the margin expected by the margin tester based on the target channel. If a low margin is detected as a result of evaluating the electrical margin of the multi-lane high-speed I / O link, it automatically generates debug information. You can switch to using a variable inter-symbol interference (ISI) signal source to find out how much inter-symbol interference (ISI) causes a failure in a lane of the multi-lane high-speed I / O link. You can test each lane individually to identify the amount of margin loss caused by crosstalk in the DUT's multi-lane high-speed I / O link. You can turn off the DFE in the margin tester receiver to evaluate the margin with and without DFE, and the amount of nonlinear discontinuity in each channel related to the multi-lane high-speed I / O link.The ability to indicate expected margins using a reference receiver and typical channels, thereby flagging lower-than-expected margins even if they are consistently lower than expected across all lanes of a multi-lane high-speed I / O link for one DUT and multiple DUTs. The ability to select from multiple speeds of a multi-lane high-speed I / O link and perform an electrical margin evaluation for it. The ability to use protocol-specific knowledge to allow the margin tester to infer when an error occurred at the DUT's receiver based on traffic traveling in the opposite direction on the multi-lane high-speed I / O link, enabling the margin tester to perform margin testing on the production line without software on the DUT. The ability to automatically capture time-domain reflectometry (TDR) values ​​of low-margin channels detected as a result of the electrical margin evaluation of the multi-lane high-speed I / O link. The ability to automatically connect to an oscilloscope and automatically capture digitized waveforms when low margins are detected as a result of the electrical margin evaluation of the multi-lane high-speed I / O link. Furthermore, a software plugin is provided to configure the DUT silicon, thereby enabling the setting of one or more user-selectable options for the DUT and the implementation of one or more user-selectable options. Some of the above functions may also be provided as user-selectable options for operating the margin tester 102 under the control of the controller 210.

[0031] A further feature of embodiments of the disclosed technology may be a trigger function that operates under the control of a controller 210. That is, the margin tester 102 may have a programmable trigger signal input or output. That is, a test may be performed in response to a signal received by the controller 210 (trigger signal input), or a signal that functions as a trigger signal may be generated by the controller 210 when a specific event occurs during the test (trigger signal output). In some examples, this programmable trigger signal may be set by a user-selectable option. For example, as described above, the controller 210 may be configured to automatically capture time-domain reflectance measurements (TDR) of low-margin channels detected as a result of evaluating the electrical margin of a multi-lane high-speed I / O link, or to automatically connect to an oscilloscope and automatically capture a digitized waveform when a low margin is detected as a result of evaluating the electrical margin of a multi-lane high-speed I / O link.

[0032] In other words, the controller 210 may output a trigger signal when a specific event or measurement is performed by the controller 210, or the controller 210 may operate based on a trigger signal received by the controller 210.

[0033] A trigger signal may be generated by the controller 210, for example, when a transmitter or receiver measurement falls below a specified eye width or specified eye height. In addition, or instead, the controller 210 may generate a trigger signal when a two-dimensional eye measurement of the transmitter or receiver falls below a specified eye shape or eye mask. The controller 210 may also generate a trigger signal when the receiver margin is smaller than a certain voltage or other measurement. Furthermore, a trigger signal may be generated when there is some state transition in the LTSSM (Link Training and Status State Machine) while the PCIe link is training, or when an error is introduced into a specific lane in a particular LTSSM state or in a particular PCIe packet.

[0034] In some cases, a programmable delay can be specified between a particular event and trigger using a user-selectable control. In addition, or alternatively, another trigger mode may be provided for the slow encoding of this event format, and a specific margin tester model, such as a trigger that uses this mode, can be defined for the oscilloscope, in which case the oscilloscope will automatically configure and post-process the same clock data recovery, continuous time linear equalization, and decision feedback equalization as the margin product.

[0035] The triggers configured by the controller 210 can be programmed into a number of different modes. For example, the controller 210 can receive triggers in the signal based on configuration settings or settings, including link speed, with or without reset / link training. When this configuration setting is made, the controller 210 can perform margin measurements. In addition, or alternatively, the controller 210 can receive triggers in the signal when a programmable error is introduced, and can perform margin measurements when the controller 210 receives triggers in the signal.

[0036] Figure 6 is a block diagram showing a general-purpose margin tester 602 according to an exemplary embodiment, in which multiple interfaces 604 are configured to be connected, for example, via one or more cables to at least one test fixture in one or both directions of the DUT's multi-lane high-speed I / O links to evaluate the electrical margins of the DUT's multi-lane high-speed I / O links.

[0037] The general-purpose margin tester 602 comprises a controller 210 and associated memory 214, which may store instructions and other data for the controller 210 to read, use, and execute to perform the functions described herein. The general-purpose margin tester 602 has several lanes, which can be connected (e.g., by cable connection) to standard test fixtures via interface 604, such as a standard PCI Express compliance load board (CLB), and perform the same tests as the margin tester's technically specific embodiments (e.g., add-in card margin tester 202 and motherboard margin tester 302) under the control of the controller 210. In addition, the general-purpose margin tester 602 supports multiple protocols, and the configuration software for the general-purpose margin tester 602 has options to configure lanes for various protocols and host / device roles. The general-purpose margin tester 602 can also be used to test add-in cards by cabling it to a test fixture such as a standard PCI Express compliance base board (CBB) for testing add-in cards. The interface 604 of the general-purpose margin tester 602 may have standard coaxial connectors and cables for each high-speed differential signal, or, in various other embodiments, may have custom high-density connectors and fixtures to minimize the number of cables and make switching from one DUT to another more efficient.

[0038] In some cases, the DUT (Device Under Test) may involve testing interconnects, which have traditionally been tested using a vector network analyzer (VNA). However, VNAs are often costly and complex. Furthermore, the S-parameters (scatter parameters) generated by VNA measurements are generally considered increasingly unreliable when used in statistical simulations of high frequencies, especially high-speed serial links.

[0039] However, an example of the technology disclosed herein is that the margin tester 102 can be used to test one or more passive or active interconnects, such as cables or PCB segments, and to quickly evaluate the actual margin differences between many lanes and components. These tests can easily identify the worst-case scenario and risk level of the interconnect. Thus, the margin tester 102 may include a “VNA” mode for testing active or passive interconnects.

[0040] When using a single-port margin tester, a single-port transmitter is connected to one side of the interconnect under test, and a single-port receiver is connected to the opposite side of the interconnect. The interconnect under test can then be tested by performing a margin test using a non-protocol PRBS. However, in the examples of the technology disclosed herein, testing the interconnect under test is not limited to a single margin tester 102. Rather, the test can also be performed using multiple transmitters of one margin tester 102 connected to the interconnect under test and multiple receivers of another margin tester 102 connected to the other end of the interconnect under test.

[0041] In addition, or alternatively, a multi-port margin tester 102 may be used to measure the interconnect under test in the active protocol state after training. In such a setup, the interconnect under test may be connected to one port of the multi-port margin tester 102, and the other end of the interconnect under test may be connected to a different port of the multi-port margin tester 102. The interconnect under test may then be tested to measure the margin in the protocol in the active protocol state after training. Alternatively, instead of a multi-port tester 102, multiple margin testers 102 may be used to perform the margin test on the interconnect under test.

[0042] Figure 7 is a lower-level block diagram of a margin tester 102 according to an exemplary embodiment for testing the electrical margin of a multi-lane high-speed I / O link of a DUT in one or both directions of Tx and Rx.

[0043] The diagram shows an FPGA 714, which is operably connected to a support unit 710 (which may have Ethernet® or other communication functions), a time base unit 708 that supplies a reference clock to the system, a high-speed I / O (HSIO) output unit 702, and an HSIO input unit 704. The margin tester 102 may also be powered by an AC / DC power supply unit 716. The HSIO output unit 702 and HSIO input unit 704 are also operably coupled to an I / O connector 706. The FPGA 714 is a semiconductor device based on a matrix of configurable logic blocks (CLBs) connected by programmable interconnects. In various embodiments, the margin tester 102 may have fewer or more components than those shown, and some of the shown components or the functions of some of the components may be located outside or separately from the margin tester 102, or may be located within or integrated into the FPGA 714, even if they communicate with the margin tester 102 in an operable manner.

[0044] The FPGA714 can be reprogrammed after manufacture for desired applications or functional requirements, such as performing the functions of the margin tester 102 described herein. For example, the firmware of the FPGA714 may function as a standard PCI Express upstream port (also called an endpoint, for testing a motherboard, as in an embodiment of the add-in card margin tester 202) or a standard PCI Express root port (also called an upstream port or root complex, for testing an add-in card, as in an embodiment of the motherboard margin tester 302), including the link layer logic of the margin tester 102, to infer when an error began at the DUT's receiver based on traffic in the opposite direction, and to rapidly mitigate margin stress when an error occurs, preventing a fatal link failure. In some embodiments, the FPGA714 may be implemented using a system-on-module (SoM) architecture that allows for the incorporation of memory, interfaces, etc., into the FPGA714, or it may include an SoM architecture. SoM can be implemented, for example, using an advanced RISC (Reduced Instruction Set) machine (originally the ARM (Acorn RISC Machine) architecture).

[0045] The configuration application or script may be implemented via the FPGA714 or stored in another accessible memory device or other non-temporary computer-readable storage medium, allowing end users to easily configure margin tester options for the margin tester 102, including multiple runs with one or more of the following options. In some embodiments, an option for a target bit error rate (BER) may be set with respect to the margin scan (in milliseconds for E-6 type margins and in minutes for E-12 type margins). For example, such targets may include, but are not limited to, margins, margin timing or voltage cycles, processes for fixing the Tx equalization process of the margin tester or DUT transmitter, and processes for fixing the CTLE and DFE of the margin tester receiver Rx. In some embodiments, optional applications or scripts are provided that retrieve data from the margin tester 102 and provide visualization tools for the user to view large margin data sets across multiple products / samples, view averages, variations per run, trends over time, and compare margins across numerous runs with various configuration options (such as adjusted Tx equalization) for the same DUT. In some embodiments, optional applications are provided (which may be implemented on a bootable drive for installation on the motherboard under test) that unlock additional options for motherboard testing. These additional options include running on loopback instead of L0 and using specific patterns, using on-die margin setting functions in the DUT's silicon instead of voltage swing and Sj margin setting from the DUT's transmitter, and running on both and comparing their results.

[0046] PCIe and high-speed link simulations increasingly utilize statistical simulation tools along with transmitter and receiver models to predict the eye diagram of links that would inherently close without complex reference transmitter and receiver equalization models. One of the most common formats for simulation models is IBIS-AMI.

[0047] Examples of the technologies disclosed herein include, but are not limited to, generating simulation models such as a margin tester 102, an IBIS-AMI model for silicon and interconnects. The user can use the simulation model of the margin tester 102, along with DUT channel and silicon connection models, and employ statistical simulation tools to simulate expected margin results in either direction.

[0048] In some embodiments, an optional plug-in model is provided, which, if a plug-in is available for a particular DUT silicon, allows the margin tester configuration application to also configure Rx equalization settings on that DUT silicon. In some embodiments, an optional IBIS-AMI (or similar) software model is provided for each individual margin test unit, which designers and system integrators can use to incorporate into their simulations to help specific customers establish test limits / methodologies for their setups. IBIS-AMI is a serializer / deserializer (SerDes) physical layer (PHY) modeling standard that enables high-speed, accurate, and statistically significant simulations of multi-gigabit serial links. In some embodiments, the optional IBIS-AMI model is provided for the margin test unit along with a customer model (IBIS-AMI or S-parameters) and can also be used in subsequent efforts to incorporate a certain level of system, which is de-embedded for increased accuracy and repeatability. A general-purpose model of the margin tester 102 can be provided as a model used as part of manufacturing testing and characterization, i.e., a model specifically tailored for a particular margin tester 102.

[0049] Figure 8 is a block diagram of an example field-programmable gate array (FPGA) 714 configured according to an example embodiment, which can be used in the controller 210 of a margin tester 102 to test the electrical margin of the DUT's multi-lane high-speed I / O links in one or both directions, Tx and Rx.

[0050] In various embodiments, FPGA 714 may have fewer or more components than those shown, and some of the shown components or the functions of these components may be located outside or separated from FPGA 714, even if they operably communicate with FPGA 714. Illustrated is a register interface 804 operably coupled to a local area network (LAN) connection 802, which may have a SerDes. The register interface 804 is also operably coupled to a link training and status state machine (LTSSM) Rx controller 806. One of the physical layer operations of margin tester 102 is link initialization and training. In PCI Express devices, this process establishes many important tasks, including link width negotiation, link data rate negotiation, lane-by-lane bit locking, and lane-by-lane symbol locking / block alignment. All of these functions are performed by the LTSSM device, which observes stimuli and the current state of the link from a remote link partner and responds accordingly. The register interface 804 is also operablely coupled to one or more additional LTSSM controller units, such as the LTSSM Universal Serial Bus (USB) controller 808 and the additional LTSSM USB controller 810. In the illustrated embodiment, the LTSSM Rx controller 806 is operablely coupled to the PCIe physical layer (PHY) 16x SerDes 812, and the LTSSM USB controller 808 is operablely coupled to the USB / Thunderbolt / DisplayPort (USB / TBT / DP) PHY x4 unit 814.

[0051] When margin tester 102 is testing a specific protocol such as PCIe, margin tester 102 fully executes that protocol, and the link is trained to an active state by LTSSM controller units 806, 808, and 810, allowing it to track the link state. The FPGA 714 of margin tester 102 repeatedly performs margin measurements as training progresses, capturing a log of electrical margins against the link training state over time, either unidirectionally or bidirectionally.

[0052] The electrical margin for the link training state is displayed to the user by plotting time and LTSSM state on one axis and margins for each direction, lanes, etc., on the other axis. hand This is also acceptable. Figures 16A and 16B show transmit plot 1600 and receive plot 1602, which may be displayed to the user. Plot 1600 shows the margin for the LTSSM state in the Tx direction, and plot 1602 shows the margin for the LTSSM state in the Rx direction. For example, the x-axis represents the link state (L0~L n The y-axis (shown by) represents the margin, which in some examples may be defined by the area of ​​the eye.

[0053] However, the user can configure this mode in a variety of ways, for example, by setting the margin measurement time, or by configuring the DUT transmit or receiver margin measurements used in this mode (whether to use height, width, both, or a 2D eye for DUT transmit margin measurement, continuous measurement of LTSSM state changes or measurement of each LTSSM state change, or measurement of bidirectional or unidirectional DUT transmit margin height and width). An example of the technology disclosed herein generates a data log while link training is progressing on the DUT, showing (plotting) the changing values ​​to the user in coordinates, allowing the user to visualize what is happening during the test.

[0054] Additionally, there is a jitter control unit 816, either as part of the FPGA 714 or operably coupled to the FPGA 714, to control the jitter insertion unit so that the eye margin expected in the DUT's receiver can be changed to a specific target in terms of timing or voltage margin without requiring software running on the DUT.

[0055] The skew control unit 826 may be part of the FPGA 714 for programmable skew controllers, or operably coupled with the FPGA 714. Traditionally, the only test equipment capable of generating varying amounts of skew on a lane-by-lane basis across multiple lanes was the highly complex and expensive multi-lane BERT (bit error rate tester). However, multi-lane BERTs cannot perform complete training protocols such as the margin tester disclosed herein, including transmission equalization training for modern protocols like PCIe. Therefore, traditionally, there has been no way to perform lab tests with a wide variety of skews and protocols without setting up highly expensive and complex test equipment. However, an example of the technology disclosed herein allows for the addition of transmission skew on a lane-by-lane basis in numerous different ways using the skew control unit 826.

[0056] For example, the skew control unit 826 may have a programmable FIFO (First-In, First-Out) buffer with a separate length for each lane to set the amount of skew for each lane. In addition, or alternatively, the skew control unit 826 may program a variable-length transmission FIFO within the FPGA 714 fabric (structure) for each lane. In addition, or alternatively, the skew control unit 826 may have a software controller that can programmably change the length of the controller's logic circuit (logic) for each lane's transmission FIFO and provides transmitters for each physical layer.

[0057] Figure 9 is a block diagram of an example of output drive options for an FPGA (such as FPGA714) according to an exemplary embodiment, which may be used with a margin tester controller (such as controller 210) to test the electrical margin of the DUT's multi-lane high-speed I / O links in one or both directions, Tx and Rx.

[0058] The first output drive option is the FPGA direct drive option 818, which is unbuffered and does not introduce delay or jitter by a varactor (variable capacitance diode). The second output drive option is the buffered drive option 820, which has a linear buffer amplifier or limiting amplifier 826 with a differential output voltage (Vod), but does not introduce varactor delay or jitter. The third output drive option is the varactor delay introduction option 822, which has a linear buffer 826 and a varactor component 828, which result in some delay (e.g., about 3-5 picoseconds) in addition to intersymbol interference (ISI). The fourth output drive option is the jitter introduction option 824, which in one embodiment may have a linear buffer 826 (which may or may not be present) and a delay ASIC (application-specific integrated circuit) 830 (about 100 picoseconds at 32GBd) (delay ASICs are also available from ADSANTEC). In some embodiments, the linear buffer 826 is not included. For example, in embodiments that do not include a linear buffer 826, jitter introduction may be performed by introducing differential noise.

[0059] In various embodiments, the margin tester 102 may utilize various types of stress to identify a wide variety of corresponding failure modes, but these failure modes may include, without limitation, those related to assembly, interconnects (surface mount technology (SMT), packages, connectors, through-holes, vias, etc.), defects, effects of series resistance, failure modes causing ISI and baseline wonder (fluctuations), effects of eye closure, failure modes caused by factors other than width closure, functional test escapes, operator setting errors, new material, process variations, receiver bandwidth (which is analogous to interconnect variations), power supply rejection ratio (PSRR), vertical / horizontal eye closures, PLL stability, design, and lane differences. Varactor-based jitter insertion methods are particularly effective in exacerbating assembly-related defects.

[0060] Figure 10 is a flowchart of an exemplary method 1000 for margin testing a DUT according to one embodiment.

[0061] In step 1002, the margin tester 102 establishes a multi-lane high-speed I / O link for the device under test (DUT).

[0062] In 1004, the margin tester 102 evaluates the electrical margin for each high-speed input / output (I / O) lane of the multi-lane high-speed I / O link in one or both of the transmit (Tx) and receive (Rx) directions. For example, the process of evaluating the electrical margin may include introducing adjustable stress to the margin test transmitter of the multi-lane high-speed I / O link. The adjustable stress may include introducing jitter and voltage swing, which are applied simultaneously to all lanes of the multi-lane high-speed I / O link. The process of evaluating the electrical margin may also include evaluating the electrical margin simultaneously in both the transmit (Tx) and receive (Rx) directions for each high-speed input / output (I / O) lane of the multi-lane high-speed I / O link.

[0063] Figure 11 is a flowchart of an exemplary method 1100 by an embodiment for identifying potential assembly or production problems of a DUT based on a process of margin testing the electrical margins of the DUT's multi-lane high-speed I / O links in one or both of the Tx and Rx directions.

[0064] In 1102, the margin tester 102 evaluates the timing of the eye width margin for each of the multiple DUTs, with respect to each high-speed input / output (I / O) lane of the DUT's multi-lane high-speed I / O link, in either the Tx direction or both of the receive Rx direction.

[0065] In 1104, the margin tester 102 detects, based on the above evaluation, eye width margin measurements for each of the multiple DUTs at timings where the measurement consistently falls below a predetermined threshold for the same lane spanning multiple DUTs.

[0066] In 1106, the margin tester 102 identifies potential problems in the DUT design based on the detection of timing eye width margin measurements for each of the multiple DUTs at times when they consistently fall below a predetermined threshold for the same lane spanning the multiple DUTs. The above detection process may further, or alternatively, include a process based on the above evaluation to detect timing eye width margin measurements for some of the multiple DUTs at times when they fall below a predetermined threshold for different lanes spanning these several DUTs.

[0067] Figure 12 is a flowchart of an exemplary method 1200 for margin tester 102 to initiate electrical margin evaluation operation based on user-selectable options according to one embodiment.

[0068] In 1202, margin tester 102 provides user-selectable options for a margin tester configured to establish a multi-lane high-speed input / output (I / O) link of a device under test (DUT) and evaluate the electrical margin of the multi-lane high-speed I / O link in one or both of the transmit (Tx) and receive (Rx) directions. User-selectable options may include customization for evaluating the electrical margin of the multi-lane high-speed I / O link.

[0069] In 1204, the margin tester 102 is instructed to select from one or more user-selectable options for the margin tester 102.

[0070] In 1206, the margin tester 102 initiates the evaluation of the electrical margins of the multi-lane high-speed I / O link based on instructions to select from one or more user-selectable options for the margin tester 102. The user-selectable options may include, but are not limited to, one or more of the following: Select one or more different high-speed I / O protocols and use them to perform margin testing based on the DUT's multi-lane high-speed I / O links. A selectable option for testing multiple ports on the DUT using various protocols simultaneously. For multi-lane high-speed I / O links, an optional option is available to output the margin variation per execution run through any number of execution runs of the margin tester's margin test. An optional feature for implementing a fixed Tx equalization (EQ) on the DUT to test how much of the margin variation is due to variations in Tx equalization (EQ) training. A selectable option for testing the effect of receiver equalization processing on the margin of the DUT's multi-lane high-speed I / O link, using a tuned CTLE in the margin tester receiver. A selectable option for testing the effect of the receiver's equalization process on the margin of the DUT's multi-lane high-speed I / O link, using a decision feedback equalizer (DFE) in the margin tester receiver. Selectable options for calculating the expected margin for the margin tester based on the target channel. An optional feature to automatically generate debug information when low margins are detected as a result of evaluating the electrical margins of a multi-lane high-speed I / O link. A selectable option for the margin tester to switch to using a variable inter-symbol interference (ISI) signal source to determine how much ISI will cause interference in the lanes of a multi-lane high-speed I / O link. A selectable option for the margin tester to test each lane individually to identify the amount of margin loss due to crosstalk in the DUT's multi-lane high-speed I / O links. A selectable option to turn off DFE on the margin tester receiver to evaluate the margin with and without DFE, and the amount of nonlinear discontinuity in each channel associated with a multi-lane high-speed I / O link. Selectable options for margin tester characterization data that allow flagging lower-than-expected margins even when they are consistently lower than expected across all lanes of a multi-lane high-speed I / O link for one of multiple DUTs. Selectable options for choosing from multiple speeds of multi-lane high-speed I / O links and evaluating their electrical margins. A margin tester is a selectable option that allows the margin tester to perform margin testing on the production line without software on the DUT, by using protocol-specific knowledge to infer when an error occurred at the DUT's receiver based on traffic traveling in the opposite direction on a multi-lane high-speed I / O link. A selectable option for automatically capturing time-domain reflectance measurements (TDRs) of low-margin channels detected as a result of evaluating the electrical margins of multi-lane high-speed I / O links. A selectable option to automatically connect to an oscilloscope and automatically capture digitized waveforms when low margins are detected as a result of evaluating the electrical margins of a multi-lane high-speed I / O link. Selectable options for setting up a DUT with one or more user-selectable options by configuring the DUT's silicon to implement options that one or more users can select.

[0071] Figure 13 is a flowchart of an exemplary method 1300 for providing a calibrated margin tester according to one embodiment.

[0072] In 1302, the margin tester 102 provides an option to perform calibration of the margin tester 102, or may perform calibration, thereby allowing the user to receive a set of expected margins on a series of reference channels.

[0073] In 1304, a calibrated margin tester is provided, configured to measure the electrical eye margin in one or both the transmit (Tx) and receive (Rx) directions of the Device Under Test (DUT) in full operation of the DUT's normally used link without special test modes, capturing the full effects of loading and crosstalk. Individually calibrated models of the margin tester may also be provided, enabling the calculation of expected margins for one or more individualized system channels, receiver models, and transmitter models. Furthermore, the DUT silicon may be provided with a function that indicates, using vendor-defined messages or another protocol mechanism, that a margin test is about to be performed by the margin tester, allowing the DUT silicon to disable logic circuits that would reduce link width or link speed due to errors during the duration of the margin test.

[0074] A margin tester software application is also provided, which enables the margin tester to perform testing of the channel component under test (e.g., a printed circuit board (bare printed circuit board) or cable) in a test configuration, where the margin tester is used on one or both ends of the channel component under test. In some embodiments, the margin tester hardware is provided to a company that manufactures printed circuit boards (PCBs), and data related to the use of the margin tester is provided to silicon companies that supply the silicon used in the manufacture of the PCBs.

[0075] Figure 14 is a flowchart of an exemplary method 1400 for setting up a DUT to perform a margin test according to one embodiment.

[0076] In 1402, the margin tester 102 receives configuration settings related to the device under test (DUT).

[0077] In 1404, the margin tester 102 configures the DUT to perform margin testing under various conditions relating to the DUT's silicon. The margin tester 102 may receive a software plug-in that enables the configuration for the margin tester 102 to perform margin testing under various conditions relating to the DUT's silicon, along with parameters of the DUT silicon. These DUT silicon parameters may, but are not limited to, include one or more parameters related to the receiver's continuous time (CTLE) and parameters related to the DFE.

[0078] Figure 15 shows an example of a margin tester 102 with a self-calibration function. Calibration of the margin tester 102 can be performed by electrically connecting the transmitter to the receiver. This can be done, for example, by electrically connecting a switch within the margin tester 102 to the transmitter within the same margin tester 102. This eliminates the need for external test equipment.

[0079] Figure 15 is similar to the lower-level block diagram of Figure 7. Similar to Figure 7, Figure 15 is a lower-level block diagram of a margin tester 102 for testing the electrical margin of the DUT's multi-lane high-speed I / O link in both the Tx and Rx directions, and additionally, it has a self-calibration function. To perform self-calibration, one or more switches 1500 are provided to connect each of the transmitters in the HSIO output unit 702 to each of the receivers in the HSIO input unit 704. These transmitters can output signals, and these receivers can receive signals to determine whether the margin tester 102 is within the desired range. For simplicity of explanation, Figure 15 illustrates a single switch 1500, but as those skilled in the art will see, multiple switches 1500 may be provided to connect multiple transmitters to multiple receivers. Instead of switches 1500, a calibration device or fixture may be provided at the I / O connector 706 to loop back the transmitters to the receivers and perform self-calibration.

[0080] Various operating modes may be provided for calibrating the margin tester 102. For example, self-calibration may only be performed in a factory equipped with a special loopback fixture that allows the transmitter to be connected to the receiver via one or more I / O connectors 706.

[0081] Another operating mode that may be provided is one in which the end user performs a self-test of the margin tester 102. This can be done by activating switch 1500 or by inserting a fixture that allows the transmitter to be routed to the receiver of the margin tester 102. During the self-test, the margin tester 102 may output information to the front panel indicator 712 if the result exceeds a specified range.

[0082] In some cases, calibration can be performed in protocol mode, non-protocol mode of the PRBS pattern, or both. However, in protocol mode, the I / O connector 706 may not be able to function as both the host and the test device simultaneously. If the margin tester 102 has two sets of I / O connectors 706, the margin tester 102 may need to be connected to two different I / O connectors 706, or a second margin tester 102 may need to be connected.

[0083] Internal calibration offers faster and potentially lower-cost factory calibration for the Margin Tester 102 compared to conventional equipment. This internal calibration also allows end-users to perform their own calibration tests.

[0084] The advantages, effects, and improvements of the disclosed embodiments include, but are not limited to, the following: Some embodiments can be implemented almost entirely with off-the-shelf components, including standard FPGAs and sinusoidal jitter introduction chips or delay lines, and are significantly less expensive than conventional BERT and oscilloscopes. Examples of embodiments can be run on a full multi-lane link operating under normal operating conditions without requiring special software, and capture any effects resulting from all lanes operating simultaneously. Another effect is that embodiments of the disclosed technology can be tested in one direction or both directions (Tx and Rx) with a single self-contained unit. Various embodiments can also be run in a production environment (e.g., a motherboard production testing environment) without requiring software on the DUT or modifications to the DUT. Different logic for specific tests per protocol may be provided in the form of silicon / firmware for the margin tester 102, allowing the DUT receiver to recognize very quickly when an error has occurred based on the data sent back by the device under test to the margin tester. In some exemplary embodiments, a margin test is about to be performed, and the DUT silicon may have a function implemented in its form to recognize, through PCI Express vendor-specific messages or other standard protocol functions, that the DUT silicon is in a state where errors would not normally cause a reduction in link width or link speed. This is useful for ensuring that the process of setting a margin in the DUT receiver using noise introduction or voltage swing adjustment is performed without the risk of link width or link speed reduction due to the normal protocol mechanisms. This is an alternative to special logic circuits that can quickly infer when an error has started and reduce stress before a link or speed reduction occurs.

[0085] Another improvement provided by the embodiments described herein is that, since each margin tester unit among the multiple margin tester units is individually calibrated and its characteristics are measured, the user can know the expected margin value for each particular unit and flag it if the difference from the expected value across the user's multiple prototype and production units is minimal. As part of this individual characterization and calibration, a model such as the IBIS-AMI model is provided to each of the individual margin testers 102 so that the end user can calculate the expected margin for a particular channel model based on simulated or measured S-parameters.

[0086] This disclosure describes an innovative margin tester that is extremely fast and easy to use. Convenient and efficient configuration software is provided for length margin measurement and various user-configurable options. Once configured, the margin tester 102 calls a link as any standard device and then automatically performs measurements on the operating link. Testing is performed simultaneously on all lanes, enabling rapid electrical margin scans in milliseconds. This allows for high-volume testing, including full testing of all high-speed I / O ports and lanes. Various embodiments provide, but are not limited to, a variety of margin testing modes that enable a certain level of problem characterization without the need for conventional equipment. The number of iterations and analysis of the variability per execution of the likelihood of the training problem in the DUT's Tx or Rx training algorithm, including the margin, the selected Tx equalization process (for both the DUT and the margin tester), the selected Rx equalization process (for the margin tester's receiver), and the likelihood of the training problem in the DUT's Tx or Rx training algorithm. A process to adjust the transmitter equalization process using one of the methods and observe its effect on the margin. This process adjusts (fixes) the receiver equalization process (CTLE) and the number of DFE taps (including zeros) in the margin tester's receiver, and observes the effect on the margin value. These are some examples. For instance, a significant change in margin when DFE is off indicates a significant discontinuity in a particular channel.

[0087] Another benefit offered by the various embodiments of the margin tester 102 is the ability to test electrical margins for all high-speed I / O ports and lanes of a particular DUT, through all prototype units and in actual production, creating an unprecedented ability to flag problems and potential issues before production or before delivery to the customer. Furthermore, the various embodiments also allow for margin analysis before and after various link events, such as power state transitions (in some cases using software on the DUT).

[0088] Conventional solutions include highly versatile and advanced jitter and noise injection methods. The various embodiments of this disclosure offer advantages over these solutions by significantly simplifying (but not eliminating) the required task of jitter / amplitude stress. This simplicity leads to reduced operating costs, faster results, and improved product reliability (through the collection of large data sets) compared to what is required using existing methods.

[0089] Embodiments of the disclosed technology can operate on a specially programmed general-purpose computer, including specially created hardware, firmware, digital signal processors, or processors that operate according to programmed instructions. The terms “controller” or “processor” in this application mean microprocessors, microcomputers, ASICs, and dedicated hardware controllers, etc. Embodiments of the disclosed technology can be implemented by one or more computers (including monitoring modules) or other devices, using computer-readable data such as program modules and computer-executable instructions. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform specific tasks or implement specific abstract data formats. Computer-executable instructions may be stored on computer-readable storage media such as hard disks, optical disks, removable storage media, solid-state memory, RAM, etc. As will be understood by those skilled in the art, the functions of the program modules may be combined or distributed as needed in various embodiments. Furthermore, these functions can be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits or field-programmable gate arrays (FPGAs). One or more aspects of the disclosed technology can be more effectively implemented using specific data structures, such data structures are considered to be within the scope of computer-executable instructions and computer-usable data described herein.

[0090] The disclosed embodiments may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored in one or more computer-readable media that can be read and executed by one or more processors. Such instructions may be referred to as computer program products. The computer-readable media described herein means any medium accessible by a computing device. For example, but not limited to, computer-readable media may include computer storage media and communication media.

[0091] Computer storage media means any medium that can be used to store computer-readable information. Examples of computer storage media include, but are not limited to, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), DVD (Digital Video Disc) and other optical disc storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices and other magnetic storage devices, and any other volatile or non-volatile removable or non-removable media implemented by any technology. Computer storage media exclude signals themselves and temporary forms of signal transmission.

[0092] A communication medium means any medium that can be used for the communication of computer-readable information. Examples of communication mediums, though not limited to them, include coaxial cables, fiber optic cables, air, or any other medium suitable for the communication of electrical, optical, radio frequency (RF), infrared, sound, or other forms of signals.

[0093] In addition, the description of this application refers to certain features. It should be understood that the disclosures herein include all possible combinations of these specific features. Where a particular feature is disclosed in relation to a particular aspect or example, that feature may, to the extent possible, also be used in relation to other aspects and examples.

[0094] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, as long as the circumstances do not rule out such possibilities.

[0095] For the sake of explanation, specific embodiments of the present invention have been illustrated and described, but it should be understood that various modifications are possible without deviating from the gist and scope of the present invention. Therefore, the present invention should not be limited to anything other than the appended claims. [Explanation of symbols]

[0096] 102 Margin Tester 104 Device under test (DUT) 106 Display device 108 Eye Pattern Display 110 Multi-lane high-speed I / O link 202 PCI Express Add-in Card Margin Tester 204 Motherboard under test 206 PCI Express Motherboard Slots 208 connector 210 Controller 212 PCB 214 memory 302 Motherboard Margin Tester for Specific Technologies 304 Add-in Card DUT 306 PCI Express slots 312 PCB 602 General-purpose margin tester 604 Interface 702 HSIO Output Unit 704 HSIO Input Unit 706 I / O connector 708-hour reference unit 710 Support Unit 712 Front panel indicators 714 FPGA 716 AC / DC Power Supply Unit 802 Local Area Network (LAN) Connection 804 Register Interface 806 LTSSM Rx Controller 808 USB Controller 810 USB Controller 812 PCIe Physical Layer (PHY) 16x SerDes 814 USB / Thunderbolt / DisplayPort (USB / TBT / DP) PHY x4 Units 816 Jitter Control Unit 818 FPGA Direct Drive Option 820 Buffering Drive Option 822 Varactor Delay Introduction Option 824 Jitter Introduction Option 826 Linear buffer or limiting amplifier 828 Varactor Components

Claims

1. A method for testing the electrical margin of a device under test (DUT), The process of connecting the above DUT to multiple lanes of the margin tester, The process involves establishing a multi-lane high-speed I / O link with the DUT through the above-mentioned multiple lanes, The above margin tester measures the electrical margin for each high-speed input / output (I / O) lane of the multi-lane high-speed I / O link in one or both of the transmission (Tx) and reception (Rx) directions. When measuring the above electrical margin, a process is performed to capture a log of the electrical margin relative to the link training state, The process involves displaying a graph with the above link training status as the first axis and the above measured electrical margin as the second axis. An electrical margin testing method that includes [the following].

2. The electrical margin testing method according to claim 1, further comprising a process of changing the amount of skew for each lane when evaluating the above electrical margin.

3. A margin tester, One or more lanes configured to be coupled to the device under test (DUT), Display device and A single-lane or multi-lane high-speed input / output (I / O) link is established with the DUT through one or more of the lanes mentioned above. The above margin tester measures the electrical margin of the single-lane or multi-lane high-speed I / O link in one or both of the transmit (Tx) and receive (Rx) directions. While measuring the above electrical margin, capture the log of the electrical margin relative to the link training state. The display device will show a graph on which the above-mentioned link training status is the first axis and the above-mentioned measured electrical margin is the second axis. One or more controllers configured as follows A margin tester equipped with [a specific feature].

4. The margin tester according to claim 3, wherein one or more of the above-mentioned controllers are further configured to function as a root complex or endpoint to establish a single-lane or multi-lane high-speed I / O link with the DUT at the margin tester.

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