Power supply system

Abstract

To provide a power supply system that enables effective parallel operation in applications where linear power supply devices are connected in parallel.SOLUTION: A power supply system (5) includes a plurality of linear power supply devices (1A) including an electrode pad (P1A) that is connected to a node where a second main electrode of an output transistor (M1A) and a first feedback resistor (R1A) are connected, the electrode pad being connected to an output terminal (ToA) by a wire (W1A). The output terminals can be commonly connected to a load (RL).SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This disclosure relates to a power supply system.

Background Art

[0002] Conventionally, linear power supply devices (linear regulators) capable of generating a desired output voltage from an input voltage have been mounted in various applications (such as in-vehicle devices, industrial devices, office equipment, digital household appliances, or portable devices).

[0003] Some linear power supply devices use two linear power supply devices and commonly connect output terminals for outputting the output voltages of the respective linear power supply devices to a common load (for example, Patent Document 1). That is, such linear power supply devices are connected in parallel to a common load. The purpose of such a linear power supply device is to perform heat dissipation by dispersing the load current into the output current output from the output terminals, or to increase the load current to a large current based on the output current output from each output terminal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when linear power supply devices are connected in parallel as described above, a difference may occur in the output voltages output from the respective output terminals due to the influence of variations in the linear power supply devices. In this case, an output current is not output from the linear power supply device with the lower output voltage, and a phenomenon occurs where the load current is supplied only by the output current of the linear power supply device with the higher output voltage. As a result, there is a risk that the parallel connection of the linear power supply devices may be meaningless.

[0006] In light of the above circumstances, this disclosure aims to provide a power supply system that enables effective parallel operation in applications involving the parallel connection of linear power supply units. [Means for solving the problem]

[0007] For example, the power supply system relating to this disclosure is An output transistor having a first main electrode configured to be connectable to the input voltage application terminal, and a second main electrode configured to be connectable to the first feedback resistor in a first feedback resistor and a second feedback resistor connected in series, An error amplifier is configured to receive a feedback voltage generated at the node where the first feedback resistor and the second feedback resistor are connected, and a reference voltage, and to drive the control terminal of the output transistor. Output terminals, Electrode pads and Equipped with, The electrode pad is connected to the node to which the second main electrode and the first feedback resistor are connected. Multiple linear power supply units are provided, with the electrode pads and output terminals connected by wires. The aforementioned output terminals are configured to be connectable to a common load. [Effects of the Invention]

[0008] According to the power supply system described herein, it becomes possible to effectively perform parallel operation in applications involving the parallel connection of linear power supply units. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows the configuration of a power supply system related to a comparative example. [Figure 2] Figure 2 shows the configuration of a linear power supply unit according to a reference example. [Figure 3] Figure 3 shows the configuration of a power supply system according to an exemplary embodiment of the present disclosure. [Figure 4] Figure 4 shows the configuration of a linear power supply according to one modified example. [Figure 5] Figure 5 shows a first configuration example related to reference voltage adjustment. [Figure 6] Figure 6 shows a second example configuration related to reference voltage adjustment. [Modes for carrying out the invention]

[0010] <1. Comparative Example> Before describing a novel embodiment of a linear power supply, we will first describe comparative examples that are comparable to it.

[0011] Figure 1 shows the configuration of a power supply system 50 according to a comparative example. The power supply system 50 comprises a linear power supply unit 10A, a linear power supply unit 10B, and ballast resistors Ra and Rb. The power supply system 50 supplies load current Iout to the load RL using the two linear power supply units 10A and 10B.

[0012] Linear power supplies 10A and 10B are linear regulators that step down the input voltage Vin to generate the desired output voltages VoA and VoB, respectively. Linear power supplies 10A and 10B are identical semiconductor IC (Integrated Circuit) packages, and their corresponding components are indicated by the same symbol followed by "A" or "B". The configuration of linear power supply 10A will be described below as a representative example.

[0013] As shown in Figure 1, the linear power supply unit 10A comprises an output transistor M10A, feedback resistors R11A and R12A, and an error amplifier AP10A, all of which are integrated and packaged onto a single chip.

[0014] The source of the output transistor M10A configured as a PMOS transistor (P-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) is connected to the input terminal of the input voltage Vin. The drain of the output transistor M10A and the first terminal of the feedback resistor R11A are commonly connected to an output terminal ToA for outputting the output voltage VoA. The second terminal of the feedback resistor R11A is connected to the first terminal of the feedback resistor R12A. The second terminal of the feedback resistor R12A is connected to the ground terminal. The non-inverting input terminal (+) of the error amplifier AP10A is connected to the connection node where the feedback resistors R11A and R12A are connected (= the applied terminal of the feedback voltage VfbA). The inverting input terminal (-) of the error amplifier AP10A is connected to the applied terminal of the reference voltage VrefA. The output terminal of the error amplifier AP10A is connected to the gate of the output transistor M10A.

[0015] The error amplifier AP10A described above controls the gate of the output transistor M10A so that the feedback voltage VfbA (= VoA × {R12A / (R11A + R12A)}) corresponding to the output voltage VoA matches a predetermined reference voltage VrefA. That is, the on-resistance value of the output transistor M10A is continuously controlled so that the output voltage VoA matches its target value (= VrefA × {(R11A + R12A) / R12A}).

[0016] Similarly, in the linear power supply device 10B, the on-resistance value of the output transistor M10B is continuously controlled so that the output voltage VoB matches its target value.

[0017] The output terminal ToA is connected to the first terminal of a ballast resistor Ra provided outside the linear power supply devices 10A and 10B. The output terminal ToB is connected to the first terminal of a ballast resistor Rb provided outside the linear power supply devices 10A and 10B. The second terminals of the ballast resistors Ra and Rb are commonly connected to the load RL. Therefore, the linear power supply devices 10A and 10B are connected in parallel to a common load RL.

[0018] Here, although the standard values (Typ values) of the output voltages VoA and VoB of the linear power supply devices 10A and 10B are set to be the same, due to variations in the linear power supply devices, the output voltage may vary with respect to the standard value. For example, it may vary by ±2% with respect to the standard value of 5V. Such variations are caused by, for example, variations in the reference voltage, feedback voltage, or threshold voltage of the output transistor, and further variations in the input offset voltage of the error amplifier.

[0019] In the case of a configuration where the output terminals ToA and ToB are directly connected, if, for example, the output voltage VoA is higher than VoB due to variations, the output transistor M10B on the linear power supply device 10B side remains off, and the output current IoutB is not output from the output terminal ToB. The load current Iout is supplied only by the output current IoutA output from the output terminal ToA in the linear power supply device 10A. Therefore, the output current concentrates on one side of the linear power supply device.

[0020] On the other hand, in the configuration according to this comparative example shown in FIG. 1, for example, when the output voltage VoA is higher than VoB, as the load current Iout gradually increases from 0A, the output voltage VoA is voltage - dropped by the resistor Ra, and the output voltage Vo generated at the node to which the second ends of the ballast resistors Ra and Rb are connected gradually decreases. When the output voltage Vo reaches the output voltage VoB, the output transistor M10B on the linear power supply device 10B side starts to operate, and the output of the output current IoutB from the output terminal ToB is started. That is, a parallel operation in which the load current Iout is supplied by both of the output currents IoutA and IoutB is started. The ballast resistors Ra and Rb may be set to a resistance value such that the voltage drop in the resistor is not less than the voltage difference between the maximum value and the minimum value due to the variation of the output voltage.

[0021] Thus, with the configuration of this comparative example, parallel operation is possible even when there are variations in output voltage when two linear power supplies are connected in parallel. However, in this comparative example, the resistance values ​​of the ballast resistors Ra and Rb were large, resulting in low load regulation (stableness of output voltage with respect to load current).

[0022] <2.Reference example> Here, Figure 2 shows the configuration of a linear power supply unit 100 according to a reference example. The linear power supply unit 100 is a packaged configuration that integrates an output transistor M100, feedback resistors R110 and R120, and an error amplifier AP100. In the linear power supply unit 100, the drain of the output transistor N100 is connected to electrode pad P11. Electrode pad P11 is connected to the output terminal To, which is an external terminal, via wire W11. The first end of the feedback resistor R110 is connected to electrode pad P12. Electrode pad P12 is connected to the output terminal To via wire W12.

[0023] With this configuration, the output voltage Vo generated at the output terminal To is controlled by feedback resistors R110 and R120, taking into account the voltage drop caused by the current flowing through the output transistor M100 and the impedance of wire W11, thereby improving the accuracy of the output voltage Vo.

[0024] <3. Embodiments of the Disclosure> Figure 3 shows the configuration of a power supply system 5 according to an exemplary embodiment of the present disclosure. The power supply system 5 includes a linear power supply unit 1A and a linear power supply unit 1B. Linear power supply units 1A and 1B are semiconductor IC packages with the same configuration, and their corresponding components are shown with the same reference numerals, "A" or "B". The configuration of linear power supply unit 1A will be described in a representative manner below.

[0025] Linear power supply unit 1A is a packaged unit that integrates the output transistor M1A, feedback resistors R1A and R2A, and error amplifier AP1A. Linear power supply unit 1A also has external terminals such as the output terminal ToA and the reference voltage terminal TrefA.

[0026] In contrast to the previously mentioned example (Figure 2), in linear power supply unit 1A, the node to which the drain of output transistor M1A and the first terminal of feedback resistor R1A are connected is connected to electrode pad P1A. Electrode pad P1A is connected to output terminal ToA via wire W1A. Also, the application terminal of the reference voltage VrefA input to error amplifier AP1A is connected to reference voltage terminal TrefA.

[0027] The output terminals ToA of linear power supply unit 1A and ToB of linear power supply unit 1B are commonly connected to the load RL. In other words, linear power supplies 1A and 1B are connected in parallel to the load RL.

[0028] In linear power supply unit 1A, the output voltage VoA generated at electrode pad P1A is controlled to match its target value (=VrefA × {(R1A + R2A) / R2A}). In linear power supply unit 1B, the output voltage VoB generated at electrode pad P1B is controlled to match its target value (=VrefB × {(R1B + R2B) / R2B}).

[0029] Assume that due to variations in reference voltages VrefA and VrefB, the output voltage VoA is higher than the output voltage VoB. In this case, when the load current Iout starts flowing, the output current IoutB is not output from output terminal ToB, and the load current Iout is supplied only by the output current IoutA output from output terminal ToA.

[0030] As the load current Iout increases, the voltage at output terminal ToA decreases due to the voltage drop across wire W1A in linear power supply unit 1A. However, because the impedance of wire W1A is small, if the difference between VoA and VoB varies greatly, the voltage at output terminal ToA may not reach VoB even when the load current Iout reaches a steady state. Therefore, in the configuration shown in Figure 3, the reference voltage terminals TrefA and TrefB are connected externally to linear power supplies 1A and 1B. This ensures that even if there is variation in the reference voltages VrefA and VrefB, one of them takes priority in controlling the output voltages VoA and VoB, thereby reducing the difference between the output voltages VoA and VoB. Consequently, even with the low-impedance wire W1A, the voltage at output terminal ToA can reach VoB. Once the voltage at output terminal ToA reaches VoB, the output current IoutB begins to flow, and parallel operation commences. At this time, the output currents IoutA and IoutB are controlled to be nearly equal.

[0031] Thus, according to this embodiment, parallel operation is possible by utilizing the voltage drop across wires W1A and W1B inside the semiconductor package, and since the wires have low impedance, load regulation is improved.

[0032] If Au wires are used for wires W1A and W1B, the wire impedance will be relatively high, allowing the use of low-sensitivity error amplifiers AP1A and AP1B. Alternatively, if Cu wires are used for wires W1A and W1B, costs can be reduced.

[0033] Furthermore, as shown in Figure 4, multiple wires W1 may be connected in parallel between the electrode pad P1 and the output terminal To. This reduces the impedance of the wires and improves load regulation.

[0034] Furthermore, if the reference voltages VrefA and VrefB can be adjusted as described later, it is not necessarily required to connect the reference voltage terminals TrefA and TrefB externally.

[0035] Figure 5 shows an example of a configuration for adjusting the reference voltage Vref using fuses. As shown in Figure 5, the variable resistor Rd has resistors Rd0 to Rdm connected in series between the lead end and the power supply end of the reference voltage Vref, and trimming fuses Fd1 to Fdm connected in parallel with resistors Rd1 to Rdm. The variable resistor Re has resistors Re0 to Ren connected in series between the lead end and the ground end of the reference voltage Vref, and trimming fuses Fe1 to Fen connected in parallel with resistors Re1 to Ren.

[0036] This configuration allows for adjusting the resistance ratio of the variable resistors Rd and Re (and consequently the voltage value of the reference voltage Vref) by appropriately laser-cutting the fuses Fd1 to Fdm and Fe1 to Fen.

[0037] Figure 6 shows an example of a configuration for adjusting the reference voltage Vref using OTP (One Time Programmable) memory. The OTP memory 6 shown in Figure 6 is a memory that can only be written to once. Multiple N resistors R1_1 to R1_N are connected in series between the power supply terminal and the ground terminal. Multiple N bypass switches M1_1 to M1_N are connected in parallel to each of the resistors R1_1 to R1_N. The reference voltage Vref is drawn from somewhere along the resistors R1_1 to R1_N and the bypass switches M1_1 to M1_N.

[0038] The bypass switches M1_1 to M1_N are switched on / off according to the data written to OTP6, and the reference voltage Vref is adjusted by setting the voltage division ratio.

[0039] <4. Others> Furthermore, various technical features relating to this disclosure can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered illustrative and not restrictive in all respects, and the technical scope of the present invention should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above. Moreover, the embodiments described above may be combined as appropriate, as long as they do not contradict each other.

[0040] <5. Addendum> As described above, for example, the power supply system (5) relating to this disclosure is An output transistor (M1A) having a first main electrode configured to be connectable to the input voltage (Vin) application terminal, and a second main electrode configured to be connectable to the first feedback resistor in a first feedback resistor (R1A) and a second feedback resistor (R2A) connected in series, An error amplifier (AP1A) is configured to receive a feedback voltage (VfbA) generated at the node where the first feedback resistor and the second feedback resistor are connected, and a reference voltage (VrefA), and to drive the control terminal of the output transistor. Output terminal (ToA), Electrode pad (P1A), Equipped with, The electrode pad is connected to the node to which the second main electrode and the first feedback resistor are connected. The electrode pads and the output terminals are connected by a wire (W1A), and the system includes multiple linear power supply units (1A). The aforementioned output terminals are configured to be connectable to a common load (RL).

[0041] Furthermore, in the first configuration described above, the linear power supply (1A) further comprises a reference voltage terminal (TrefA) connected to the application terminal of the reference voltage (VrefA), The aforementioned reference voltage terminals may be configured to be externally connectable (second configuration).

[0042] Furthermore, in the first or second configuration described above, the wire (W1A) may include an Au wire (third configuration).

[0043] Furthermore, in any of the first to third configurations described above, the wire (W1A) may include a Cu wire (fourth configuration).

[0044] Furthermore, in any of the first to fourth configurations described above, the wire (W1A) may be connected in parallel between the electrode pad (P1A) and the output terminal (ToA) (fifth configuration).

[0045] Furthermore, in any of the first to fifth configurations described above, the reference voltage (VrefA) may be adjustable using a voltage divider resistor (Rd1 to Rdm, Re1 to Ren) in which laser-bluntable fuses (Fd1 to Fdm, Fe1 to Fen) are connected in parallel (sixth configuration).

[0046] Furthermore, in any of the first to fifth configurations described above, the reference voltage (VrefA) may be adjustable by switching bypass switches (M1_1 to M1_N) connected in parallel to the voltage divider resistors (R1_1 to R1_N) based on data written to the OTP memory (6) (seventh configuration). [Industrial applicability]

[0047] This disclosure can be used in power supply systems installed in various devices. [Explanation of Symbols]

[0048] 1A, 1B Linear Power Supply 5. Power System 6 OTP memory 10A, 10B Linear Power Supply 50 Power Systems 100 Linear Power Supply AP100 Error Amplifier AP10A Error Amplifier AP1A, AP1B Error Amplifier M100 Output Transistor M10A Output Transistor M10B Output Transistor M1A Output Transistor P1 Electrode Pad P11 Electrode Pads P12 Electrode Pads P1A Electrode Pads P1B Electrode Pads R1 Resistor R110, R120 Feedback resistors R11A Feedback resistor R11A,12A Feedback resistors R1A, R2A Feedback resistors RL load Ra resistance Ra ballast resistor Ra, Rb ballast resistors ToA, ToB output terminals To output terminal TrefA, TrefB Reference voltage terminals W1 Wire W11 Wire W12 wire W1A, W1B wires

Claims

1. A power supply system comprising a plurality of linear power supply units, Each of the aforementioned multiple linear power supply units is a semiconductor IC package having the same configuration. Each of the aforementioned plurality of linear power supply units is An output transistor having a first main electrode configured to be connectable to the input voltage application terminal, and a second main electrode configured to be connectable to the first feedback resistor in a first feedback resistor and a second feedback resistor connected in series, An error amplifier is configured to receive a feedback voltage generated at the node where the first feedback resistor and the second feedback resistor are connected, and a reference voltage, and to drive the control terminal of the output transistor. Output terminals, Electrode pads and A reference voltage terminal directly connected to the application terminal of the reference voltage input to the error amplifier, Equipped with, In each of the plurality of linear power supply units, the electrode pad is connected to the node to which the second main electrode and the first feedback resistor are connected. In each of the aforementioned linear power supply units, the electrode pads and the output terminals are connected by wires. Each of the output terminals of the plurality of linear power supply units can be commonly connected to a load. The reference voltage terminal of each of the plurality of linear power supply units is an externally connectable power supply system.

2. The power supply system according to claim 1, wherein the wire includes an Au wire.

3. The power supply system according to claim 1, wherein the wire includes a Cu wire.

4. The power supply system according to claim 1, wherein the wire is connected in parallel between the electrode pad and the output terminal.

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