Method for manufacturing a semiconductor device and a semiconductor device.

Abstract

To provide a manufacturing method for a semiconductor device, in which both the increase in capacitance of a capacitor and the reduction in leak current can be achieved, and a semiconductor device.SOLUTION: A manufacturing method for a semiconductor device includes the steps of: forming a lower electrode on a substrate; forming a high dielectric constant film made of an oxide containing a tetravalent metal cation on the lower electrode; forming an oxide film made of an oxide containing a pentavalent cation on the high dielectric constant film; causing a reaction between the high dielectric film and the oxide film, thereby forming a mixture layer with conductivity in which the oxide containing the tetravalent metal cation and the oxide containing the pentavalent metal cation are mixed; and forming an upper electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure relates to a method for manufacturing a semiconductor device and to a semiconductor device. [Background technology]

[0002] Capacitors used in DRAMs and the like typically have a lower electrode, a high dielectric constant film, and an upper electrode formed on a substrate in that order. Patent Document 1 describes a capacitor using zirconium oxide as the high dielectric constant film.

[0003] Furthermore, Patent Document 2 describes a device comprising a first dielectric film containing tantalum oxide or niobium oxide, a second dielectric film provided between the lower electrode and the first dielectric film, and a third dielectric film between the first dielectric film and the upper electrode. It also describes the use of zirconium oxide or the like as the second and third dielectric films. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2001-152339 [Patent Document 2] Japanese Patent Publication No. 2004-266009 [Overview of the project] [Problems that the invention aims to solve]

[0005] This disclosure provides a method for manufacturing a semiconductor device and a semiconductor device that can achieve both high capacitance and low leakage current of the capacitor. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes a step of forming a lower electrode on a substrate, a step of forming a high dielectric constant film made of an oxide containing a tetravalent metal cation on the lower electrode, a step of forming an oxide film made of an oxide containing a pentavalent metal cation on the high dielectric constant film, and a step of reacting the high dielectric constant film and the oxide film to form a conductive mixed layer in which the oxide containing the tetravalent metal cation and the oxide containing the pentavalent metal cation are mixed, and a step of forming an upper electrode.

Advantages of the Invention

[0007] According to the present disclosure, there are provided a method for manufacturing a semiconductor device and a semiconductor device that can achieve both high capacitance and low leakage current of a capacitor.

Brief Description of the Drawings

[0008] [Figure 1] It is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 2] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] It is a diagram showing the relationship between CET and leakage current in a conventional ZrO2 single-layer capacitor. [Figure 4] It is a cross-sectional view showing a part of the structure of a conventional capacitor. [Figure 5] It is a diagram showing the distribution of the calculated density of states (DOS) when 5 out of 16 sites of Ti in TiO2 are replaced with Zr. [Figure 6] It is a diagram showing the relationship between the number of Zr atoms replacing the Ti sites in TiO2 and the band gap. [Figure 7] It is a diagram showing the distribution of the calculated density of states (DOS) when the number of substitutions of Zr for Nb sites in Nb2O5 is 0 and 8. [Figure 8] It is a diagram showing the relationship between the number of Zr atoms replacing the Nb sites in Nb2O5 and the band gap. [Figure 9]This figure shows the results of actually manufacturing a semiconductor device (capacitor) according to the first embodiment and determining its characteristics. [Figure 10] This is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 11] This is a cross-sectional view showing a part of the process of the method for manufacturing a semiconductor device according to the second embodiment. [Figure 12] This figure shows the calculated density of states (DOS) distribution when the number of Zr substitutions at 4 of the 28 Nb sites in oxygen-deficient Nb12O29 relative to Nb2O5 is 4. [Figure 13] This figure shows the relationship between the number of Zr atoms substituting the Nb sites in Nb12O29 and the band gap, compared to the case where the Nb sites in Nb2O5 are substituted with Zr atoms. [Figure 14] This figure shows the relationship between the number of Zr atoms substituting Ti sites in Ti9O17 and the band gap, compared to the case where Ti sites in TiO2 are substituted with Zr atoms. [Figure 15] This figure shows the results of actually manufacturing a semiconductor device (capacitor) according to the second embodiment and determining its characteristics. [Figure 16] This is a flowchart showing a method for manufacturing a semiconductor device according to the third embodiment. [Figure 17] This is a cross-sectional view showing a part of the process of a semiconductor device manufacturing method according to the third embodiment. [Figure 18] This figure shows the results of actually manufacturing a semiconductor device (capacitor) according to the third embodiment and determining its characteristics. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the attached drawings.

[0010] <First Embodiment> First, the first embodiment will be described. Figure 1 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment, and Figure 2 is a cross-sectional view of the process.

[0011] In this embodiment, first, a lower electrode 102 is formed on the substrate 101 (step ST1, Figure 2(a)). The substrate 101 is not particularly limited, but a semiconductor substrate, such as a Si substrate, is an example. The lower electrode 102 may be a TiN film. In addition to a TiN film, a TiSiN film, TiAlN film, TiMeN (Me: transition metal) film, W film, Mo film, or Ru film can also be used as the lower electrode 102. The lower electrode 102 can be formed by CVD, ALD, or PVD (sputtering).

[0012] Next, a high-dielectric constant film (High-k film) 103 made of an oxide containing tetravalent metal cations is formed on the lower electrode 102 as a capacitance film (Step ST2, Figure 2(b)). The High-k film 103 made of an oxide containing tetravalent metal cations may be a ZrO2 film or an HfO2 film. The High-k film 103 can be deposited by CVD, ALD, or PVD (sputtering). The thickness of the High-k film 103 may be in the range of 2 to 10 nm.

[0013] Next, an oxide film 104 made of an oxide containing a pentavalent metal cation is formed on the High-k film 103 (Step ST3, Figure 2(c)). The oxide film 104 made of an oxide containing a pentavalent metal cation may be an Nb2O5 film, a Ta2O5 film, or a V2O5 film. The oxide film 104 can be deposited by CVD, ALD, or PVD (sputtering). The thickness of the oxide film 104 may be 1 nm or less.

[0014] Next, the High-k film 103 and the oxide film 104 are reacted at the interface to form a conductive mixed layer 105 in which an oxide containing a tetravalent metal cation and an oxide containing a pentavalent metal cation are mixed (Step ST4, Figure 2(d)). The mixed layer 105 can be formed as a reaction layer during annealing for crystallization of the High-k film 103. For example, if the High-k film 103 is a ZrO2 film and the oxide film 104 is an Nb2O5 film, annealing causes diffusion of Zr and Nb, forming a conductive mixed layer 105 containing NbZrO x A layer is formed. The annealing temperature may be in the range of 250 to 600°C. The annealing time may be 120 minutes or less. The composition of the mixed layer 105 can be adjusted by the temperature and time during annealing, and it can become conductive by increasing the amount of Zr.

[0015] Next, an upper electrode 106 is formed on the mixed layer 105 or oxide film 104 (step ST5, Figure 2(e)). The upper electrode 106 may be a TiN film. In addition to a TiN film, a TiSiN film, TiAlN film, TiMeN (Me: transition metal) film, W film, Mo film, or Ru film can also be used as the upper electrode 106. The upper electrode 106 can be deposited by CVD, ALD, or PVD (sputtering).

[0016] After forming the upper electrode 106, annealing is performed to remove damage and other imperfections, and the process is completed. Even with this annealing, it is unlikely that a mixed layer will form between the upper electrode 106 and the mixed layer 105 due to atomic diffusion.

[0017] In this embodiment, the formation of the mixed layer 105 in step ST4 may be performed after the formation of the upper electrode 106 in step ST5.

[0018] The semiconductor device manufactured in this manner is used as a capacitor, typically as a capacitor in a DRAM.

[0019] As shown in Figure 2(e), the semiconductor device manufactured by the method of this embodiment includes a lower electrode 102 formed on a substrate 101, a High-k film 103 made of an oxide containing a tetravalent metal cation formed on the lower electrode 102, a mixed layer 105 formed on the High-k film 103, and an upper electrode 106 formed thereon.

[0020] In this embodiment, the mixed layer 105 is composed of a combination of tetravalent and pentavalent metal cations, and as described later, defects are generated to satisfy the charge neutrality condition, making it conductive. The formation of a conductive mixed layer 105 reduces the thickness of the dielectric portion, thereby reducing the CET (Capacitance Equivalent Thickness) and increasing the capacitance. In addition, the presence of the mixed layer 105 can also reduce the leakage current.

[0021] The details are explained below. Recently, as LSIs have become more highly integrated and faster, the design rules for semiconductor elements constituting LSIs are becoming increasingly miniaturized. Consequently, the capacitance of capacitors used in DRAMs, for example, is tending to decrease, and an increase in capacitance is required. In a capacitor like the one shown in Patent Document 1, where a single layer of high-k ZrO2 film is provided as a dielectric film between TiN electrodes, the capacitance can be increased by reducing the CET by thinning the ZrO2 film. However, thinning the ZrO2 film increases the leakage current, making it difficult to achieve both high capacitance and low leakage current through CET reduction. That is, as shown in Figure 3, the relationship between CET and leakage current is almost linear up to about 3.5 nm of ZrO2 film thickness, but when the ZrO2 film thickness becomes thinner than 3 nm, for example to 2.5 nm, the leakage current rises above that linear relationship (trend line). Furthermore, Patent Document 2 describes a capacitor having multiple dielectric films, but it does not intend to achieve both high capacitance and low leakage current.

[0022] Therefore, in this embodiment, an oxide film 104, for example, Nb2O5, made of an oxide containing a pentavalent metal cation, is formed on a High-k film 103, for example, a ZrO2 film, made of an oxide containing a tetravalent metal cation. Then, by annealing, the High-k film 103 and the oxide film 104 react (atomic diffusion) at the interface, forming a mixed layer 105 in which they are mixed. For example, if the High-k film 103 is a ZrO2 film and the oxide film 104 is Nb2O5, then NbZrO x A mixed layer 105 containing the above is formed.

[0023] In the case of a conventional capacitor with a configuration in which a ZrO2 film 103' is provided as a dielectric film between the lower electrode 102' and upper electrode 106' made of TiN, as shown in Figure 4, a reaction (atomic diffusion) occurs between the upper electrode 106' and the ZrO2 film 103' due to annealing after the formation of the upper electrode 106', and TiZrO x A mixed layer (interface layer) 105' consisting of the above is formed.

[0024] In this case, the mixed layer 105' can be considered as having some of the Ti sites replaced by Zr, and the defect structure formula in that case is as shown in equation (1) below.

number

[0025] FIG. 6 is a diagram showing the relationship between the number of Zr atoms substituting the Ti sites of TiO2 and the band gap. As shown in this figure, regardless of the substitution number of Zr atoms in TiO2, the band gap does not close and it can be seen that it behaves as an insulator. Therefore, due to the formation of the mixed layer 105´, the dielectric layer is thickened accordingly.

[0026] That is, the CET of the ZrO2 film is CET ZrO2 and the CET of TiZrO2 which is the mixed layer 105´ is CET TiZrO2 Then, CET TZT which is the CET of the entire capacitor is as follows: CET ZrO2 and CET TiZrO2 and the sum of them, and the mixed layer 105´ acts in the direction of increasing the CET. CET TZT =CET TiZrO2 +CET ZrO2

[0027] In contrast, the mixed layer 105 of the present embodiment is a mixture of an oxide containing a pentavalent metal cation, for example, Nb2O5, and an oxide containing a tetravalent metal cation, for example, ZrO2, and is, for example, NbZrO x When ZrO2 which is an oxide containing a tetravalent metal cation is added to Nb2O5 which is an oxide containing a pentavalent metal cation, that is, when a part of the Nb sites are substituted with Zr, the defect structural formula is as shown in the following formula (2).

Equation

[0028] Figure 7 shows the calculated density of states (DOS) distributions for Nb2O5 when the number of Zr substitutions at the 24 Nb sites is 0 and when it is 8. As shown in Figure 7, calculations also confirm that when there are 8 Zr substitutions, energy levels originating from the electron orbitals of oxygen and Zr are generated within the gap in the DOS distribution, resulting in conductivity.

[0029] Figure 8 shows the relationship between the number of Zr atoms substituting Nb sites in Nb2O5 and the band gap. As shown in this figure, the band gap narrows as the number of Zr atom substitutions in Nb2O5 increases, and when the number of Zr atom substitutions exceeds 8, the band gap closes, and the material changes to a conductor.

[0030] In other words, in this embodiment, the mixed layer 105 can be made conductive by increasing the number of tetravalent metal cations (Zr in this example) in the mixed layer 105. In this embodiment, a conductive mixed layer 105 is formed by adjusting the heat treatment conditions during annealing.

[0031] The high-k film 103 is a ZrO2 film, and the mixed layer 105 is NbZrO x If so, the CET of the ZrO2 film is CET ZrO2 ,NbZrO x CET to CET NbZrOx Therefore, the CET of the entire capacitor is CET TNZT CET ZrO2 and CET NbZrOx It is the sum of the two. CET TNZT =CET NbZrOx +CET ZrO2 Here, NbZrO x Because it is conductive, CET NbZrOx It is almost 0. Therefore, the dielectric film thickness can be reduced compared to conventional ZrO2 single-film capacitors, and CET can be reduced. In addition, the mixed layer 105 is NbZrO xThe presence of the mixed layer 105 prevents damage to the High-k film 103 during the formation of the upper electrode 106. In other words, without the mixed layer 105, the High-k film 103 would be subjected to chemical damage by Cl and NH3 when the upper electrode 106 is deposited by ALD, or physical damage by plasma when it is deposited by PVD. However, the presence of the mixed layer 105 prevents such damage. Therefore, even with a small CET, the increase in leakage current can be suppressed. Consequently, it is possible to achieve both high capacitance and low leakage current in the capacitor.

[0032] The semiconductor device (capacitor) of this embodiment was actually manufactured and its characteristics were determined. Here, a 4 nm thick ZrO2 film and a 0.6 nm thick Nb2O5 film were formed on a lower electrode consisting of a TiN film formed on a Si substrate, and then annealed to produce NbZrO x A capacitor was fabricated by forming a film and then forming an upper electrode made of a TiN film on top of it (Sample 1). The CET and leakage current of this Sample 1 capacitor were determined. As a result, as shown in Figure 9, it was confirmed that the CET could be reduced by about 15% while suppressing the increase in leakage current compared to a conventional capacitor structure using a single film of ZrO2 (Ref), and that the characteristics were improved compared to the trend line of a single film of ZrO2.

[0033] <Second Embodiment> Next, a second embodiment will be described. Figure 10 is a flowchart showing a method for manufacturing a semiconductor device according to the second embodiment, and Figure 11 is a cross-sectional view showing some of the steps.

[0034] In this embodiment, steps ST11 to ST13 are performed in the same manner as steps ST1 to ST3 of the first embodiment. Specifically, a lower electrode 102 is formed on the substrate 101 (step ST11), a high dielectric constant film (High-k film) 103 made of an oxide containing a tetravalent metal cation is formed as a capacitance film (step ST12), and an oxide film 104 made of an oxide containing a pentavalent metal cation is formed on the High-k film 103 (step ST13).

[0035] Next, similar to step ST4 of the first embodiment, for example, during annealing for crystallization of the High-k film 103, the High-k film 103 and the oxide film 104 are reacted at the interface to form a conductive mixed layer 105 in which an oxide containing a tetravalent metal cation and an oxide containing a pentavalent metal cation are mixed (step ST14, Figure 11(a)).

[0036] Next, an oxygen abstraction layer 108 is formed on the mixed layer 105 to abstract oxygen (step ST15, Figure 11(b)). At this time, as shown in Figure 11(b), the oxygen abstraction layer 108 is formed via a barrier film 107 made of, for example, a TiN film. As the oxygen abstraction layer 108, a metal film made of an active metal such as TiAl can be used. In addition to TiAl, Ti, Al, etc. can be used as the oxygen abstraction layer 108.

[0037] Next, an upper electrode 106, made of, for example, a TiN film, is formed on the oxygen abstraction layer 108, similar to step ST5 of the first embodiment (step ST16, Figure 11(c)).

[0038] Next, heat treatment is performed in a reducing atmosphere (step ST17, Figure 11(d)). This causes oxygen to be extracted from the lower mixed layer 105 to the oxygen abstraction layer 108, forming an oxygen-deficient mixed layer 105a. This heat treatment can be carried out in an H2-containing atmosphere (hydrogen concentration: 1-100%, e.g., 4%), at a temperature of 350-600°C, e.g., 400°C, and for a time of 120 min or less, e.g., 10 min.

[0039] The formation of the oxygen abstraction layer 108 in step ST15 and the heat treatment in a reducing atmosphere in step ST17 constitute a reduction treatment process.

[0040] After step ST17, perform further annealing as needed, and then complete the process.

[0041] In this embodiment, the formation of the mixed layer 105 in step ST14 may be performed at the time of step ST17, or during annealing after step ST17. If step ST14 is performed during annealing after step ST17, the oxygen abstraction (reduction treatment) in ST17 is performed on the oxide film 104.

[0042] In this embodiment as well, the semiconductor device manufactured as described above is used as a capacitor, typically as a capacitor for a DRAM.

[0043] In this embodiment, a mixed layer 105 is formed from a combination of tetravalent and pentavalent metal cations, and defects are generated to satisfy the charge neutrality condition. A reduction treatment, which involves oxygen abstraction, is then performed to create an oxygen vacancy, forming a mixed layer 105a with an oxygen vacancy. As a result, the mixed layer 105a is more conductive than the mixed layer 105 due to the presence of the oxygen vacancy, thereby increasing conductivity. Consequently, the effect of reducing CET can be increased compared to the first embodiment. Furthermore, the presence of the mixed layer 105a prevents not only damage to the High-k film 103 during the formation of the upper electrode 106 as described above, but also damage to the High-k film 103 during the reduction treatment, thereby suppressing the increase in leakage current.

[0044] The details are explained below. As described above, a mixed layer 105, formed by mixing an oxide containing a pentavalent metal cation, such as Nb2O5, with an oxide containing a tetravalent metal cation, such as ZrO2, can become conductive due to the generation of oxygen vacancies and defects originating from Zr that are negatively charged. Furthermore, a mixed layer 105a, in which oxygen has been extracted from the mixed layer 105 and the oxygen vacancy has increased, becomes even more conductive.

[0045] Figure 12 shows oxygen-deficient Nb in relation to Nb2O5. 12 O 29 This figure shows the calculated density of states (DOS) distribution when the number of substitutions of Zr at 28 sites of Nb is 4. As shown in Figure 12, oxygen-deficient Nb 12 O 29 In this case, even with a small number of Zr substitutions (4), energy levels originating from the electron orbitals of oxygen and Zr are generated within the gap of the DOS distribution, confirming that conductivity is achieved.

[0046] Figure 13 shows Nb 12 O 29 This figure shows the relationship between the number of Zr atoms substituting the Nb sites and the band gap, compared to the case where the Nb sites of Nb2O5 are substituted with Zr atoms. As shown in this figure, oxygen-deficient Nb 12 O 29 In this case, the band gap narrows more rapidly than in the case of Nb2O5 due to the substitution of Zr atoms, and it can be seen that the band gap closes and the material changes to a conductor when the number of Zr atom substitutions is 4 or more.

[0047] In other words, in this embodiment, the mixed layer 105a, which has an increased oxygen deficiency due to an oxygen abstraction treatment (a reduction treatment) performed on the mixed layer 105, is more conductive than the mixed layer 105. Therefore, CET can be reduced even further than in the first embodiment.

[0048] Furthermore, in the case of conventional capacitors that do not form an oxide film 104 consisting of an oxide containing a pentavalent metal cation as described above, even if oxygen vacancies are created by reduction treatment after forming the mixed layer (interface layer) 105', the band gap changes as shown in Figure 14, and it remains an insulator. Specifically, Figure 14 shows Ti9O 17 This figure shows the relationship between the number of Zr atoms substituting the Ti sites and the band gap, compared to the case where the Ti sites of TiO2 are substituted with Zr atoms. As shown in this figure, Ti9O 17 Similar to TiO2, the band gap does not close regardless of the number of Zr atom substitutions, and it behaves as an insulator.

[0049] The semiconductor device (capacitor) of this embodiment was actually manufactured and its characteristics were determined. Here, a 4nm thick ZrO2 film and a 0.6nm thick Nb2O5 film were formed on a lower electrode made of a TiN film formed on a Si substrate, and then annealing was performed to form an NbZrOx film. Then, a 3nm TiN film and a 3nm TiAl film were deposited on top of that, and after forming an upper electrode made of a TiN film, a capacitor was manufactured by heat treatment at 400°C in a reducing atmosphere (Sample 2). The CET and leakage current of this Sample 2 capacitor were determined. As a result, as shown in Figure 15, it was possible to reduce the CET by about 35% while suppressing the increase in leakage current to less than two orders of magnitude compared to a conventional capacitor structure using a single ZrO2 film (Ref), and it was confirmed that the characteristics were improved compared to the trend line of a single ZrO2 film. Also, Figure 15 shows the results for Sample 1 of the first embodiment, and it can be seen that the CET reduction effect is higher for Sample 2 than for Sample 1.

[0050] <Third Embodiment> Next, a third embodiment will be described. Figure 16 is a flowchart showing a method for manufacturing a semiconductor device according to the third embodiment, and Figure 17 is a cross-sectional view showing some of the steps.

[0051] In this embodiment, steps ST21 to ST23 are performed in the same manner as steps ST1 to ST3 of the first embodiment. Specifically, a lower electrode 102 is formed on the substrate 101 (step ST21), a high dielectric constant film (High-k film) 103 made of an oxide containing a tetravalent metal cation is formed as a capacitance film (step ST22), and an oxide film 104 made of an oxide containing a pentavalent metal cation is formed on the High-k film 103 (step ST23).

[0052] Next, similar to step ST4 of the first embodiment, for example, during annealing for crystallization of the High-k film 103, the High-k film 103 and the oxide film 104 are reacted at the interface to form a conductive mixed layer 105 in which an oxide containing a tetravalent metal cation and an oxide containing a pentavalent metal cation are mixed (step ST24, Figure 17(a)).

[0053] Next, a reduction treatment is performed (step ST25, Figure 17(b)). This reduces the mixed layer 105, forming a mixed layer 105b with oxygen deficiencies. The reduction treatment can be carried out by heat treatment in a hydrogen gas (H2 gas) atmosphere or a deuterium gas (D2 gas) atmosphere as the reducing atmosphere, for example, under conditions of temperature: 250~600°C and time: 60 min or less. Alternatively, the reduction treatment may be carried out using H2 plasma.

[0054] Next, an upper electrode 106 made of, for example, a TiN film is formed on the mixed layer 105b, similar to step ST5 of the first embodiment (step ST26, Figure 17(c)).

[0055] After step ST26, perform further annealing as needed, and then complete the process.

[0056] In this embodiment, the formation of the mixed layer 105 in step ST24 may be performed at the time of step ST26, or during the annealing after step ST26. If step ST24 is performed during the annealing after step ST26, oxygen deficiencies will occur in the oxide film 104 during the reduction treatment in step ST25.

[0057] In this embodiment as well, the semiconductor device manufactured as described above is used as a capacitor, typically as a capacitor for a DRAM.

[0058] In this embodiment, as in the second embodiment, a mixed layer 105 is constructed from a combination of tetravalent and pentavalent metal cations, and a reduction treatment is performed on the mixed layer 105, which has defects generated to satisfy the charge neutrality condition, to form a mixed layer 105b in which oxygen vacancies are generated relative to the mixed layer 105. As a result, the mixed layer 105b is more conductive than the mixed layer 105 due to the presence of oxygen vacancies, and its conductivity can be increased. Therefore, the effect of reducing CET can be increased compared to the first embodiment. In addition, the mixed layer 105b, as in the mixed layer 105a of the second embodiment, can prevent damage to the High-k film 103 not only when forming the upper electrode 106 but also during the reduction treatment, and can suppress the increase in leakage current.

[0059] The semiconductor device (capacitor) of this embodiment was actually manufactured and its characteristics were determined. Here, a 4 nm thick ZrO2 film and a 0.6 nm thick Nb2O5 film were formed on a lower electrode made of a TiN film formed on a Si substrate, and then annealing was performed to form an NbZrOx film. Then, a reduction treatment was performed at 541°C in an H2 gas atmosphere, and a top electrode made of a TiN film was formed on top of it to manufacture a capacitor (Sample 3). A capacitor was also manufactured under the same conditions as Sample 3, except that the reduction treatment was performed in a D2 gas atmosphere (Sample 4). The CET and leakage current were determined for this capacitor. As a result, as shown in Figure 18, it was confirmed that the CET could be reduced by about 30% while suppressing the increase in leakage current to less than two orders of magnitude compared to a conventional capacitor structure using a single ZrO2 film (Ref), and that the characteristics were improved compared to the trend line of a single ZrO2 film.

[0060] <Other applications> Although embodiments have been described above, the embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The above embodiments may be omitted, replaced, or modified in various ways without departing from the scope and spirit of the appended claims. [Explanation of Symbols]

[0061] 101; substrate 102; Lower electrode High-k film consisting of oxide containing 10³⁴ valent metal cations Oxide film consisting of an oxide containing 104;5 valent metal cations 105,105a,105b;Mixed layer 106;Top electrode 107;TiN film 108; Oxygen abstraction layer

Claims

1. A process of forming a lower electrode on a substrate, A step of forming a high dielectric constant film made of an oxide containing a tetravalent metal cation on the lower electrode, A step of forming an oxide film made of an oxide containing a pentavalent metal cation on the high dielectric constant film, The steps include: reacting the high dielectric constant film and the oxide film to form a conductive mixed layer in which the oxide containing the tetravalent metal cation and the oxide containing the pentavalent metal cation are mixed; The process of forming the upper electrode, A method for manufacturing a semiconductor device having the following characteristics.

2. The high dielectric constant film made of the oxide containing the tetravalent metal cation is ZrO ２ Membrane and HfO ２ A method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is one of the films.

3. The oxide film consisting of the aforementioned oxide containing a pentavalent metal cation is Nb ２ O ５ membrane, V ２ O ５ film, and Ta ２ O ５ A method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is one of the films.

4. The high dielectric constant film made of an oxide containing the tetravalent metal cation is a ZrO ２ film, and the oxide film made of an oxide containing the pentavalent metal cation is Nb ２ O ５ film. The method of manufacturing a semiconductor device according to claim 1.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the upper electrode and the lower electrode are made of a TiN film.

6. A method for manufacturing a semiconductor device according to any one of claims 1 to 5, further comprising the step of performing a reduction treatment after at least the step of forming the oxide film.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the reduction treatment step involves forming an oxygen abstraction layer on the mixed layer or the oxide film, and abstracting oxygen from the mixed layer or the oxide film to the oxygen abstraction layer by heat treatment in a reducing atmosphere.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the heat treatment in the reducing atmosphere is performed after the step of forming the upper electrode.

9. A method for manufacturing a semiconductor device according to claim 7, wherein oxygen is extracted to the oxygen extraction layer, thereby causing an oxygen deficiency in the mixed layer.

10. The method for manufacturing a semiconductor device according to claim 6, wherein the reduction treatment step is performed by heat treatment in a hydrogen gas atmosphere or a deuterium gas atmosphere.

11. A method for manufacturing a semiconductor device according to claim 10, wherein oxygen deficiencies are created in the mixed layer by heat treatment in the hydrogen gas atmosphere or the deuterium gas atmosphere.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the reduction treatment step is performed before the step of forming the upper electrode.

13. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the thickness of the oxide film is 1 nm or less.

14. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is a capacitor for a DRAM.

15. circuit board and The lower electrode formed on the substrate, A high dielectric constant film made of a one-component metal oxide containing tetravalent metal cations formed on the lower electrode, A conductive mixed layer is formed on the high dielectric constant film, and is a mixture of a one-component metal oxide containing a tetravalent metal cation and a one-component metal oxide containing a pentavalent metal cation. An upper electrode formed on the aforementioned mixed layer, A semiconductor device having

16. The semiconductor device according to claim 15, wherein the mixed layer has oxygen deficiencies.

17. A semiconductor device according to claim 15 or claim 16, used as a capacitor for a DRAM.

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