Semiconductor equipment

Abstract

To provide a technique of being able to narrow the distance between adjacent guard rings.SOLUTION: A semiconductor device includes a plurality of lower guard rings 16a and a plurality of upper guard rings 16b. An upper part of each of the lower guard rings 16a overlaps with a lower part of the corresponding one of the upper guard rings 16b. A lower inner peripheral surface 162 of each of the lower guard rings 16a is offset in one direction of inner and outer directions with respect to an upper inner peripheral surface 166 of the corresponding one of the upper guard rings 16b. A lower outer peripheral surface 164 of each of the lower guard rings is offset in the one direction of the inner and outer directions with respect to an upper outer peripheral surface 168 of the corresponding one of the upper guard rings 16b.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The technology disclosed in this specification relates to semiconductor devices.

[0002] The semiconductor device includes a semiconductor layer including an element region where an element structure is formed and a termination region located around the element region. A structure for ensuring the breakdown voltage of the semiconductor device is provided in the termination region of the semiconductor layer. Patent Documents 1 to 3 disclose semiconductor devices provided with a plurality of p-type guard rings as a breakdown voltage structure.

[0003] When the semiconductor device is turned off, a depletion layer spreads from the element region toward the termination region. The depletion layer spreads from the inner peripheral side to the outer peripheral side of the termination region while passing through the plurality of guard rings. As the depletion layer spreading from the element region spreads greatly from the inner peripheral side to the outer peripheral side of the termination region, the breakdown voltage of the semiconductor device is improved.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] In this type of semiconductor device, it is desired to increase the concentration of the drift region in order to reduce losses. In order to spread the depletion layer well in a semiconductor device provided with a high-concentration drift region, it is necessary to narrow the interval between adjacent guard rings. This specification provides a technology capable of narrowing the interval between adjacent guard rings.

Means for Solving the Problems

[0006] The semiconductor devices (1, 2, 3, 4, 5, 6) disclosed herein may include a semiconductor layer (10) comprising an element region (101) on which an element structure is formed, and a termination region (102) located around the element region. The semiconductor layer located in the termination region may have a drift region (12) of a first conductivity type, a plurality of lower guard rings (16a) of a second conductivity type surrounded by the drift region and provided in a first depth range (Dep1), and a plurality of upper guard rings (16b) of a second conductivity type surrounded by the drift region and provided in a second depth range (Dep2) different from the first depth range. Each of the plurality of lower guard rings extends around the element region when the semiconductor layer is viewed from above, and may be spaced apart from each other along the inward-outward direction connecting the element region and the termination region. Each of the plurality of upper guard rings may extend around the perimeter of the element region when the semiconductor layer is viewed in plan, and may be spaced apart from each other along the inward-outward direction. Each of the plurality of lower guard rings may have a lower inner circumferential surface (162) facing the element region and a lower outer circumferential surface (164) opposite to the lower inner circumferential surface. Each of the plurality of upper guard rings may have an upper inner circumferential surface (166) facing the element region and an upper outer circumferential surface (168) opposite to the upper inner circumferential surface. The upper portion of each of the plurality of lower guard rings may overlap with the lower portion of the corresponding upper guard ring among the plurality of upper guard rings. The lower inner circumferential surface of each of the plurality of lower guard rings may be offset in one direction in the inward-outward direction with respect to the upper inner circumferential surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings may be offset in one of the inward or outward directions relative to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. The center line (CL1) of each of the plurality of lower guard rings may extend parallel to and not intersect with the center line (CL2) of the corresponding upper guard ring among the plurality of upper guard rings when the semiconductor layer is viewed in plan.

[0007] In the semiconductor device described above, the relative positions of the plurality of lower guard rings and the plurality of upper guard rings are formed to be offset in the inward and outward directions, so that the minimum distance between adjacent lower guard rings and upper guard rings can be made smaller than the minimum machining dimension. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view showing the layout of multiple trench gates and multiple guard rings provided in the semiconductor device of the first embodiment, and schematically shows a plan view of the semiconductor device with structures on the semiconductor layer removed. [Figure 2] This is a cross-sectional view of the main part of the semiconductor device of this embodiment, schematically showing the cross-sectional view along line II-II in Figure 1. [Figure 3] This figure schematically shows enlarged cross-sectional views of the vicinity of multiple guard rings, which are part of the main cross-sectional view in Figure 2. [Figure 4] This diagram shows how the centerlines of the lower guard ring and the upper guard ring run parallel to each other. [Figure 5] This is a cross-sectional view of the main part of the semiconductor device of the second embodiment, schematically showing the cross-sectional view along line II-II in Figure 1. [Figure 6] This is a cross-sectional view of the main part of the semiconductor device of the third embodiment, schematically showing the cross-sectional view along line II-II in Figure 1. [Figure 7] This is a cross-sectional view of the main part of the semiconductor device of the fourth embodiment, schematically showing the cross-sectional view along line II-II in Figure 1. [Figure 8] This is a cross-sectional view of the main part of the semiconductor device of the fifth embodiment, schematically showing the cross-sectional view along line II-II in Figure 1. [Figure 9] This is a cross-sectional view of the main part of the semiconductor device according to the sixth embodiment, schematically showing the cross-sectional view along line II-II in Figure 1. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the drawings. Components that are substantially common throughout the embodiments will be denoted by the same reference numerals, and their descriptions will be omitted. In addition, for the purpose of clarity in the illustration, only some of the components that are repeatedly arranged may be denoted by reference numerals.

[0010] (First Embodiment) As shown in Figures 1 and 2, the semiconductor device 1 of this embodiment includes a semiconductor layer 10, a source electrode 22 covering a portion of the upper surface 10A of the semiconductor layer 10, an interlayer insulating film 24 covering a portion of the upper surface 10A of the semiconductor layer 10, a drain electrode 26 covering the entire lower surface 10B of the semiconductor layer 10, and a plurality of trench-type insulated gates 30. The semiconductor device 1 is a vertical MOSFET and is used as a power semiconductor device. As shown in Figure 2, the source electrode 22 and the interlayer insulating film 24 are provided on the upper surface 10A of the semiconductor layer 10, but these components are omitted in Figure 1.

[0011] The semiconductor layer 10 is not particularly limited, but may be a semiconductor layer made of silicon carbide (SiC), for example. The semiconductor layer 10 has an element region 101 and a termination region 102. As shown in Figure 1, the element region 101 is located in the center of the semiconductor layer 10 when viewed from a direction perpendicular to the upper surface 10A of the semiconductor layer 10 (Z direction) (hereinafter referred to as "when the semiconductor layer 10 is viewed from above"), and is partitioned within the semiconductor layer 10 as the area where a switching element structure (MOSFET structure in this example) is formed. The termination region 102 is located in the peripheral part of the semiconductor layer 10, around the element region 101, when the semiconductor layer 10 is viewed from above, and is partitioned within the semiconductor layer 10 as the area where a breakdown structure (multiple guard rings 16, described later in this example) is formed.

[0012] As shown in Figure 2, the semiconductor layer 10 is n + A drain region 11 of type n - A drift region 12 of type p, a body region 13 of type p, and n +A plurality of source regions 14 of the type, and p + A plurality of body contact regions 15 of the type, and p + A plurality of guard rings 16 of the type, and. In this embodiment, a case where the plurality of guard rings 16 are composed of three guard rings 16 is illustrated, but they may be composed of a different number. Also, the guard ring 16 is also referred to as a FLR (Field Limiting Ring). The body region 13, the plurality of source regions 14, and the plurality of body contact regions 15 are selectively formed in the surface layer portion of the element region 101. The plurality of guard rings 16 are selectively formed in the surface layer portion of the termination region 102. In this embodiment, the boundary between the element region 101 and the termination region 102 is defined by the periphery of the outermost source region 14 among the plurality of source regions 14.

[0013] The drain region 11 is disposed in the back layer portion of the semiconductor layer 10 in both the element region 101 and the termination region 102, and is provided at a position exposed to the lower surface 10B of the semiconductor layer 10. The drain region 11 contains a high concentration of n-type impurities (for example, nitrogen or phosphorus, etc.), and is in ohmic contact with the drain electrode 26 covering the lower surface 10B of the semiconductor layer 10.

[0014] The drift region 12 is provided on the drain region 11 in both the element region 101 and the termination region 102. The n-type impurity concentration of the drift region 12 is lower than the n-type impurity concentration of the drain region 11.

[0015] The body region 13 is disposed on the drift region 12 located in the element region 101, and is provided in the surface layer portion of the semiconductor layer 10. The body region 13 is not particularly limited, but for example, it may be formed by introducing p-type impurities (for example, aluminum or boron, etc.) into the surface layer portion of the semiconductor layer 10 using ion implantation technology.

[0016] The source region 14 is disposed on the body region 13 located in the element region 101 and provided at a position exposed to the upper surface 10A of the semiconductor layer 10. The source region 14 is separated from the drift region 12 by the body region 13. The source region 14 is not particularly limited, but for example, it may be formed by introducing n-type impurities into the surface layer portion of the semiconductor layer 10 using ion implantation technology. The source region 14 contains n-type impurities at a high concentration and is in ohmic contact with the source electrode 22 covering the upper surface 10A of the semiconductor layer 10.

[0017] The body contact region 15 is disposed on the body region 13 located in the element region 101 and provided at a position exposed to the upper surface 10A of the semiconductor layer 10. The body contact region 15 is not particularly limited, but for example, it may be formed by introducing p-type impurities into the surface layer portion of the semiconductor layer 10 using ion implantation technology. The body contact region 15 contains p-type impurities at a high concentration and is in ohmic contact with the source electrode 22 covering the upper surface 10A of the semiconductor layer 10.

[0018] As shown in FIG. 1, a plurality of trench-type insulated gates 30 arranged in a stripe shape are formed on the upper surface 10A of the semiconductor layer 10 in the range corresponding to the element region 101 when viewed in plan. Each of the plurality of trench-type insulated gates 30 extends along one direction (Y direction). As shown in FIG. 2, the trench-type insulated gate 30 has a gate insulating film 32 made of silicon oxide and a gate electrode 34 made of polysilicon. The gate electrode 34 faces the body region 13 in the portion separating the drift region 12 and the source region 14 through the gate insulating film 32. Thereby, the body region 13 in the portion separating the drift region 12 and the source region 14 can function as a channel region.

[0019] Thus, a MOSFET structure is formed in the element region 101 of the semiconductor layer 10, consisting of a drain region 11, a drift region 12, a body region 13, a source region 14, a body contact region, and a trench-type insulated gate 30. On the other hand, a breakdown voltage structure consisting of multiple guard rings 16 is formed in the termination region 102 of the semiconductor layer 10.

[0020] As shown in Figures 2 and 3, the multiple guard rings 16 are arranged on the drift region 12 located in the termination region 102 and are positioned to be exposed on the upper surface 10A of the semiconductor layer 10. The potential of each of the multiple guard rings 16 is floating. As shown in Figure 1, each of the multiple guard rings 16 is arranged to encircle the element region 101 when the semiconductor layer 10 is viewed from above. In this way, each of the multiple guard rings 16 is spaced apart from each other along the direction connecting the element region 101 and the termination region 102 (the X direction in Figures 2 and 3, hereinafter referred to as the "inner-outer direction").

[0021] Each of the multiple guard rings 16 has multiple lower guard rings 16a and multiple upper guard rings 16b. Each of the multiple guard rings 16 consists of one lower guard ring 16a and one upper guard ring 16b.

[0022] As shown in Figure 3, the multiple lower guard rings 16a are surrounded by the drift region 12 and are provided in a first depth range Dep1 of the semiconductor layer 10. The first depth range Dep1 is a depth range away from the upper surface 10A of the semiconductor layer 10. When the semiconductor layer 10 is viewed from above, each of the multiple lower guard rings 16a extends around the perimeter of the element region 101 and is spaced apart from each other along the inward and outward directions. When the semiconductor layer 10 is viewed from above, each of the multiple lower guard rings 16a is concentric and similar in shape to the other lower guard rings 16a. Each of the multiple lower guard rings 16a has a lower inner circumferential surface 162 facing the element region 101 and a lower outer circumferential surface 164 opposite to the lower inner circumferential surface 162. The width of each of the multiple lower guard rings 16a, i.e., the width W1 measured between the lower inner circumferential surface 162 and the lower outer circumferential surface 164 along the inward-outward direction, is not particularly limited, but may be common among the multiple lower guard rings 16a. The lower guard rings 16a are formed by introducing p-type impurities into the surface layer of the semiconductor layer 10 using ion implantation technology. In this example, the lower guard rings 16a and the body region 13 are formed by ion implantation using a common mask.

[0023] The multiple upper guard rings 16b are surrounded by the drift region 12 and are provided in a second depth range Dep2 of the semiconductor layer 10. The second depth range Dep2 is a different depth range from the first depth range Dep1 and is a depth range from the upper surface 10A of the semiconductor layer 10 to a predetermined depth. Note that the second depth range Dep2 may be a depth range located away from the upper surface 10A of the semiconductor layer 10. When the semiconductor layer 10 is viewed from above, each of the multiple upper guard rings 16b extends around the perimeter of the element region 101 and is spaced apart from each other along the inward and outward directions. When the semiconductor layer 10 is viewed from above, each of the multiple upper guard rings 16b is concentric and similar in shape to the other upper guard rings 16b. Each of the multiple upper guard rings 16b has an upper inner circumferential surface 166 facing the element region 101 and an upper outer circumferential surface 168 opposite to the upper inner circumferential surface 166. The width of each of the multiple upper guard rings 16b, i.e., the width W2 measured between the upper inner circumferential surface 166 and the upper outer circumferential surface 168 along the inward-outward direction, is not particularly limited, but may be common among the multiple upper guard rings 16b. The width W1 of the lower guard ring 16a and the width W2 of the upper guard rings 16b may be the same. The upper guard rings 16b are formed by introducing p-type impurities into the surface layer of the semiconductor layer 10 using ion implantation technology. In this example, the upper guard rings 16b and the body contact region 15 are formed by ion implantation using a common mask.

[0024] The upper portion of each of the multiple lower guard rings 16a overlaps with the lower portion of the corresponding upper guard ring 16b among the multiple upper guard rings 16b. In other words, the top surface of each of the multiple lower guard rings 16a is located above the bottom surface of the corresponding upper guard ring 16b among the multiple upper guard rings 16b, i.e., at a shallow position in the semiconductor layer 10. Thus, the upper portion of the first depth range Dep1 in which the lower guard rings 16a exist and the lower portion of the second depth range Dep2 in which the upper guard rings 16b exist overlap, and there exists a third overlapping depth range Dep3.

[0025] Each of the lower inner circumferential surfaces 162 of the multiple lower guard rings 16a is offset to one side in the inward or outward direction relative to the upper inner circumferential surface 166 of the corresponding upper guard ring 16b among the multiple upper guard rings 16b. In this example, each of the lower inner circumferential surfaces 162 of the multiple lower guard rings 16a is offset in the inward or outward direction toward the element region 101 relative to the upper inner circumferential surface 166 of the corresponding upper guard ring 16b among the multiple upper guard rings 16b.

[0026] Each of the lower outer peripheral surfaces 164 of the multiple lower guard rings 16a is offset to one side in the inward or outward direction relative to the upper outer peripheral surface 168 of the corresponding upper guard ring 16b among the multiple upper guard rings 16b. In this example, each of the lower outer peripheral surfaces 164 of the multiple lower guard rings 16a is offset in the inward or outward direction toward the element region 101 relative to the upper outer peripheral surface 168 of the corresponding upper guard ring 16b among the multiple upper guard rings 16b.

[0027] The line passing through the center of each of the multiple lower guard rings 16a in the inward and outward directions is defined as the center line CL1, and the line passing through the center of each of the multiple upper guard rings 16b in the inward and outward directions is defined as the center line CL2. As shown in Figure 4, when the semiconductor layer 10 is viewed in plan, the center line CL1 of the lower guard ring 16a runs parallel to the center line CL2 of the upper guard ring 16b and does not intersect with it. Note that Figure 4 shows only the center line CL1 of the lower guard ring 16a and the center line CL2 of the upper guard ring 16b that constitute one of the multiple guard rings 16, but the other guard rings 16 are similar. Thus, the lower guard ring 16a and upper guard ring 16b that constitute one guard ring 16 are diffusion regions formed with intentionally different patterns, and are offset beyond the range of manufacturing error that would occur if the center lines CL1 and CL2 were to be formed to coincide.

[0028] As shown in FIG. 3, between adjacent guard rings 16, minimum intervals d2 and d3 are formed between the lower inner peripheral surface 162 of the lower guard ring 16a and the upper outer peripheral surface 168 of the upper guard ring 16b. The minimum interval d3 is larger than the minimum interval d2. In this example, three guard rings 16 are provided. However, if an additional guard ring 16 is provided on the outer peripheral side of the terminal region 102, the minimum interval formed by that guard ring 16 is larger than the minimum intervals d2 and d3. Thus, the plurality of lower guard rings 16a and the plurality of upper guard rings 16b are configured such that the minimum intervals between adjacent lower guard rings 16a and upper guard rings 16b increase in order from the inner peripheral side to the outer peripheral side of the terminal region 102.

[0029] Furthermore, the minimum interval d1 between the lowermost lower guard ring 16a of the innermost periphery of the terminal region 102 and the p-type region (in this example, the body contact region 15) of the element region 101 is smaller than the minimum interval d2. Thus, in the semiconductor device 1, the relationship d1 < d2 < d3 holds.

[0030] Next, the operation of the semiconductor device 1 will be described. During the operation of the semiconductor device 1, a voltage is applied between the drain and source such that the potential of the drain electrode 26 becomes higher than the potential of the source electrode 22. When the voltage between the gate electrode 34 and the source electrode 22 becomes higher than the threshold value, a channel is formed in the body region 13 in the range contacting the gate insulating film 32. Then, electrons flow from the source electrode 22 through the source region 14, the channel, the drift region 12, and the drain region 11 to the drain electrode 26. On the other hand, when the voltage between the gate electrode 34 and the source electrode 22 becomes lower than the threshold value, the channel disappears and the flow of electrons stops. Thus, the semiconductor device 1 can control the current flowing between the source electrode 22 and the drain electrode 26 based on the voltage between the gate electrode 34 and the source electrode 22.

[0031] When the semiconductor device 1 is turned off, a depletion layer spreads from the pn junction surface of the drift region 12 and the body region 13 into the drift region 12. In the drift region 12 of the element region 101, the depletion layer spreads from the upper surface 10A to the lower surface 10B. In the drift region 12 of the termination region 102, the depletion layer spreads from the inner circumference to the outer circumference. Since the semiconductor device 1 has multiple guard rings 16 in the termination region 102, the depletion layer spreading from the element region 101 can spread significantly from the inner circumference to the outer circumference of the termination region 102 via the multiple guard rings 16. Specifically, when the depletion layer spreading from the guard ring 16 located at the innermost circumference of the termination region 102 reaches the adjacent guard ring 16, the depletion layer begins to spread from that guard ring 16. In this way, the depletion layer spreading from the element region 101 spreads from the inner circumference to the outer circumference of the termination region 102, passing through the multiple guard rings 16 in sequence.

[0032] In such a semiconductor device 1, it is desirable to increase the density of the drift region 12 in order to reduce losses. However, when the density of the drift region 12 is increased, it is necessary to narrow the spacing between adjacent guard rings 16 in order to expand the depletion layer by passing through multiple guard rings 16 in sequence. In the semiconductor device 1, the relative positions of multiple lower guard rings 16a and multiple upper guard rings 16b are formed to be offset in the inward and outward directions, so the minimum spacing between adjacent lower guard rings 16a and upper guard rings 16b can be made smaller than the minimum processing dimension. In this way, the semiconductor device 1 can achieve both low loss and high voltage resistance.

[0033] In the semiconductor device 1, the multiple lower guard rings 16a are formed to be offset in the inward and outward direction toward the element region 101 relative to the multiple upper guard rings 16b. In this case, when the semiconductor device 1 is turned off, the equipotential lines formed in the termination region 102 including the multiple guard rings 16 have a greater curvature than when the multiple lower guard rings 16a are formed to be offset in the inward and outward direction toward the termination region 102 relative to the multiple upper guard rings 16b. As a result, electric field concentration can be suppressed, and the semiconductor device 1 can have high breakdown voltage characteristics.

[0034] In semiconductor device 1, the minimum distance between adjacent lower guard rings 16a and upper guard rings 16b is configured to increase sequentially from the inner circumference to the outer circumference of the termination region 102. In such semiconductor device 1, even if adjacent guard rings 16 connect in the inward and outward directions on the inner circumference of the termination region 102 due to manufacturing variations, adjacent guard rings 16 on the outer circumference of the termination region 102 can remain separated. Therefore, in semiconductor device 1, a decrease in withstand voltage caused by the connection of guard rings 16 due to manufacturing variations is suppressed.

[0035] In semiconductor device 1, the minimum distance between adjacent lower guard rings 16a and upper guard rings 16b can be narrowed while ensuring a wide distance between adjacent upper guard rings 16b. Therefore, the amount of charge (i.e., concentration × depth) of the n-type region to be depleted can be secured between adjacent upper guard rings 16b, thus suppressing excessive expansion of the depletion layer. Consequently, semiconductor device 1 can have high breakdown voltage characteristics while suppressing an increase in the area of ​​the termination region 102.

[0036] In the semiconductor device 1, multiple lower guard rings 16a are formed using the same ion implantation process as the body region 13, and multiple upper guard rings 16b are formed using the same ion implantation process as the body contact region 15. Since no separate ion implantation process is required to form the multiple guard rings 16, the semiconductor device 1 can be manufactured at a low manufacturing cost.

[0037] (Second Embodiment) As shown in Figure 5, the semiconductor device 2 of this embodiment includes a p-type electric field relaxation region 17 provided in contact with the bottom surface of the trench-type insulated gate 30. The electric field relaxation region 17 can alleviate the electric field concentration at the bottom surface of the trench-type insulated gate 30. In the semiconductor device 2 of this embodiment, the drift region 12 further includes a low-concentration drift region 122 and a high-concentration drift region 124. The low-concentration drift region 122 is located between the drain region 11 and the high-concentration drift region 124. The high-concentration drift region 124 is located on the low-concentration drift region 122, and the concentration of n-type impurities is higher than that of the low-concentration drift region 122.

[0038] The high-concentration drift region 124 located in the element region 101 is positioned between the low-concentration drift region 122 and the body region 13, and extends between adjacent trench-type insulated gates 30. The electric field relaxation region 17 is provided so as to penetrate the high-concentration drift region 124 and reach the low-concentration drift region 122. The high-concentration drift region 124 located in the element region 101 functions as a current dispersion region, and can suppress the increase in resistance due to the JFET effect caused by the electric field relaxation region 17.

[0039] The high-concentration drift region 124 located in the terminal region 102 is arranged to surround multiple guard rings 16. It is generally known that positive charge accumulates within the interlayer insulating film 24 located in the terminal region 102. Variations in the amount of such positive charge accumulation can cause fluctuations in the breakdown voltage characteristics. In the semiconductor device 2, the high-concentration drift region 124 is provided to surround multiple guard rings 16. When the high-concentration drift region 124 becomes depleted, positive charge accumulates within the high-concentration drift region 124. In the semiconductor device 2, the high-concentration drift region 124 is formed with high concentration, so the amount of positive charge when it becomes depleted is also large. As a result, even if there is variation in the amount of positive charge within the interlayer insulating film 24, the amount of positive charge accumulated within the high-concentration drift region 124 can relatively reduce the effect of this variation.

[0040] (Third embodiment) As shown in Figure 6, the semiconductor device 3 of this embodiment includes a p-type field relaxation region 18 that protrudes downward from the body region 13 between adjacent trench-type insulated gates 30. The field relaxation region 18 is positioned away from the sides of the trench-type insulated gates 30. The field relaxation region 18 is positioned to penetrate the high-concentration drift region 124 and reach the low-concentration drift region 122. The field relaxation region 18 can alleviate the electric field concentration at the bottom surface of the trench-type insulated gates 30.

[0041] In the semiconductor device 3, multiple lower guard rings 16a are formed in the same ion implantation process as the electric field relaxation region 18, and multiple upper guard rings 16b are formed in the same ion implantation process as the body region 13. Since no separate ion implantation process is required to form the multiple guard rings 16, the semiconductor device 3 can be manufactured at a low manufacturing cost.

[0042] (Fourth embodiment) As shown in Figure 7, in the semiconductor device 4 of this embodiment, the high-concentration drift region 124 is formed to surround the electric field relaxation region 18. Even in such a high-concentration drift region 124, it functions as a current dispersion region, and the increase in resistance due to the JFET effect caused by the electric field relaxation region 18 can be suppressed.

[0043] In the semiconductor device 4, multiple lower guard rings 16a are formed in the same ion implantation process as the electric field relaxation region 18, and multiple upper guard rings 16b are formed in the same ion implantation process as the body contact region 15. Since no separate ion implantation process is required to form the multiple guard rings 16, the semiconductor device 4 can be manufactured at a low manufacturing cost.

[0044] (Fifth embodiment) As shown in Figure 8, in this embodiment, the semiconductor device 5 has a high-concentration drift region 124 formed only in a portion of the depth range where multiple upper guard rings 16b exist and which is exposed to the upper surface 10A of the semiconductor layer 10. In this example as well, the effect of variations in the amount of positive charge in the interlayer insulating film 24 can be suppressed. On the other hand, since the high-concentration drift region 124 is not provided in the portion where the gap between adjacent lower guard rings 16a and upper guard rings 16b is the smallest, the depletion layer can spread well when the semiconductor device 1 is turned off.

[0045] In the semiconductor device 5, multiple lower guard rings 16a are formed in the same ion implantation process as the electric field relaxation region 18, multiple upper guard rings 16b are formed in the same ion implantation process as the body contact region 15, and the high-concentration drift region 124 is formed in the same ion implantation process as the source region 14. Since no separate ion implantation process is required to form the multiple guard rings 16 and the high-concentration drift region 124, the semiconductor device 5 can be manufactured at a low manufacturing cost. Note that the high-concentration drift region 124 and the source region 14 may be formed in the same process using crystal growth technology instead of the ion implantation process.

[0046] (Sixth Embodiment) As shown in Figure 9, in the semiconductor device 6 of this embodiment, the semiconductor layer 10 further includes a connecting region 103 between the element region 101 and the termination region 102. The connecting region 103 is provided with a plurality of p-type lower connecting p-type regions 42 formed by the same ion implantation process as the electric field relaxation region 18 of the element region 101 and the plurality of lower guard rings 16a of the termination region 102. Each of the plurality of lower connecting p-type regions 42 extends around the perimeter of the element region 101 when the semiconductor layer 10 is viewed from above, and is spaced apart from each other along the inward and outward directions. The connecting region 103 is further provided with a p-type upper connecting p-type region 44 formed by the same ion implantation process as the body contact region 15 of the element region 101 and the plurality of upper guard rings 16b of the termination region 102. The upper connecting p-type region 44 extends around the perimeter of the element region 101 when the semiconductor layer 10 is viewed in plan view, and is formed to be wide in both the inward and outward directions. When such a connecting region 103 is provided, the electrical resistance when holes generated in the avalanche flow laterally is reduced.

[0047] In the semiconductor device 6 of this embodiment, the high-concentration drift region 124 further comprises a lower layer 124a, an intermediate layer 124b, and an upper layer 124c. The intermediate layer 124b is located in a depth range between the lower layer 124a and the upper layer 124c. In particular, the intermediate layer 124b is located in a portion where the distance between adjacent lower guard rings 16a and upper guard rings 16b is minimized (i.e., a portion including the third depth range Dep3 shown in Figure 3).

[0048] Such a three-layer high-concentration drift region 124 can have the functions described above: a current distribution function in the element region 101, a function to suppress the effect of variations in the amount of positive charge accumulated in the interlayer insulating film 24 of the termination region 102, and a function to broaden the depletion layer well when the semiconductor device 6 is turned off.

[0049] The technical elements disclosed in this specification are listed below. Each of these technical elements is useful independently.

[0050] (Feature 1) A semiconductor device, The semiconductor layer comprises an element region in which an element structure is formed, and a termination region located around the element region. The semiconductor layer located in the termination region is The drift region of the first conductivity type, Surrounded by the aforementioned drift region, a plurality of lower guard rings of the second conductivity type are provided in the first depth range, It has a plurality of upper guard rings of a second conductivity type that are surrounded by the drift region and provided in a second depth range different from the first depth range, Each of the plurality of lower guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction connecting the element region and the termination region. Each of the plurality of upper guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction. Each of the plurality of lower guard rings has a lower inner circumferential surface facing the element region and a lower outer circumferential surface opposite to the lower inner circumferential surface. Each of the plurality of upper guard rings has an upper inner circumferential surface facing the element region and an upper outer circumferential surface opposite to the upper inner circumferential surface. The upper portion of each of the plurality of lower guard rings overlaps with the lower portion of the corresponding upper guard ring among the plurality of upper guard rings. The lower inner surface of each of the plurality of lower guard rings is offset in one direction in the inward or outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings is offset in one of the inward and outward directions with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. A semiconductor device in which the centerlines of each of the plurality of lower guard rings extend parallel to and do not intersect the centerline of the corresponding upper guard ring among the plurality of upper guard rings when the semiconductor layer is viewed in plan.

[0051] (Feature 2) The semiconductor device according to feature 1, wherein the plurality of lower guard rings and the plurality of upper guard rings are configured such that the minimum distance between adjacent rings in the inward and outward directions increases sequentially in the direction toward the terminal region in the inward and outward directions.

[0052] (Feature 3) The lower inner surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The semiconductor device according to feature 1 or 2, wherein the lower outer peripheral surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings.

[0053] The aforementioned drift region is Low concentration drift region, It is provided on the low-concentration drift region and has a high-concentration drift region in which the impurity concentration of the first conductivity type is higher than that of the low-concentration drift region. The semiconductor device according to any one of features 1 to 3, wherein the high-concentration drift region is located in at least the region between adjacent upper guard rings in the inward and outward directions.

[0054] The semiconductor device according to feature 4, wherein the high-concentration drift region is also located in the region between the adjacent lower guard rings in the inward and outward directions.

[0055] The aforementioned high-concentration drift region has a lower layer, an intermediate layer, and an upper layer. The impurity concentration of the first conductivity type in the intermediate layer is lower than the impurity concentration of the first conductivity type in the lower layer and the upper layer. The semiconductor device according to feature 5, wherein the intermediate layer is arranged to include a depth range in which the first depth range and the second depth range overlap.

[0056] The semiconductor device according to any one of features 1 to 6, wherein the semiconductor layer is silicon carbide.

[0057] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0058] 1,2,3,4,5,6: Semiconductor device, 10: Semiconductor layer, 11: Drain region, 12: Drift region, 13: Body region, 14: Source region, 15: Body contact region, 16: Guard ring, 16a: Lower guard ring, 16b: Upper guard ring, 26: Drain electrode, 30: Trench-type insulated gate, 101: Element region, 102: Termination region

Claims

1. Semiconductor devices (1, 2, 3, 4, 5, 6), The semiconductor layer (10) includes an element region (101) on which an element structure is formed, and a termination region (102) located around the element region. The semiconductor layer located in the termination region is The drift region (12) of the first conductivity type, Surrounded by the aforementioned drift region, a plurality of lower guard rings (16a) of the second conductivity type are provided in the first depth range (Dep1), It has a plurality of upper guard rings (16b) of a second conductivity type that are surrounded by the drift region and provided in a second depth range (Dep2) different from the first depth range, Each of the plurality of lower guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction connecting the element region and the termination region. Each of the plurality of upper guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction. Each of the plurality of lower guard rings has a lower inner circumferential surface (162) facing the element region and a lower outer circumferential surface (164) opposite to the lower inner circumferential surface. Each of the plurality of upper guard rings has an upper inner circumferential surface (166) facing the element region and an upper outer circumferential surface (168) opposite to the upper inner circumferential surface. The upper portion of each of the plurality of lower guard rings overlaps with the lower portion of the corresponding upper guard ring among the plurality of upper guard rings. The lower inner surface of each of the plurality of lower guard rings is offset in one direction in the inward or outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings is offset in one of the inward and outward directions with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. The centerlines (CL1) of each of the plurality of lower guard rings extend parallel to and do not intersect the centerlines (CL2) of the corresponding upper guard rings when the semiconductor layer is viewed in plan view. The plurality of lower guard rings and the plurality of upper guard rings are configured such that the minimum distance (d2, d3) between adjacent rings in the inward and outward directions increases sequentially in the direction toward the end region in the inward and outward directions. The lower inner surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. A semiconductor device in which the lower outer peripheral surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings.

2. The aforementioned drift region is Low concentration drift region (122), It is provided on the low-concentration drift region and has a high-concentration drift region (124) in which the impurity concentration of the first conductivity type is higher than that of the low-concentration drift region. The semiconductor device according to claim 1, wherein the high-concentration drift region is located in at least the region between adjacent upper guard rings in the inward and outward directions.

3. The semiconductor device according to claim 2, wherein the high-concentration drift region is also located in the region between the adjacent lower guard rings in the inward and outward directions.

4. The high-concentration drift region has a lower layer (124a), an intermediate layer (124b), and an upper layer (124c). The impurity concentration of the first conductivity type in the intermediate layer is lower than the impurity concentration of the first conductivity type in the lower and upper layers. The semiconductor device according to claim 3, wherein the intermediate layer is arranged to include a depth range in which the first depth range and the second depth range overlap.

5. The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor layer is silicon carbide.

6. Semiconductor devices (2, 3, 4, 5, 6), The semiconductor layer (10) includes an element region (101) on which an element structure is formed, and a termination region (102) located around the element region. The semiconductor layer located in the termination region is The drift region (12) of the first conductivity type, Surrounded by the aforementioned drift region, a plurality of lower guard rings (16a) of the second conductivity type are provided in the first depth range (Dep1), It has a plurality of upper guard rings (16b) of a second conductivity type that are surrounded by the drift region and provided in a second depth range (Dep2) different from the first depth range, Each of the plurality of lower guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction connecting the element region and the termination region. Each of the plurality of upper guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction. Each of the plurality of lower guard rings has a lower inner circumferential surface (162) facing the element region and a lower outer circumferential surface (164) opposite to the lower inner circumferential surface. Each of the plurality of upper guard rings has an upper inner circumferential surface (166) facing the element region and an upper outer circumferential surface (168) opposite to the upper inner circumferential surface. The upper portion of each of the plurality of lower guard rings overlaps with the lower portion of the corresponding upper guard ring among the plurality of upper guard rings. The lower inner surface of each of the plurality of lower guard rings is offset in one direction in the inward or outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings is offset in one of the inward and outward directions with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. The centerlines (CL1) of each of the plurality of lower guard rings extend parallel to and do not intersect the centerlines (CL2) of the corresponding upper guard rings when the semiconductor layer is viewed in plan view. The lower inner surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. The aforementioned drift region is Low concentration drift region (122), It is provided on the low-concentration drift region and has a high-concentration drift region (124) in which the impurity concentration of the first conductivity type is higher than that of the low-concentration drift region. A semiconductor device wherein the high-concentration drift region is located at least in the region between adjacent upper guard rings in the inward and outward directions.

7. Semiconductor devices (1, 2, 3, 4, 5, 6), The semiconductor layer (10) includes an element region (101) on which an element structure is formed, and a termination region (102) located around the element region. The semiconductor layer located in the termination region is The drift region (12) of the first conductivity type, Surrounded by the aforementioned drift region, a plurality of lower guard rings (16a) of the second conductivity type are provided in the first depth range (Dep1), It has a plurality of upper guard rings (16b) of a second conductivity type that are surrounded by the drift region and provided in a second depth range (Dep2) different from the first depth range, Each of the plurality of lower guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction connecting the element region and the termination region. Each of the plurality of upper guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction. Each of the plurality of lower guard rings has a lower inner circumferential surface (162) facing the element region and a lower outer circumferential surface (164) opposite to the lower inner circumferential surface. Each of the plurality of upper guard rings has an upper inner circumferential surface (166) facing the element region and an upper outer circumferential surface (168) opposite to the upper inner circumferential surface. The upper portion of each of the plurality of lower guard rings overlaps with the lower portion of the corresponding upper guard ring among the plurality of upper guard rings. The lower inner surface of each of the plurality of lower guard rings is offset in one direction in the inward or outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings is offset in one of the inward and outward directions with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. The centerlines (CL1) of each of the plurality of lower guard rings extend parallel to and do not intersect the centerlines (CL2) of the corresponding upper guard rings when the semiconductor layer is viewed in plan view. The lower inner surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. The semiconductor device is characterized in that the semiconductor layer is silicon carbide.

8. Semiconductor device (6), The semiconductor layer (10) includes an element region (101) on which an element structure is formed, and a termination region (102) located around the element region. The semiconductor layer located in the termination region is The drift region (12) of the first conductivity type, Surrounded by the aforementioned drift region, a plurality of lower guard rings (16a) of the second conductivity type are provided in the first depth range (Dep1), It has a plurality of upper guard rings (16b) of a second conductivity type that are surrounded by the drift region and provided in a second depth range (Dep2) different from the first depth range, Each of the plurality of lower guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction connecting the element region and the termination region. Each of the plurality of upper guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction. Each of the plurality of lower guard rings has a lower inner circumferential surface (162) facing the element region and a lower outer circumferential surface (164) opposite to the lower inner circumferential surface. Each of the plurality of upper guard rings has an upper inner circumferential surface (166) facing the element region and an upper outer circumferential surface (168) opposite to the upper inner circumferential surface. The upper portion of each of the plurality of lower guard rings overlaps with the lower portion of the corresponding upper guard ring among the plurality of upper guard rings. The lower inner surface of each of the plurality of lower guard rings is offset in one direction in the inward or outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings is offset in one of the inward and outward directions with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. The centerlines (CL1) of each of the plurality of lower guard rings extend parallel to and do not intersect the centerlines (CL2) of the corresponding upper guard rings when the semiconductor layer is viewed in plan view. The aforementioned drift region is Low concentration drift region (122), It is provided on the low-concentration drift region and has a high-concentration drift region (124) in which the impurity concentration of the first conductivity type is higher than that of the low-concentration drift region. The high-concentration drift region is located at least in the region between adjacent upper guard rings in the inward and outward directions. The high-concentration drift region is also located in the region between the adjacent lower guard rings in the inward and outward directions. The high-concentration drift region has a lower layer (124a), an intermediate layer (124b), and an upper layer (124c). The impurity concentration of the first conductivity type in the intermediate layer is lower than the impurity concentration of the first conductivity type in the lower and upper layers. A semiconductor device wherein the intermediate layer is arranged to include a depth range in which the first depth range and the second depth range overlap.

9. Semiconductor devices (1, 2, 3, 4, 5, 6), The semiconductor layer (10) includes an element region (101) on which an element structure is formed, and a termination region (102) located around the element region. The semiconductor layer located in the termination region is The drift region (12) of the first conductivity type, Surrounded by the aforementioned drift region, a plurality of lower guard rings (16a) of the second conductivity type are provided in the first depth range (Dep1), It has a plurality of upper guard rings (16b) of a second conductivity type that are surrounded by the drift region and provided in a second depth range (Dep2) different from the first depth range, Each of the plurality of lower guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction connecting the element region and the termination region. Each of the plurality of upper guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction. Each of the plurality of lower guard rings has a lower inner circumferential surface (162) facing the element region and a lower outer circumferential surface (164) opposite to the lower inner circumferential surface. Each of the plurality of upper guard rings has an upper inner circumferential surface (166) facing the element region and an upper outer circumferential surface (168) opposite to the upper inner circumferential surface. The upper portion of each of the plurality of lower guard rings overlaps with the lower portion of the corresponding upper guard ring among the plurality of upper guard rings. The lower inner surface of each of the plurality of lower guard rings is offset in one direction in the inward or outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings is offset in one of the inward and outward directions with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. The centerlines (CL1) of each of the plurality of lower guard rings extend parallel to and do not intersect the centerlines (CL2) of the corresponding upper guard rings when the semiconductor layer is viewed in plan view. The lower inner surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. A semiconductor device in which the width (W1) measured between the lower inner circumferential surface and the lower outer circumferential surface along the inward-outward direction is the same as the width (W2) measured between the upper inner circumferential surface and the upper outer circumferential surface along the inward-outward direction.

10. Semiconductor devices (1, 2, 3, 4, 5, 6), The semiconductor layer (10) includes an element region (101) on which an element structure is formed, and a termination region (102) located around the element region. The semiconductor layer located in the termination region is The drift region (12) of the first conductivity type, Surrounded by the aforementioned drift region, a plurality of lower guard rings (16a) of the second conductivity type are provided in the first depth range (Dep1), It has a plurality of upper guard rings (16b) of a second conductivity type that are surrounded by the drift region and provided in a second depth range (Dep2) different from the first depth range, Each of the plurality of lower guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction connecting the element region and the termination region. Each of the plurality of upper guard rings extends around the perimeter of the element region when the semiconductor layer is viewed in plan, and is spaced apart from each other along the inward-outward direction. Each of the plurality of lower guard rings has a lower inner circumferential surface (162) facing the element region and a lower outer circumferential surface (164) opposite to the lower inner circumferential surface. Each of the plurality of upper guard rings has an upper inner circumferential surface (166) facing the element region and an upper outer circumferential surface (168) opposite to the upper inner circumferential surface. The upper portion of each of the plurality of lower guard rings overlaps with the lower portion of the corresponding upper guard ring among the plurality of upper guard rings. The lower inner surface of each of the plurality of lower guard rings is offset in one direction in the inward or outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings is offset in one of the inward and outward directions with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. The centerlines (CL1) of each of the plurality of lower guard rings extend parallel to and do not intersect the centerlines (CL2) of the corresponding upper guard rings when the semiconductor layer is viewed in plan view. The lower inner surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper inner surface of the corresponding upper guard ring among the plurality of upper guard rings. The lower outer peripheral surface of each of the plurality of lower guard rings is offset in the direction toward the element region in the inward and outward direction with respect to the upper outer peripheral surface of the corresponding upper guard ring among the plurality of upper guard rings. A semiconductor device in which the second depth range, provided with the plurality of upper guard rings, is a depth range located away from the upper surface of the semiconductor layer.

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