Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device which has a deep groove that penetrates a semiconductor substrate and a manufacturing method of the same.SOLUTION: A semiconductor device includes a semiconductor substrate 1 that has a first main surface 1a and a second main surface 1c opposed to the first main surface, and in which a groove 2 that penetrates from the first main surface to the second main surface is formed. When the longitudinal direction of the groove is a first direction, the short side direction of the groove is a second direction orthogonal to the first direction, and the direction orthogonal to the first direction and the second direction and perpendicular to the first main surface and the second main surface is a third direction, the side surface of the groove being the plane including the first direction and third direction and the plane including the second direction and the third direction is the (111) plane, respectively.SELECTED DRAWING: Figure 2B

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor capacitor in which a capacitor is formed inside a groove of a semiconductor substrate is known. The semiconductor capacitor is formed by laminating a dielectric film and a conductive film inside a groove formed on the surface of the semiconductor substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to increase the capacitance of the semiconductor capacitor, it is necessary to form a deep groove in the semiconductor substrate.

[0005] An embodiment of the present invention provides a semiconductor device having a semiconductor substrate in which a deep groove is formed and a method for manufacturing the same.

Means for Solving the Problems

[0006] A semiconductor device according to an aspect of the present invention includes a semiconductor substrate having a first main surface and a second main surface facing the first main surface, and a groove penetrating from the first main surface to the second main surface. With the longitudinal direction of the groove as the first direction, the short-side direction of the groove as the second direction orthogonal to the first direction, and the direction orthogonal to the first direction and the second direction and perpendicular to the first main surface and the second main surface as the third direction, the side surfaces of the groove in the plane including the first direction and the third direction and the plane including the second direction and the third direction are each (111) planes.

Effects of the Invention

[0007] According to embodiments of the present invention, a semiconductor device having a deep groove penetrating a semiconductor substrate and a method for manufacturing the same can be provided. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view showing the arrangement of grooves on the main surface of the semiconductor substrate of the semiconductor device according to the first embodiment. [Figure 2A] Figure 2A is an enlarged view of the main part of the semiconductor device according to the first embodiment. [Figure 2B] Figure 2B is a cross-sectional view along the line A1-A1 in Figure 2A. [Figure 3A] Figure 3A is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment (part 1). [Figure 3B] Figure 3B is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment (part 2). [Figure 3C] Figure 3C is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment (part 3). [Figure 3D] Figure 3D is a cross-sectional view illustrating the manufacturing method of a semiconductor device according to the first embodiment (part 4). [Figure 4] Figure 4 is a cross-sectional view illustrating the relationship between the length of the groove mask pattern and the etching depth. [Figure 5A] Figure 5A is a schematic plan view showing an example of dividing a semiconductor substrate, whose orientation flat plane is the (100) plane, into chips. [Figure 5B] Figure 5B is a magnified view of the chip shown in Figure 5A. [Figure 5C] Figure 5C is a cross-sectional view along the VC-VC direction in Figure 5B. [Figure 5D] Figure 5D is a cross-sectional view along the VD-VD direction in Figure 5B. [Figure 6A] Figure 6A is a schematic plan view showing an example of dividing a semiconductor substrate, whose orientation flat plane is the (111) plane, into chips. [Figure 6B] Figure 6B is a magnified view of the chip shown in Figure 6A. [Figure 6C] FIG. 6C is a cross-sectional view taken along the line VI-VI of FIG. 6B. [Figure 7] FIG. 7 is a schematic plan view showing another example of dividing a semiconductor substrate having an orifice plane as a (100) plane into chips. [Figure 8A] FIG. 8A is an enlarged view of a main part of a semiconductor device according to a modified example of the first embodiment. [Figure 8B] FIG. 8B is a cross-sectional view taken along the line A2-A2 of FIG. 8A. [Figure 8C] FIG. 8C is a schematic diagram for explaining mask patterns on the first main surface and the second main surface of a semiconductor device according to a modified example of the first embodiment. [Figure 9A] FIG. 9A is a cross-sectional view (part 1) for explaining a method of manufacturing a semiconductor device according to a modified example of the first embodiment. [Figure 9B] FIG. 9B is a cross-sectional view (part 2) for explaining a method of manufacturing a semiconductor device according to a modified example of the first embodiment. [Figure 9C] FIG. 9C is a cross-sectional view (part 3) for explaining a method of manufacturing a semiconductor device according to a modified example of the first embodiment. [Figure 10A] FIG. 10A is an enlarged view of a main part of a semiconductor device according to the second embodiment. [Figure 10B] FIG. 10B is a cross-sectional view taken along the line A3-A3 of FIG. 10A. [Figure 10C] FIG. 10C is a schematic diagram for explaining mask patterns on the first main surface and the second main surface of a semiconductor device according to the second embodiment. [Figure 11A] FIG. 11A is a cross-sectional view (part 1) for explaining a method of manufacturing a semiconductor device according to the second embodiment. [Figure 11B] FIG. 11B is a cross-sectional view (part 2) for explaining a method of manufacturing a semiconductor device according to the second embodiment. [Figure 11C] FIG. 11C is a cross-sectional view (part 3) for explaining a method of manufacturing a semiconductor device according to the second embodiment. [Figure 12A] FIG. 12A is an enlarged view of a main part of a semiconductor device according to the third embodiment. [Figure 12B] Figure 12B is a cross-sectional view along the line A4-A4 in Figure 12A. [Figure 12C] Figure 12C is a schematic diagram illustrating the mask patterns of the first and second main surfaces of the semiconductor device according to the third embodiment. [Figure 13A] Figure 13A is an enlarged view of the main part of the semiconductor device according to the fourth embodiment. [Figure 13B] Figure 13B is a cross-sectional view along the line A5-A5 in Figure 13A. [Figure 13C] Figure 13C is a schematic diagram illustrating the mask patterns of the first and second main surfaces of the semiconductor device according to the fourth embodiment. [Figure 14A] Figure 14A is a cross-sectional view illustrating the method of forming grooves by wet etching (Part 1). [Figure 14B] Figure 14B is a cross-sectional view illustrating the method of forming grooves by wet etching (part 2). [Figure 14C] Figure 14C is a cross-sectional view illustrating the method of forming grooves by wet etching (part 3). [Figure 14D] Figure 14D is a cross-sectional view illustrating the method of forming grooves by wet etching (part 4). [Figure 14E] Figure 14E is a cross-sectional view illustrating the method of forming grooves by wet etching (part 5). [Figure 15A] Figure 15A is a cross-sectional view illustrating another method of forming grooves by wet etching (part 1). [Figure 15B] Figure 15B is a cross-sectional view illustrating another method of forming grooves by wet etching (part 2). [Figure 15C] Figure 15C is a cross-sectional view illustrating another method of forming grooves by wet etching (part 3). [Figure 16] Figure 16 is an enlarged view of a key part of a semiconductor device in which multiple grooves are formed. [Figure 17A]Figure 17A is a cross-sectional view showing an example of a semiconductor capacitor included in the semiconductor device according to the embodiment. [Figure 17B] Figure 17B is a cross-sectional view showing another example of a semiconductor capacitor included in the semiconductor device according to the embodiment. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals and their descriptions are omitted. However, the drawings are schematic and may contain parts that differ from reality, such as the relationship between thickness and planar dimensions and the ratio of the thickness of each layer. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings.

[0010] (First Embodiment) Figure 1 is a plan view showing the semiconductor substrate 1 of the semiconductor device 10 according to the first embodiment. The semiconductor substrate 1 has a first main surface 1a and a second main surface 1c facing the first main surface 1a. In the following, unless otherwise specified, the first main surface 1a and the second main surface 1c will be referred to as the main surface. Figure 2A is an enlarged view of the main part P of the semiconductor device 10 shown in Figure 1. Figure 2B is a cross-sectional view along the line A1-A1 in Figure 2A. The configuration of the semiconductor device 10 according to the first embodiment will be described below with reference to Figures 1, 2A, and 2B. In the following description, the XYZ coordinate system, which is an example of a Cartesian coordinate system, will be used. That is, the plane parallel to the main surface of the semiconductor substrate 1 will be the XY plane, and the direction perpendicular to the XY plane will be the Z axis. The X axis and Y axis will be perpendicular directions within the XY plane. In the following explanation, for the sake of clarity, we will use a top-down relationship where the positive Z-axis side (first principal surface 1a side) is the top of the drawing and the negative Z-axis side (second principal surface 1c side) is the bottom of the drawing. However, this does not represent a universal top-down relationship.

[0011] As shown in Figure 2B, the semiconductor device 10 includes a semiconductor substrate 1 in which a trench 2, which is a groove penetrating from the first main surface 1a to the second main surface 1c, is formed.

[0012] As shown in Figure 1, the semiconductor substrate 1 has an orientation flat (hereinafter referred to as the orientation flat surface) called the orientation flat surface 1b. The first main surface 1a and the second main surface 1c are (110) planes. The orientation flat surface 1b is a (100) plane that is perpendicular to the (110) planes of the first main surface 1a and the second main surface 1c.

[0013] The semiconductor substrate 1 has a diamond crystal structure. The semiconductor substrate 1 may be, for example, a silicon substrate. The thickness t of the semiconductor substrate 1 is, for example, about 625 to 665 μm. By using an easily available silicon substrate for the semiconductor substrate 1, the semiconductor device 10 can be manufactured at low cost. Furthermore, when the semiconductor device 10 includes a semiconductor capacitor, the resistance of the semiconductor substrate 1 that serves as the electrode for the semiconductor capacitor can be reduced by increasing the impurity concentration of the silicon substrate. This reduces the influence of parasitic resistance on the electrical characteristics of the capacitor.

[0014] A stripe pattern of trenches 2 is formed on the semiconductor substrate 1 when viewed from the direction of the surface normal to the main surface (hereinafter also referred to as "plan view"). As shown in Figure 2B, the trenches 2 penetrate from the first main surface 1a to the second main surface 1c. On the first main surface 1a, the trenches 2 have one end along the longitudinal direction with a length La (hereinafter referred to as "La") and the other end along the short direction perpendicular to the longitudinal direction with a length Wa (hereinafter referred to as "Wa"). On the second main surface 1c, the trenches 2 have one end along the longitudinal direction with a length Lb (hereinafter referred to as "Lb") and the other end along the short direction perpendicular to the longitudinal direction with a length Wb (hereinafter referred to as "Wb"). In the following description, the length of one end of the trenches 2 in the longitudinal direction is also referred to as the length of the trenches 2, and the length of the other end of the trenches 2 in the short direction is also referred to as the width of the trenches 2. Furthermore, the opening on the first main surface 1a side of trench 2 is also referred to as the upper part 2a of trench 2, and the opening on the second main surface 1c side of trench 2 is also referred to as the lower part 2c of trench 2. The longitudinal direction of trench 2 is referred to as the first direction, the short direction of trench 2 as the second direction, and the direction perpendicular to the longitudinal and short directions of trench 2 (the depth direction of trench 2) as the third direction. The third direction is perpendicular to the first and second directions and perpendicular to the first main surface 1a and the second main surface 1c.

[0015] Trench 2 is formed such that, in a plan view, one end of the trench 2 in the longitudinal direction (hereinafter also referred to as the "longitudinal end") is parallel to the (111) plane of the semiconductor substrate 1. Also, in a plan view, trench 2 is formed such that, in a plan view, the other end of the trench 2 in the short direction (hereinafter also referred to as the "short end") is perpendicular to the (111) plane of the semiconductor substrate 1. When the first main surface 1a and the second main surface 1c are (110) planes and the orientation flat surface 1b is a (100) plane, the plane having an angle θ1 of 35.3° with respect to the orientation flat surface 1b is the (111) plane of the semiconductor substrate 1. That is, the plane that intersects the (100) plane, which is perpendicular to the XY plane and extends in the X-axis direction as shown in Figure 2A, at an angle θ1 is the (111) plane.

[0016] As shown in Figure 2B, the trench 2 penetrates the semiconductor substrate 1 perpendicularly to its main surface. The longitudinal side surface 2b1, which is a plane containing the first and third directions, is the (111) plane. Similarly, the short side surface 2b2, which is a plane containing the second and third directions, is also the (111) plane. The relationship between the lengths La and Lb of the trench 2 and the thickness t of the semiconductor substrate 1 will be described later.

[0017] A method for manufacturing the semiconductor device 10 according to the first embodiment will be described below with reference to the drawings. The method for manufacturing the semiconductor device 10 described below is an example of forming trenches 2 in the semiconductor substrate 1 by wet etching, and can be realized by various other wet etching methods. The masking process for forming the trenches 2 will be described in detail in the explanation of Figures 14A to 15C.

[0018] First, as shown in Figure 3A, a semiconductor substrate 1 with a (110) plane is prepared, where the first main surface 1a and the second main surface 1c are (110) planes.

[0019] Next, as shown in Figure 2A, the longitudinal direction of the trench 2 is aligned with the (111) plane of the semiconductor substrate 1. Then, as shown in Figure 3B, anisotropic etching is performed on the trench 2 region of the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 from both sides of the first main surface 1a and the second main surface 1c by wet etching. The etching solution used for wet etching of the semiconductor substrate 1 is, for example, an alkaline aqueous solution. Examples of alkaline aqueous solutions include potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). By etching the silicon substrate with relatively readily available and inexpensive etching solutions such as KOH and TMAH, it is possible to manufacture the semiconductor device 10 at a low cost.

[0020] Anisotropic wet etching can be achieved by etching with an alkaline aqueous solution. Specifically, in the thickness direction, the semiconductor substrate 1 is etched perpendicular to the main surface at the longitudinal end of a trench 2 of lengths La and Lb. On the other hand, at the short end of a trench 2 of widths Wa and Wb, as shown in Figure 3B, the (111) plane of the semiconductor substrate 1 is exposed by anisotropic etching, and a first bevel 2d1 and a second bevel 2d2 are formed. At this time, as etching progresses from both sides of the first main surface 1a and the second main surface 1c, an intermediate region is formed on both sides of the central part 2e1 and 2e2, which are recessed in the thickness direction of the semiconductor substrate 1 from the first main surface 1a and the second main surface 1c, as the trench 2 penetrates the semiconductor substrate 1. The central part 2e1 and 2e2 are the (110) plane and are connected to the first bevel 2d1 and the second bevel 2d2, respectively.

[0021] Next, wet etching is further carried out from the first main surface 1a and the second main surface 1c to etch away the intermediate region having central portions 2e1 and 2e2, as shown in Figure 3C, so that the center of the trench 2 penetrates from the first main surface 1a to the second main surface 1c. In this way, in order to form a trench 2 whose sides are perpendicular to the first main surface 1a and the second main surface 1c of the semiconductor substrate 1, the grooves formed by wet etching from the first main surface 1a and the second main surface 1c respectively must be connected, and the intermediate region must penetrate through them. In the following description, the region that penetrates the intermediate region with central portions 2e1 and 2e2 of the trench 2 on both sides will also be referred to as the "initial penetration portion". The formation of this initial penetration portion will be described later with reference to Figure 4.

[0022] After the initial penetration is formed, etching proceeds in the direction of the substrate plane on the slanted surfaces on both sides of the penetration, as shown in Figure 3D. That is, the first slanted surface 2d1 and the second slanted surface 2d2 of the trench 2 are anisotropically etched. Specifically, after the initial penetration is formed, etching of the first slanted surface 2d1 and the second slanted surface 2d2 of the semiconductor substrate 1 proceeds from the leading edge of the first slanted surface 2d1 and the second slanted surface 2d2 to the short-side end of the trench 2 with widths Wa and Wb. Ultimately, the first slanted surface 2d1 and the second slanted surface 2d2 are completely etched away, and a trench 2 is formed in which the (111) plane, the short-side surface 2b2 of the trench 2 with widths Wa and Wb, is perpendicular to the main surface of the semiconductor substrate 1.

[0023] As described above, in the method for manufacturing the semiconductor device 10, the longitudinal direction of the trench 2 is set to be parallel or perpendicular to the (111) plane of the semiconductor substrate 1 in the trench 2 regions of the first main surface 1a and the second main surface 1c of the semiconductor substrate 1. Then, by anisotropic etching using wet etching, a trench 2 can be formed in which the side surface is perpendicular to the main surface of the semiconductor substrate 1. If the semiconductor substrate 1 is etched by wet etching from only one of the first main surface 1a or the second main surface 1c, a slope of the (111) plane is formed, making it difficult to form a stripe-type trench 2 in which the side surface is perpendicular to the main surface. However, according to the above manufacturing method, by etching the semiconductor substrate 1 from both the first main surface 1a and the second main surface 1c by wet etching, a stripe-type trench 2 in which the side surface is perpendicular to the main surface can be formed.

[0024] Next, the conditions for forming the initial penetration when using anisotropic etching with wet etching on both the first main surface 1a and the second main surface 1c will be explained with reference to Figure 4. By forming the initial penetration, etching proceeds from the initial penetration in the direction of the substrate plane by wet etching, and finally, a trench 2 with a stripe pattern is formed, in which the side surface is a (111) plane perpendicular to the main surface.

[0025] Figure 4 shows an example of a groove formed by wet etching from the first main surface 1a and the second main surface 1c during the formation of trench 2. The length of the groove formed from the first main surface 1a is La and the depth of the groove is Da, while the length of the groove formed from the second main surface 1c is Lb and the depth of the groove is Db. As shown in Figure 4, the length of the first slope 2d1 in plan view is Lae, the length of the second slope 2d2 in plan view is Lbe, and the length of the initial penetration is Lt. The sum of the groove depths Da and Db is the thickness t of the semiconductor substrate 1. These relationships are expressed by the following equations (1), (2), and (3).

[0026] La = 2Lae + Lt (1) Lb = 2Lbe + Lt (2) Da + Db = t (3) When the crystal structure of semiconductor substrate 1 is a diamond structure, the relationship between the lengths Lae and Lbe of the (111) plane slopes formed by wet etching and the etching depths Da and Db is expressed by equations (4) and (5).

[0027] Lae = √2Da (4) Lbe = √2Db (5) The sum of the length La of trench 2 in the first main surface 1a and the length Lb of trench 2 in the second main surface 1c is expressed by equation (6), based on equations (1) to (5) above.

[0028] La + Lb = 2√2t + 2Lt (6) Therefore, the length Lt of the initial penetration is given by equation (7).

[0029] Lt = (La + Lb) / 2 - √2t (7) From equation (7), for the initial penetration to be formed, the length of the initial penetration, Lt, must be 0. Therefore, from equation (7), the following relationship, equation (8), is obtained.

[0030] Lt = (La + Lb) / 2 - √2t > 0 (8) From equation (8), the sum of the lengths La and Lb of trench 2 is expressed by the following equation (9).

[0031] La + Lb > 2√2t (9) In other words, if the sum of the length La of the trench 2 in the first direction on the first main surface 1a and the length Lb of the trench 2 in the first direction on the second main surface 1c is 2√2 times or more the thickness t of the semiconductor substrate 1, then an initial penetration is formed.

[0032] Furthermore, as shown in Figure 2B, when the length La of trench 2 on the first main surface 1a and the length Lb of trench 2 on the second main surface 1c are equal (La = Lb = L), the following relationship (10) is obtained from equation (9). Therefore, the condition for the length L of trench 2 when lengths La and Lb are equal is expressed by the following equation (11).

[0033] La + Lb = 2L > 2√2t (10) L>√2t (11) According to equations (10) and (11), if the length L of the trench 2 is √2 times or more the thickness t of the semiconductor substrate 1, an initial penetration is formed, and a trench 2 with a side perpendicular to the main surface is formed. For example, when the lengths of the trenches 2 or the mask pattern of the trench 2 on the first main surface 1a and the second main surface 1c are equal, the condition for the trench 2 is that the length of the trench 2 or the mask pattern of the trench 2 is √2 times or more the thickness t of the semiconductor substrate 1. The "mask pattern" is the shape of the opening of the etching mask used for wet etching (hereinafter also simply referred to as "mask"). The portion exposed to the mask pattern is etched by wet etching.

[0034] As described above, by making the length of the mask pattern formed on the first main surface 1a the same as the length of the mask pattern formed on the second main surface 1c, etching of both the first main surface 1a and the second main surface 1c is possible with the same mask pattern. This makes it easier to design the mask pattern and procure the mask material, and also shortens the etching time because the semiconductor substrate 1 is etched to the same depth from both the first main surface 1a and the second main surface 1c.

[0035] As described above, the formation of trenches 2 in the semiconductor device 10 according to the first embodiment can be achieved by wet etching. On the other hand, dry etching, which etches the material with a reactive gas (etching gas), ions, or radicals, can also be used to form deep trenches 2 in the semiconductor substrate 1. However, dry etching is a single-wafer etching process that processes wafers one at a time, resulting in low throughput and high costs. In contrast, in wet etching, multiple wafers are placed in a wafer case, and the etching process is performed by immersing the wafer case in an etching solution. Therefore, wet etching makes it possible to process multiple wafers simultaneously, and manufacturing costs can be reduced compared to dry etching.

[0036] Wet etching allows for the formation of trenches by taking advantage of the fact that the etching rate differs depending on the crystal plane. Specifically, by utilizing the fact that some crystal planes are relatively easy to etch and others are relatively difficult to etch, deep trenches can be formed at low cost. For example, in a semiconductor substrate 1 where the first main surface 1a and the second main surface 1c are (110) planes and the orientation flat surface 1b is a (100) plane, deep trenches 2 with a stripe pattern and an angle θ1 of 35.3 degrees with the orientation flat surface 1b can be formed by wet etching from the main surfaces. In this case, the side surface of trench 2 is the (111) plane.

[0037] When the semiconductor substrate 1 is etched from the main surface of the (110) plane by wet etching, a bevel of the (111) plane is formed at the bottom of the end of the trench 2 of the stripe pattern. However, in the manufacturing method of the semiconductor device 10 according to the first embodiment, grooves are formed from both the first main surface 1a and the second main surface 1c by wet etching to form a starting penetration. Then, as etching progresses from the starting penetration in the direction of the substrate plane, trenches 2 can be formed throughout the entire stripe pattern, with the sides perpendicular to the main surface in the depth direction, similar to trenches formed by dry etching. As a result, for example, when the trench 2 is used as a semiconductor capacitor, the area of ​​the sides of the trench 2 can be increased to increase the capacitor capacity.

[0038] In the following, we will examine a method for manufacturing a semiconductor device 10 by dividing a semiconductor substrate 1 into multiple chips. Below, we will illustrate with an example a method of dividing the semiconductor substrate 1 into a rectangular shape based on the orientation flat plane 1b. When using the orientation flat plane 1b as a reference, cutting lines are set to cut the semiconductor substrate 1 parallel and perpendicular to the orientation flat plane 1b. A semiconductor device 10 containing a trench 2 is formed in each of the chips obtained by dividing the semiconductor substrate 1 along the cutting lines.

[0039] First, consider the case where the semiconductor substrate 1 is a diamond-structured wafer, as shown in Figure 5A, with the first main surface 1a and the second main surface 1c being (110) planes and the orientation flat surface 1b being a (100) plane. In this case, the rectangular chip 101 obtained by dividing the semiconductor substrate 1 along cutting lines set parallel and perpendicular to the orientation flat surface 1b has a chip side surface 101S that is (100) plane and parallel to the orientation flat surface 1b, as shown in Figure 5B. The longitudinal direction of the trench 2 containing the chip 101 intersects the chip side surface 101S at an angle θ1 of 35.3°.

[0040] As already explained, if the sum of the length La in the first direction of the first main surface 1a of the trench 2 and the length Lb in the first direction of the second main surface 1c is 2√2 times or more the thickness t of the semiconductor substrate 1, an initial penetration is formed. However, in the corner region 101C of the chip 101 shown in Figure 5B, both length La and length Lb are short. Therefore, even if anisotropic etching of the semiconductor substrate 1 is performed by wet etching from both the first main surface 1a and the second main surface 1c, an initial penetration is not formed, as shown in Figure 5C, a cross-sectional view along the VC-VC direction in Figure 5B. That is, the first bevel 2d1 is exposed inside the first groove 201 formed on the first main surface 1a, and the second bevel 2d2 is exposed inside the second groove 202 formed on the second main surface 1c, after which the central portions 2e1 and 2e2 are not formed. As a result, the bottom of the first groove 201 and the bottom of the second groove 202 do not communicate, and an initial penetration is not formed. Therefore, in the corner region 101C, it is not possible to form a trench 2 with a side perpendicular to the main surface using wet etching. On the other hand, in the region excluding the corner region 101C, where the sum of length La and length Lb is 2√2 times or more the thickness t, a starting penetration is formed. As a result, as shown in Figure 5D, a cross-sectional view along the VD-VD direction in Figure 5B, a trench 2 having a side perpendicular to the first main surface 1a and the second main surface 1c is formed. However, in the method of dividing the semiconductor substrate 1 shown in Figure 5A, there are regions in the chip 101 where a starting penetration is not formed, which reduces the manufacturing efficiency of the semiconductor device 10.

[0041] Next, we consider the case where the semiconductor substrate 1 is a diamond-structured wafer, as shown in Figure 6A, with the first main surface 1a and the second main surface 1c being (110) planes and the orientation flat surface 1b being a (111) plane. In order to divide the semiconductor substrate 1 into multiple rectangular chips 101, the cutting lines on the first main surface 1a are determined parallel and perpendicular to the orientation flat surface 1b, using the orientation flat surface 1b as a reference. Since the orientation flat surface 1b is a (111) plane, the cutting plane of the semiconductor substrate 1 parallel to the orientation flat surface 1b is a (111) plane. Then, the semiconductor substrate 1 is cut along this cutting line, dividing the semiconductor substrate 1 into multiple chips 101.

[0042] As described above, the rectangular chip 101 obtained by dividing the semiconductor substrate 1, whose orientation flat surface 1b is the (111) plane, includes the chip side surface 101S of the (111) plane, as shown in Figure 6B. Therefore, as shown in Figure 6B, the longitudinal direction of the trench 2 can be made parallel to the chip side surface 101S of the chip 101. In other words, a semiconductor device 10 is obtained formed on a chip 101 having a chip side surface 101S that is perpendicular and adjacent to the first main surface 1a and the second main surface 1c, and parallel to the first direction.

[0043] In the chip 101 obtained by dividing the semiconductor substrate 1 shown in Figure 6A, the sum of the length La in the first direction of the first main surface 1a and the length Lb in the first direction of the second main surface 1c of the trench 2 can be made to be 2√2 times or more the thickness t of the semiconductor substrate 1 across the entire main surface of the chip 101. As a result, a starting point for the trench 2 is formed across the entire surface of the chip 101. Consequently, as shown in Figure 6C, a trench 2 having sides perpendicular to the first main surface 1a and the second main surface 1c can be formed across the entire surface of the chip 101.

[0044] As described above, by dividing a semiconductor substrate 1, whose orientation flat plane 1b is the (111) plane, into multiple chips 101 based on the orientation flat plane 1b, the area of ​​the chips 101 can be effectively utilized. For example, by manufacturing a semiconductor device 10 using a semiconductor substrate 1 whose orientation flat plane 1b is the (111) plane, the manufacturing efficiency of a semiconductor device 10 having a capacitor with a high capacitance density can be improved. In addition, although the case in which the longitudinal direction of the trench 2 is parallel to the orientation flat plane 1b was described above, the longitudinal direction of the trench 2 may also be perpendicular to the orientation flat plane 1b.

[0045] In the explanation using Figures 6A to 6C, a semiconductor substrate 1 with an orientation flat plane 1b being the (111) plane was prepared, and the case where the cutting lines were determined parallel and perpendicular to the orientation flat plane 1b was explained as an example. By cutting the semiconductor substrate 1 along these cutting lines, the semiconductor substrate 1 is divided into a plurality of chips 101, each containing a chip side surface 101S of the (111) plane. However, regardless of the crystal plane of the orientation flat plane 1b, the cutting line on the first main surface 1a may be determined so that the cut surface of the semiconductor substrate 1 is the (111) plane. In other words, by determining the cutting line parallel to the (111) plane and cutting the semiconductor substrate 1 along the cutting line, the semiconductor substrate 1 is divided into a plurality of chips 101, each containing a chip side surface 101S of the (111) plane. For example, as shown in Figure 7, for a semiconductor substrate 1 with an orientation flat plane 1b being the 100 plane, the direction CC of the cutting line may be set so that it intersects the orientation flat plane 1b at an angle θ1.

[0046] (Modified version of the first embodiment) The configuration of the semiconductor device 10 according to a modification of the first embodiment will be described with reference to Figures 8A to 9C. In the semiconductor device 10 shown in Figure 8A, the length La2 and width Wa2 of the first main surface 1a of the trench 2A are different from the length La and width Wa of the first main surface 1a of the trench 2 in the first embodiment. Although not shown, the length Lb2 and width Wb2 of the second main surface 1c of the trench 2A are different from the length Lb and width Wb of the second main surface 1c of the trench 2 in the first embodiment. For components of the semiconductor device 10 according to the modification of the first embodiment that overlap with the first embodiment, the reference numerals are used and their explanation is omitted. The following description will focus on the differences between the modification of the first embodiment and the first embodiment.

[0047] As shown in Figures 8B and 8C, the length LaM2 of the mask pattern of the trench 2A in the first direction on the first main surface 1a is shorter than the length LbM2 of the mask pattern of the trench 2A in the first direction on the second main surface 1c. Similarly, as shown in Figure 8C, the width WaM2 of the mask pattern of the trench 2 in the second direction on the first main surface 1a is smaller than the width WbM2 of the mask pattern of the trench 2 in the second direction on the second main surface 1c. If the sum of the length LaM2 of the mask pattern of the trench 2A in the first direction on the first main surface 1a and the length LbM2 of the mask pattern of the trench 2A along the first direction on the second main surface 1c is 2√2 times or more the thickness t of the semiconductor substrate 1, then an initial penetration is formed. As a result, a trench 2A with sides perpendicular to the first main surface 1a and the second main surface 1c is formed. The length of the trench 2A is the longer of the mask pattern length LaM2 and the mask pattern length LbM2. In other words, the lengths La2 and Lb2 of the trench 2A after formation are approximately equal to the length LbM2 of the mask pattern.

[0048] A method for manufacturing a semiconductor device 10 according to a modified example of the first embodiment will be described below with reference to the drawings.

[0049] First, as shown in Figure 8C, the longitudinal direction of the trench 2A is aligned parallel to the (111) plane of the semiconductor substrate 1. Alternatively, the longitudinal direction of the trench 2A may be aligned perpendicularly to the (111) plane of the semiconductor substrate 1. Then, anisotropic etching is performed on both sides of the trench 2A region of the first main surface 1a and the second main surface 1c of the semiconductor substrate 1. Moving from the first main surface 1a and the second main surface 1c toward the thickness direction of the semiconductor substrate 1, the semiconductor substrate 1 is etched perpendicular to the main surface at the longitudinal end of the trench 2A with lengths La2 and Lb2. On the other hand, at the short end of the trench 2A with widths Wa and Wb, as shown in Figure 9A, the (111) plane of the semiconductor substrate 1 is exposed by anisotropic etching, and the first bevel 2d1 and the second bevel 2d2 are formed. Then, as anisotropic etching progresses from the first main surface 1a and the second main surface 1c of the semiconductor substrate 1, an intermediate region is formed with central portions 2e1 and 2e2 on both sides, which are recessed in the thickness direction of the semiconductor substrate 1 from the first main surface 1a and the second main surface 1c.

[0050] Next, as shown in Figure 9B, anisotropic etching is performed to form a starting penetration through the central parts 2e1 and 2e2 of the trench 2A. Specifically, wet etching is further performed in the thickness direction of the semiconductor substrate 1 to completely etch away the central parts 2e1 and 2e2 and form the starting penetration.

[0051] Next, as shown in Figure 9C, wet etching is performed from the leading edges of the first and second bevel surfaces 2d1 and 2d2 to the shorter end of the width Wa2. In other words, after the initial penetration is formed, etching proceeds in the direction of the substrate plane of the semiconductor substrate 1 on the first and second bevel surfaces 2d1 and 2d2. Finally, the shorter side surface 2b2 of the trench 2A with width Wa2 is formed perpendicular to the first main surface 1a and the second main surface 1c. That is, even if the length LaM2 of the mask pattern of the trench 2A on the first main surface 1a is different from the length LbM2 of the mask pattern of the trench 2A on the second main surface 1c, the lengths La2 and Lb2 of the formed trench 2A will be approximately equal to the length LbM2 of the mask pattern. Furthermore, even if the width WaM2 of the mask pattern of trench 2A on the first main surface 1a is different from the width WbM2 of the mask pattern of trench 2A on the second main surface 1c, the widths Wa2 and Wb2 of the formed trench 2A will be approximately equal to the width WbM2 of the mask pattern.

[0052] As described above, in the semiconductor device 10 in the modified version of the first embodiment, the trench 2A is formed by anisotropic etching using wet etching with the longitudinal direction of the trench 2A aligned parallel or perpendicular to the (111) plane of the semiconductor substrate 1. The side surface of the trench 2A is perpendicular to the main surface.

[0053] According to the semiconductor device 10 in a modified version of the first embodiment, even if there is a misalignment in plan view between the position of the mask pattern of the trench 2A on the first main surface 1a and the position of the mask pattern of the trench 2A on the second main surface 1c, a trench 2A having a side perpendicular to the main surface can be formed. That is, after forming an initial penetration, anisotropic etching by wet etching can be performed to form a trench 2A having a (111) plane side. When there is a misalignment in plan view between the positions of the mask patterns, the area in which the trench 2A is formed has a shape that includes the region where the mask pattern of the first main surface 1a and the mask pattern of the second main surface 1c overlap in plan view. In other words, the size of the trench 2A in plan view is larger than the size of the mask pattern in plan view.

[0054] (Second Embodiment) The configuration of the semiconductor device 10 according to the second embodiment will be described with reference to Figures 10A to 11C. In the semiconductor device 10 according to the second embodiment, the length La3 and width Wa3 of the first main surface 1a of trench 2B are approximately equal to the length La and width Wa of the first main surface 1a of trench 2 in the first embodiment. Also, the length Lb3 and width Wb3 of the second main surface 1c of trench 2B are approximately equal to the length Lb and width Wb of the second main surface 1c of trench 2 in the first embodiment. The difference between the semiconductor device 10 according to the second embodiment and the first embodiment is the mask pattern during trench formation. For components of the second embodiment that overlap with the first embodiment, the reference numerals are used and their explanation is omitted. The following will mainly describe the differences between the first and second embodiments.

[0055] As shown in Figures 10B and 10C, the length LaM3 of the mask pattern of the trench 2B in the first direction on the first main surface 1a is longer than the length LbM3 of the mask pattern of the trench 2B in the first direction on the second main surface 1c. On the other hand, as shown in Figure 10C, the width WaM3 of the mask pattern of the trench 2B in the second direction on the first main surface 1a is approximately equal to the width WbM3 of the mask pattern of the trench 2B in the second direction on the second main surface 1c. If the sum of the length LaM3 of the mask pattern of the trench 2B on the first main surface 1a and the length LbM3 of the mask pattern on the second main surface 1c is 2√2 times or more the thickness t of the semiconductor substrate 1, an initial penetration is formed. As a result, a trench 2B with its side surface perpendicular to the main surface is formed by wet etching. The length of the trench 2B is the longer of the mask pattern length LaM3 and the mask pattern length LbM3. In other words, the lengths La3 and Lb3 of the trench 2B after formation are approximately equal to the length LaM3 of the mask pattern.

[0056] A method for manufacturing the semiconductor device 10 according to the second embodiment will be described below with reference to the drawings.

[0057] First, as shown in Figure 10C, the longitudinal direction of the trench 2B is aligned parallel to the (111) plane of the semiconductor substrate 1. Alternatively, the longitudinal direction of the trench 2B may be aligned perpendicular to the (111) plane of the semiconductor substrate 1. Then, anisotropic etching is performed on the trench 2B region of the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 from both sides by wet etching. Due to this wet etching, the semiconductor substrate 1 is etched perpendicular to the main surface at the longitudinal end of the trench 2B with lengths La2 and Lb2, in the thickness direction from the first main surface 1a and the second main surface 1c. On the other hand, at the short end of the trench 2B with widths Wa and Wb, as shown in Figure 11A, the (111) plane of the semiconductor substrate 1 is exposed by anisotropic etching, and the first bevel 2d1 and the second bevel 2d2 are formed. Then, as anisotropic etching progresses from the first main surface 1a and the second main surface 1c of the semiconductor substrate 1, an intermediate region is formed with central portions 2e1 and 2e2 on both sides, which are recessed in the thickness direction of the semiconductor substrate 1 from the first main surface 1a and the second main surface 1c.

[0058] Next, as shown in Figure 11B, anisotropic etching is performed on the central portions 2e1 and 2e2 of the trench 2B. Specifically, wet etching is further performed in the thickness direction of the semiconductor substrate 1 to etch away the central portions 2e1 and 2e2, forming the initial penetration portion.

[0059] Next, as shown in Figure 11C, further wet etching is performed in the substrate plane direction of the semiconductor substrate 1 from the tips of the first and second inclined surfaces 2d1 and 2d2 to the short-side end of the trench 2B with width Wa2. In other words, after the formation of the initial penetration, etching proceeds in the substrate plane direction of the semiconductor substrate 1 on the first and second inclined surfaces 2d1 and 2d2. Ultimately, a trench 2B is formed with a short-side surface 2b2 of width Wa2 perpendicular to the main surface of the semiconductor substrate 1. That is, even if the length LbM3 of the mask pattern of the trench 2B on the second main surface 1c is different from the length LaM2 of the mask pattern of the trench 2B on the first main surface 1a, the lengths La3 and Lb3 of the formed trench 2B will be approximately equal to the length LaM3 of the mask pattern.

[0060] In the semiconductor device 10 of the second embodiment, the trench 2B is formed by anisotropic etching using wet etching with the longitudinal direction of the trench 2B aligned parallel or perpendicular to the (111) plane of the semiconductor substrate 1. That is, an initial penetration is formed, and after the formation of the initial penetration, anisotropic etching is carried out to form the trench 2B.

[0061] According to the semiconductor device 10 of the second embodiment, even if the length of the mask pattern of the trench 2B on the first main surface 1a and the length of the mask pattern of the trench 2B on the second main surface 1c are different, a trench 2B having a side surface perpendicular to the main surface can be formed.

[0062] Furthermore, according to the semiconductor device 10 of the second embodiment, the trench 2B can be formed based on the length of the mask pattern of the trench 2B on the first main surface 1a. That is, by making the length of the mask pattern of the trench 2B on the second main surface 1c shorter than the length of the mask pattern of the trench 2B on the first main surface 1a, a trench 2B of the reference length can be formed.

[0063] (Third embodiment) The configuration of the semiconductor device 10 according to the third embodiment will be described with reference to Figures 12A to 12C. In the semiconductor device 10 according to the third embodiment, the length La4 and width Wa4 of the trench 2C on the first main surface 1a are approximately equal to the length La and width Wa of the trench 2 on the first main surface 1a of the first embodiment. Also, the length Lb4 and width Wb4 of the trench 2C on the second main surface 1c are approximately equal to the length Lb and width Wb of the trench 2 on the second main surface 1c of the trench 2 of the first embodiment. The difference between the semiconductor device 10 according to the third embodiment and the first embodiment is the mask pattern during trench formation. For components of the third embodiment that overlap with the first embodiment, their reference numerals are used and their explanation is omitted. The following will mainly describe the differences between the first and third embodiments.

[0064] As shown in Figures 12B and 12C, the length LaM4 of the mask pattern of the trench 2C in the first direction on the first main surface 1a is approximately equal to the length LbM4 of the mask pattern of the trench 2C in the first direction on the second main surface 1c. On the other hand, the width WaM4 of the mask pattern of the trench 2C in the second direction on the first main surface 1a is longer than the width WbM4 of the mask pattern of the trench 2C in the second direction on the second main surface 1c. If the sum of the lengths LaM4 and LbM4 of the mask pattern of the trench 2C is √2 times or more the thickness t of the semiconductor substrate 1, a starting penetration is formed. As a result, a trench 2C with a side surface perpendicular to the main surface is formed. The width of the trench 2C is the longer of the mask pattern width WaM4 and the mask pattern width WbM4. That is, the widths Wa4 and Wb4 of the trench 2C are approximately equal to the mask pattern width WaM4. Note that the manufacturing method is omitted because the explanation of the cross-sectional view is the same as in the first embodiment.

[0065] In the semiconductor device 10 of the third embodiment, the trench 2C is formed by anisotropic etching using wet etching when the longitudinal direction of the trench 2C is aligned parallel or perpendicular to the (111) plane of the semiconductor substrate 1. According to the semiconductor device 10 of the third embodiment, even if the width of the mask pattern of the trench 2C on the first main surface 1a and the width of the mask pattern of the trench 2C on the second main surface 1c are different, a trench 2C having a side surface perpendicular to the main surface can be formed. That is, the trench 2C is formed by proceeding with anisotropic etching by wet etching after forming an initial penetration.

[0066] Furthermore, according to the semiconductor device 10 in the third embodiment, the trench 2B can be formed based on the width of the mask pattern of the trench 2B on the first main surface 1a. That is, by making the width of the mask pattern of the trench 2B on the second main surface 1c smaller than the width of the mask pattern of the trench 2B on the first main surface 1a, a trench 2B of a reference length can be formed.

[0067] (Fourth Embodiment) The configuration of the semiconductor device 10 according to the fourth embodiment will be described with reference to Figures 13A to 13C. In the semiconductor device 10 according to the fourth embodiment, the length La5 and width Wa5 of the first main surface 1a of trench 2D, which is an example of a trench, are approximately equal to the length La and width Wa of the first main surface 1a of trench 2 in the first embodiment. Also, the length Lb5 and width Wb5 of the second main surface 1c of trench 2D are approximately equal to the length Lb and width Wb of the second main surface 1c of trench 2 in the first embodiment. The difference between the semiconductor device 10 according to the fourth embodiment and the first embodiment is the mask pattern during trench formation. For components of the fourth embodiment that overlap with the first embodiment, the reference numerals are used and their explanation is omitted. The following will focus on the differences.

[0068] As shown in Figures 13B and 13C, the length LaM5 of the mask pattern of the trench 2D in the first direction on the first main surface 1a is longer than the length LbM5 of the mask pattern of the trench 2D in the first direction on the second main surface 1c. Furthermore, as shown in Figure 13C, the width WaM5 of the mask pattern of the trench 2D in the second direction on the first main surface 1a is greater than the width WbM5 of the mask pattern of the trench 2D in the second direction on the second main surface 1c. If the sum of the length LaM5 of the mask pattern of the trench 2D on the first main surface 1a and the length LbM5 of the mask pattern of the trench 2D on the second main surface 1c is 2√2 times or more the thickness t of the semiconductor substrate 1, a starting penetration is formed. As a result, a trench 2D with sides perpendicular to the first main surface 1a and the second main surface 1c is formed. The length of the trench 2D is the longer of the mask pattern length LaM5 and the mask pattern length LbM5. In other words, the lengths La5 and Lb5 of the formed trench 2D are approximately equal to the length LaM5 of the mask pattern. Furthermore, the width of the trench 2D is the longer of the widths WaM5 and WbM5 of the mask pattern. In other words, the widths Wa5 and Wb5 of the formed trench 2D are approximately equal to the width WaM5 of the mask pattern. Note that the description of the manufacturing method of the semiconductor device 10 according to the fourth embodiment is omitted because the description of the cross-sectional view is the same as that of the second embodiment.

[0069] In the semiconductor device 10 of the fourth embodiment, the trench 2D is formed by anisotropic etching using wet etching, with the longitudinal direction of the trench 2D aligned parallel or perpendicular to the (111) plane of the semiconductor substrate 1.

[0070] According to the semiconductor device 10 of the fourth embodiment, even if the length and width of the mask pattern of the trench 2D on the first main surface 1a are different from the length and width of the mask pattern of the trench 2D on the second main surface 1c, a trench 2D having a side surface perpendicular to the main surface can be formed. That is, after forming an initial penetration, anisotropic etching by wet etching is performed to form a trench 2D having a (111) plane side surface.

[0071] Furthermore, according to the semiconductor device 10 in the fourth embodiment, a trench 2D can be formed based on the length and width of the mask pattern of the trench 2D on the first main surface 1a. That is, by making the length and width of the mask pattern of the trench 2D on the second main surface 1c smaller than the length and width of the mask pattern of the trench 2D on the first main surface 1a, a trench 2D of the standard length and width can be formed.

[0072] (First method of mask formation) A first mask formation method for forming an etching mask used in the manufacture of the semiconductor device 10 according to the first to fourth embodiments will be described below with reference to the drawings. Below, an example of the steps in the process flow for forming the trench 2 using wet etching will be described.

[0073] First, as shown in Figure 14A, a nitride film 3, which is an example of a mask material, is formed on the first main surface 1a and the second main surface 1c. For example, the semiconductor substrate 1 is a silicon substrate with a diamond structure, and the first main surface 1a and the second main surface 1c are (110) planes. The nitride film 3 is deposited on the first main surface 1a and the second main surface 1c of the semiconductor substrate 1 using, for example, chemical vapor deposition (hereinafter referred to as the CVD method). Note that in the step of forming the nitride film 3, any method that can deposit the nitride film 3 is acceptable and is not limited to the CVD method.

[0074] Next, as shown in Figure 14B, a resist 4 is formed on the nitride film 3 on the first main surface 1a and the second main surface 1c. Specifically, the resist 4 is applied to the entire surface of the nitride film 3 on the first main surface 1a and the second main surface 1c. After applying the resist 4, the resist 4 is patterned by exposure and development using photolithography technology.

[0075] Next, as shown in Figure 14C, the nitride film 3 is etched on the first main surface 1a and the second main surface 1c using the resist 4 as a mask. For example, the nitride film 3 may be etched using dry etching.

[0076] Next, as shown in Figure 14D, the resist 4 is removed from the first main surface 1a and the second main surface 1c. For example, the resist 4 may be removed by oxygen ashing using a plasma ashing method.

[0077] Next, as shown in Figure 14E, the semiconductor substrate 1 is etched from both the first main surface 1a and the second main surface 1c using the nitride film 3 as a mask. Specifically, the semiconductor substrate 1 is anisotropically etched by wet etching using the nitride film 3 as a mask. The etching solution used for wet etching may be an alkaline aqueous solution. For example, KOH or TMAH can be used as the alkaline aqueous solution. The following steps, which involve anisotropically etching the semiconductor substrate 1 to form the trench 2, are omitted because they are part of a general and known process flow.

[0078] In the first mask formation method, a nitride film 3 that is resistant to dissolving in KOH solution is used as an etching mask to etch the semiconductor substrate 1, thereby enabling the formation of trenches 2 according to the mask pattern. According to the first mask formation method, by forming the trenches 2 using low-cost wet etching, the manufacturing process of the semiconductor device 10 can be simplified, shortening the lead time and reducing costs.

[0079] (Second mask formation method) A second mask formation method for forming an etching mask used in the manufacture of the semiconductor device 10 according to the first to fourth embodiments will be described below with reference to the drawings. Below, an example of the steps in the process flow for forming the trench 2 using wet etching will be described.

[0080] The difference between the second mask formation method and the first mask formation method lies in the mask material. In the second mask formation method, instead of using the nitride film 3 as the mask material, a resist 4 that is resistant to insolubility in etching solutions is used as the mask material.

[0081] First, as shown in Figure 15A, a resist 4 is formed on the first main surface 1a and the second main surface 1c. For example, the semiconductor substrate 1 is a silicon substrate with a diamond structure, and the first main surface 1a and the second main surface 1c are (110) planes. The resist 4 is applied to the entire surface of the semiconductor substrate 1 on the first main surface 1a and the second main surface 1c.

[0082] Next, as shown in Figure 15B, the resist 4 formed on the first main surface 1a and the second main surface 1c is patterned. Specifically, the resist 4 is patterned by exposure and development using photolithography technology.

[0083] Next, as shown in Figure 15C, the semiconductor substrate 1 is etched from both the first main surface 1a and the second main surface 1c using the resist 4 as an etching mask. Specifically, the semiconductor substrate 1 is anisotropically etched by wet etching using the resist 4 as a mask. The etching solution used for wet etching may be an alkaline aqueous solution. For example, KOH or TMAH can be used as the alkaline aqueous solution. The following steps, which involve anisotropically etching the semiconductor substrate 1 to form the trench 2, are omitted because they are part of a general and known process flow.

[0084] In the second mask formation method, since a nitride film 3 is not used as the mask material, the photolithography and etching processes required for patterning the nitride film and other materials used in the mask material can be reduced to only the photolithography process for the resist. Therefore, the second mask formation method reduces the number of steps in the manufacturing process of the semiconductor device 10 compared to the first mask formation method. In addition, the second mask formation method can suppress manufacturing costs compared to the first mask formation method.

[0085] (Other embodiments) As described above, embodiments of the present invention have been presented, but the statements and drawings that constitute part of this disclosure should not be understood as limiting the invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0086] For example, although the above description showed only one trench 2, multiple trenches 2 in a stripe pattern may be formed, as shown in Figure 16. The trenches 2 may be selectively formed on the semiconductor substrate 1.

[0087] Furthermore, the semiconductor device 10 according to the first to fourth embodiments may also be configured in which the trench 2 is used as a semiconductor capacitor. In the semiconductor capacitor, a dielectric film and a conductive film are arranged inside the trench 2. A specific example of a semiconductor capacitor will be described with reference to Figures 17A and 17B.

[0088] The semiconductor capacitor shown in Figure 17A includes a dielectric film 6 that is in contact with the interior of the trench 2 and the main surface of the semiconductor substrate 1. The semiconductor capacitor also includes a conductive film 5 laminated on the dielectric film 6. The semiconductor capacitor shown in Figure 17A has a structure in which one layer each of the dielectric film 6 and the conductive film 5 are laminated. The semiconductor capacitor includes a first electrode 11A that is electrically connected to the semiconductor substrate 1 and a second electrode 11B that is electrically connected to the conductive film 5.

[0089] The semiconductor capacitor shown in Figure 17B has a structure in which dielectric films 6 and conductive films 5 are stacked alternately in three layers each. The semiconductor capacitor comprises a first electrode 11A that is electrically connected to the semiconductor substrate 1 and the second layer of conductive film 5, and a second electrode 11B that is electrically connected to the first and third layers of conductive film 5.

[0090] The semiconductor capacitors shown in Figures 17A and 17B realize capacitive device characteristics that accumulate charge between the conductive film 5 sandwiched between the dielectric film 6, or between the semiconductor substrate 1 and the conductive film 5.

[0091] For example, an oxide film can be used for the dielectric film 6. For example, a polysilicon film can be used for the conductive film 5. For example, an aluminum film can be used for the first electrode 11A and the second electrode 11B.

[0092] The semiconductor capacitor formed inside trench 2 can be a deeper trench 2, with its side surface perpendicular to the main plane, compared to a trench with a (111) plane slope on its side surface. As a result, the surface area of ​​the trench 2 increases, and the capacitance of the capacitor increases. Furthermore, as shown in Figure 17B, by creating a multilayer laminated structure of the dielectric film 6 and conductive film 5, the capacitance of the capacitor can be increased compared to the single-layer semiconductor capacitor of the dielectric film 6 and conductive film 5 shown in Figure 17A. [Explanation of symbols]

[0093] 1. Semiconductor substrate 2, 2A~2D Trench 3. Nitride film 4 Resist 5. Conductive film 6 Dielectric film 10 Semiconductor Devices 11A 1st electrode 11B 2nd electrode 1a First main surface 1b Orientation Flat 1c Second main surface 2b1, 2b2 side 2d1 First slope 2d2 Second slope 2e1, 2e2 center 101 chips 101S chip side

Claims

1. The semiconductor substrate has a first main surface and a second main surface opposite to the first main surface, and a groove is formed that penetrates from the first main surface to the second main surface. The longitudinal direction of the groove is defined as the first direction, the short direction of the groove as the second direction perpendicular to the first direction, and the direction perpendicular to the first and second directions and perpendicular to the first and second main surfaces as the third direction. The side surface of the groove, which is a plane including the first direction and the third direction, and a plane including the second direction and the third direction, is a (111) plane. Semiconductor equipment.

2. A semiconductor device formed as a rectangular chip when viewed from the direction of the surface normal to the first main surface, The chip has chip sides that are adjacent to the first main surface and the second main surface in a perpendicular manner and parallel to the (111) surface, The semiconductor device according to claim 1.

3. The sum of the length of the groove in the first direction of the first main surface and the length of the groove in the first direction of the second main surface is 2√2 times or more the thickness of the semiconductor substrate. The semiconductor device according to claim 1.

4. The length of the groove in the first direction of the first main surface is equal to the length of the groove in the first direction of the second main surface, and the length of the grooves in the first direction of the first and second main surfaces is at least √2 times the thickness of the semiconductor substrate. The semiconductor device according to claim 1.

5. The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon substrate.

6. The semiconductor device according to claim 5, wherein the first main surface is a (110) surface.

7. Displaced inside the groove and in contact with the semiconductor substrate, A conductive film is arranged inside the groove and laminated on the dielectric film, A first electrode electrically connected to the semiconductor substrate and a second electrode electrically connected to the conductive film. A semiconductor device according to any one of claims 1 to 6, further comprising the above.

8. The steps include preparing a semiconductor substrate having a first main surface and a second main surface facing the first main surface, The steps include forming a mask material on both the first main surface and the second main surface of the semiconductor substrate, The steps include using the mask material as an etching mask to wet-etch the semiconductor substrate from both the first main surface and the second main surface to form a groove that penetrates from the first main surface to the second main surface, and Equipped with, The mask pattern of the opening in the mask material is formed such that the longitudinal direction of the groove is the first direction, the short direction of the groove is the second direction perpendicular to the first direction, and the third direction is perpendicular to the first and second directions and perpendicular to the first and second main surfaces, and the side surface of the groove, which is a plane including the first and third directions, and a plane including the second and third directions, becomes a (111) plane. A method for manufacturing a semiconductor device.

9. The step further comprises dividing the semiconductor substrate into a plurality of chips, each including the chip side surface of the (111) plane, The semiconductor substrate is divided into a plurality of chips, each of which has a semiconductor device including the groove formed thereon. The method for manufacturing a semiconductor device according to claim 8.

10. The steps include preparing the semiconductor substrate in which the orientation flat is the (111) plane, The steps include determining the cutting line on the first main surface to be parallel to the orientation flat, The steps include cutting the semiconductor substrate along the cutting line and dividing the semiconductor substrate into a plurality of chips, each including the chip side surface of the (111) plane, and Furthermore, The semiconductor substrate is divided into a plurality of chips, each of which has a semiconductor device including the groove formed thereon. The method for manufacturing a semiconductor device according to claim 8.

11. The steps include forming a dielectric film inside the groove, The steps include: laminating a conductive film onto the dielectric film inside the groove; The steps include forming a first electrode that is electrically connected to the semiconductor substrate and a second electrode that is electrically connected to the conductive film. A method for manufacturing a semiconductor device according to claim 8, further comprising the above.

12. The sum of the length of the mask pattern on the first main surface in the first direction and the length of the mask pattern on the second main surface in the first direction is 2√2 times or more the thickness of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 8.

13. The length of the mask pattern of the first main surface in the first direction is equal to the length of the mask pattern of the second main surface in the first direction. The length of the mask pattern of the first main surface and the second main surface in the first direction is √2 times or more the thickness of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 8.

14. The method for manufacturing a semiconductor device according to claim 8, wherein the length of the mask pattern on the first main surface in the first direction is longer than the length of the mask pattern on the second main surface in the first direction.

15. The method for manufacturing a semiconductor device according to claim 8, wherein the width of the mask pattern of the first main surface in the second direction is greater than the width of the mask pattern of the second main surface in the second direction.

16. The length of the mask pattern of the first main surface in the first direction is longer than the length of the mask pattern of the second main surface in the first direction. The width of the mask pattern of the first main surface in the second direction is greater than the width of the mask pattern of the second main surface in the second direction. The method for manufacturing a semiconductor device according to claim 8.

17. The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor substrate is a silicon substrate.

18. The method for manufacturing a semiconductor device according to claim 17, wherein the first main surface is a (110) surface.

19. The method for manufacturing a semiconductor device according to claim 18, wherein the etching solution used in the wet etching is an alkaline aqueous solution.

20. The method for manufacturing a semiconductor device according to claim 8, wherein the mask material includes a nitride film.

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