Trench gate type IGBT and its drive method

Abstract

To reduce a loss in accordance with a use condition of high frequency use and low frequency use.SOLUTION: A trench gate type IGBT includes: a gate trench 120G which extends from a front face of a semiconductor substrate toward a rear face side and causes a current to flow in a channel region formed around it by applying a voltage; a switch trench 120SW which extends from the front face of the semiconductor substrate toward the rear face side and in which a channel region is not formed around it; and a setting terminal for controlling a voltage of the switch trench 120SW from the outside. It can be switched in accordance with a voltage applied to the setting terminal between a first state where a voltage drop at an ON time is relatively small and an energy loss at a turning-off time is relatively large and a second state where the voltage drop at the ON time is relatively large and the energy loss at the turning-off time is relatively small.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Conventionally, an IGBT (Insulated Gate Bipolar Transistor) has been widely used as a switching element for a circuit that drives a high-power motor.

[0002] For example, Patent Document 1 shows that in a trench gate type IGBT, a carrier store (CS: Carrier Store) layer for accumulating holes is provided below the channel of the IGBT.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Here, when a carrier store layer is provided, the voltage drop (collector-emitter voltage VCE) when the IGBT is on can be reduced. That is, the voltage drop due to the on-resistance of the IGBT can be reduced, and the energy loss during on can be made small. However, when the IGBT turns off (switching from on to off), due to the influence of the remaining holes, the time required for turning off becomes long, and the energy consumption (switching loss) becomes large. Thus, the conduction loss and switching loss of the IGBT are in a trade-off relationship, which is determined by the structure and the carrier store layer concentration when manufacturing the IGBT, and it has been impossible for the user side to control this trade-off.

Means for Solving the Problems

[0005] The trench gate type IGBT according to the present disclosure is a semiconductor substrate, A gate trench extends from the front surface to the back surface of the semiconductor substrate, and when a voltage is applied, it allows current to flow into a channel region formed around it. A switch trench extending from the front surface to the back surface of the semiconductor substrate, with no channel region formed around it, A setting terminal for externally controlling the voltage of the switch trench, Includes, The voltage applied to the setting terminal can be used to switch between a first state, where the voltage drop during on-state is relatively small and the energy loss during turn-off is relatively large, and a second state, where the voltage drop during on-state is relatively large and the energy loss during turn-off is relatively small. The first state is adopted when the on / off frequency is low, and the second state is adopted when the on / off frequency is high. ru. [Effects of the Invention]

[0006] According to the trench gate type IGBT of this disclosure, by setting the voltage of the switch trench, it is possible to select whether to reduce switching losses or reduce the voltage drop when on, depending on the operating conditions (whether the on / off is at a high frequency or a low frequency). Therefore, a trench gate type IGBT with reduced losses can be obtained depending on the operating conditions. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic cross-sectional view showing the configuration of a trench gate type IGBT according to the embodiment. [Figure 2] This shows the change in hole density in the depth direction around switch trench 120SW immediately after the IGBT is turned off, when the switch trench 120SW is set to 0V or -15V. [Figure 3] This figure shows the changes in VCE and ICE when the switch trench 120SW is turned off, when SW is set to 0V or -15V. [Figure 4] This diagram shows the switching loss and conduction loss when the switching frequency is 30kHz, 10kHz, and 3kHz. [Figure 5] It is a graph showing the relationship between Eoff and VCE(saturation) according to the voltage of SW. [Figure 6] It is a plan view showing an example of the metal layer (single layer) of an IGBT. In this example, the IGBT has a square planar shape. [Figure 7A] It is an enlarged schematic view of part A in FIG. 6. [Figure 7B] It is a cross-sectional view taken along the line A-A' of FIG. 7A. [Figure 7C] It is a cross-sectional view taken along the line B-B' of FIG. 7A. [Figure 8] It is a plan view showing another example of the metal layer (single layer) of an IGBT. [Figure 9] It is an enlarged view of part B in FIG. 8. [Figure 10] It is a plan view showing an example of the metal layer (two layers) of an IGBT. [Figure 11A] It is an enlarged view of part B in FIG. 10. <� [Figure 11B] It is a cross-section taken along the line A-A' in FIG.IIA. [Figure 12] It is a diagram showing the manufacturing process of an IGBT according to an embodiment.

Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present disclosure will be described below with reference to the drawings. Note that the following embodiments do not limit the present disclosure, and configurations formed by selectively combining a plurality of examples are also included in the present disclosure.

[0009] FIG. 1 is a cross-sectional view schematically showing the configuration of a trench gate type IGBT according to an embodiment.

[0010] On the surface of the semiconductor substrate 100, an interlayer insulating film l02 is formed. On this interlayer insulating film 102, a metal wiring layer is provided to make necessary electrical connections. In FIG. 1, an emitter pad 104 is shown. [[ID=I52]]

[0011] For the semiconductor substrate 100, a silicon (Si) wafer such as an FZ (Floating Zone) wafer is used, for example, but a wafer of silicon carbide (SiC) or the like may also be used. For the interlayer insulating film 102, an insulating material such as silicon oxide is used. For the metal wiring, a metal material such as aluminum is usually used.

[0012] On the back surface of the semiconductor substrate 100, a collector pad 106 is formed. For the collector pad 106, a metal material such as aluminum is usually used.

[0013] On the back surface portion of the semiconductor substrate above the collector pad 106, a P+ P collector layer 110 with a high impurity concentration is formed, and on top of that, an N+ field stop layer 112 with a higher impurity concentration than the N drift layer 114 described later is formed. These N-type and P-type regions in the semiconductor substrate 100 are formed by doping impurities of their respective types. The P collector layer 110 functions as a collector region, and the field stop layer 112 prevents the expansion of the depletion layer during the off state.

[0014] Above the field stop layer 112, an N drift layer 114 composed of the N-type semiconductor substrate is located. This N drift layer 114 is the body of the semiconductor substrate 100 and has a function as the base of the PNP bipolar transistor of the IGBT.

[0015] Above the N drift layer 114, an N+ carrier storage layer 116 with a higher impurity concentration than the N drift layer 114 is provided. This carrier storage layer 116 has a function of reducing the on-resistance by accumulating holes and reducing VCE, which is the voltage drop during the on state.

[0016] Above the carrier storage layer 116, a P- P body layer 118 with a relatively low impurity concentration is provided. This P body layer 118 functions as the emitter of the PNP bipolar transistor.

[0017] Furthermore, multiple trenches 120 are formed downward from the surface of the semiconductor substrate 100. The trenches 120 extend downward from the surface of the semiconductor substrate 100 (below the interlayer insulating film 102), penetrating the P-body layer 118 and the carrier store layer 116, and reaching the N-drift layer 114.

[0018] The trench 120 is insulated from the surroundings by an insulating film, such as silicon oxide, on its peripheral walls, and filled with a conductive material, such as polysilicon. In this example, it includes a gate trench 120G, whose interior is connected to a gate electrode (not shown) and forms a gate region, and a switch trench 120SW, which is connected to a switch 140. Figure 1 schematically shows the wiring connecting the switch trench 120SW and the switch 140. In this example, the switch SW is a changeover switch and is connected to either 0V or -15V. For example, a terminal for the switch 140 can be provided on the surface of the semiconductor substrate 100, and 0V or -15V can be supplied to it from the outside by switching.

[0019] Furthermore, an emitter region 122 with a high impurity concentration of N+ is formed on the surface side of the P body layer 118, adjacent to the gate trench 120G. This emitter region 122 is electrically connected to the emitter pad 104. For example, in a portion not shown, the interlayer insulating film 102 is removed, and the emitter pad 104 and the emitter region 122 are directly connected.

[0020] As a result, the region between the emitter region 122 and the carrier store layer 116 functions as a channel of the FET, and when the FET is turned on, electrons, which are carriers, flow from the emitter region through the carrier store layer 116 into the N-drift layer 114.

[0021] Furthermore, the contact 132 from the emitter pad 104 is positioned to extend into the P-body layer 118 of each mesa section formed between the multiple trenches 120. This contact 132 is connected to a (P+) contact region 134 with a high impurity concentration formed inside (in the middle portion) of the P-body layer 118 of the mesa section. Thus, the emitter pad 104 is electrically connected to the contact 132 and the contact region 134, allowing holes accumulated in the N-drift layer 114 during turn-off to be drawn out to the emitter electrode via the P-body layer 118.

[0022] In this embodiment, not only is a P-body layer 118 that functions as a channel with an emitter region 122 formed on its surface, but a contact region 134 is also provided on the P-body layer 118 that does not function as a channel and does not have an emitter region 122 formed thereon, and it is connected to the emitter pad 104 by a contact 132.

[0023] Furthermore, the inside of the gate trench 120G is connected to a separately provided gate electrode, and the insulating film on the peripheral wall of the gate trench 120G functions as a gate insulating film.

[0024] "IGBT operation" With a voltage applied between the collector pad 106 and the emitter pad 104 (for example, 400V on the collector pad 106 and 0V on the emitter pad 104), a positive voltage (for example, 15V) is applied to the gate trench 120G. Note that the 400V applied voltage to the collector pad 106 mentioned above is just an example, and depending on the application, a lower voltage such as 10V may be used.

[0025] This creates an inversion layer in the channel around the gate trench 120G, turning on the FET and causing an electron current to flow from the emitter region 122 towards the N-drift layer 114. Specifically, the P region of the P body layer 118 makes the gate trench 120G positive, causing negative charges to accumulate on the sidewall of the gate trench 120G, and this channel region inverts from P-type to N-type, allowing current to flow. This turns on the PNP bipolar transistor, supplying holes from the collector side and electrons from the emitter side to the N-drift layer 114, turning on the IGBT. In other words, the movement of both holes and electrons causes a current to flow from the collector pad 106 towards the emitter pad 104.

[0026] Furthermore, the field stop layer 112 can suppress the spread of the depletion layer, thus reducing the overall thickness.

[0027] In this embodiment of the IGBT, not only is a gate trench 120G provided, but an emitter trench 120E is also provided, and in the P body layer 118, a region without an emitter region 122 is provided on its surface.

[0028] In other words, the P-body layer 118 region adjacent to the gate trench 120G, where the emitter region 122 is located on the surface side, functions as a channel. This region is called the first mesa region. Therefore, this gate area (IGBT GATE in Figure 1) functions as the gate of the IGBT.

[0029] On the other hand, the P-body layer 118, which lacks an emitter region 122 on its surface, does not function as a channel even when adjacent to the gate trench 120G, and the region adjacent to the switch trench 120SW also does not function as a channel. This region is called the second mesa region. Therefore, this non-gate area (IGBT non-GATE in Figure 1) does not function as a gate for the IGBT. The number of gate trenches 120G in the gate area, and the number of gate trenches 120G and emitter trenches 120E in the non-gate area can be set to any number.

[0030] Furthermore, in this embodiment of the IGBT, the contact 132 also connects to the P-body layer 118, which does not function as a channel. When the IGBT is turned off, holes remaining in the N-drift layer 114 can be drawn out to the emitter pad 104 at an early stage. The contact 132 is also placed in the P-body layer 118, which functions as a channel, and holes can be drawn out there as well when the IGBT is turned off. In addition, although a gate trench 120G is placed in the non-gate area, holes are similarly drawn out from the P-body layer 118 around this gate trench 120G.

[0031] In particular, in this embodiment, a gate trench 120G and a switch trench 120SW are arranged in the non-gate region. By controlling the voltage of the switch trench 120SW, the state of holes in the surrounding region can be controlled. For example, by setting the switch trench 120SW to -15V, hole extraction can be performed at high speed when the IGBT switches from on to off. On the other hand, by setting the switch trench 120SW to 0V, the voltage drop (collector-emitter voltage VCE (saturation)) when the IGBT is on can be reduced.

[0032] Figure 2 shows the hole density of the IGBT at turn-on for the switch trench 120SW when set to 0V (first state) or -15V (second state). The solid line shows the case of -15V, and the dashed line shows the case of 0V. As shown, setting to -15V reduces hole accumulation at turn-on, so VCE(sat) increases, but Eoff and td(OFF) become smaller because hole discharge takes less time. Therefore, the -15V setting is suitable for high-frequency operation. On the other hand, setting to 0V results in more hole accumulation and a decrease in VCE(sat), but Eoff and td(OFF) become larger because hole discharge takes longer. Therefore, the 0V setting is suitable for low-frequency operation.

[0033] Figure 3 shows the changes in VCE (collector-emitter voltage) and ICE (collector current) during turn-off when SW = 0V or -15V for the switch trench 120SW.

[0034] Thus, when SW=0, the delay time Td(off)=5.9e -6 For seconds (s), if SW = -15V, then Td(off) = 1.0e -6 The delay is reduced to seconds (s). Also, the slope dv / dt of VCE becomes larger when SW=-15V. Therefore, the energy loss during turn-off (also called switching loss) is 25.4mJ when SW=-15V and 51.3mJ when SW=0, so setting SW=-15 allows for rapid hole extraction and reduces switching loss.

[0035] On the other hand, when SW=0V, VCE (saturation) was 0.78V at a conduction current of 30A and 1.09V at a conduction current of 300A, while when SW=-15V, VCE (saturation) was 1.12V at a conduction current of 30A and 1.57V at a conduction current of 300A.

[0036] A high VCE (saturation) voltage indicates that there is a large energy loss (conduction loss) when the IGBT is energized.

[0037] In other words, when SW=0V, hole accumulation is high and VCE (saturation) is low, but because it takes time to discharge the accumulated holes, Eoff and Td(off) become large. On the other hand, when SW=-15V, hole accumulation decreases. Therefore, VCE (saturation) becomes large, but because there are fewer holes accumulated at the time of turn-off, Eoff and Td(off) become small.

[0038] Thus, IGBTs have a trade-off between VCE (saturation), which corresponds to the conduction loss, and Eoff, which is the switching loss during turn-off. This trade-off can be adjusted by the carrier concentration in the collector region and the carrier concentration in the carrier store layer, but this is determined by the IGBT design. Therefore, it cannot be adjusted by the user of the IGBT during use.

[0039] On the other hand, in this embodiment of the IGBT, by changing the voltage of the switch trench 120SW, it is possible to address the trade-off between reducing conduction loss or reducing switching loss.

[0040] Figure 4 shows the switching loss and conduction loss for switching frequencies (on / off frequencies) of 30kHz, 10kHz, and 3kHz. It can be seen that at 30kHz, SW=-15V results in lower losses, and at 3kHz, SW=0V results in lower losses.

[0041] In the IGBT according to this embodiment, the user can set the voltage of the switch trench 120SW. That is, for low frequencies, this SW is set to 0V, and for high frequencies... S By changing the wattage (W) to -15V, the characteristics of the IGBT can be altered, thereby reducing losses.

[0042] Figure 5 is a graph showing the relationship between switching loss Eoff and collector-emitter voltage VCE (saturation) depending on the SW voltage. As shown, the switching loss Eoff and collector-emitter voltage VCE (saturation) are determined according to the SW voltage. Therefore, with the IGBT of this embodiment, it is possible to always set appropriate Eoff and VCE (saturation) by setting the SW voltage according to the switching frequency.

[0043] "Plan and Sectional Configuration" Figure 6 is a plan view showing an example of a metal layer (single layer) of an IGBT. In this example, the IGBT has a square planar shape.

[0044] The square surface is provided with three emitter pads 104, divided into three sections in the vertical direction as shown in the figure. The three emitter pads 104 are spaced apart at their periphery, and a predetermined gap is provided between the three emitter pads 104.

[0045] In the diagram, the emitter pad 104 on the left side has a recess in the upper left corner, where a switch pad 142 is located. A rectangular switch wiring 142a is connected to the switch pad 142 and runs along the outer perimeter of the IGBT surface. The switch wiring 142a is positioned inward from the outer perimeter by a scribe pitch. The switch pad 142 functions as a setting terminal for setting the voltage of the switch trench 120SW.

[0046] Furthermore, the left center of the left emitter pad 104 is recessed, and a gate pad 108 is positioned there. A gate wire 108a is connected to this gate pad 108, and this gate wire 108a extends to both the left and right sides, the bottom, and the vertical gap between the three emitter pads 104.

[0047] Figure 7A is an enlarged schematic diagram of section A in Figure 6, showing the structure within the semiconductor substrate 100. Figure 7B is a cross-sectional view taken along line A-A' in Figure 7A, and Figure 7C is a cross-sectional view taken along line B-B' in Figure 7A.

[0048] Thus, the gate trench 120G and switch trench 120SW are located below the emitter pad 104, gate wiring 108a, and switch wiring 142a, which extend horizontally and vertically, respectively.

[0049] Then, the gate trench 120G and the gate wiring 108a are connected by a contact 108b that extends downward, and the switch trench 120SW and the switch wiring 142a are connected by a contact 142b that extends downward.

[0050] Figure 8 is a plan view showing another example of the metal layer (single layer) of an IGBT. Figure 9 is an enlarged view of section B in Figure 8.

[0051] In this example, the switch wiring 142a extends into the gap between the divided emitter pads 104. Therefore, the number of contacts 142b between the switch wiring 142a and the switch trench 120SW can be increased, and the electric field by the switch trench 120SW can be established earlier.

[0052] Note that the A-A' and B-B' cross-sectional views in Figure 9 are the same as those in Figures 7B and 7C, respectively.

[0053] Figure 10 is a plan view showing an example of the metal layer (2 layers) of an IGBT. Figure 11A is a plan view. 10 Figure 11B is an enlarged view of section B, and Figure 11B is the A-A' section in Figure 11A.

[0054] As shown in Figure 10, the surface of the semiconductor substrate 100 has an emitter pad 104, a gate pad 108, a switch pad 142, and a switch wiring 142a, but no gate wiring 108a. As shown in Figure 11B, the gate wiring 108a is located within the interlayer insulating film 102 below the switch wiring 142a. In this way, by creating a two-layer wiring structure, it becomes possible to reduce the area required to arrange multiple wirings.

[0055] <Manufacturing process> Figure 12 shows the manufacturing process of an IGBT according to the embodiment. First, a semiconductor substrate 100 is prepared and put into the manufacturing process (S11). As the semiconductor substrate 100, for example, an FZ (Floating Zone) wafer of type N is used.

[0056] First, the surface is oxidized to form an interlayer insulating film 102 (S12). Since multiple elements (in this case, IGBTs) are to be created on a single wafer, it is advisable to perform element isolation processing at this stage.

[0057] Next, a P+ P-body layer 118 is formed by doping with P-type impurities from the surface side (S13). A trench is formed by etching from the surface side (S14), and an oxide film is formed on the wall surface of the formed trench (S15). If it is a gate trench, this oxide film becomes the gate insulating film. Then, polysilicon is deposited inside the trench (S16). This polysilicon is conductive.

[0058] Next, a carrier store layer (CS layer) 116 is formed by implanting N-type impurities (S17). Then, an emitter region is formed by implanting N-type impurities from the surface side (S18).

[0059] Contact holes are formed by etching from the surface side, and contact regions 134 are formed by implanting P-type impurities. Next, an interlayer insulating film 102 is formed, and then the necessary contact holes are formed. Then, the emitter pad 104, gate pad 108, switch pad 142, and contacts extending within the contact holes are formed by depositing metal. ru ( S20). Then, the surface is covered with a passivation film (S21).

[0060] Next, the back side is polished (S22), and the field stop layer 112 and the P collector layer 110 are formed sequentially from the back side (S22, S24). Then, the collector pad 106 is formed by depositing metal (S24).

[0061] In this way, the IGBT is formed, and then various inspections are performed on it (S25), completing the manufacturing process. [Explanation of Symbols]

[0062] 100 Semiconductor substrate, 102 Interlayer insulating film, 104 Emitter pad, 106 Collector pad, 108 Gate pad, 108a Gate wiring, 110 P collector layer, 112 Field stop layer, 114 N drift layer, 116 Carrier store layer, 118 P body layer, 120 Trench, 120E Emitter trench, 120G Gate trench, 120SW: Switch trench, 122 Emitter region, 132 Contact, 134 Contact region, 140 Switch, 142 Switch pad, 142a Switch wiring, 142b Contact.

Claims

1. Semiconductor substrate and A gate trench extends from the front surface to the back surface of the semiconductor substrate, and when a voltage is applied, it allows current to flow into a channel region formed around it. A switch trench extending from the front surface to the back surface of the semiconductor substrate, with no channel region formed around it, A setting terminal for externally controlling the voltage of the switch trench, Includes, By applying a voltage to the setting terminal, it is possible to switch between a first state in which the voltage drop during on-time is relatively small and the energy loss during turn-off is relatively large, and a second state in which the voltage drop during on-time is relatively large and the energy loss during turn-off is relatively small. The first state is adopted when the on / off frequency is low, and the second state is adopted when the on / off frequency is high. Trench gate type IGBT.

2. A trench gate type IGBT according to claim 1, The voltage applied to the setting terminal can be continuously changed. Trench gate type IGBT.

3. Semiconductor substrate and An emitter electrode formed on the surface of the semiconductor substrate, A collector pad formed on the back surface of the semiconductor substrate, A P-type P collector layer formed on the back side of the semiconductor substrate above the collector pad, An N-type N-drift layer located on the P-collector layer in the semiconductor substrate, An N-type carrier store layer is formed on the aforementioned N-drift layer and has a higher impurity concentration than the aforementioned N-drift layer, A P-type P-body layer formed on the surface side of the carrier store layer of the semiconductor substrate, A plurality of trenches are discretely formed from the surface side of the semiconductor substrate with a mesa section interposed therebetween, extending toward the back side to the N-drift layer, and each of the plurality of gate trenches has a gate region formed therein with an insulating film interposed therebetween, A trench discretely formed from the surface side of the semiconductor substrate with a mesa section in between, extending toward the N-drift layer toward the back side, having an insulating film formed inside, connected to a setting terminal from which a voltage can be set externally, and comprising a switch trench, The mesa section adjacent to the gate trench, comprising an emitter region formed on the surface side of the P-body layer and connected to the emitter electrode, The P-body layer of the mesa section, comprising a first mesa region that is connected to the emitter electrode by a contact and functions as a channel by having the emitter region formed on its surface side, The P-body layer of the mesa section, which is connected to the emitter electrode by a contact and does not function as a channel because the emitter region is not formed on its surface, Includes, The second mesa region is located around the switch trench. The switch trench can be switched between a first state, in which the voltage drop when on is relatively small and the energy loss when turned off is relatively large, and a second state, in which the voltage drop when on is relatively large and the energy loss when turned off is relatively small, depending on the voltage applied to the setting terminal. The first state is adopted when the on / off frequency is low, and the second state is adopted when the on / off frequency is high. Trench gate type IGBT.

4. A trench gate type IGBT according to claim 3, The voltage applied to the setting terminal can be continuously changed. Trench gate type IGBT.

5. Semiconductor substrate and A gate trench extends from the front surface to the back surface of the semiconductor substrate, and when a voltage is applied, it allows current to flow into a channel region formed around it. A switch trench extending from the front surface to the back surface of the semiconductor substrate, with no channel region formed around it, A setting terminal for externally controlling the voltage of the switch trench, A method for driving a trench gate type IGBT, including, When the on / off frequency is low, the first state is defined as one in which the voltage drop during on-time is relatively small and the energy loss during turn-off is relatively large. The second state is defined as one where the on / off frequency is high, or where the voltage drop during on- is relatively large and the energy loss during turn-off is relatively small. A method for driving trench gate type IGBTs.

6. A method for driving a trench gate type IGBT according to claim 5, The voltage applied to the setting terminal can be continuously changed. A method for driving trench gate type IGBTs.

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