Enable branch recording when the branch recording configuration value meets the specified conditions.

Abstract

The apparatus includes a reset circuit that performs a cold reset and performs a warm reset by resetting a subset of states reset in a cold reset, and a branch record circuit that performs branch record to store information about processed branch instructions in a branch record storage circuit. The branch record circuit determines whether a warm branch record configuration value and a cold branch record configuration value held in at least one register satisfy a predetermined condition, and invalidates the branch record when the warm branch record configuration value and the cold branch record configuration value do not satisfy the predetermined condition. The branch record storage circuit is configured to make information about processed branch instructions available for diagnostic analysis. The cold reset includes resetting both the warm branch record configuration value and the cold branch record configuration value, and the warm reset includes resetting the warm branch record configuration value and leaving the cold branch record configuration value unchanged.

Description

Technical Field

[0004] , , , , , , , ,

[0003] ,

[0001] This technique relates to the field of data processing.

Background Art

[0002] A data processing device may be configured to perform branch recording, which is a technique that captures information regarding processed branch instructions and uses the captured information to enable subsequent software to execute processes (e.g., diagnostic, debug, and / or profiling processes).

Summary of the Invention

[0003] Viewed from an example of this technique, a processing circuit that processes instructions, a reset circuit that performs a cold reset by resetting the processing circuit in response to a cold reset trigger event and performs a warm reset by resetting a subset of the states that are reset in response to the cold reset trigger event in response to a warm reset trigger event, and a branch recording circuit that performs branch recording and stores information regarding processed branch instructions in a branch recording storage circuit, The branch recording circuit, determines whether warm branch recording configuration values and cold branch recording configuration values held in at least one register satisfy a predetermined condition, is configured to enable branch recording when the warm branch recording configuration values and the cold branch recording configuration values satisfy the predetermined condition, [[ID=3..​​​​​Looking at another example of this technique, Processing instructions on a processing circuit, Performing a cold reset by resetting the processing circuit in response to a cold reset trigger event, Performing a warm reset in response to a warm reset trigger event involves resetting a subset of the states that are reset in response to a cold reset trigger event, Determine whether the warm branch record configuration value and the cold branch record configuration value held in at least one register satisfy predetermined conditions, A method for activating a branch record when a warm branch record configuration value and a cold branch record configuration value satisfy predetermined conditions, wherein the branch record includes storing information about the processed branch instruction in a branch record storage circuit. The method includes making information about processed branch instructions available for diagnostic analysis. A method is provided for a cold reset which includes resetting both the warm branch record configuration value and the cold branch record configuration value, and a warm reset which includes resetting the warm branch record configuration value and leaving the cold branch record configuration value unchanged. [Brief explanation of the drawing]

[0005] Further aspects, features, and advantages of this technique will become apparent from the following example description, which should be read in conjunction with the attached drawings. [Figure 1] A schematic diagram of a data processing system in which this technique can be implemented is provided. [Figure 2] The warm reset domain, non-warm reset domain, and cold reset domain are outlined below. [Figure 3] This table shows an example of how worm branch recording configuration values ​​and cold branch recording configuration values ​​(BREW, BREC) can be configured to control the operation of the branch recording circuit. [Figure 4]This figure shows what happens to the warm branch record configuration values ​​and cold branch record configuration values ​​(BREW, BREC) after software configuration and after a warm reset, using the example shown in Figure 3. [Figure 5] This table shows another example of how worm branch recording configuration values ​​and cold branch recording configuration values ​​(BREW, BREC) can be configured to control the operation of a branch recording circuit. [Figure 6] This flowchart illustrates an example of how branch recording circuits perform tasks under the control of warm branch recording configuration values ​​and cold branch recording configuration values ​​(BREW, BREC). [Figure 7] This is a flowchart illustrating an example of the reset process. [Figure 8] This outlines the various processes that can be performed in a data processing system. [Figure 9] This flowchart illustrates an example of determining whether a process at a privileged execution level lower than a given execution level (EL3 in the example in Figure 9) is allowed to access information stored in the branch log buffer. [Modes for carrying out the invention]

[0006] Before considering exemplary implementation configurations with reference to the attached drawings, the following description of exemplary embodiments and their related advantages is provided.

[0007] According to one exemplary configuration, a device is provided that includes a processing circuit for processing instructions. For example, the processing circuit may be a central processing unit (CPU), a processing pipeline within a CPU, or any other circuit in the device that can process instructions.

[0008] The device also includes a reset circuit that performs a cold reset in response to a cold reset trigger event by resetting the processing circuit, and a warm reset in response to a warm reset trigger event by resetting a subset of the states that are reset in response to the cold reset trigger event. For example, a reset may involve setting the value of any state to be reset to a default (reset) value (for example, this could be 0 or 1 - there may be some items of the state that are reset to 0 and other items of the state that are reset to 1). A warm reset can be thought of as a partial reset that involves resetting some, but not all, of the states that are reset in a cold reset (for example, an appropriate subset). In this context, “state” can be understood to mean information stored (e.g., stored) by the components of the processing circuit, which may include data stored in storage circuits such as registers, caches, or memory, but may also include any information recorded by flip-flops within the components of the processing circuit.

[0009] The device also provides a branch recording circuit that performs branch recording to store information about processed branch instructions in a branch recording storage circuit. The branch recording circuit is configured to determine whether a worm branch recording configuration value and a cold branch recording configuration value held in at least one register satisfy predetermined conditions, and to activate branch recording when the worm branch recording configuration value and the cold branch recording configuration value satisfy the predetermined conditions.

[0010] For example, when branch recording is enabled, the branch recording circuit may detect that a branch instruction (e.g., a program flow change instruction, when executed, causes a processing circuit to branch to another instruction other than the instruction that follows it in program order) is being processed when it is fetched by a fetch circuit in the processing circuit, decoded by a decoding circuit in the processing circuit, issued by an issuer circuit in the processing circuit, or executed by an execution circuit in the processing circuit. However, these are all just examples, and it will be understood that the branch recording circuit may be configured to detect that a branch instruction is being processed at any stage / part of the processing circuit. When a particular branch instruction is detected and branch recording is enabled, whether or not information about the branch is stored in the branch recording circuit may depend on factors other than the warm branch recording configuration values ​​and cold branch recording configuration values ​​(e.g., whether or not a branch is taken, or whether or not the filter criteria, as further described below, are met). Therefore, when branch recording is enabled, this generally means that branch recording is enabled and allows information about a particular processed branch to be recorded, but this does not mean that all branches processed while branch recording is enabled must have information recorded in the branch recording memory circuit.

[0011] The worm branch record configuration values ​​and cold branch record configuration values ​​may be, for example, a pair of values ​​held in one or more registers, and may be any value (e.g., 1, 0, or any other value), but it will be understood that the worm branch record configuration values ​​and cold branch record configuration values ​​may contain more than two values. The predetermined conditions may depend on the values ​​to which the worm branch record configuration values ​​and cold branch record configuration values ​​are set, and in some examples, the predetermined conditions include conditions that should be satisfied by both the worm branch record configuration values ​​and cold branch record configuration values ​​(e.g., conditions that should be satisfied together by a pair of branch record configuration values). In at least some states of the processing circuit, the satisfaction of the predetermined conditions indicates that the branch recording circuit should enable branch recording. When the predetermined conditions are not satisfied, branch recording is disabled.

[0012] When branch recording is enabled, information about processed branch instructions is stored in a branch recording memory circuit, which may be, for example, a dedicated storage structure or a data structure in memory (e.g., a circular buffer). The branch recording memory circuit is configured to make information about processed branch instructions available for diagnostic analysis. Information stored in the branch recording buffer may be useful in diagnostic processes such as debugging or code profiling, and the branch recording buffer may be configured to make this information available to diagnostic processes performing such analysis. Information about branches may be made available for diagnostic analysis by enabling diagnostic software or debugging tools to read the information from the branch recording memory circuit, or by outputting the recorded branch information to an external debugger or computer via a trace port for performing diagnostic analysis.

[0013] In the apparatus of this technique, a cold reset includes resetting both the warm branch recording configuration value and the cold branch recording configuration value, while a warm reset includes resetting the warm branch recording configuration value and leaving the cold branch recording configuration value unchanged. For example, a state reset in response to a cold reset trigger may include both the cold branch recording configuration value and the warm branch recording configuration value, and a state reset in response to a warm reset trigger (e.g., a subset of states reset in response to a cold reset trigger) may include the warm branch recording configuration value but not the cold branch recording configuration value. Thus, the value of the warm branch recording configuration value may be reset to its default / reset value during a warm reset, while the cold branch recording configuration value retains the value it had before the warm reset trigger was received / detected (which may be its default / reset value, but may be a different value), and the cold branch recording configuration value is not affected by a warm reset.

[0014] The inventors of this technique recognized that being able to examine information about branches processed around a warm reset could be useful for diagnostic processes. For example, this could enable post-event diagnostics (e.g., examining information captured regarding branches executed before the reset to identify the cause of the reset), or even diagnostics against any reset firmware that may be executed by the processing circuit immediately after a warm reset. However, reset signals are typically asynchronous, meaning they can occur at any time, making it difficult to predict when a reset will occur. This can make it difficult to control whether or not branch recording is performed around a warm reset.

[0015] This technique addresses these problems by providing two control values, namely a warm branch record configuration value and a cold branch record configuration value, which can be used (by determining whether a pair of branch record configuration values meets a predetermined condition) to control whether branch recording is enabled or disabled before and after a reset. In particular, by providing two control values, a control value (warm branch record configuration value) that is reset in response to both a warm reset and a cold reset, and a control value (cold branch record configuration value) that is reset in response to a cold reset without responding to a warm reset, the warm branch record configuration value and the cold branch record configuration value can be set (for example, by considering a predetermined condition and the fact that the warm branch record configuration value is reset by a warm reset) to control when branch recording starts and stops near a warm reset. Furthermore, this technique can be implemented without significantly increasing the circuit area and power consumption. Therefore, this device enables more useful diagnostic information to be captured around a warm reset without significantly increasing the circuit cost with respect to the increase in circuit area.

[0016] <000009l>In some examples, the branch recording circuit is configured to determine whether the warm branch record configuration value and the cold branch record configuration value held in at least one register meet a predetermined condition based on a comparison between the warm branch record configuration value and the cold branch record configuration value. <000^093> This can be a particularly advantageous way of implementing the branch recording circuit of this technique because performing a simple comparison of a pair of values requires less circuit area (compared to a more complex set of logic for decoding any state of the bits in each of the branch record configuration values), and thus incurs less cost.

[0018] In some examples, a given condition includes one of the following: the worm branch record configuration value and the cold branch record configuration value are equal, and the worm branch record configuration value and the cold branch record configuration value are different. For example, a given condition may be considered satisfied when both the worm branch record configuration value and the cold branch record configuration value have the same value (e.g., both may have a value of 1, or both may have a value of 0, but in other examples it will be understood that the branch record configuration value may have a value other than 0 or 1). Alternatively, a given condition may be considered satisfied when the worm branch record configuration value has a different value from the cold branch record configuration value (e.g., one value may be 1 and the other 0, but (again) in other examples it will be understood that the branch record configuration value may have a value other than 0 or 1).

[0019] Thus, this technique can be implemented using a simple comparator circuit, and therefore requires only a slight increase in circuit area.

[0020] Another advantage of evaluating a given condition based on whether the warm branch record configuration value and the cold branch record configuration value are equal or unequal is that this means there can be multiple different combinations of settings for the warm branch record configuration value and the cold branch record configuration value, each of which may or may not satisfy the given condition. For example, the equal condition may be satisfied when both configuration values ​​are either 0 or both are 1, and the unequal condition may be satisfied when both configuration values ​​are either 0 and 1, or 1 and 0. Providing multiple settings corresponding to "enable" or multiple settings corresponding to "disable" can be useful because it means that a user can configure the configuration value with different settings that provide different enable / disable statuses for branch records after a warm reset, even if the enable / disable status before a warm reset is the same for each of those settings (or conversely, a user can configure the configuration value with different settings for the enable / disable status before a warm reset, even if the desired behavior for the enable / disable status of branch records after a warm reset is the same). In contrast, an approach that provides only a single configuration setting for enabled branch records and a single configuration setting for disabled branch records (e.g., using a single enable / disable bit) offers less flexibility when configuring different options before and after a warm reset.

[0021] In some examples, at least one register can be configured by software to set a worm branch record configuration value and a cold branch record configuration value to one of several states, the worm branch record configuration value having one of a worm configuration value and a worm reset value, and both worm reset and cold reset include resetting the worm branch record configuration value to the worm reset value. For example, a programmer may configure the worm branch record configuration value and the cold branch record configuration value by including one or more instructions in the software to update the values ​​stored in at least one register. The warm reset value is the value to which the warm branch record configuration value returns after a warm or cold reset (for example, if a warm reset and a cold reset involve resetting the warm branch record configuration value to 0, the warm reset value is 0, and similarly, if a warm reset and a cold reset involve resetting the warm branch record configuration value to 1, the warm reset value is 1. However, it will be understood that other examples of warm reset values ​​are possible. The warm configuration value can be a different value from the warm reset value. Furthermore, as will be understood, the above-mentioned "states" describe what the software writes to at least one register before a warm reset occurs, and the value of the warm branch record configuration value can be changed by a warm reset (for example, from a warm configuration value to a warm reset value), and therefore, a state set by the software does not necessarily remain through a warm reset.

[0022] By allowing the software to set warm branch recording configuration values ​​and cold branch recording configuration values, this enables the programmer to control whether branch recording is performed before and after a warm reset. This can be particularly useful as it allows the programmer to control the diagnostic information collected by the branch recording circuit.

[0023] In some examples, multiple states include a reset start state, and the branch recording circuit responds to the warm branch recording configuration value and cold branch recording configuration value indicating a reset start state in response to the reset circuit performing a warm reset to enable branch recording. For example, the reset start state (e.g., mode or configuration) of the warm branch recording configuration value and cold branch recording configuration value causes the branch recording circuit to not perform branch recording before a warm reset (e.g., a predetermined condition is not met before the warm reset) and to perform branch recording after a warm reset (e.g., the warm branch recording configuration value is reset by the warm reset, and as a result, a predetermined condition is met following the warm reset).

[0024] The reset start state can be advantageous because it allows the branch recording circuit to capture information about the reset process itself (for example, recording information about branches in the reset firmware executed after a warm reset to identify or respond to the cause of the warm reset event) without wasting power or degrading performance by performing branch recording before a warm reset that may not be necessary, and this information can be overwritten (at least in the case of a small cyclic branch recording buffer) with any more recent information collected after the warm reset (for example, in some implementations, enabling branch recording may limit the maximum performance achievable by the processing circuitry compared to when branch recording is disabled, for example, when branch recording is enabled, the branch recording circuitry may impose a limit on the number of branches that can be processed by the processing circuitry in one cycle). For example, a developer may want to select the reset start state when performing a diagnostic analysis to analyze the performance or correct functioning of the reset firmware.

[0025] In some examples, the reset start state is indicated by a worm branch record configuration value having a worm configuration value and a cold branch record configuration value having a first value. The branch record circuit is configured to determine that a predetermined condition is met when the worm branch record configuration value has a worm reset value and the cold branch record configuration value has a first value, and to determine that the predetermined condition is not met when the worm branch record configuration value has a worm configuration value and the cold branch record configuration value has a first value. In this configuration, assuming that the cold branch record configuration value retains the first value after a worm reset event, the transition from the worm configuration value to the worm reset value during a worm reset ensures that the predetermined condition is met after the worm reset if it was not met before the worm reset, and as a result, branch recording is enabled during the worm reset.

[0026] for example, When the warm reset value is 0 and the warm branch record configuration value and the cold branch record configuration value are different (not equal), a predetermined condition is met, and the cold branch record configuration value is set to 1 (for example, the first value is 1), and the warm branch record configuration value is set to 1 (for example, the warm configuration value is 1), thereby configuring the reset start state. When the warm reset value is 1 and the warm branch record configuration value and the cold branch record configuration value are different (not equal), a predetermined condition is met, and the cold branch record configuration value is set to 0 (for example, the first value is 0), and the warm branch record configuration value is set to 0 (for example, the warm configuration value is 0), thereby configuring the reset start state. When the worm branch record configuration value and the cold branch record configuration value are the same (equal), the worm reset value is 1, and when the predetermined conditions are met, the reset start state can be configured by setting the cold branch record configuration value to 1 (for example, the first value is 1) and setting the worm branch record configuration value to 0 (for example, the worm configuration value is 0), and When the warm reset value is 0 and the warm branch record configuration value and the cold branch record configuration value are the same (equal), a predetermined condition is met, and the cold branch record configuration value is set to 0 (for example, the first value is 0) and the warm branch record configuration value is set to 1 (for example, the warm configuration value is 1), thereby configuring the reset start state.

[0027] In some examples, multiple states include a reset stop state, and the branch recording circuit disables branch recording in response to the reset circuit performing a warm reset in response to warm branch recording configuration values ​​and cold branch recording configuration values ​​indicating a reset stop state. For example, the reset stop state (e.g., mode or configuration) of the warm branch recording configuration values ​​and cold branch recording configuration values ​​causes the branch recording circuit to perform branch recording until a warm reset occurs (e.g., predetermined conditions are met before the warm reset), but not after the warm reset (e.g., the warm branch recording configuration value is reset by the warm reset, and as a result, predetermined conditions are no longer met following the warm reset).

[0028] A reset-stopped state can be advantageous because it allows information about the program flow immediately preceding the warm reset (e.g., information about any firmware configured to run after the reset) to be reconstructed, and allows any problems in the code executed immediately preceding the warm reset (e.g., the problem that caused the warm reset) to be diagnosed. By disabling branch records after a warm reset, this prevents branch records recorded before the warm reset from being overwritten by branch records related to branches executed after the warm reset.

[0029] In some examples, a reset stop state is indicated by a worm branch record configuration value having a worm configuration value and a cold branch record configuration value having a second value, and the branch record circuit is configured to determine that a predetermined condition is met when the worm branch record configuration value has a worm configuration value and the cold branch record configuration value has a second value, and the branch record circuit is configured to determine that a predetermined condition is not met when the worm branch record configuration value has a worm reset value and the cold branch record configuration value has a second value. For example, the second value may be any value different from the first value. In this configuration, assuming that the cold branch record configuration value retains the second value after a worm reset event, the transition in a worm reset from a worm configuration value to a worm reset value means that the predetermined condition is no longer met after the worm reset (e.g., it stops being met) when it was met before the worm reset, so the branch record is invalidated in a worm reset.

[0030] for example, When the warm reset value is 0 and the warm branch record configuration value and the cold branch record configuration value are different (not equal), a predetermined condition can be met by setting the cold branch record configuration value to 0 (for example, the second value is 0) and setting the warm branch record configuration value to 1 (for example, the warm configuration value is 1), thereby configuring a reset stop state. When the warm reset value is 1 and the warm branch record configuration value and the cold branch record configuration value are different (not equal), a predetermined condition can be met by setting the cold branch record configuration value to 1 (for example, the second value is 1) and setting the warm branch record configuration value to 0 (for example, the warm configuration value is 0), thereby configuring a reset stop state. When the warm reset value is 1 and the warm branch record configuration value and the cold branch record configuration value are the same (equal), a reset stop state can be configured by setting the cold branch record configuration value to 0 (for example, the second value is 0) and setting the warm branch record configuration value to 0 (for example, the warm configuration value is 0), and When the warm reset value is 0 and the warm branch record configuration value and the cold branch record configuration value are the same (equal), a reset stop state can be configured by setting the cold branch record configuration value to 1 (for example, the second value is 1) and setting the warm branch record configuration value to 1 (for example, the warm configuration value is 1).

[0031] In some examples, multiple states include recording states via reset, and the branch recording circuit responds to warm branch recording configuration values ​​and cold branch recording configuration values ​​indicating the recording state via reset in order to perform branch recording both before and after the reset circuit performs a warm reset. For example, the recording state via reset (e.g., mode or configuration) of the warm branch recording configuration values ​​and cold branch recording configuration values ​​causes the branch recording circuit to perform branch recording until a warm reset (e.g., predetermined conditions are met before the warm reset), and then to continue branch recording after the warm reset (e.g., the warm reset does not change any of the branch recording configuration values, and as a result, the predetermined conditions continue to be met after the warm reset). For example, the recording state via reset instructs the branch recording circuit to enable branch recording on both sides (before and after) a warm reset.

[0032] A recording configuration via a reset can be useful for developers if there is diagnostic information of interest that should be captured both before and after a warm reset (for example, if a developer wants to test whether the reset firmware behaves correctly if certain conditions occur in the software running before the warm reset, and therefore the developer needs some information about a branch in the software before the warm reset to probe whether that event occurred).

[0033] In some examples, the recording state via reset is indicated by a worm branch recording configuration value having a worm reset value and a cold branch recording configuration value having a first value, and the branch recording circuit is configured to determine that a predetermined condition is met when the worm branch recording configuration value has a worm reset value and the cold branch recording configuration value has a first value. In this configuration, assuming that the cold branch recording configuration value retains the first value after a worm reset event and the worm branch recording configuration value retains the worm reset value after a worm reset event, the worm reset does not change whether the predetermined condition is met or not. Therefore, the predetermined condition remains met after the worm reset if it was met before the worm reset, and as a result, branch recording is enabled both before and after the worm reset.

[0034] for example, When the warm reset value is 0 and the warm branch recording configuration value and the cold branch recording configuration value are different (not equal), a predetermined condition is met, and the cold branch recording configuration value is set to 1 (for example, the first value is 1), and the warm branch recording configuration value is set to 0, thereby configuring the recording state via reset. When the warm reset value is 1 and the warm branch recording configuration value and the cold branch recording configuration value are different (not equal), and a predetermined condition is met, the recording state via reset can be configured by setting the cold branch recording configuration value to 0 (for example, the first value is 0) and setting the warm branch recording configuration value to 1. When the warm reset value is 1 and the warm branch recording configuration value and the cold branch recording configuration value are the same (equal), a predetermined condition is met, and the cold branch recording configuration value is set to 1 (for example, the first value is 1), and the warm branch recording configuration value is set to 1, thereby configuring a recording state via reset, and When the warm reset value is 0 and the warm branch recording configuration value and the cold branch recording configuration value are the same (equal), a predetermined condition is met, and the cold branch recording configuration value is set to 0 (for example, the first value is 0), and the warm branch recording configuration value is set to 0, thereby configuring a recording state via reset.

[0035] Specific examples of how worm branch record configuration values ​​and cold branch record configuration values ​​can be configured are given above for each of the reset start state, reset stop state, and reset recording state, but it should be understood that these are merely examples assuming that the worm branch record configuration values ​​and cold branch record configuration values ​​can each take either a value of 1 or 0. In other examples, such as when the worm branch record configuration values ​​and cold branch record configuration values ​​are not limited to a single bit, other predetermined conditions may be set.

[0036] In some examples, the cold branch record configuration value has one of the following: a cold configuration value and a cold reset value, and the cold reset includes resetting the cold branch record configuration value to the cold reset value.

[0037] In some examples, a branch recording circuit is configured to determine that a predetermined condition is not met when the worm branch recording configuration value has a worm reset value and the cold branch recording configuration value has a cold reset value. This means that the default state of the worm branch recording configuration value and the cold branch recording configuration value after a cold reset may be to disable branch recording. For example, in a system where the reset stop state, reset start state, and / or recording state via reset are implemented as described above, the cold configuration value may be a first value and the cold reset value may be a second value so that the default state after a cold reset disables branch recording.

[0038] However, in other examples where the cold branch record configuration value is one of the cold configuration value and the cold reset value, if it is considered acceptable to enable branch recording after a cold reset, then in a system where the reset stop state, reset start state, and / or recording state via reset are implemented as described above, the cold configuration value may be the second value and the cold reset value may be the first value.

[0039] In this way, the device may be configured so that the default after a cold reset is no branch recording (e.g., branch recording is disabled) to avoid recording branch information before the software has the opportunity to set the warm branch recording configuration values ​​and the cold branch recording configuration values. This can reduce the amount of power wasted (e.g., when performing branch recording when it is not needed) and can also be more secure in systems where branch recording around resets is controlled by more privileged software. In this configuration, assuming that the cold branch recording configuration value retains the cold reset value after a warm reset event and the warm branch recording configuration value retains the warm reset value after a warm reset event, the warm reset does not change whether a given condition is met or not. Therefore, if a given condition was not met before the warm reset, the given condition will not be met after the warm reset and branch recording will not be performed.

[0040] In some examples, the value set for the cold branch record configuration in response to a cold reset may be fixed and predetermined, and may be either the first or second value as described above.

[0041] However, in other examples, in response to a cold reset trigger event, the reset circuit may reset the cold branch record configuration value to one of a first and second value specified by the reset value selection signal. Thus, whether branch recording is enabled or disabled after a cold reset may depend on the signal supplied at the time of the cold reset trigger event. This allows control over whether branch recording is enabled by default or disabled by default after a cold reset. For example, the reset value selection signal may be connected to circuit logic outside the cold reset domain and may be connected via a pin on the integrated circuit to an external circuit that supplies the reset value selection signal.

[0042] In some examples, a processing circuit prevents access to a branch record storage circuit while the processing circuit is operating at a privileged execution level lower than a given execution level, in response to a control value held in a control register having a first value. For example, a processing circuit may be configured to operate at one of several execution levels (which may also be called privileged levels or exception levels), and processes running at each execution level are permitted to access different subsets of information / states stored in or accessible to the processing circuit. For example, a process running at a more privileged execution level may be permitted to access storage structures or memory areas that are inaccessible to less privileged processes (e.g., processes running at lower execution levels). These storage structures may, in some examples, include a branch record storage circuit that, under the control of a control value stored in a control register, can be made inaccessible for at least a certain time to processes running at a privileged execution level lower than a given privilege level. For example, a control register may hold states that control various functions of the processing circuit, and the control value may be a single value (e.g., a single bit) from the states stored in the control register, or it may be a multi-bit field in which at least one encoding of its field indicates that the branch record storage circuit should not be accessible from a low privileged run level. Alternatively, the control register may be a dedicated register for holding the control value. The first value of the control value does not necessarily have to be the same as the first value of the cold branch record configuration value in the example above, and the control value may be set (e.g., by software operating at a given run level) to control whether the branch record storage circuit can be accessed by a low-privilege process operating at an run level with lower privileges than a given run level.

[0043] In this way, system security can be improved by preventing a process operating (running) at a lower privilege level than a given run level from accessing branch records generated at that run level (for example, reset firmware may run at a given run level), and thus making it more difficult for untrusted code to obtain information about higher-privileged code (for example, information recorded by a branch record circuit may be sufficient to allow the program flow to be reconstructed, so a malicious program may be able to use the information stored in the branch record storage circuit to infer sensitive information). This means that information about branch instructions processed at a given run level can still be recorded as needed without compromising system security, which can be useful in diagnostics.

[0044] In some examples, a branch recording circuit may determine whether to enable branch recording based on warm branch recording and cold branch recording configuration values ​​in response to a processing circuit operating at a given run level, and independently of the warm branch recording and cold branch recording configuration values, whether to enable or disable branch recording in response to a processing circuit operating at a privileged run level lower than a given run level. For example, the warm branch recording and cold branch recording configuration values ​​may only control branch recording for branches processed at a given run level (or a more privileged run level), and other controls may be implemented to control branch recording when running at a privileged run level lower than a given run level. For example, a control mechanism that utilizes the warm branch recording and cold branch recording configuration values ​​may be specific to a particular run level, and less privileged run levels may have different control mechanisms (e.g., using a single enable value that specifies whether branch recording is enabled or disabled).

[0045] By providing a separate mechanism for controlling branch recording at a higher privilege level, it is not necessary to allow lower privilege execution levels to access warm branch recording configuration values ​​and cold branch recording configuration values. Furthermore, providing warm branch recording configuration values ​​and cold branch recording configuration values ​​may not be justified for lower privilege execution levels because low-privilege code does not execute immediately after a warm reset, and therefore it is acceptable for software to configure enable / disable values ​​after a warm reset to control branch recording behavior (meaning simpler configuration options such as a single enable / disable value may be used). The use of warm branch recording configuration values / cold branch recording configuration values ​​is particularly useful for more privileged code that executes immediately after a warm reset, and therefore, by the time the more privileged code can make configuration changes to the branch recording configuration information, it may have already executed a reasonable number of instructions (e.g., instructions in the reset firmware that execute immediately after a warm reset) that can provide diagnostic information. By using warm branch logging configuration values / cold reset configuration values, it becomes practical to diagnose problems associated with code running immediately after a warm reset, which may not be practical if a software configuration of the enable value was required after a warm reset before branch logging could be initiated. Furthermore, in some specific cases, warm branch logging and cold branch logging configuration values ​​may also be inaccessible to processes running at a privileged runlevel lower than a given runlevel, resulting in lower-privileged (and potentially untrustworthy) programs being unable to control whether branch logging is performed for a process at a given runlevel.

[0046] In some examples, information about processed branch instructions includes information that allows the program flow of the processed instructions to be reconstructed. For example, information held in a branch record memory circuit may allow the program flow to be reconstructed by a program flow analyzer having a copy of the program (for example, by providing information indicating which branch instructions were executed, as well as the results and / or targets of the executed branches), and the stored information does not itself need to be a complete record of the program flow.

[0047] In this way, branch recording performed by the branch recording circuit can provide information that is useful for diagnosis (for example, to identify any problems in the code or processor).

[0048] In some examples, information about a processed branch instruction includes at least one of the instruction address of the instruction from which the processed branch was taken, and the target address of the instruction from which the processed branch was taken. The information stored in the branch recorder for a processed branch instruction may include one or both of these pieces of information. Other information may also be stored in the branch recorder, and it will be understood that the choice of exactly which information should be recorded depends on the specific implementation and, for example, on the diagnostic or debugging program that is intended to be used.

[0049] In this way, the behavior of processed branch instructions can be identified, and therefore, for example, the program flow can be reconstructed, which is useful for diagnosis.

[0050] In some cases, filter criteria can be set to control which types of branches have information recorded in the branch record memory circuit. For example, the types may include indirect branches, linked branch instructions that store a return address instruction in a link register, or function return branch instructions that branch to the return address indicated in the link register. The filter criteria can specify which of these types should have information recorded in the branch record memory circuit when branch recording is enabled. Therefore, even when branch recording is enabled using warm branch recording configuration values ​​and cold branch recording configuration values, it is not necessary for all branches to have information recorded in the branch record memory circuit.

[0051] In some examples, the branch record memory circuit is configured to make information about processed branch instructions available to at least one of external diagnostic hardware and a diagnostic process performed on the processing circuit. There are many different ways of performing processor diagnostics or debugging, which may include providing a diagnostic program to be run by the processing circuit itself, or providing external (e.g., external to the processing circuit itself, e.g., off-chip) diagnostic hardware (e.g., circuit) to run the diagnostic program, which may include an external diagnostic hardware component of the processing hardware that includes the branch record memory circuit. For example, the external diagnostic hardware may include an external computer that runs dedicated diagnostic (e.g., debug) hardware or diagnostic software. In any of these situations, the information stored in the branch record memory circuit can be made available to the diagnostic process.

[0052] Using dedicated external hardware for diagnostics can allow for the analysis of a larger amount of branch information (and in practice, any other information that can be captured by the processing circuit and provided to the external hardware) (for example, if the external hardware has more memory space for diagnostic information such as branch records than is available to the processing circuit), can provide greater functionality (as it does not depend on the resources available to the processing circuit), and can allow the diagnostic process to be performed even if a catastrophic error means that the processing circuit is unavailable. Therefore, making the information stored in the branch record storage circuit available to external diagnostic hardware can be very useful. However, the diagnostic process can also be performed on-chip (for example, by the processing circuit), and therefore it can also be advantageous to allow such a process running on the processing circuit to access the stored branch information.

[0053] In some examples, both the worm branch record configuration value and the cold branch record configuration value are held in the same register. While it is possible for each of the worm branch record configuration value and the cold branch record configuration value to be held in separate registers (for example, they may each be held in dedicated registers), in some implementations, both values ​​may be held in the same register. For example, this could be a dedicated register for storing the worm branch record configuration value and the cold branch record configuration value, or a control register that also stores other control states. For example, the worm branch record configuration value and the cold branch record configuration value may be held in the same control register that stores the aforementioned control value in implementations where this control value is provided. Each of the worm branch record configuration value and the cold branch record configuration value can have any size or take any value, but in some specific examples, each of the worm branch record configuration value and the cold branch record configuration value may have a single bit in the same register.

[0054] This approach, which stores both worm and cold branch record configuration values ​​in the same register, can be particularly advantageous by making the configuration of these values ​​faster. In particular, while a single system register update instruction can specify the new value of multiple bits stored in a single system register, if worm and branch record configuration values ​​are held in multiple different registers, this may require two separate system register update instructions, each specifying one of the registers, to be executed to update the values. This approach can also simplify access control in implementations where access to worm and cold branch record configuration values ​​is restricted to a specific run level.

[0055] The reset circuit may prevent the reset of the branch recorder circuit in response to a warm reset trigger event. Therefore, the branch recorder circuit may remain unchanged in response to a warm reset. The branch recorder circuit may be reset in response to a cold reset trigger event but not in response to a warm reset trigger event, thus remaining within a cold reset domain. This allows any branch information recorded in the branch recorder circuit to remain accessible after a warm reset.

[0056] In some examples, a cold reset trigger event includes a power-on event. For instance, this could be in response to the power button being pressed to turn on the processing circuit after it has been shut down. However, other examples of cold trigger events are also possible.

[0057] In some examples, a warm reset trigger event includes a timeout signal generated in response to the elapsed time of a watchdog counter. For example, a watchdog counter (e.g., a watchdog timer) may be used to check whether a processing circuit is functioning correctly. The timer may be set to a given value and made capable of counting down over time. When the processing circuit is functioning correctly, it may periodically reset the counter (e.g., set the counter to its initial value), so that the watchdog counter only elapses if the computer is not functioning correctly. If the watchdog timer elapses, it may trigger the processing circuit to perform a corrective or diagnostic action, including generating an interrupt and performing a warm reset. However, it will be understood that a watchdog event (e.g., the elapsed time of a watchdog counter) is only one example of a warm reset trigger event, and other examples are possible.

[0058] In some examples, the reset circuit resets different subsets of states that are reset in response to a cold reset trigger event, in response to each of several different warm reset trigger events. For example, there may be two or more warm reset domains, each containing a different subset of state resets in a cold reset, and these two or more reset domains may be provided in addition to a cold domain that encompasses all state resets in a cold reset.

[0059] Here, a specific embodiment will be described with reference to the drawings.

[0060] Figure 1 shows a data processing system that can implement this technique. The data processing system shown in Figure 1 includes a memory 104 and a central processing unit (CPU) 102 that communicates with an external diagnostic circuit 106, but it will be understood that other elements not shown in the figure may be present in the data processing system.

[0061] The CPU 102 includes a processor pipeline 108 with several pipeline stages for processing instructions. In particular, pipeline 108 includes a fetch stage (fetch circuit) 110, which fetches (e.g., reads) instructions from the cache 112 and passes them to the decryption stage 114. For example, the cache 112 may include multiple levels of caches, each holding a subset of data and instructions stored in memory 104. When the fetch stage 110 fetches an instruction from the cache 112, for example, if the instruction has been fetched previously or has been prefetched into the cache beforehand, the instruction may already be stored in the highest level cache (e.g., the cache closest to the fetch stage 110 - this could be the "level 1" cache, but cache levels may be labeled differently, and the level 1 cache could be the cache closest to memory 104). Alternatively, the instruction does not have to be in the highest-level cache; in that case, it may need to be fetched from memory or a lower-level cache to the highest-level cache before being returned to the fetch stage 110.

[0062] When the fetch stage receives an instruction, it passes the instruction to the decoder stage (decoder circuit) 114, which decodes the instruction and generates a control signal. This control signal controls the execution stage (execution circuit) 116 to execute the instruction. The issuer stage (issue circuit) 118 then controls when the decoded instruction (for example, the control signal generated by the decoder circuit) is issued to the execution stage 116 for execution, and the execution stage 116 executes the instruction in response to the decoded instruction (for example, in response to the control signal).

[0063] Execution stage 116 is, • As an arithmetic logic unit (ALU) 120 for executing arithmetic operations in response to arithmetic instructions such as ADD and SUBTRACT, • Floating-point unit (FPU) 122 for performing operations on floating-point operands. • A branch unit (Br) 124 that executes branch instructions, and The system includes multiple execution units, such as a load / storage unit (ld / st) 126, which performs load operations to load data from memory 104 (optionally via cache 112) into a set of registers 128, and storage operations to store the data from registers 128 into memory. For example, the load / storage unit 126 may load data into registers 128 in response to a decoded load instruction, and may store data in response to a decoded store instruction.

[0064] Pipeline 108 also includes a write-back stage (write-back circuit) 130 for writing the results of data processing operations performed by the execution stage 116 to register 128. Pipeline 108 is an example of a processing circuit that processes instructions.

[0065] The register file 128 comprises multiple registers, each register being a temporary storage structure for storing data of a given size. In the example in Figure 1, the register file 128 includes one or more control registers 136 that store information for controlling the operation of one or more elements of the CPU. The register file also stores two branch record configuration values ​​138, 140, which are examples of a warm branch record configuration value (BREW) 140 and a cold branch record configuration value (BREC) 138. Other registers (not shown) are also provided within the register file 128 to hold input and result operands for operations performed by the execution circuit 116.

[0066] The CPU 102 also includes a branch predictor 132 that makes predictions about branch instructions based on branch prediction information stored in one or more branch predictor caches 134. For example, the branch predictor 132 may predict the outcome of a branch instruction (e.g., whether a branch is taken or not) and / or the target of the branch instruction (e.g., the target address of the target instruction). The branch predictor cache 134 may be updated in response to signals received by the branch unit 124 indicating the outcome and target address of an executed branch instruction.

[0067] Furthermore, the CPU 102 is provided with a branch recording circuit 142 configured to read branch recording configuration values ​​138 and 140 and activate branch recording when the branch recording configuration values ​​satisfy predetermined conditions (e.g., have a given value). When branch recording is activated, information about executed branch instructions can be recorded in the branch recording buffer 144. In particular, for a given branch instruction from which a result is taken, the branch recording buffer 144 may store the instruction address of the processed branch instruction (e.g., a memory address indicating where the instruction is stored) and / or the target address of the processed branch instruction. Branches that do not appear in the branch recording do not need to have information stored in the branch recording buffer 144, as this can imply that no branch was taken. Such information about processed branch instructions can be useful in diagnostic operations (e.g., debugging operations, or operations to determine the cause of an error that occurred). Therefore, the branch recording buffer 144 is configured to make its contents available for inspection by an external diagnostic circuit 106, which uses the stored information to diagnose problems encountered by the CPU. The branch record buffer 144 may also (or alternatively) make its contents available to a diagnostic process being performed by the execution circuit 116. The branch record buffer 144 is an example of the branch record storage circuit described above, configured to make information about processed branch instructions available for diagnostic analysis. In another example, when branch recording is enabled, the recorded branch records can be written to a memory system, and thus the cache 112 and memory 104 can function as branch record storage circuits.

[0068] One example of a situation in which information about executed branch instructions may be useful to the external diagnostic circuit 106 or the diagnostic process is around a warm reset of all or part of the CPU 102. For example, this could be a warm reset in which a subset of the states stored in the CPU components (including the Warm Branch Record Configuration Value (BREW) 140) is reset (for example, this may be in response to the elapsed time of the watchdog timer or the occurrence of some kind of error). Considering information about branch instructions executed in the cycle preceding the warm reset trigger (e.g., the event that triggers the warm reset) may be useful for the diagnostic process because it can indicate the event that leads to the warm reset being triggered. It may also be useful to record information about branch instructions processed immediately after the reset (e.g., branch instructions in the reset firmware) to diagnose problems with the reset code itself.

[0069] However, the branch record buffer 144 has a limited size and may be implemented, for example, as a small circular buffer. Expanding the size of the branch record buffer 144 may only be used for diagnostic processes and not for normal processing by the processor pipeline 108, and may not be justified considering the additional cost incurred in terms of increased circuit area. Therefore, the number of branch instructions for which information can be stored in the branch record buffer 144 is limited. Thus, it may be useful to control when branch recording by the branch recording circuit is enabled. For example, it may be useful to control whether branch recording should be stopped when a reset is triggered (e.g., not to record information about branch instructions processed after the reset), as a result more branch instructions executed in the time preceding the reset can be recorded (by preventing information about older branch instructions from being overwritten by information about branch instructions processed after the reset signal). This also avoids wasting power by performing branch recording when it is not needed. On the other hand, it may also be useful to start branch recording on a reset. For example, if the intention is to diagnose a problem in the reset procedure itself, performing branch recording before the reset occurs may be a waste of power, and therefore, controlling the branch recording circuit 142 to start branch recording at the reset can save power. Also, in some cases, performing branch recording can be invasive and may affect the behavior of the processing circuit. For example, if the branch recording circuit 142 can handle recording a limited number of branches at once, the number of branches that can be executed by the branch unit 124 in a single cycle when branch recording is enabled may be limited to the number that the branch recording circuit 142 can support, in order to avoid missing recorded information about the branches that have been executed. Therefore, in order to avoid unnecessarily limiting performance, it may be desirable to avoid enabling branch recording when the information being collected by the branch recording circuit 142 is of no interest to the user.

[0070] However, in some situations, programmers may find it beneficial to record branch information both before and after a reset, or they may decide that branch recording can be disabled (for example, to save power).

[0071] Therefore, the BREC value 138 and BREW value 140 are provided to control branch recording around a warm reset. The BREW value 140 is configured to be reset by both a warm reset and a cold reset, while the BREC value 138 is configured to be reset by a cold reset only, and the programmer can set the values ​​of each register to control when the branch recording circuit 142 performs branch recording.

[0072] The BREC value 138 and the BREW value 140 may be stored in separate registers, or both may be stored in the same register. For example, each of the BREC value and the BREW value may be a single bit (e.g., 1 or 0) provided in one of the control registers 136.

[0073] Figure 2 shows the warm reset domain, the non-warm reset domain, and the cold reset domain. As shown in the figure, the CPU can be divided into a warm domain 202, which is reset during a warm reset (in response to a signal provided by the warm reset pin 208), and a non-warm domain 204, which is not reset during a warm reset but is reset during a cold reset (in response to a signal provided by the non-warm reset pin 210). Since a cold reset resets all states in the warm domain 202 and all states in the non-warm domain 204, the cold domain 206 of states can be considered a domain that encompasses both the warm domain 202 and the non-warm domain 204.

[0074] The data processing system also includes a reset circuit 201 that drives a worm reset pin 208 and a non-worm reset pin 210. In particular, the reset circuit 210 drives the worm reset pin 208 in response to both a worm reset signal (generated in response to a worm reset trigger event) and a cold reset signal (generated in response to a cold reset trigger event) so that all states in the worm domain 202 are reset. On the other hand, the reset circuit 210 drives the cold non-worm reset pin 210 in response to a cold reset signal (not a worm reset signal) to reset the states in the non-worm domain 204. The reset circuit may also include a reset tree that branches from either the worm reset pin 208 or the cold reset pin 210 in each of the worm domain 202 and the non-worm domain 204 to provide a set of reset signal paths that propagate reset signals corresponding to each component in the corresponding reset domain (e.g., the worm domain or the non-worm domain) and trigger the reset of the states of those components. The reset circuit 201 is an example of a reset circuit that performs a cold reset in response to a cold reset trigger event by resetting the processing circuit, and performs a warm reset in response to a warm reset trigger event by resetting a subset of the states that are reset in response to the cold reset trigger event.

[0075] In the example in Figure 2, the warm reset domain 202 includes a warm reset configuration value (BREW) 140 and various other warm domain states, such as a watchdog timer 212. The watchdog timer (also referred to as a properly functioning computer or COP timer) is a timer used to detect malfunctions. In particular, the CPU is configured to periodically restart the watchdog timer during normal operation to prevent the watchdog timer from elapsed (counting down to 0). If the CPU fails to restart the watchdog timer (e.g., due to an error), the timer elapses and generates a timeout signal. The timeout signal is used to initiate corrective action, which may be triggered by, for example, the elapsed watchdog timer being a warm reset trigger, and therefore a warm reset. For example, in a warm reset, power to the integrated circuit may remain on, and as a result, states that are not in the warm reset domain retain their current values.

[0076] On the other hand, the non-warm reset domain 204 in Figure 2 includes a cold reset configuration value 138, a branch log buffer 144, and various other warm domain states such as a debug state 214 (for example, a state related to a debug process performed by the CPU).

[0077] In general, the non-warm reset domain 204 may include states that need to be maintained after a warm reset but do not need to be maintained after a cold reset. For example, the branch record buffer 144 may store branch records generated before a warm reset and is therefore in the non-warm domain 204, which may be necessary for a diagnostic process to diagnose the cause of the warm reset (e.g., the cause of the watchdog timer 212 elapsed). Similarly, the debug state 214 is also in the non-warm domain 214, as debugging after a warm reset may require access to debug states stored before the warm reset.

[0078] Each state in the reset domain may have a flip-flop that resets to a default state (for example, this could be a value of 0, but this is just one example; in other examples, the default state could be, for example, 1). Similarly, each of the warm reset configuration values ​​138 and 140 can be reset to a default value in response to a reset signal (again, this could be, for example, 1 or 0 in response to a particular implementation).

[0079] It will be understood that each of the warm domain 202 and the non-warm domain 204 may also include other states not shown in Figure 2.

[0080] As shown in Figure 2, optionally, a reset value selection signal can be supplied to control whether the cold reset branch record configuration value 138 is reset to 1 or 0. The reset value selection signal may be supplied at the cold reset branch record configuration signal pin 216 from an external device outside the integrated circuit having the cold domain 206, or it may be generated by logic on another part of the integrated circuit outside the cold domain 206. This allows the branch record to be enabled or disabled by default during the period between the cold reset and the time when the software executed by the processing circuit configures the values ​​of BREC138 and BREW140 after a cold reset. Providing a reset value selection signal is optional; in other examples, BREC138 may simply be reset to a fixed value of 0 or 1 so that whether the branch record is enabled or disabled after a cold reset is fixed.

[0081] As described above, the BREC value 138 and BREW value 140 can be set by the programmer to control branch recording by the branch recording circuit 142 before and after a warm reset. Figure 3 shows an example of how this can be implemented.

[0082] In the example shown in Figure 3, the BREC value and BREW value can each be set to either 1 or 0, and are configured to be reset to 0 in response to a reset signal. The branch recording circuit 142 is configured to enable branch recording when the BREC value and BREW value are different (for example, when BREC ≠ BREW) and to disable branch recording when the BREC value and BREW value are equal (BREC == BREW).

[0083] The table in Figure 3 shows the values ​​that a programmer can set for BREC and BREW to select various branch recording configurations. In other words, the table shows what the BREC and BREW values ​​are from the time they are set by the programmer until a warm reset occurs and the BREW value is reset to 0. As shown in the first row of the table in Figure 3, the programmer can set the BREC value to 0 and the BREW value to 1 to enable branch recording until a warm reset, and then disable branch recording after the warm reset (e.g., a "warm reset stop" configuration). In particular, branch recording is enabled before the reset because the programmer has set the BREC and BREW values ​​to different values ​​(0 and 1). However, branch recording is disabled after the warm reset because the BREW value is reset to 0 in the warm reset so that the BREC and BREW values ​​become equal (both 0) after the reset.

[0084] As shown in the second row of the table in Figure 3, to control the branch recording circuit to enable branch recording on a warm reset (e.g., a "start on warm reset" configuration), the programmer sets both the BREC and BREW values ​​to 1. In this way, branch recording is disabled before the warm reset because the BREC and BREW values ​​are equal (both are 1), but branch recording is enabled after the warm reset because the BREW value is reset to 0 and the BREC and BREW values ​​are no longer equal (1 and 0).

[0085] Therefore, for both the "Warm Reset Stop" and "Warm Reset Start" configurations, the BREW value is set to 1 (or, more generally, the non-reset value), and as a result, the state indicated by the BREC and BREW values ​​is changed by the warm reset value (for example, because the BREW value is changed to the reset value (e.g., 0) during a warm reset). However, it will be understood that these values ​​are specific to the implementation where branch logging is enabled when BREC != BREW.

[0086] Referring to the third row of the table in Figure 3, in order to control the branch recording circuit to record via a warm reset (for example, to enable branch recording both before and after a warm reset, referred to as "record via warm reset"), the programmer sets the BREC value to 1 and the BREW value to 0. In this way, since the BREW value and BREC value are not equal (1 and 0) and neither value changes with a warm reset, branch recording is enabled both before and after a warm reset.

[0087] Finally, to control the branch recording circuit and prevent branch recording from being performed at all, the programmer sets both the BREC and BREW values ​​to 0. In this way, since the BREC and BREW values ​​are equal (both 0) and neither value changes during a warm reset, branch recording is disabled both before and after a warm reset. Since both the BREC and BREW values ​​are reset to 0 during a cold reset, the default state after a cold reset is to disable branch recording.

[0088] Therefore, for both the "record via warm reset" and "do not record" configurations, the BREW value is set to 0 (or more generally, the reset value), and as a result, the state indicated by the BREC and BREW values ​​does not change at the warm reset value (for example, the BREW value is already at the reset value (e.g., 0) before the warm reset). However, it will be understood that this is only true in implementations where branch recording is disabled when BREC == BREW.

[0089] As described above, the table in Figure 3 shows how a programmer can control branch recording before and after a reset in an implementation where branch recording is executed when BREC!=BREW and when both the BREC and BREW values ​​are reset to 0 by a cold reset (and a warm reset in the case of the BREW value). In an alternative implementation where both the BREC and BREW values ​​are reset to 1, the values ​​of 0 and 1 in the table are simply replaced with 1 and 0, respectively.

[0090] Figure 4 illustrates how the software can configure each of the settings shown in Figure 3 and how a warm reset affects the BREC and BREW values. In the diagram in Figure 4, the BREC and BREW values ​​(identified as "E3BREC" and "E3BREW" in Figure 4 to indicate that these values ​​control only branch recording for processes running at exception level 3, as will be explained in more detail below) are initially both 0, which may be due to a cold reset that resets both values ​​to 0, or because the programmer has turned off branch recording by setting both values ​​to 0.

[0091] In the "Activate" step, the software enables branch recording in one of the configurations described above. Specifically, to select the "Reset Stop" state, the software sets the BREW value to 1. This enables branch recording because BREC!=BREW. To select the "Record via Reset" configuration, the software sets the BREC value to 1, which also enables branch recording because BREC!=BREW. To select the "Reset Start" state, the software sets both BREC and BREW to 1, which disables branch recording (or rather, does not enable branch recording as it is already disabled) because BREC==BREW. Finally (not shown in Figure 4 for brevity), the software can maintain a "Do Not Record" configuration by leaving the BREC and BREW values ​​as they are (for example, setting both to 0).

[0092] During a warm reset, the BREW value is reset to 0, but the BREC value remains unchanged. This means that the BREC and BREW values ​​indicate one of two possible states after a warm reset: BREC=1 and BREW=0, therefore BREC!=BREW, where branch recording is enabled; and BREC=0 and BREW=0, therefore BREC==BREW, where branch recording is disabled. In particular, when the software selects a reset stop configuration (BREC=0 and BREW=1 before the warm reset), branch recording is disabled following the reset. When the software selects recording via a reset configuration (BREC=1 and BREW=0 before the warm reset), branch recording remains enabled after the warm reset. When the software selects a reset start configuration (BREC=1 and BREW=1 before the warm reset), branch recording is enabled during the warm reset. Finally, although not shown in the diagram, it should be understood that if the software selects a record-disable configuration (for example, leaving both the BREC and BREW values ​​at 0 before a warm reset), branch recording will remain disabled after the warm reset.

[0093] Figure 5 shows yet another exemplary implementation where the branch recording circuit is configured to enable branch recording when the BREC value and BREW value are equal (unlike Figures 3 and 4, where branch recording is performed when the BREC value and BREW value are not equal). In this example, since branch recording is enabled when the BREC value and BREW value are equal, the BREW value is set to a non-reset value to constitute both the warm reset start state and the warm reset stop state (for example, so that the BREW value changes during a warm reset), and the BREW value is set to a reset value to constitute both the recording state and the non-recording state via a warm reset (for example, so that the BREW value does not change during a warm reset).

[0094] In the specific example shown in the table in Figure 5, the BREC value is reset to 0 during a cold reset, and the BREW value is reset to 1 during both a warm reset and a cold reset. Therefore, the warm reset stop state is configured by setting BREC==BREW==1, the start of the warm reset state is configured by setting BREC==1 and BREW==0, recording through the warm reset state is configured by setting BREC==BREW==1, and the no-recording state is configured by leaving both BREC and BREW at their reset values ​​(0 and 1, respectively).

[0095] In the alternative implementation where the BREC value is reset to 1 and the BREW value is reset to 0, please note that the values ​​of 0 and 1 in the table are simply replaced with 1 and 0, respectively.

[0096] In each of the examples shown in Figures 3 to 5, four different configurations are possible (stop on warm reset, start on warm reset, record via warm reset, and not record), and branch recording both before and after a warm reset can be controlled using only two values ​​(BREC and BREW), even when the branch recording circuit is configured to behave differently before and after a warm reset (e.g., start or stop branch recording on warm reset). This is possible because (1) a pair of values ​​provide four different states (e.g., 00, 01, 10, 11), (2) the BREW value is reset on both warm and cold resets, and the BREC value is reset only on cold resets (two of the four states can control the branch recording circuit to behave differently on both sides of a warm reset), and (3) the BREC and BREW values ​​can be used to determine whether or not to perform branch recording by comparing the values ​​(e.g., to see if the values ​​are equal or unequal). Therefore, branch recording both before and after a warm reset can be implemented in a configurable manner without requiring any software configuration after the warm reset, allowing programmers to tailor the process to the specific needs of the system (e.g., in response to the requirements of diagnostic software run on the CPU or in an external diagnostic circuit, and in response to the relative importance of power saving versus performance improvement). Furthermore, since only two values ​​(BREC and BREW) are required to represent all four states, and it is possible to determine whether or not to perform branch recording at any given time by comparing the BREC and BREW values ​​(e.g., to determine whether they are equal), these advantages can be provided without a significant increase in cost. In particular, this technique utilizes two configuration values ​​to be programmed to control branch recording, and the circuit required to determine whether or not to perform branch recording at any given time can be implemented using a simple comparator circuit for comparing the two values.

[0097] Figure 6 is a flowchart illustrating the operation of the branch recording circuit under the control of BREC and BREW values. In the method shown in Figure 6, it is determined whether or not a branch instruction is processed (S610). The branch recording circuit waits until the branch instruction is processed (for example, by the processor pipeline in Figure 1) ("N" branch).

[0098] When the branch recording circuit determines that the processing circuit is processing a branch instruction ("Y (yes)" arrow, for example, the branch recording circuit can detect when the branch instruction was fetched by the fetch circuit, when the branch instruction was decoded by the decode circuit, when the branch instruction was issued by the issue circuit, or when the branch instruction was executed by the execution circuit), it then determines whether the BREC and BREW values ​​satisfy a predetermined condition (S620). For example, as shown in the examples in Figures 3 to 5, the predetermined condition can be based on whether the BREC value and the BREW value are equal (for example, in Figures 3 and 4, the predetermined condition is BREC != BREW, and in Figure 5, the predetermined condition is BREC == BREW). Alternatively, any other predetermined condition can be specified for the BREC and BREW values ​​to indicate that branch recording should be performed.

[0099] If the BREC and BREW values ​​do not meet the specified conditions ("N (No)" arrow), the method returns to step S610, and the branch recording circuit waits until another branch instruction is processed.

[0100] On the other hand, if a predetermined condition is met ("Y (Yes)" arrow), the branch recording circuit determines in step S622 whether the processed branch has been taken. If the branch has not been taken, the method returns to step S610 and waits for processing of another branch.

[0101] If it is determined in step S622 that a branch is taken, then in step S624, the branch recording circuit determines whether any filter criteria (for determining whether a particular branch should have information recorded in the branch recording buffer) are met. For example, the filter criteria can specify one or more types of branches for which branch records should be stored (or one or more types of branches for which branch records should not be stored). The filter criteria can also specify one or more address ranges, and branches having instruction addresses (or target addresses) within that range should or should not be stored in the branch recording buffer. Specifying a filter criterion is not mandatory, and if no filter criterion is currently specified, the result in step S622 can always be Y (yes).

[0102] Therefore, if any of the filter criteria are met in step S622, in step S630, the branch recording circuit records information about the processed branch instruction in the branch recording buffer. Step S630 is omitted if the imposed filter criteria are not met for the current branch. Regardless of whether any information is stored in the branch recording buffer, the method returns to step S610, and the branch recording circuit waits until another branch instruction is processed.

[0103] Figure 6 shows a series of steps in a certain order, but it should be understood that the various checks in steps S620, S622, and S624 may be performed in a different order, or at least partially in parallel.

[0104] Figure 7 is a flowchart illustrating how to perform a warm reset or a cold reset in response to a corresponding reset trigger. In the method of Figure 7, it is determined whether a cold reset trigger (e.g., power-on operation) has been detected (S710). If a cold reset trigger is detected ("Y (yes)" arrow), the cold reset S730 is performed. In particular, the cold reset S730 includes step S740 to reset the "non-warm" domain (including the BREC value) and step S760 to reset the warm domain. The method then returns to step S710.

[0105] On the other hand, if it is determined in step S710 that a cold reset trigger has occurred, it is determined whether or not a warm reset trigger has occurred (step S720). If a warm reset trigger has not occurred ("N (No)" arrow), the method returns to step S710. On the other hand, if it is determined that a warm reset trigger has occurred ("Y (Yes)" arrow), the warm domain (including the BREW value) is reset before the method returns to step S710 (S750).

[0106] Referring now to Figure 8, this figure schematically illustrates an example of a process that may be performed by a data processing device. The hypervisor 802 may manage several virtual machines (VMs, also known as guest operating systems or guest OSs) 804. Each VM 804 may manage one or more applications 806. For example, the hypervisor 802 may control which areas of the address space are allocated to each virtual machine 804 and control switching between virtual machines 804 (e.g., scheduling interrupts to share processing resources over time between each virtual machine 804). Similarly, each VM 804 may control which areas of the address space are allocated to each application 806 running under that VM 804 and may control switching between applications as needed.

[0107] As shown in Figure 8, each process is associated with a given privilege level, EL0, EL1, EL2, and EL3. In this example, higher numbered privilege levels are more privileged than lower numbered privilege levels, but in other examples, they may be numbered in other ways (for example, EL0 might instead represent the most privileged exception level). In this example, application 806 runs at privilege level EL0, VM 804 runs at privilege level EL1, and hypervisor 802 runs at privilege level EL2. Typically, processes running at higher privilege levels have rights that are unavailable to processes running at lower privilege levels.

[0108] As shown in Figure 8, the hypervisor 802, VM 804, and device 806 can operate in a normal domain. Furthermore, this device can support a secure domain separated from the normal domain so that processes running in the normal domain cannot access data or instructions associated with the secure domain. Thus, there can also be processes running in the secure domain, such as the secure operating system (OS) 810 and trusted applications 812 running within the secure domain under the control of the secure OS 810. The secure OS 810 and trusted applications 812 run at privilege levels S-EL1 and S-EL0, respectively. A secure monitor process 814 is also provided at privilege level EL3 to manage transitions between the normal domain and the secure domain. The secure monitor process 814 can, for example, manage which areas of the address space are associated with the secure domain or the non-secure domain, and some protective hardware is provided to prevent non-secure processes in the normal domain from accessing data or instructions in the secure area. The secure monitor 814 can also control the execution of reset codes following a warm reset or cold reset. One example of a technique for separating normal and secure domains is the Trustzone® technique provided by ARM® Limited in Cambridge, UK, but other examples can also be used. Providing secure domains as shown in Figure 8 is optional, and other embodiments may not support, for example, a secure monitor 814, a secure OS 810, and a trusted application 812. Normal and secure domains are unrelated to (independent of) reset domains such as warm reset domains and non-warm reset domains.

[0109] Data associated with a higher privilege level (e.g., data modified by a process running at a higher privilege level) may be inaccessible to processes running at a lower privilege level, resulting in, for example, less trusted programs being unable to access sensitive code and data. For instance, it may be desirable to prevent lower-privilege code from accessing branch records generated by branch record circuits while processing circuits are running at a higher privilege level. This is particularly true for branch records generated before and after a warm reset, as reset firmware (e.g., code executed immediately after a reset) typically runs at a higher privilege level. Therefore, it may be useful to provide some mechanism to control whether a process running at a privilege level lower than a given privilege level can access the branch record buffer.

[0110] For example, BREC and BREW values ​​may only be accessible to processes running in EL3, and branch logging may be controlled by some other mechanism at a lower privilege level (e.g., independently of BREC and BREW values). This prevents lower-privilege processes from controlling whether or not information about branches executed in EL3 is stored in the branch logging buffer, thereby improving security.

[0111] Furthermore, processes running on EL0, EL1, or EL2 may be prevented from accessing the branch record buffer. For example, a control value may be provided (e.g., in one of the control registers 136 shown in Figure 1), and the processing circuit may be configured to prevent processes running on EL0, EL1, or EL2 from accessing the branch record buffer when the control value is set to a given value. This also leads to improved security, while at the same time providing the flexibility to allow processes with lower privileges to access the branch record in situations where it is useful and safe to do so. On the other hand, in some implementations, no control value may be provided, and processes running on EL0, EL1, or EL2 may be completely prevented from accessing the branch record.

[0112] Figure 9 is a flowchart illustrating an example of a method for determining whether a currently running process should be allowed to access the branch record. In this method, it is determined whether the currently running process is running at EL3 (S902). If the current exception level is EL3, the processing circuit is allowed to access the branch record (S904). Furthermore, when the processing circuit is running at EL3, it is determined whether to activate the branch record by determining whether the BREC value and BREW value satisfy predetermined conditions (as described above, for example, the predetermined conditions may be BREC!=BREW or BREC==BREW) (S906). If the predetermined conditions are met, the branch record circuit activates the branch record (S908).

[0113] On the other hand, if the current exception level is not EL3 (for example, if the current exception level is a lower exception level such as EL0, EL1, or EL2), the branch recording circuit is configured to determine whether to enable branch recording independently of the BREC and BREW values ​​(for example, based on some other condition) (S910). Furthermore, when not executing in EL3, it is determined whether a given control value in the control register has a first value (S912), and if it has a first value, the processing circuit is prevented from accessing the branch recording (S914). On the other hand, if the control value has a different value (for example, a second value), processing is not prevented from accessing the branch recording buffer (for example, the processing circuit is allowed to access the branch recording buffer). The control value is accessible to code operating in EL3 but not to code operating in lower privileged exception levels, and as a result, updating a given control value is limited to instructions executed in EL3.

[0114] In this application, the term "configured to..." is used to mean that an element of the device has a configuration that enables it to perform a defined operation. In this context, "configuration" means the arrangement or interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to..." does not mean that any modifications must be made to the device element in order to provide the defined operation.

[0115] While exemplary embodiments of the present invention are described in detail herein with reference to the accompanying drawings, it will be understood that the present invention is not limited to these exact embodiments, and that various changes and modifications can be made to the embodiments without departing from the scope of the present invention as defined by the appended claims.

Claims

1. It is a device, A processing circuit that processes instructions, A reset circuit that performs a cold reset by resetting the processing circuit in response to a cold reset trigger event, and performs a warm reset by resetting a subset of states that are reset in response to the cold reset trigger event in response to a warm reset trigger event, The system includes a branch recording circuit that performs branch recording and stores information about the processed branch instruction in a branch recording storage circuit, The aforementioned branch recording circuit is Determine whether the worm branch record configuration value and the cold branch record configuration value held in at least one register satisfy predetermined conditions. The system is configured to activate the branch record when the warm branch record configuration value and the cold branch record configuration value satisfy the predetermined conditions. The branch recording and storage circuit is configured to make the information relating to the processed branch instruction available for diagnostic analysis. The cold reset includes resetting both the warm branch record configuration value and the cold branch record configuration value, and the warm reset includes resetting the warm branch record configuration value and leaving the cold branch record configuration value unchanged. The device wherein the worm branch record configuration value is a control value configured to be reset in response to both the worm reset and the cold reset, and the cold branch record configuration value is a control value configured to be reset in response to the cold reset but not in response to the worm reset.

2. The apparatus according to claim 1, wherein the branch recording circuit is configured to determine whether the worm branch recording configuration value and the cold branch recording configuration value held in the at least one register satisfy the predetermined conditions based on a comparison between the worm branch recording configuration value and the cold branch recording configuration value.

3. The aforementioned predetermined conditions are: The warm branch recording configuration value and the cold branch recording configuration value are equal, The apparatus according to claim 1 or 2, comprising one of the following: the warm branch recording configuration value and the cold branch recording configuration value are different.

4. The at least one register can be configured by software to set the worm branch record configuration value and the cold branch record configuration value to one of a plurality of states. The apparatus according to claim 1, wherein the worm branch record configuration value has one of a worm configuration value and a worm reset value, and both the worm reset and the cold reset include resetting the worm branch record configuration value to the worm reset value.

5. The apparatus according to claim 4, wherein the plurality of states include a reset start state, and the branch recording circuit responds to the warm branch recording configuration value and the cold branch recording configuration value indicating the reset start state in response to the reset circuit performing the warm reset, in order to activate the branch recording.

6. The reset start state is indicated by the worm branch record configuration value having the worm configuration value and the cold branch record configuration value having a first value. The branch recording circuit is configured to determine that the predetermined conditions are met when the worm branch recording configuration value has the worm reset value and the cold branch recording configuration value has the first value. The apparatus according to claim 5, wherein the branch recording circuit is configured to determine that the predetermined condition is not met when the worm branch recording configuration value has the worm configuration value and the cold branch recording configuration value has the first value.

7. The apparatus according to any one of claims 4 to 6, wherein the plurality of states include a reset stop state, and the branch recording circuit invalidates the branch recording in response to the warm branch recording configuration value and the cold branch recording configuration value indicating the reset stop state, and the reset circuit performs the warm reset.

8. The reset stop state is indicated by the worm branch record configuration value having the worm configuration value and the cold branch record configuration value having a second value. The branch recording circuit is configured to determine that the predetermined conditions are met when the worm branch recording configuration value has the worm configuration value and the cold branch recording configuration value has the second value. The apparatus according to claim 7, wherein the branch recording circuit is configured to determine that the predetermined condition is not met when the worm branch recording configuration value has the worm reset value and the cold branch recording configuration value has the second value.

9. The apparatus according to any one of claims 4 to 6, wherein the plurality of states include a recording state via reset, and the branch recording circuit responds to the warm branch recording configuration value and the cold branch recording configuration value indicating the recording state via reset in order to enable the branch recording both before and after the reset circuit performs the warm reset.

10. The recording state via the reset is indicated by the worm branch recording configuration value having the worm reset value and the cold branch recording configuration value having the first value. The apparatus according to claim 9, wherein the branch recording circuit is configured to determine that the predetermined condition is met when the worm branch recording configuration value has the worm reset value and the cold branch recording configuration value has the first value.

11. The cold branch record configuration value has one of a cold configuration value and a cold reset value, and the cold reset includes resetting the cold branch record configuration value to the cold reset value. The apparatus according to any one of claims 4 to 6, wherein the branch recording circuit is configured to determine that the predetermined condition is not met when the worm branch recording configuration value has the worm reset value and the cold branch recording configuration value has the cold reset value.

12. The apparatus according to any one of claims 4 to 6, wherein in response to the cold reset trigger event, the reset circuit is configured to reset the cold branch record configuration value to one of a first value and a second value specified by a reset value selection signal.

13. The apparatus according to claim 1 or 2, wherein the processing circuit prevents the branch recording storage circuit from being accessed while the processing circuit is operating at a privileged execution level lower than a given execution level, in response to a control value held in a control register having a first value.

14. The apparatus according to claim 1 or 2, wherein the branch recording circuit determines whether to enable the branch recording based on the warm branch recording configuration value and the cold branch recording configuration value in response to the processing circuit operating at a given execution level, and determines whether to enable or disable the branch recording independently of the warm branch recording configuration value and the cold branch recording configuration value in response to the processing circuit operating at a privilege execution level lower than the given execution level.

15. The apparatus according to claim 1 or 2, wherein the information relating to the processed branch instruction includes information that enables the program flow of the processed instruction to be reconstructed.

16. The information relating to the processed branch instruction is, The instruction address of the instruction to which the processed branch was taken, The apparatus according to claim 1 or 2, comprising at least one of the following: the target address of the instruction from which the processed branch was taken.

17. The branch recording and storage circuit records the information relating to the processed branch instruction. External diagnostic hardware and The apparatus according to claim 1 or 2, configured to be available for at least one of the diagnostic processes performed on the processing circuit.

18. The apparatus according to claim 1 or 2, wherein both the warm branch record configuration value and the cold branch record configuration value are stored in the same register.

19. The apparatus according to claim 1 or 2, wherein the reset circuit prevents the reset of the branch recording storage circuit in response to the warm reset trigger event.

20. The apparatus according to claim 1 or 2, wherein the cold reset trigger event includes a power-on event.

21. The apparatus according to claim 1 or 2, wherein the warm reset trigger event includes a timeout signal generated in response to the elapsed time of the watchdog counter.

22. The apparatus according to claim 1 or 2, wherein the reset circuit resets a different subset of the states that are reset in response to a cold reset trigger event, in response to each of a plurality of different warm reset trigger events.

23. It is a method, Processing instructions on a processing circuit, A cold reset is performed by resetting the processing circuit in response to a cold reset trigger event. Performing a warm reset in response to a warm reset trigger event by resetting a subset of states that are reset in response to a cold reset trigger event, Determine whether the warm branch record configuration value and the cold branch record configuration value held in at least one register satisfy predetermined conditions, A method for activating a branch record when the warm branch record configuration value and the cold branch record configuration value satisfy the predetermined conditions, wherein the branch record includes storing information about the processed branch instruction in a branch record storage circuit. The method includes making the information relating to the processed branch instruction available for diagnostic analysis, The cold reset includes resetting both the warm branch record configuration value and the cold branch record configuration value, and the warm reset includes resetting the warm branch record configuration value and leaving the cold branch record configuration value unchanged. The method wherein the worm branch record configuration value is a control value that is reset in response to both the worm reset and the cold reset, and the cold branch record configuration value is a control value that is reset in response to the cold reset but not in response to the worm reset.

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