Gate drive circuit

Abstract

In this gate drive circuit (101), a first switch (121) turns a driven element (1) on when a gate drive signal (GDS) has a first logical value. A second switch (122) turns the driven element (1) off when the gate drive signal (GDS) has a second logic value. A diode (108) is connected between the second switch (122) and a reference node (103). A first electrode of a capacitor (109) is connected to a connection node connecting the second switch (122) and the diode (108). A reference potential (VSS) is applied to the second electrode of the capacitor (109) after the charge in the gate terminal (4) of the driven element (1) is discharged after the gate drive signal (GDS) switches from the first logic value to the second logic value, and a positive potential (VCC) is applied to the second electrode of the capacitor (109) before the gate drive signal switches from the second logic value to the first logic value.

Description

[Technical Field]

[0001] This disclosure relates to a gate drive circuit, and more particularly to a gate drive circuit used to drive a power semiconductor device. [Background technology]

[0002] Power semiconductor devices include types such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors). These power semiconductor devices are used in semiconductor devices such as inverters. In inverters, multiple power semiconductor devices are connected in series. In the simplest case, two power semiconductor devices are connected in series and switched on and off alternately to raise and lower the potential at the connection point of these devices.

[0003] To turn on a power semiconductor device, a positive voltage is applied to the gate terminal of the power semiconductor device. To turn off a power semiconductor device, a zero or negative voltage is applied to the gate terminal of the power semiconductor device. A gate drive circuit is a device for applying these voltages to a power semiconductor device, i.e., a driven element.

[0004] Each of the power semiconductor devices connected in series is called an arm. The arms, connected vertically, are controlled to turn on alternately, that is, not simultaneously, so that when one is on, the other is off. Focusing on one arm, the other arm (hereinafter referred to as the counter arm) is on only when that arm (hereinafter referred to as the self arm) is off. The moment a power semiconductor device turns on is called turn-on, and the moment a power semiconductor device turns off is called turn-off.

[0005] If both the upper and lower arms are turned on simultaneously, the power supply voltage will be short-circuited through both arms. In this case, a large current will flow through both arms, and the resulting heat can destroy the power semiconductor devices.

[0006] When the local arm is off and the opposing arm turns on, the voltage at the connection point of the upper and lower arms fluctuates rapidly, causing a voltage to be rapidly applied to the local arm's power semiconductor device. For example, in the case of a MOSFET, a voltage is rapidly applied between the drain and source terminals. This is due to the operation of the opposing arm, and the local arm must remain off at that moment.

[0007] Generally, when a voltage is rapidly applied to a power semiconductor device, a phenomenon occurs where the voltage at the gate terminal is raised. For example, in the case of a MOSFET, a current flows from the drain terminal to the gate terminal to charge the parasitic capacitance between the drain terminal and the gate terminal, and this current flows through the resistor connected to the gate terminal (gate resistor). As a result, a potential difference is generated across the gate resistor, and the potential at the gate terminal rises.

[0008] If the gate drive unit has poor ability to maintain a low voltage at the gate terminal, the gate voltage will rise too high and exceed the gate threshold voltage required to turn on the power semiconductor device. As a result, both the power semiconductor devices on the arm and the opposing arm will turn on, which can lead to a power short circuit and ultimately the destruction of the power semiconductor devices.

[0009] The phenomenon in which an arm turns on incorrectly when the opposing arm turns on is called a false turn-on phenomenon. To prevent false turn-on, methods such as reducing the resistance value of the gate resistor, increasing the apparent gate capacitance by installing an additional capacitance between the gate terminal and the source terminal, or applying a negative voltage to the gate terminal can be used. However, reducing the resistance value of the gate resistor may increase the switching speed and thus increase electromagnetic noise. Increasing the gate capacitance increases the load on the gate drive circuit and generates more heat.

[0010] Therefore, a common method is to make the gate voltage negative when the gate is off, i.e., to apply a negative bias. Applying a negative bias generally requires a negative power supply. However, since this requires another power supply in addition to the positive power supply used to turn the gate on, using this negative power supply increases the circuit size and cost. To avoid these problems, a method of generating a negative bias using only a positive power supply is known.

[0011] For example, in the drive circuit disclosed in Figure 2 of Japanese Patent Publication No. 2004-159424 (Patent Document 1), a capacitor for generating a negative bias is provided. This capacitor is pre-charged when the MOSFET, which is the driven element, is turned on, and is connected in reverse polarity between the gate terminal and source terminal of the driven element when the driven element is turned off.

[0012] Japanese Patent Publication No. 2013-201883 (Patent Document 2) also shows a negative bias generation circuit similar to that of Patent Document 1. In particular, in the drive circuit shown in Figure 20 of this document, the capacitor for generating the negative bias is connected between the gate terminal and source terminal of the MOSFET for a certain period of time after the MOSFET is turned off. [Prior art documents] [Patent Documents]

[0013] [Patent Document 1] Japanese Patent Publication No. 2004-159424 [Patent Document 2] Japanese Patent Publication No. 2013-201883 [Overview of the Initiative] [Problems that the invention aims to solve]

[0014] In the conventional technology described above, the capacitor connection is switched during turn-off, causing the negative charge accumulated on one electrode of the capacitor to be canceled out by the positive charge accumulated at the gate terminal of the driven element. This results in the problem that a sufficient negative bias cannot be applied to the gate terminal of the driven element. This problem is particularly pronounced when the gate capacitance of the driven element is large. Increasing the capacitance of the capacitor used to generate the negative bias can suppress the effect of charge cancellation, but this increases the circuit size and costs.

[0015] This disclosure was made to solve the above-mentioned problems, and its purpose is to provide a gate drive circuit that can apply the necessary negative bias to the gate with a capacitor of minimum capacity. [Means for solving the problem]

[0016] In one embodiment, a gate drive circuit is provided that drives a driven element based on a gate drive signal. The gate drive circuit comprises a first switch, a second switch, a diode, a capacitor, a potential switching circuit, and a signal generation circuit. The first switch is connected between a power supply node to which a positive potential is applied and the gate terminal of the driven element, and turns the driven element ON by conducting when the gate drive signal is a first logic value. The second switch is connected between a reference node to which a reference potential is applied and the gate terminal of the driven element, and turns the driven element OFF by conducting when the gate drive signal is a second logic value. The diode is connected between the second switch and the reference node so that the reference node is on the cathode side. The first electrode of the capacitor is connected to the connection node between the second switch and the diode. The potential switching circuit applies a reference potential to the second electrode of the capacitor when the control signal is enabled, and applies a positive potential to the second electrode of the capacitor when the control signal is disabled. The signal generation circuit generates the control signal based on the gate drive signal. The signal generation circuit activates the control signal after the gate drive signal switches from the first logic value to the second logic value and the charge at the gate terminal of the driven element has been discharged, and deactivates the control signal before the gate drive signal switches from the second logic value to the first logic value. [Effects of the Invention]

[0017] According to the gate drive circuit of the above embodiment, the control signal for activating the negative bias is activated after the gate drive signal switches from the first logic value to the second logic value and the charge at the gate terminal of the driven element has been discharged, and the control signal is deactivated before the gate drive signal switches from the second logic value to the first logic value. This makes it possible to provide a gate drive circuit that can apply the necessary negative bias to the gate with a capacitor of minimum capacity. [Brief explanation of the drawing]

[0018] [Figure 1] This is a circuit diagram showing an example of the configuration of a gate drive circuit according to Embodiment 1. [Figure 2]Figure 1 is a timing diagram showing the operation of the gate drive circuit. [Figure 3] This is a schematic circuit diagram conceptually showing the charge status of the capacitor and the gate capacitance immediately after the second electrode of the capacitor is connected to a reference potential. [Figure 4] This figure shows the actual time change of the gate voltage after the driven element has been turned off. [Figure 5] This timing diagram shows the operation of the gate drive circuit in Figure 1 when the on-pulse width of the gate drive signal is very short. [Figure 6] This is a timing diagram showing the operation of a modified version of the gate drive circuit in Figure 1. [Figure 7] This is a circuit diagram showing an example of the configuration of a gate drive circuit according to Embodiment 2. [Figure 8] Figure 7 is a timing diagram showing the operation of the gate drive circuit. [Figure 9] This is a circuit diagram showing an example configuration of the gate drive circuit of Embodiment 3. [Figure 10] This is a circuit diagram showing an example configuration of the gate drive circuit of Embodiment 4. [Modes for carrying out the invention]

[0019] Each embodiment will be described in detail below with reference to the drawings. Note that the same or corresponding parts will be denoted by the same reference numerals, and their descriptions will not be repeated.

[0020] Embodiment 1. [Configuration of the gate drive circuit] Figure 1 is a circuit diagram showing an example of the configuration of a gate drive circuit according to Embodiment 1. In Figure 1, the driven element 1 is a MOSFET.

[0021] The driven element 1 has a drain terminal 2 as a first main terminal, a source terminal 3 as a second main terminal, and a gate terminal 4 as a control terminal. The gate voltage applied to the gate terminal 4 controls the on / off state of the main current flowing between the first and second main terminals. In the example in Figure 1, the driven element 1 also has a source reference terminal 5 between the source electrode and the source terminal 3 to obtain the source potential.

[0022] A parasitic gate capacitance 6 exists between the gate and source of the driven element 1. Although the gate capacitance does not exist as a physical component, it is virtually represented in Figure 1 by a dotted line, as if it were connected.

[0023] The gate drive circuit 101 is connected to the gate terminal 4 and source terminal 3 of the driven element 1. In the example in Figure 1, instead of source terminal 3, it is connected to source reference terminal 5, which is provided between the source electrode and source terminal 3 of the driven element 1. The gate drive circuit 101 has a positive potential V from a positive power supply inside. CC Power node 102 and reference potential V are provided. SS It has a reference node 103 to which the reference potential V is given. SS This is equal to the potential of source reference terminal 5.

[0024] The gate drive circuit 101 is driven by the gate drive signal GDS input to the signal input terminal 104. The gate drive circuit 101 has a mechanism to switch whether to connect the gate terminal 4 of the driven element 1 to the positive potential side or to the reference potential side according to the input gate drive signal GDS.

[0025] Specifically, in the example shown in Figure 1, the gate drive circuit 101 includes a turn-on gate resistor 106 and a switch 121 (first switch) connected in series between the gate terminal 4 and the power supply node 102 to switch the gate terminal 4 to the positive potential side. The gate drive circuit 101 also includes a turn-off gate resistor 107 and a switch 122 (second switch) connected in series between the gate terminal 4 and the reference node 103 to connect the gate terminal 4 to the reference potential side. In the example shown in Figure 1, switch 121 is a P-channel MOSFET and switch 122 is an N-channel MOSFET. The gate resistor 106 is connected closer to the gate terminal 4 than switch 121, and the gate resistor 107 is connected closer to the gate terminal 4 than switch 122.

[0026] Furthermore, the gate drive circuit 101 includes a non-inverting buffer 105 for driving the gate terminals of switch 121 and switch 122 in accordance with the gate drive signal GDS. The gate drive signal GDS input to the signal input terminal 104 is input to the non-inverting buffer 105.

[0027] Furthermore, the gate drive circuit 101 includes a diode 108, a capacitor 109, a potential switching circuit 201, a non-inverting buffer 110, and a signal generation circuit 301 as a mechanism for inputting a negative potential to the gate terminal 4 of the driven element 1.

[0028] Diode 108 is connected between switch 122 and reference node 103, with the anode of diode 108 facing switch 122 and the cathode of diode 108 facing reference node 103.

[0029] The first electrode 109A of capacitor 109 is connected to the connection point between switch 122 and diode 108. The second electrode 109B of capacitor 109 is connected to potential switching circuit 201.

[0030] The potential switching circuit 201 includes a pull-up resistor 202 and a switch 203 (a third switch). In this example, the switch 203 is an N-channel MOSFET. The first end of the pull-up resistor 202 is connected to the power node 102, and the second end of the pull-up resistor 202 is connected to both the second electrode 109B of the capacitor 109 and the drain terminal of the switch 203. The source terminal of the switch 203 is connected to the reference node 103. The gate terminal of the switch 203 is driven by the non-inverting buffer 110.

[0031] The signal generation circuit 301 receives the gate drive signal input to the signal input terminal 104 as input and outputs a control signal to drive the non-inverting buffer 110. When a high-level control signal is output from the signal generation circuit 301 to the non-inverting buffer 110, the switch 203 is turned on, thereby enabling the negative bias of the gate terminal 4 of the driven element 1. When a low-level control signal is output from the signal generation circuit 301 to the non-inverting buffer 110, the switch 203 is turned off, thereby disabling the negative bias of the gate terminal 4 of the driven element 1. In the above case, the high-level control signal is also referred to as the enabled control signal, and the low-level control signal is also referred to as the disabled control signal.

[0032] The signal generation circuit 301 includes a first delay circuit 320, a logic operation circuit 306, and a second delay circuit 321.

[0033] The first delay circuit 320 receives a negative logic gate drive signal GDS as input. The first delay circuit 320 generates a first delayed signal by delaying the turn-off edge (i.e., rising edge) of the input negative logic gate drive signal GDS without delaying the turn-on edge (i.e., falling edge). Furthermore, the first delay circuit 320 outputs a signal obtained by inverting the logic value of the first delayed signal.

[0034] More specifically, as shown in Figure 1, the first delay circuit 320 includes a low-pass filter (also called an RC filter) consisting of a resistor 303 and a capacitor 304, a diode 302, and a Schmitt trigger inverter 305. The resistor 303 and capacitor 304 are connected in series between the signal input terminal 104 and the reference node 103 in this order. The diode 302 is connected in parallel with the resistor 303. The anode terminal of the diode 302 is connected to node B, which is the connection node between the resistor 303 and the capacitor 304. As a result, the RC filter functions as a unidirectional RC filter that delays only the rising edge of the gate drive signal GDS. The signal that has passed through the RC filter is input to the Schmitt trigger inverter 305. The Schmitt trigger inverter 305 shapes the input signal and inverts its logic value.

[0035] The logic circuit 306 calculates the logical AND of the inverted signal of the first delay signal output from the first delay circuit 320 and the gate drive signal GDS. In the example in Figure 1, a NAND (Not AND) circuit is used as the logic circuit 306, so the logic circuit 306 outputs the result of the logical AND calculation inverted. The logic circuit 306 may also calculate the logical OR of the first delay signal and the inverted signal of the gate drive signal GDS, and the logical calculation result will be the same.

[0036] The output signal of the logic circuit 306 is input to the second delay circuit 321. The second delay circuit 321 delays the output signal of the logic circuit 306 (i.e., both the rising edge and the falling edge). The delayed signal output from the second delay circuit 321 is input to the non-inverting buffer 110. This generates a control signal for controlling the potential switching circuit 201.

[0037] More specifically, as shown in Figure 1, the second delay circuit 321 includes a low-pass filter (also called an RC filter) composed of a resistor 307 and a capacitor 308, and a Schmitt trigger inverter 309. The resistor 307 and capacitor 308 are connected in series in this order between the output node D of the logic circuit 306 and the reference node 103. The signal that has passed through the RC filter is input to the Schmitt trigger inverter 309. The Schmitt trigger inverter 309 shapes the input signal and inverts its logic value.

[0038] [Operation of the gate drive circuit] Next, the operation of the gate drive circuit 101 in Figure 1, and in particular the operation of the signal generation circuit 301, will be described.

[0039] Figure 2 is a timing diagram showing the operation of the gate drive circuit 101 in Figure 1. In Figure 2, the signal waveforms of nodes A to F in Figure 1 and the gate voltage V of the driven element 1 are shown. G The waveform is shown. The following will explain it in order.

[0040] The signal at node A is the gate drive signal GDS, which is input to the gate terminals of switch 121 (P-channel MOSFET) and switch 122 (N-channel MOSFET) via the non-inverting buffer 105. Switches 121 and 122 constitute a complementary MOS (CMOS: Complementary Metal-Oxide-Semiconductor).

[0041] When the gate drive signal GDS is at a high level, switch 122 is turned on, connecting the gate terminal 4 of the driven element 1 to the reference node 103. This turns the driven element 1 off. On the other hand, when the gate drive signal GDS is at a low level, switch 121 is turned on, connecting the gate terminal 4 of the driven element 1 to the power node 102. This turns the driven element 1 on. Therefore, the gate drive signal GDS is negative logic.

[0042] The time t1 when the gate drive signal GDS switches from a high level to a low level (i.e., the falling edge of the gate drive signal GDS) corresponds to the turn-on edge. The time t3 when the gate drive signal GDS switches from a low level to a high level (i.e., the rising edge of the gate drive signal GDS) corresponds to the turn-off edge.

[0043] The signal at node B represents the signal output from the unidirectional RC filter of the first delay circuit 320, which is formed when the signal at node A (i.e., the gate drive signal GDS) is input to this unidirectional RC filter.

[0044] Generally, a low-pass filter composed of a resistor and a capacitor cuts out the high-frequency components of an input signal and allows the low-frequency components to pass through. As a result, the signal that passes through the low-pass filter has a shape with blunted edges. However, in the low-pass filter of the first delay circuit 320 in Figure 1, the diode 302 is connected in parallel with the resistor 303. The cathode of the diode 302 is connected to the input side of the low-pass filter, and the anode of the diode 302 is connected to the output side of the low-pass filter. Therefore, when the input signal rises, the diode is closed and the low-pass filter becomes effective. Conversely, when the input signal falls, the diode becomes conductive and the voltage across the capacitor 304 drops rapidly. Thus, the RC filter of the first delay circuit 320 functions as a unidirectional filter that is effective only when the input signal is rising.

[0045] Specifically, at time t1, which is the falling edge (i.e., turn-on edge) of the gate drive signal GDS, the output signal of the unidirectional RC filter (i.e., the signal at node B) falls rapidly. On the other hand, at time t3, which is the rising edge (i.e., turn-off edge) of the gate drive signal GDS, the output signal of the unidirectional RC filter (i.e., the signal at node B) rises slowly.

[0046] The signal at node C represents the signal output from the Schmitt trigger inverter 305, which is formed when the signal at node B (i.e., the output signal of the unidirectional RC filter) is input to the Schmitt trigger inverter 305.

[0047] Generally, a Schmitt trigger element is an element that has hysteresis in its input threshold voltage. However, in the first delay circuit 320, a Schmitt trigger inverter 305 is used, so the output signal is the inverted logic value of the input signal.

[0048] Specifically, if the input signal to the Schmitt trigger inverter 305 (i.e., the signal at node B) falls at time t1 in Figure 2, the Schmitt trigger inverter 305 outputs an inverted signal of the input signal only after the input signal has fallen considerably below the midpoint potential. Since the signal at node B falls sharply at time t1, the output signal of the Schmitt trigger inverter 305 rises at time t2 with almost no delay from time t1.

[0049] On the other hand, if the input signal to the Schmitt trigger inverter 305 (i.e., the signal at node B) rises at time t3, the Schmitt trigger inverter 305 outputs an inverted signal of the input signal only after the input signal has risen considerably above the midpoint potential. Since the signal at node B rises slowly at time t3, the output signal of the Schmitt trigger inverter 305 falls at time t5, which is significantly delayed from time t3.

[0050] As described above, when a waveform with only the rising edge of the signal slowed down is input to the Schmitt trigger inverter 305, the Schmitt trigger inverter 305 outputs an inverted signal in which only the rising edge of the input signal is significantly delayed.

[0051] The signal at node D represents the output signal of the NAND gate, which functions as the logic circuit 306. As shown in Figure 1, the NAND gate 306 outputs a signal that is the inverted logical AND of the signal at node A (i.e., the gate drive signal GDS) and the signal at node C (i.e., the output signal of the Schmitt trigger inverter 305).

[0052] In Figure 2, the logical AND of the signal at node A and the signal at node C is true only for a certain period T from the turn-off edge (for example, from time t3 to time t5 in Figure 2), and false for the rest of the period. Therefore, the signal at node D (i.e., the output signal of the NAND gate 306) is at the reference potential only for a certain period T from the turn-off edge, and is at the positive potential for the rest of the period.

[0053] The signal at node E represents the signal output from an RC filter, which is formed by inputting the signal at node D into a filter consisting of resistor 307 and capacitor 308. Since no diode is connected to resistor 307 in this RC filter, the signal waveform at node D has blunted rising and falling edges.

[0054] The signal at node F represents the signal output from the Schmitt trigger inverter 309, which is formed when the signal at node E (i.e., the output signal of the RC filter) is input to the Schmitt trigger inverter 309. As shown in Figure 2, the signal at node F is obtained by delaying both the rising and falling edges of the signal at node D and then inverting its logical value. Specifically, the signal at node F goes from a low level to a high level at time t4, a certain time after the turn-off edge at time t3, and then returns from a high level to a low level at time t6.

[0055] The signal generation circuit 301 inputs the signal from node F to the gate terminal of switch 203 of the potential switching circuit 201 via the non-inverting buffer 110 as a control signal to activate the negative bias. Therefore, switch 203 conducts during the period when the signal from node F is high (from time t4 to t6) within the period when the gate drive signal GDS is high (from time t3 to time t7). Switch 203 is non-conducting during the rest of the period.

[0056] As described above, the first electrode 109A of the capacitor 109 is connected to the connection point between the switch 122 for off-drive and the diode 108. The second electrode 109B of the capacitor 109 is connected to the power node 102 via the pull-up resistor 202 and also to the reference node 103 via the switch 203.

[0057] Therefore, during the period when switch 203 is not conducting, current flows in the following order: power node 102, pull-up resistor 202, capacitor 109, diode 108, and reference node 103, charging capacitor 109 such that its second electrode 109B is positive and its first electrode 109A is negative. On the other hand, during the period when switch 203 is conducting, the second electrode 109B of capacitor 109 is connected to the reference node 103 via switch 203, so the source terminal of switch 122, which is connected to the first electrode 109A of capacitor 109, is at the reference potential V SS It is biased to a negative potential.

[0058] The operation of the signal generation circuit 301 and the potential switching circuit 201 described above results in the gate voltage waveform shown in the bottom row of Figure 2.

[0059] Specifically, from the turn-on edge at time t1 to the turn-off edge at time t3 in Figure 2, the switch 121 of the gate drive circuit 101 conducts, thereby applying a positive potential to the gate terminal 4 of the driven element 1.

[0060] During the period from the turn-off edge at time t3 to time t4, switch 121 of the gate drive circuit 101 becomes non-conductive and switch 122 becomes conductive, causing the charge accumulated at the gate terminal 4 of the driven element 1 to discharge through the gate resistor, switch 122, and forward diode 108. As a result, the gate terminal 4 of the driven element 1 changes from positive potential to reference potential. During this period, since the signal at node F is low level, switch 203 of the potential switching circuit 201 is non-conductive. Therefore, the first electrode 109A of capacitor 109 is at the reference potential V via diode 108. SS It is maintained at the same potential.

[0061] During the period from time t4 to time t6, the signal at node F becomes high level, causing switch 203 of the potential switching circuit 201 to conduct. As a result, the second electrode 109B of capacitor 109 is connected to the reference node 103 via switch 203. Consequently, the first electrode 109A of capacitor 109 becomes negatively biased, and the gate terminal 4 of the driven element 1, which is connected to the first electrode 109A of capacitor 109 via the conducting switch 122 and gate resistor, also becomes negatively biased. That is, the potential of gate terminal 4 changes from the reference potential to a negative potential. Note that diode 108 is non-conducting because a voltage is applied in the reverse direction. By turning on the driving element of the opposing arm during this negative bias application period from time t4 to time t6, misfiring of the arm is prevented.

[0062] During the period from the next time t6 to the turn-on edge at time t7, the signal at node F becomes low level, and the switch 203 of the potential switching circuit 201 becomes non-conductive. As a result, the second electrode 109B of capacitor 109 is disconnected from the reference node 103 and reconnected to the power node 102. As a result, the first electrode 109A of capacitor 109 is connected to the reference node 103 via the forward diode 108. The gate terminal 4 of the driven element 1, which is connected to the first electrode 109A of capacitor 109 via the conductive switch 122 and gate resistor, also becomes the reference potential. Thereafter, the above voltage change is repeated.

[0063] [Effect of Embodiment 1] According to the configuration and operation of the gate drive circuit 101 described above, even if a capacitor 109 with a minimum capacitance is used, false arcing of the driven element 1 can be prevented. The reason for this will be specifically described below.

[0064] FIG. 3 is a circuit schematic diagram conceptually showing the charging status of the capacitor 109 and the charging status of the gate capacitance 6 immediately after the second electrode 109B of the capacitor 109 is connected to the reference potential.

[0065] FIG. 3(A) shows the charging status of the capacitor 109 and the gate capacitance 6 in the case of the comparative example. In the case of the comparative example, the capacitor 109 for generating a negative bias is connected to the gate capacitance 6 of the driven element 1 immediately after the driven element 1 is turned off. That is, from the state where the driven element 1 is on and positive charge is accumulated in the gate terminal 4, the gate terminal 4 is disconnected from the power supply node 102 and at the same time the capacitor 109 for generating a negative bias is connected to the gate capacitance 6.

[0066] In this case, the negative charge accumulated in the first electrode 109A of the capacitor 109 for generating a negative bias cancels out the positive charge accumulated in the gate terminal 4. As a result, the potential of the gate terminal 4 does not become sufficiently low. That is, the effect of the negative bias is reduced.

[0067] For example, assume that the gate capacitance C GS is equal to the capacitance C1 of the capacitor 109. Before the gate capacitance 6 and the capacitor 109 are connected, assume that both the gate capacitance 6 and the capacitor 109 are charged by the positive potential V CC . In this case, when the gate capacitance 6 and the capacitor 109 are connected, the charges completely cancel each other out. As a result, the gate potential after the capacitor 109 for generating a negative bias is connected is zero, that is, the reference potential V SSThis would result in the same value, and would not be negative. In order to apply a sufficient negative bias to gate terminal 4, the capacitance C1 of capacitor 109 would need to be sufficiently large, which leads to an increase in circuit size and cost.

[0068] Figure 3(B) shows the charge status of capacitor 109 and gate capacitance 6 in this embodiment. In this embodiment, the drawbacks of the comparative example described above can be resolved.

[0069] Specifically, as explained above, when the driven element 1 is turned off, the gate terminal 4 is temporarily connected to the reference node 103. As a result, the charge stored in the gate capacitance 6 is discharged, and the voltage at the gate terminal 4 becomes zero. Subsequently, the capacitor 109 for generating the negative bias is connected between the gate terminal 4 and the reference node 103 with reverse polarity. This situation is shown in Figure 3(B).

[0070] As shown in Figure 3(B), when the charge connected to the gate capacitance 6 becomes zero, the capacitor 109 for generating the negative bias is connected between the gate terminal 4 and the reference node 103. Therefore, some of the negative charge accumulated on the first electrode 109A of the capacitor 109 is transferred to the gate terminal 4, and the remaining negative charge remains on the first electrode 109A of the capacitor 109. Thus, unlike the comparative example in Figure 3(A), the negative charge on the first electrode 109A of the capacitor 109 is not canceled out by the positive charge on the gate terminal 4. As a result, it is not necessary to increase the capacitance C1 of the capacitor 109 for generating the negative bias.

[0071] Thus, in the gate drive circuit 101 of this embodiment, the capacitance of the negative bias generation capacitor 109 can be made smaller than in conventional designs. Next, we will explain how much the capacitance C1 of the capacitor 109 can be reduced.

[0072] In the following explanation, the gate capacitance of the driven element 1 is C. GS Let C1 be the capacitance of the capacitor used to generate the negative bias, and let V be the gate power supply voltage. CCThe turn-on threshold of the driven element 1 is set to V TH In the case where a capacitor 109 for generating a negative bias is not provided, i.e., when a negative bias is not applied to the gate terminal 4, the peak value of the surge voltage generated at the gate terminal of the arm when the opposing arm turns on is V. SURGE Let's assume that.

[0073] The peak value V of the surge voltage generated at the gate terminal of the arm when the opposing arm is turned on. SURGE However, the turn-on threshold V of the driven element 1 of the arm TH If it exceeds this value, the arm will misfire. As a result, the driven elements of the arm may be damaged. Therefore, the peak value of the surge voltage V SURGE The turn-on threshold V TH A negative bias should be applied to gate terminal 4 as follows:

[0074] In this embodiment, the gate capacitance C GS Once discharged, the capacitor 109 for generating the negative bias has gate capacitance C GS This is connected to the capacitor 109 used for generating the negative bias. As a result, the charge Q1 stored in the capacitor 109 is connected to the gate capacitance C. GS It will be divided proportionally between them.

[0075] First, if we let the capacitance of capacitor 109 be C1, then the above charge Q1 is: Q1 = C1 × V CC …(1) It is represented as follows.

[0076] Capacitor 109 has gate capacitance C GS After connecting, the charge distributed between the two is the charge between capacitance C1 and capacitance C GS This is the capacitance ratio. Therefore, the charge Q1 remaining in the capacitor 109 with capacitance C1 R teeth, Q1 R =C1 / (C1+C GS )×Q1 =C1 / (C1+C GS ) × C1 × V CC =C1 2 / (C1+C GS )×V CC …(2) It is represented as follows.

[0077] Similarly, from capacitor 109 to gate capacitance C GS Charge Q that transitions to G R teeth, Q G R =C GS / (C1+C GS )×Q1 =C GS / (C1+C GS ) × C1 × V CC =C1×C GS / (C1+C GS )×V CC …(3) It is represented as follows.

[0078] Therefore, capacitor 109 has a gate capacitance C GS After connecting, the absolute value of the potential difference across capacitor 109 is |V C1 R | is, |V C1 R |=Q1 R / C1 =C1 2 / (C1+C GS )×V CC / C1 =C1 / (C1+C GS )×V CC …(4) It is represented as follows.

[0079] Similarly, capacitor 109 has a gate capacitance C GS After connecting, the gate capacitance C GS The absolute value of the potential difference across the two ends of the wire |V GS R | is, |V GS R |=Q G R / C GS =C1×C GS / (C1 + C GS )×V CC / C GS =C1 / (C1 + C GS )×V CC …(5) is represented by

[0080] Of course, the absolute value of the voltage of capacitor 109, |V C1 R | and the absolute value of the voltage of gate capacitance C GS |V GS R | are equal. This voltage acts as a negative bias. <--[[ID=]]

[0081] To prevent the misfiring of the driven element 1, the peak of the surge voltage should be reduced by the negative bias so that it is below the gate threshold voltage V TH That is, the absolute value of the minimum required voltage as a negative bias is the surge peak V SURGE of the gate voltage of the self-arm when the opposing arm turns on without applying the negative bias, and the gate threshold voltage V TH of the driven element. That is, the absolute value of the potential difference across capacitor 109, |V C1 ((ID=39]]<--[[ID=]] R | only needs to be greater than or equal to this difference, so V SURGE - V TH ≦ |V GS R | = C1 / (C1 + C GS )×V CC …(6) holds.

[0082] When the above equation (6) is transformed, (V SURGE - V TH )×(C1 + C GS ) ≦ C1×V CC (V SURGE - V TH )×C1 + (V SURGE - V TH )×C GS ≦ C1×V CC (V SURGE -V TH ) × C1 - C1 × V CC ≦ -(V SURGE -V TH ) × C GS (V SURGE -V TH -V CC ) × C1 ≦ -(V SURGE -V TH ) × C GS -(V SURGE -V TH -V CC ) × C1 ≧ (V SURGE -V TH ) × C GS C1 ≧ (V SURGE -V TH ) / (V CC -(V SURGE -V TH )) × C GS …(7)<000048​​​​​​​​​​​​​​​​​​​​Specifically, after the own arm turns off at time t10, there is a dead time, and then the opposing arm turns on at time t12. When the opposing arm turns on, a rise occurs in the gate voltage of the own arm, resulting in a surge peak V SURGE The voltage rises up to this point. In the case of the thin solid line waveform in Figure 4, the surge peak V SURGE The gate threshold voltage V TH Because it exceeds the limit, there is a risk that the element may be damaged due to incorrect firing.

[0087] Therefore, between time t11 and time t13, with time t12 being the time when the opposing arm is turned on, the capacitor 109 for generating the negative bias has a gate capacitance C GS By connecting to this, a negative bias is applied to gate terminal 4. In this case, it is important not to unnecessarily increase the capacitance C1 of capacitor 109.

[0088] For example, if the capacitance C1 of capacitor 109 is made extremely large, the power supply voltage V of the gate drive circuit 101 will change as shown by the thick solid line waveform in Figure 4. CC Inverting voltage -V CC The gate voltage V is close to the gate voltage V G This can lower the voltage. However, such a large negative bias is unnecessary. The surge voltage peak is at the gate threshold voltage V. TH This is because even if it falls significantly below the threshold, the effect of preventing false firing remains unchanged. Furthermore, unnecessarily increasing the capacitance C1 of capacitor 109 leads to problems of increased circuit size and higher costs. Moreover, when the driven element is a SiC-MOSFET (silicon carbide MOSFET), it is known that if the negative bias voltage is too high, it puts unnecessary stress on the gate oxide film of the driven element, lowering the gate threshold voltage. Therefore, the magnitude of the negative bias should be kept to the absolute minimum. In this embodiment, as described above, the minimum value of the negative bias voltage was clarified, and the circuit configuration necessary to achieve it was clarified.

[0089] While there are no operational limitations on the upper limit of capacitance C1, as mentioned above, unnecessarily large capacitance leads to increased circuit size and cost, as well as adverse effects on the gate oxide film. One possibility that capacitance C1 may need to be increased to a certain extent is when the gate threshold voltage V TH A decrease in the gate threshold voltage V is possible. TH The gate threshold voltage V may decrease from its initial value due to various factors, in which case it is necessary to increase the capacitance C1 accordingly. However, even considering the worst case, the gate threshold voltage V TH This is a positive value and is greater than 0V.

[0090] In equation (6), V TH If we set = 0, V SURGE ≤C1 / (C1+C GS )×V CC …(8) We obtain this. Rearranging equation (8), C1≧V SURGE / (V CC -V SURGE )×C GS …(9) This is obtained. The right-hand side of equation (9) is the worst case (i.e., V TH The capacitance C1 of capacitor 109 is required when = 0, and there is no need to increase the capacitance C1 any further. Therefore, the right-hand side of equation (9) is the upper limit of capacitance C1. That is, the equation that specifies the upper limit of capacitance C1 is: C1 ≤ V SURGE / (V CC -V SURGE )×C GS …(10) This is obtained. Combining equation (10) with equation (7), V SURGE / (V CC -V SURGE )×C GS ≥C1 ≧(V SURGE -V TH ) / (V CC -(V SURGE -V TH ))×C GS …(11) This is obtained. Equation (11) specifies the upper and lower limits of the capacitance C1 of capacitor 109.

[0091] The dashed waveform in Figure 4 represents the gate voltage V when the capacitance of capacitor 109 for negative bias generation is optimized. G This shows the time evolution.

[0092] Negative bias is minimized, and the surge peak of the gate voltage of the own arm when the opposing arm turns on is V TH It will never exceed that.

[0093] Furthermore, in this embodiment, the gate voltage is temporarily set to 0 before a negative bias is applied when the own arm turns off, thus minimizing the duration for which the negative bias is applied. As mentioned earlier, applying a negative bias to the gate of a SiC-MOSFET puts stress on the gate oxide film, so it is desirable to keep not only the magnitude of the negative bias but also the duration for which it is applied as short as possible. According to this embodiment, the time for which a negative bias is applied to the gate can be limited to a short period that includes the moment when the opposing arm turns on.

[0094] The duration of the negative bias can be controlled by adjusting the time constant of the low-pass filter used to generate the first signal in Figure 1, i.e., the magnitudes of resistor 303 and / or capacitor 304. Furthermore, the time position of the moment when the negative bias begins to be applied can be controlled by adjusting the time constant of the low-pass filter that delays the first signal, i.e., the magnitudes of resistor 307 and / or capacitor 308. By controlling these, the duration of negative bias application can be minimized. This is an effect that could not be achieved with conventional technology.

[0095] [Why a unidirectional RC filter is necessary] The reason why a unidirectional RC filter is used in the first delay circuit 320 of the signal generation circuit 301 will be explained below.

[0096] In this embodiment, the first delay circuit 320 is configured as a unidirectional RC filter that delays only the turn-off edge of the gate drive signal GDS without delaying the turn-on edge. Pa Even with a very short pulse width, a negative bias can be reliably applied to the gate terminal 4 of the driven element 1. A specific example will be provided below.

[0097] Figure 5 is a timing diagram showing the operation of the gate drive circuit 101 in Figure 1 when the on-pulse width of the gate drive signal GDS is very short. The timing diagram in Figure 5 corresponds to the timing diagram in Figure 2, and shows the signal waveforms of nodes A to F in Figure 1 and the gate voltage V of the driven element 1. G The waveforms are shown. The times t1 to t7 in Figure 5 correspond to the times t1 to t7 in Figure 2, respectively.

[0098] As shown in Figure 5, the on-pulse width of the gate drive signal GDS (i.e., the signal at node A) (i.e., from time t1 to time t3) is very short. Even in such a case, a negative bias can be applied to gate terminal 4 between time t4 and time t6 after the turn-off edge at time t3.

[0099] Figure 6 is a timing diagram showing the operation of a modified version of the gate drive circuit 101 in Figure 1. In the modified gate drive circuit, the first delay circuit 320 of the signal generation circuit 301 in Figure 1 is configured so as not to include the diode 302. Therefore, the modified first delay circuit is a bidirectional delay circuit that delays both the turn-on edge and the turn-off edge.

[0100] The timing diagram in Figure 6 shows the signal waveforms of nodes A to F in Figure 1 and the gate voltage V of the driven element 1 when the timing is changed as described above. G The waveforms are shown. In Figure 6, the waveform of the gate drive signal GDS (signal from node A) is the same as in Figure 5.

[0101] The waveform of the signal at node B (i.e., the output signal of the modified first delay circuit) begins to slowly decrease at the turn-on edge of the gate drive signal GDS at time t1. However, because the on-pulse width of the gate drive signal GDS is very short, the signal at node B is quickly and slowly pulled back towards its original high level at the turn-off edge at time t3.

[0102] As a result, the signal at node B does not exceed the operating threshold of the Schmitt trigger inverter 305 of the first delay circuit 320, and therefore the Schmitt trigger inverter 305 does not operate. Consequently, the modified signal generation circuit cannot detect the turn-off edge of the gate drive signal GDS. Therefore, the signal at node C remains at a low (L) level, and consequently, the signals at nodes D and E remain at a high (H) level, and as a result, the signal at node F remains at a low (L) level. Finally, no negative bias is applied to gate terminal 4. This causes false firing.

[0103] To avoid such problems, it is necessary to use a unidirectional filter in the first delay circuit 320 of the signal generation circuit 301 so as to delay only the turn-off edge of the gate drive signal GDS without delaying the turn-on edge.

[0104] Embodiment 2. [Configuration of the gate drive circuit] Figure 7 is a circuit diagram showing an example configuration of the gate drive circuit 101A according to Embodiment 2. The gate drive circuit 101A in Figure 7 is a modified example of the gate drive circuit 101 in Figure 1.

[0105] Specifically, the gate drive circuit 101A in Figure 7 differs from the gate drive circuit 101 in Figure 1 in that an NPN transistor 131 (first switch) is used instead of the switch 121 which is made of a P channel MOSFET, and a PNP transistor 132 (second switch) is used instead of the switch 122 which is made of an N channel MOSFET.

[0106] The base terminals of the NPN transistor 131 and the PNP transistor 132 are connected to the signal input terminal 104. The connection point 133 between the NPN transistor 131 and the PNP transistor 132 is connected to the gate terminal 4 of the driven element 1 via a turn-on gate resistor 106 and a forward diode, and also connected to the gate terminal 4 of the driven element 1 via a turn-off gate resistor 107 and a reverse diode.

[0107] The NPN transistor 131 and PNP transistor 132 described above constitute an emitter follower circuit, where the logic value of the input signal matches the logic value of the output signal. On the other hand, in the CMOS circuit composed of switches 121 and 122 in Figure 1, the logic value of the input signal and the logic value of the output signal are inverted. For this reason, the gate drive signal GDS was input in negative logic to the gate drive circuit 101 in Figure 1, whereas the gate drive signal GDS is input in positive logic to the gate drive circuit 101 in Figure 7.

[0108] By making the gate drive signal GDS positive logic, even if the circuit that generates the gate drive signal GDS fails for some reason and the input signal to the gate drive circuit 101 remains at the reference potential for a long time, the driven element 1 will not remain on for a long time. This has the advantage of making it less likely to cause short-circuit faults.

[0109] By setting the gate drive signal GDS to positive logic, the signal generation circuit 301 in Figure 1 is changed to the signal generation circuit 301A in Figure 7. Specifically, the signal generation circuit 301A in Figure 7 includes a first delay circuit 320A, a NOT circuit 311, a logic operation circuit 306, a second delay circuit 321, a diode 108, a capacitor 109, and a non-inverting buffer 110. Of these components, the configuration and connection of the second delay circuit 321, diode 108, capacitor 109, and non-inverting buffer 110 are the same as in the case of the signal generation circuit 301 in Figure 1, so the same or corresponding parts are denoted by the same reference numerals and the explanation is not repeated.

[0110] The first delay circuit 320A receives a positive logic gate drive signal GDS as input. The first delay circuit 320A generates a first delayed signal by delaying the turn-off edge (i.e., falling edge) of the input positive logic gate drive signal GDS without delaying the turn-on edge (i.e., rising edge). The first delay circuit 320A outputs the generated first delayed signal.

[0111] More specifically, as shown in Figure 7, the first delay circuit 320A includes a low-pass filter (also called an RC filter) consisting of a resistor 303 and a capacitor 304, a diode 302, and a Schmitt trigger buffer 305A. The resistor 303 and capacitor 304 are connected in series between the signal input terminal 104 and the reference node 103 in this order. The diode 302 is connected in parallel with the resistor 303 and in the opposite direction to that in Figure 1. That is, the cathode terminal of the diode 302 is connected to node B, the connection node between the resistor 303 and the capacitor 304. As a result, the RC filter functions as a unidirectional RC filter that delays only the falling edge of the gate drive signal GDS. The signal that has passed through the RC filter is input to the Schmitt trigger buffer 305A. The Schmitt trigger buffer 305A shapes the input signal but does not invert its logic value.

[0112] The logic circuit 306 calculates the logical AND of the first delay signal output from the first delay circuit 320 and the signal obtained by inverting the gate drive signal GDS using the NOT circuit 311. In the example shown in Figure 1, a NAND gate is used as the logic circuit 306, so the logic circuit 306 outputs the result of the logical AND operation inverted. Alternatively, the logic circuit 306 may calculate the logical OR of the inverted signal of the first delay signal and the gate drive signal GDS, and the result of the logical operation will be the same.

[0113] Since the other components of Figure 7 are the same as those in Figure 1, the same reference numerals are used for the same or corresponding parts, and the explanation will not be repeated.

[0114] [Operation of the gate drive circuit] Next, we will explain the operation of the gate drive circuit 101A in Figure 7, and in particular the operation of the signal generation circuit 301A.

[0115] Figure 8 is a timing diagram showing the operation of the gate drive circuit 101A in Figure 7. The timing diagram in Figure 8 corresponds to the timing diagram in Figure 2. 7 The signal waveforms of nodes A to F and the gate voltage V of driven element 1. G The waveform is shown. The differences from Figure 2 will be explained below.

[0116] The signal at node A is the gate drive signal GDS, which is input to the base terminal of NPN transistor 131 and the base terminal of PNP transistor 132.

[0117] When the gate drive signal GDS is low level, the PNP transistor 132 turns on, connecting the gate terminal 4 of the driven element 1 to the reference node 103. This turns the driven element 1 off. On the other hand, when the gate drive signal GDS is high level, the NPN transistor 131 turns on, connecting the gate terminal 4 of the driven element 1 to the power supply node 102. This turns the driven element 1 on.

[0118] Therefore, the gate drive signal GDS is positive logic. The time t1 when the gate drive signal GDS switches from a low level to a high level (i.e., the rising edge of the gate drive signal GDS) corresponds to the turn-on edge. The time t3 when the gate drive signal GDS switches from a high level to a low level (i.e., the falling edge of the gate drive signal GDS) corresponds to the turn-off edge.

[0119] The signal at node B represents the signal output from the unidirectional RC filter of the first delay circuit 320A, which is input to the unidirectional RC filter of the first delay circuit 320A when the signal at node A (i.e., the gate drive signal GDS) is input to this unidirectional RC filter. In the unidirectional RC filter of the first delay circuit 320A, the low-pass filter is disabled when the input signal is rising because the diode is in a conducting state. Conversely, the low-pass filter is enabled when the input signal is falling because the diode is in a blocked state.

[0120] Specifically, at time t1, which is the rising edge (i.e., turn-on edge) of the gate drive signal GDS, the output signal of the unidirectional RC filter (i.e., the signal at node B) rises rapidly. On the other hand, at time t3, which is the falling edge (i.e., turn-off edge) of the gate drive signal GDS, the output signal of the unidirectional RC filter (i.e., the signal at node B) falls slowly.

[0121] The signal at node C shows the signal output from the Schmitt trigger buffer 305A when the signal at node B (i.e., the output signal of the unidirectional RC filter) is input to the Schmitt trigger buffer 305A. When a signal with only the falling edge blunted, as shown in the signal at node B in Figure 8, is input to the Schmitt trigger buffer 305A, the Schmitt trigger buffer 305A outputs a signal with only the falling edge of the input signal significantly delayed.

[0122] The signal at node D represents the output signal of the NAND gate, which functions as the logic circuit 306. As shown in Figure 8, the NAND gate 306 outputs a signal obtained by inverting the logical AND of the signal at node C (i.e., the output signal of the Schmitt trigger buffer 305A) with the signal at node C (i.e., the signal obtained by inverting the signal at node A (i.e., the gate drive signal GDS) using the NOT gate 311).

[0123] In the case of Figure 8, the logical AND of the inverted signal of node A and the signal of node C is true only for a certain period T from the turn-off edge (for example, from time t3 to time t5 in Figure 2), and false for the rest of the period. Therefore, the signal of node D (i.e., the output signal of the NAND circuit 306) is at the reference potential only for a certain period T from the turn-off edge, and is at the positive potential for the rest of the period. This signal of node D is the same as the signal in Figure 2 in the case of Embodiment 1.

[0124] Signals and gate voltage waveforms V from nodes E and F G This is the same as in Figure 2, so we will not repeat the explanation.

[0125] [Effects of Embodiment 2] As described above, when the gate drive signal GDS is positive logic, a logical AND operation is performed between a first delayed signal, which delays only the turn-off edge of the gate drive signal GDS without delaying the turn-on edge, and the inverted signal of the original gate drive signal GDS. By delaying both the rising and falling edges of the result of this logical AND operation, a control signal for enabling the negative bias is generated and output to the potential switching circuit 201. With this configuration of Embodiment 2, as in Embodiment 1, false firing can be prevented by applying the minimum necessary negative bias to the gate terminal 4 of the driven element 1.

[0126] Embodiment 3. Figure 9 is a circuit diagram showing an example configuration of the gate drive circuit 101B of Embodiment 3. In the gate drive circuit 101B of Figure 7, the configuration of the potential switching circuit 201B differs from the configuration of the potential switching circuit 201 of Figure 1.

[0127] Specifically, the potential switching circuit 201 in Figure 1 is an open-drain type utilizing a pull-up resistor 202 and a switch 203 composed of an N-channel MOSFET. In contrast, the potential switching circuit 201B in Figure 9 is composed of an emitter follower circuit utilizing an NPN transistor 204 (third switch) and a PNP transistor 205 (fourth switch). Furthermore, unlike the open-drain circuit in Figure 1, the emitter follower circuit operates in positive logic, so an inverting buffer 111 is provided instead of the non-inverting buffer 110 in Figure 1.

[0128] More specifically, the NPN transistor 204 and the PNP transistor 205 are connected in series between the power node 102 and the reference node 103 in that order. The base terminals of the NPN transistor 204 and the PNP transistor 205 are connected to the output terminals of the inverting buffer 111. connection The connection point between the NPN transistor 204 and the PNP transistor 205 is connected to the second electrode 109B of the capacitor 109.

[0129] When the control signal output from the inverting buffer 111 is low level (enabled), the PNP transistor 205 turns on and the NPN transistor 204 turns off, thus enabling the negative bias. When the control signal output from the inverting buffer 111 is high level (disabled), the PNP transistor 205 turns off and the NPN transistor 204 turns on, thus disabling the negative bias and charging the capacitor 109.

[0130] Since the other components of Figure 9 are the same as those in Figure 1, the same reference numerals are used for the same or corresponding parts, and the explanation will not be repeated.

[0131] In the case of the potential switching circuit 201 shown in Figure 1, when the switch 203 is turned ON to apply a negative bias to the gate terminal 4, the power supply node 102 is connected to the reference node 103 via the pull-up resistor 202. This results in a problem of increased power consumption.

[0132] In contrast, in the case of the potential switching circuit 201B shown in Figure 9, when the PNP transistor 205 is turned on to apply a negative bias to the gate terminal 4, the power supply node 102 is isolated from other circuits by the NPN transistor 204, which is in the off state. Therefore, the gate drive circuit 101B of Embodiment 3 has the advantage of consuming less power compared to the gate drive circuit 101 of Embodiment 1.

[0133] Embodiment 4. Figure 10 is a circuit diagram showing an example configuration of the gate drive circuit 101C of Embodiment 4. In the gate drive circuit 101C of Figure 10, the configuration of the potential switching circuit 201C is different from both the configuration of the potential switching circuit 201 in Figure 1 and the configuration of the potential switching circuit 201B in Figure 9.

[0134] Specifically, the potential switching circuit 201 in Figure 1 is an open-drain type utilizing a pull-up resistor 202 and a switch 203 composed of an N-channel MOSFET. The potential switching circuit 201B in Figure 9 is composed of an emitter follower circuit utilizing an NPN transistor 204 and a PNP transistor 205. On the other hand, the potential switching circuit 201C in Figure 10 is composed of a CMOS push-pull circuit utilizing a P-channel MOSFET 206 (third switch) and an N-channel MOSFET 207 (fourth switch). The CMOS push-pull circuit operates in negative logic, similar to the open-drain circuit.

[0135] More specifically, the P-channel MOSFET 206 and N-channel MOSFET 207 are connected in series between the power node 102 and the reference node 103 in that order. The connection point between the P-channel MOSFET 206 and N-channel MOSFET 207 is connected to the second electrode 109B of the capacitor 109. A resistor 208 and a diode 210 are connected in parallel between the gate terminal of the P-channel MOSFET 206 and the output terminal of the non-inverting buffer 110. The cathode of diode 210 is connected to the gate terminal of the P-channel MOSFET 206, and the anode of diode 210 is connected to the output terminal of the non-inverting buffer 110. Also, a resistor 209 and a diode 211 are connected in parallel between the gate terminal of the N-channel MOSFET 207 and the output terminal of the non-inverting buffer 110. The cathode of diode 211 is connected to the output terminal of the non-inverting buffer 110, and the anode of diode 211 is connected to the gate terminal of the N-channel MOSFET 207.

[0136] When the control signal output from the non-inverting buffer 110 is high level (enabled), the N-channel MOSFET 207 turns on and the P-channel MOSFET 206 turns off, thus enabling the negative bias. When the control signal output from the non-inverting buffer 110 is low level (disabled), the N-channel MOSFET 207 turns off and the P-channel MOSFET 206 turns on, thus disabling the negative bias and charging the capacitor 109.

[0137] Since the other components of Figure 10 are the same as those in Figure 1, the same reference numerals are used for the same or corresponding parts, and the explanation will not be repeated.

[0138] In the case of the potential switching circuit 201 shown in Figure 1, when the switch 203 is turned ON to apply a negative bias to the gate terminal 4, the power supply node 102 is connected to the reference node 103 via the pull-up resistor 202. This results in a problem of high power consumption. Furthermore, in the case of the emitter follower circuit used in the potential switching circuit 201B shown in Figure 9, there is a problem of power consumption due to the base current during switching. In contrast, the push-pull circuit used in the potential switching circuit 201C shown in Figure 10 avoids these problems and has the advantage of reducing power consumption compared to the cases of embodiments 1 to 3.

[0139] [Summary of each embodiment] In summary, the gate drive circuits 101, 101A, 101B, and 101C of Embodiments 1 to 4 can apply a sufficient negative bias to the gate of the driven element 1 to prevent false firing using a capacitor with the minimum necessary capacity. Furthermore, the gate drive circuits 101, 101A, 101B, and 101C of Embodiments 1 to 4 do not require a negative power supply, do not require any special processing of the gate drive signal, and do not require a separate signal to enable the negative bias. In other words, the gate drive circuits of Embodiments 1 to 4 can be installed by directly replacing a conventional simple gate drive circuit without negative bias. This means that they can be easily attached to operating equipment, thereby easily adding a false firing prevention function. Therefore, the gate drive circuits of Embodiments 1 to 4 have the remarkable feature of having a wide range of applications.

[0140] [Modified examples of each embodiment] The types of semiconductor elements used in the above descriptions of each embodiment are not limited to those described above and can be replaced with other types. For example, the driven element 1 is not limited to a MOSFET but may also be an IGBT. In the case of an IGBT, the drain terminal of the MOSFET is read as the collector terminal, and the source terminal of the MOSFET is read as the emitter terminal. The potential switching circuit 201 in embodiments 1 and 2 may be an open-collector circuit as well as an open-drain circuit. The potential switching circuit 201B described in embodiment 3 and the potential switching circuit 201C described in embodiment 4 can also be combined with an emitter follower circuit composed of an NPN transistor 131 and a PNP transistor 132 described in embodiment 2.

[0141] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this application is indicated by the claims and not by the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of symbols]

[0142] 1 Driven element, 2 Drain terminal, 3 Source terminal, 4 Gate terminal, 5 Source reference terminal, 6 Gate capacitance, 101, 101A, 101B, 101C Gate drive circuit, 102 Power node, 103 Reference node, 104 Signal input terminal, 105, 110 Non-inverting buffer, 106, 107 Gate resistor, 108, 210, 211, 302 Diode, 109, 304, 308 Capacitor, 109A First electrode, 109B Second electrode, 111 Inverting buffer, 121, 122, 203 Switch, 131, 132, 204, 205 Bipolar transistor, 133 Connection point, 201, 201B, 201C Potential switching circuit, 202 Pull-up resistor, 206, 207 MOSFET, 208, 209, 303, 307 Resistors, 301, 301A; Signal generation circuits, 305, 309; Schmitt trigger inverter, 305A; Schmitt trigger buffer, 306; Logic circuit (NAND gate), 311; NOT gate, 320, 320A; First delay circuit, 321; Second delay circuit.

Claims

1. A gate drive circuit that drives a driven element based on a gate drive signal, A first switch is connected between a power node to which a positive potential is applied and the gate terminal of the driven element, and turns on the driven element when the gate drive signal is a first logic value, A second switch is connected between a reference node to which a reference potential is applied and the gate terminal of the driven element, and turns off the driven element when the gate drive signal is a second logic value. A diode is connected between the second switch and the reference node such that the reference node is on the cathode side, A capacitor with a first electrode connected to the connection node between the second switch and the diode, A potential switching circuit that applies the reference potential to the second electrode of the capacitor when the control signal is activated, and applies the positive potential to the second electrode of the capacitor when the control signal is deactivated, The system includes a signal generation circuit that generates the control signal based on the gate drive signal, The signal generation circuit is a gate drive circuit that activates the control signal after the gate drive signal switches from the first logic value to the second logic value and the charge at the gate terminal of the driven element has been discharged, and deactivates the control signal before the gate drive signal switches from the second logic value to the first logic value.

2. The aforementioned signal generation circuit is A first delay circuit generates a first delay signal by delaying the turn-off edge at which the gate drive signal switches from the first logic value to the second logic value, and not delaying the turn-on edge at which the gate drive signal switches from the second logic value to the first logic value. A logic circuit that performs a logic operation using the first delay signal and the gate drive signal, The gate drive circuit according to claim 1, further comprising a second delay circuit that generates the control signal or its inverted signal by delaying the calculation result of the logic operation circuit.

3. The first logical value is low level, and the second logical value is high level. The gate drive circuit according to claim 2, wherein the logic operation of the logic operation circuit includes a logical AND of the inverted signal of the first delay signal and the gate drive signal, or a logical OR of the inverted signal of the first delay signal and the gate drive signal.

4. The first logical value is high level, and the second logical value is low level. The gate drive circuit according to claim 2, wherein the logic operation of the logic operation circuit includes a logical AND of the first delay signal and the inverted signal of the gate drive signal, or a logical OR of the inverted signal of the first delay signal and the gate drive signal.

5. The aforementioned potential switching circuit is A resistor connected between the power node and the second electrode of the capacitor, The capacitor includes a third switch connected between the second electrode and the reference node, The gate drive circuit according to any one of claims 1 to 4, wherein the third switch is turned on when the control signal is activated and is turned off when the control signal is deactivated.

6. The aforementioned potential switching circuit is A third switch connected between the power node and the second electrode of the capacitor, The capacitor includes a fourth switch connected between the second electrode and the reference node, The third switch is turned off when the control signal is enabled and turned on when the control signal is disabled. The gate drive circuit according to any one of claims 1 to 4, wherein the fourth switch is turned on when the control signal is activated and is turned off when the control signal is deactivated.

7. The self-arm, which is composed of the driven element, is connected in series with the opposing arm, which is composed of other driving elements. The gate drive circuit according to any one of claims 1 to 4, wherein the period during which the control signal is activated includes the timing at which the drive element of the opposing arm is turned on.

8. The potential difference between the positive potential and the reference potential is V ＣＣ The gate capacitance of the driven element is set to C. ＧＳ The turn-on threshold of the driven element is set to V ＴＨ The peak value of the surge voltage when the drive element of the opposing arm is turned on, in the case where the capacitor is not provided, is V ＳＵＲＧＥ Therefore, the lower limit of the capacitance of the capacitor is, (V ＳＵＲＧＥ -V ＴＨ ) / (V ＣＣ -(V ＳＵＲＧＥ -V ＴＨ ))×C ＧＳ The upper limit of the capacitance of the capacitor is V ＳＵＲＧＥ / (V ＣＣ -V ＳＵＲＧＥ )×C ＧＳ The gate drive circuit according to claim 7.

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