Ball grid array card edge connector

Abstract

To provide a card edge connector to provide high speed communications while maintaining acceptable signal integrity.SOLUTION: In one embodiment, a card edge connector includes: a housing having an opening into which a first circuit board is to be inserted; a plurality of pins each having a first end and a second end, the plurality of pins extending from within the opening through a bottom surface of the housing, the first end of the plurality of pins configured to mate with a corresponding contact of the first circuit board; and a plurality of ball grid array (BGA) solder balls each adapted to the second end of a corresponding one of the pins, the plurality of pins configured to mate with a corresponding conductive area of a second circuit board to which the card edge connector mates via the plurality of BGA solder balls. Other embodiments are described and claimed.SELECTED DRAWING: Figure 1

Description

Background Art

[0001] The data rate of electrical signals transmitted via PCIe (Peripheral Component Interconnect Express)-based communication according to the PCIe specification has increased dramatically over time. For example, the PCIe data rate has increased eight-fold in less than 10 years from Gen3 (8 gigabits per second (Gbps)) to Gen6 (64 Gbps PAM4 (pulse amplitude modulation 4-level)). At the same time, the integrity requirements for electrical signals in platform interconnects are becoming increasingly stringent.

[0002] Many PCIe-based communications occur between devices that are connected together using a card edge connector such as a CEM (card electromechanical) connector. Historically, THM (through hole mount) CEM connectors have been used in PCIe implementations, but currently, in PCIe 5.0 according to the PCIe Card Electromechanical Specification Rev. 4.0 (September 2019), SMT (surface mount technology) CEM connectors are used due to electrical performance requirements. However, current SMT connectors still have a relatively large footprint that directly affects performance. Additionally, the size of the solder pads requires an input of traces that enter the connector only in one direction, which limits routing flexibility and potentially drives longer PCIe routes and board sizes.

Brief Description of the Drawings

[0003] [Figure 1] It is a diagram of a system arrangement according to an embodiment.

[0004] [Figure 2] It is a cross-sectional view of a system environment according to an embodiment.

[0005] [Figure 3] This is one embodiment of a fabric, which consists of point-to-point links that interconnect a set of components.

[0006] [Figure 4] This is an embodiment of a system-on-chip design according to one embodiment.

[0007] [Figure 5] This is a block diagram of a system according to one embodiment of the present invention. [Modes for carrying out the invention]

[0008] In various embodiments, the card edge connector may be configured with ball grid array (BGA) solder balls that provide interconnection between the card edge connector and a printed circuit board, such as the motherboard of a given system. This arrangement allows another circuit board, such as an add-in card, to be fitted within the card edge connector to provide high-speed communication while maintaining acceptable signal integrity. Additionally, both toe-based and heel-based signal routing from outside the connector footprint can be used to communicate signals between components on the add-in card and components on the motherboard, thus enabling easier routing through the motherboard.

[0009] Referring here to Figure 1, a diagram of the system layout according to one embodiment is shown. As shown in Figure 1, the system 100 includes a printed circuit board 110. In various implementations, the circuit board 110 may be the main motherboard of the system. The circuit board 110 may be a multilayer circuit board including internal routing interconnects, providing connections to various system components, including integrated circuit packages, electrical components, power components, connectors, etc. Additionally, the circuit board 110 provides a connection area (generally 111) to which a card edge connector can be fitted. This embodiment is for the implementation of a CEM (card electromechanical) connector, but the embodiments are understood to be not limited thereto. In other implementations, card edge connectors with BGA solder balls may be U.2 connectors according to the SSFFWG (Solid State Form Factor Working Group), M.2 connectors according to the PCIe M.2 Specification 4.0 (November 2020), TA-1002 connectors according to the SNIA (Storage Networking Industry Association) SFF (Small Form Factor) Technical Working Group SFF-TA-1002 Specification, or memory connectors such as DIMM (dual inline memory module) connectors. Such connectors can be used in connection with solid-state drives, non-volatile memory, and volatile memory, among other applications. These connectors can be distinguished from conventional card edge connectors with SMT or THM configurations.

[0010] At the high level shown in Figure 1, only a few differential pin pairs of the CEM connector are shown, namely differential pins 1201, 2 and 1241, 2 (generally pins 120, 124), rather than the complete CEM connector. As shown, pins 120, 124 are fixed to the circuit board 110 via BGA solder balls 1221, 2 and 1261, 2. Solder balls 122, 126 may be formed from a lead-free tin / silver / copper alloy and may be fitted to pins 120, 124 via flux, pin transfer, and reflow processes. Thus, interconnections between the circuits on the device interconnected to the CEM connector and other components of the system are provided via signal lines or routing lines 1151, 2 and routing lines 1161, 2.

[0011] In the illustrated example, routing line 115 may have toe-based routing, and routing line 116 may have heel-based routing. In this way, greater flexibility is achieved. When a signal trace or pad is not in the signal path (only one end is connected and the other end is floating), it is called a stub. Stubs cause resonance and thus degrade signal performance. Generally, toe-based routing lines leave minimal stubs, while heel-based routing leaves larger stubs. In one embodiment, the signal integrity of communication over these different types of signal lines may be the same, or at least substantially the same.

[0012] In various configurations, these routing lines lead from exposed conductive material within connection areas 111 on the surface of the circuit board 110 (such as exposed copper pads to which BGA solder balls 122, 126 are fitted) to other circuits such as one or more processor packages or other integrated circuits (ICs) fitted to the circuit board 110. Note that these ICs may be fitted to the circuit board 110, for example, via through-hole mounting (THM), surface mount technology (SMT), or BGA connections.

[0013] Greater electrical performance can be achieved via BGA solder balls 122, 126 fitted to the bottom of corresponding pins 120, 124. Furthermore, a BGA CEM connector according to one embodiment offers routing flexibility and higher mechanical performance compared to an SMT connector. According to one embodiment, a BGA CEM connector may be fitted to a circuit board using a solder reflow process in which the connector is aligned above corresponding conductive pads (within the connection area). The connector is then mated to these pads using, for example, a flux material. The connector is then bonded to the circuit board by a predetermined assembly process. For the sake of clarity in Figure 1, only two sets of pins for differential signal pairs are shown, but it is understood that a given BGA CEM connector according to one embodiment may include more pins for additional signal pairs. Furthermore, while a differential implementation is shown, such as one used to provide PCIe communication, single-ended signals may be communicated using a BGA card edge connector in other implementations.

[0014] A BGA connector according to one embodiment can provide better insertion and return losses over the frequency range of interest compared to an SMT connector due to its smaller footprint on the printed circuit board. Because of the smaller footprint, the BGA connector offers much greater routing flexibility and is free from the limitations on toe-entry or heel-entry that are present in SMT connectors. In contrast, SMT connectors with heel-entry suffer significant performance degradation due to the large stub caused by heel routing, which is unavoidable in some board designs due to area constraints. Furthermore, the smaller footprint enabled by the embodiment is better suited to smaller form factors or half-width boards. Additionally, BGA reflow is easier and warping issues are less pronounced.

[0015] The embodiment reduces routing congestion and improves overall connector performance. By using BGA solder balls, a smaller pad size on the circuit board can be achieved. In the embodiment, there may be lower capacitive dips for heel-based routing, and lower differential insertion and return losses. In SMT connectors, the loss difference for heel-based routing was approximately 1.5 dB at a Nyquist frequency of 16 gigahertz (GHz) for PCIe 5.0 / 6.0. In contrast, in one embodiment, there is little performance difference between toe routing and heel routing. Additionally, BGA connectors have better insertion and return losses compared to SMT connectors with toe routing.

[0016] Referring now to Figure 2, a cross-sectional view of a system environment according to one embodiment is shown. As shown in the cross-sectional view of Figure 2, the system 200 includes a CEM connector 210 fitted to a circuit board 110 via BGA solder balls 122, 128. Of course, only two BGA solder balls are shown in this cross-sectional view, but in embodiments, more BGA solder balls may be present.

[0017] As shown in the figure, the CEM connector 210 includes a housing 211 having a first side 212 and a second side 214. Additionally, the housing 211 includes a cavity 216 into which a circuit board 250 can be fitted. In various embodiments, the circuit board 250 may be any type of suitable add-in card, such as a networking card for a network interface circuit (NIC) or a graphics card that provides video / graphics functionality via one or more graphics processing units (GPUs). In other cases, the circuit board 250 may provide any other type of accelerator or other functional circuit.

[0018] In either case, it is understood that the circuit board 250 may include so-called finger contacts (e.g., gold-plated finger contacts) into which the pins of the CEM connector 210 mate. Although not shown for the sake of clarity in Figure 2, these pins may take the form shown in Figure 1 and may have a first end that contacts the finger contacts of the circuit board 110 and a second end that terminates with corresponding BGA solder balls, e.g., BGA solder balls 122, 128. In this configuration, signal routing may occur between components of the circuit board 250 and components adapted to the circuit board 110. For this purpose, signal lines on or within the circuit board 110 may be terminated on exposed conductive surfaces on the circuit board 110 into which the BGA solder balls 122, 128 mate. The improved electrical signal integrity using the BGA connector allows for the use of heel routing or toe routing for signal routing through the circuit board 110. In either case, signal integrity may be substantially identical, in contrast to other CEM connector technologies such as through-hole mount or surface mount techniques, and heel routing may substantially impair signal integrity compared to toe routing. While this level is demonstrated in the embodiment of Figure 2, many variations and alternatives may be possible.

[0019] To understand the impact of BGA connectors on overall platform performance, a full link-level analysis was performed on a 13-inch motherboard routing using PCIe 6.0 with the assumption of basic specifications for equalization. Table 1 below lists a comparison of eye openings between BGA and SMT connectors in one embodiment. This is an exemplary comparison to demonstrate the available improvements using one exemplary embodiment, but understand that the embodiment is not limited in this respect. Also note that the eye opening requirement in PCIe 6.0 is only 6 millivolts (mV) / 3.125 picoseconds (ps). There is no link margin difference for BGA connectors with heel routing and toe routing. On the other hand, a significant margin degradation was observed in SMT connectors with heel routing compared to toe routing. In this example, the eye opening in the BGA connector is 4.9 mV / 1.6 ps better than the SMT connector with heel routing. In particular, the eye height improvement in the BGA connector is more than double compared to the SMT connector with heel routing. Furthermore, SMT connectors with heel routing do not meet eye margin requirements and simply do not operate at PCIe 6.0 speeds. This is because PAM4 signaling is more sensitive to noise levels compared to NRZ signaling. Additionally, BGA connectors are approximately 0.5mv / 0.5ps better than SMT connectors with toe routing, which are approximately 8% / 16% in eye mask budget. Overall, BGA connectors in one embodiment exhibit far better electrical performance and routing flexibility compared to SMT connectors, as well as better mechanical performance and routing flexibility in board architecture planning compared to SMT connectors. Moreover, BGA connector technology can be applied to other card edge connectors such as High Speed ​​Input / Output (IO) (HSIO) connectors like Ethernet®, Intel® UPI (Ultra Path Interconnect), USB (Universal Serial Bus), and SATA (Serial Attachment Technology). [Table 1]

[0020] The embodiments can be implemented in a wide variety of interconnection structures. Referring to Figure 3, one embodiment of a fabric consisting of point-to-point links interconnecting a set of components is shown. System 300 includes a processor 305 and system memory 310 coupled to a controller hub 315. The processor 305 includes any processing element such as a microprocessor, host processor, embedded processor, coprocessor, or other processor. The processor 305 is coupled to the controller hub 315 via a link 306, such as an Intel® UPI serial point-to-point interconnect.

[0021] The system memory 310 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in the system 300. The system memory 310 is coupled to the controller hub 315 via a memory interface 316. Examples of memory interfaces include a DDR (double-data rate) memory interface, a dual-channel DDR memory interface, and a DRAM (dynamic RAM) memory interface.

[0022] In one embodiment, the controller hub 315 is a root hub, root complex, or root controller in the PCIe interconnect hierarchy. Examples of controller hubs 315 include chip sets, memory controller hubs (MCHs), north bridges, interconnect controller hubs (ICHs), south bridges, and root controllers / hubs. The term chip set often refers to two physically distinct controller hubs, namely, a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems include an MCH integrated with the processor 305, but the controller 315 often communicates with I / O devices in a manner similar to that described below. In some embodiments, peer-to-peer routing is optionally supported via the root complex 315.

[0023] Here, the controller hub 315 is coupled to the switch / bridge 320 via the serial link 319. The input / output modules 317 and 321, which may also be referred to as interfaces / ports 317 and 321, include / implement a layered protocol stack that provides communication between the controller hub 315 and the switch 320. In one embodiment, multiple devices can be coupled to the switch 320.

[0024] Switch / bridge 320 routes packets / messages of device 325 upstream to controller hub 315, i.e., ascends the hierarchy towards the root complex, and routes them downstream from processor 305 or system memory 310 to device 325, i.e., descends the hierarchy away from the root controller. Device 325 includes any internal or external device or component coupled to the electronic system via a BGA card edge connector, such as an I / O device, NIC, add-in card, audio processor, network processor, memory expander, hard drive, solid state drive and other storage devices, CD / DVD ROM, monitor, printer, mouse, keyboard, router, portable storage device, FireWire device, USB (Universal Serial Bus) device, scanner, and other input / output devices. For this purpose, device 325 may be implemented on a circuit board adapted within the BGA card edge connector as described herein.

[0025] Graphics accelerator 330 is also coupled to controller hub 315 via serial link 332. In one embodiment, graphics accelerator 330 is coupled to an MCH that is coupled to an ICH. Then, switch 320, and thus I / O device 325, is coupled to the ICH. I / O modules 331 and 318 also implement a layered protocol stack that communicates between graphics accelerator 330 and controller hub 315. The graphics controller or graphics accelerator 330 itself may be integrated within processor 305.

[0026] Referring now to Figure 4, an embodiment of the SoC design according to one embodiment is shown. As a specific exemplary example, the SoC 400 may be configured to be inserted into any type of computing device ranging from portable devices to server systems. Here, the SoC 400 includes two cores 406 and 407. Cores 406 and 407 may conform to instruction set architectures such as Intel® Architecture Core® based processors, AMD (Advanced Micro Devices, Inc.) processors, MIPS-based processors, ARM-based processor designs, or their customers, as well as their licensees or adopters. Cores 406 and 407 are coupled to a bus interface unit 409 and a cache controller 408 associated with an L2 cache 410, and communicate with the rest of the system 400 via an interconnect 412.

[0027] The interconnect 412 provides communication channels to other components such as a SIM module 430 for interface with a SIM (Subscriber Identity Module) card, a boot ROM 435 for initializing and booting the SoC 400 by holding boot code for execution by cores 406 and 407, an SDRAM controller 440 for interface with external memory (e.g., DRAM 460), a flash controller 445 for interface with non-volatile memory (e.g., flash 465), a peripheral controller 450 for interface with peripherals, a video codec 420 and video interface 425 for displaying and receiving inputs (e.g., touch-enabled input), and a GPU 415 for performing graphics-related calculations. Additionally, the system includes peripherals for communication such as a Bluetooth® module 470, a 3G modem 475, a GPS 480, and a WiFi 485, one or more of which may be mounted on a circuit board so as to fit within a BGA card edge connector as described herein.

[0028] The system also includes a power controller 455. Furthermore, as shown in Figure 4, the system 400 may additionally include interfaces, for example, a MIPI interface 492 for a display and / or an HDMI® interface 495 which can be coupled to the same or different displays.

[0029] Figure 5 shows a block diagram of a system according to one embodiment of the present invention. As shown in Figure 5, the multiprocessor system 500 includes a first processor 570 and a second processor 580 coupled via a point-to-point interconnect 550. As shown in Figure 5, each of the processors 570 and 580 may be a multicore processor including representative first and second processor cores (i.e., processor cores 574a and 574b, and processor cores 584a and 584b).

[0030] Referring further to Figure 5, the first processor 570 further includes a memory controller hub (MCH) 572 and point-to-point (PP) interfaces 576 and 578. Similarly, the second processor 580 includes an MCH 582 and PP interfaces 586 and 588. As shown in Figure 5, the MCHs 572 and 582 connect the processors to their respective memories, namely memory 532 and memory 534, which may be part of system memory (e.g., DRAM) locally attached to each processor. The first processor 570 and the second processor 580 may be connected to the chipset 590 via PP interconnects 562 and 564, respectively. As shown in Figure 5, the chipset 590 includes PP interfaces 594 and 598.

[0031] Furthermore, the chipset 590 includes an interface 592 for coupling the chipset 590 with a high-performance graphics engine 538 via a PP interconnect 539. As shown in Figure 5, various input / output (I / O) devices 514 may be coupled to the first bus 516, along with a bus bridge 518 that couples the first bus 516 to a second bus 520. One or more of the I / O devices 514 may be mounted on a circuit board that is fitted within a BGA card edge connector, as described herein.

[0032] In one embodiment, various devices may be coupled to the second bus 520, including, for example, a keyboard / mouse 522, a communication device 526, and a data storage unit 528, such as a disk drive or other mass storage device 530. Furthermore, an audio I / O 524 may be coupled to the second bus 520.

[0033] The following examples relate to further embodiments.

[0034] In one example, a card edge connector comprising: a housing having an opening into which a first circuit board is inserted; a plurality of pins, each having a first end and a second end, the plurality of pins extending from the opening through the bottom surface of the housing, the first ends of the plurality of pins mating with corresponding contacts on the first circuit board; and a plurality of BGA solder balls, each fitted to the second end of a corresponding pin among the plurality of pins, the plurality of pins mating with corresponding conductive areas on a second circuit board with which the card edge connector mates via the plurality of BGA solder balls.

[0035] In one example, the card edge connector includes a BGA connector.

[0036] In one example, the BGA connector includes a PCIe connector for receiving a first circuit board, which includes a PCIe circuit board.

[0037] In one example, the card edge connector is fitted to the edge portion of a second circuit board, which includes a motherboard.

[0038] In one example, at least a first portion of the plurality of pins is coupled to a first corresponding conductive region of a second circuit board to which a heel-routed signal line is connected, and at least a second portion of the plurality of pins is coupled to a second corresponding conductive region of the second circuit board to which a toe-routed signal line is connected.

[0039] In one example, the card edge connector enables communication between at least one memory device fitted to a first circuit board and a processor fitted to a second circuit board.

[0040] In another example, the system includes a processor fitted onto a circuit board, the circuit board having a first connection area on its surface, and the circuit board further having a plurality of signal lines for coupling the processor to one or more devices on a second circuit board; and a card edge connector, the card edge connector being fitted onto the first connection area of ​​the circuit board via a plurality of solder balls on the bottom surface of the card edge connector, and the card edge connector having a housing with an opening into which the second circuit board is inserted.

[0041] In one example, the card edge connector further includes a plurality of pins, each having a first end and a second end, the plurality of pins extending from within an opening through a bottom surface, and the first ends of the plurality of pins mating with corresponding contacts on a second circuit board.

[0042] In one example, the plurality of solder balls includes a plurality of BGA solder balls, each fitted to the second end of a corresponding pin among a plurality of pins, and each of the plurality of pins is coupled to the corresponding conductive pad of the first connection area via one of the plurality of BGA solder balls.

[0043] In one example, at least a first portion of the plurality of pins is coupled to a first corresponding conductive pad in a first connection area to which a first signal line from within the footprint of the card edge connector is connected, and at least a second portion of the plurality of pins is coupled to a second corresponding conductive pad in the first connection area to which a second signal line from outside the footprint of the card edge connector is connected.

[0044] In one example, the card edge connector communicates signals at a data rate of at least 64 gigabits per second.

[0045] In one example, the system further includes one or more memory devices adapted to a second circuit board.

[0046] In one example, the card edge connector includes a BGA PCIe connector, and the second circuit board includes a PCIe circuit board.

[0047] In one example, the second circuit board includes a network interface circuit.

[0048] In one example, a card edge connector is fitted to the edge portion of a circuit board, and the circuit board includes a motherboard.

[0049] In yet another example, a CEM connector includes a housing having an opening for receiving a first circuit board, a plurality of pins, each having a first end and a second end, the plurality of pins extending from the opening through the bottom surface of the housing, the first end of each of the plurality of pins mating with a corresponding contact on the first circuit board, and a plurality of solder balls, each fitted to the second end of a corresponding pin, the plurality of pins mating with a corresponding conductive area on a first motherboard via the plurality of solder balls.

[0050] In one example, the CEM connector includes a PCIe connector for receiving a first circuit board, which includes a PCIe circuit board.

[0051] Multiple solder balls include a ball grid array of solder balls.

[0052] In one example, at least a first portion of the multiple pins is coupled to a first corresponding conductive region on the motherboard to which the tow-routed signal line is connected, and at least a second portion of the multiple pins is coupled to a second corresponding conductive region on the motherboard to which the heel-routed signal line is connected.

[0053] In one example, the CEM connector makes it possible to make the signal integrity of a first signal communicated via the heel-routed signal line at least substantially equal to the signal integrity of a second signal communicated via the toe-routed signal line.

[0054] Understand that various combinations of the above examples are possible.

[0055] It should be noted that the terms “circuit” and “circuitry” are used interchangeably herein. Where used herein, these terms and the term “logic” are used to refer to analog circuits, digital circuits, hardwired circuits, programmable circuits, processor circuits, microcontroller circuits, hardware logic circuits, state-machine circuits, and / or any other type of physical hardware component, either alone or in any combination. Embodiments may be used in many different types of systems. For example, in one embodiment, a communication device may be configured to perform various methods and techniques described herein. Of course, the scope of the present invention is not limited to communication devices, and other embodiments may instead be directed to one or more machine-readable media containing instructions that cause a device to perform one or more of the methods and techniques described herein, in response to being executed on other types of devices for processing instructions or on a computer device.

[0056] Embodiments may be implemented in code and stored on a non-temporary storage medium that stores instructions that can be used to program a system in order to execute those instructions. Embodiments may also be implemented in data and, if used by at least one machine, stored on a non-temporary storage medium that causes at least one machine to manufacture at least one integrated circuit to perform one or more operations. Yet another embodiment may be implemented on a computer-readable storage medium that contains information that, when manufactured into an SoC or other processor, configures the SoC or other processor to perform one or more operations. The storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, solid-state drives (SSDs), compact disk read-only memory (CD-ROM), compact disk rewritable memory (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), random access memory (RAM) (including dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), etc.); magnetic cards or optical cards; or any type of medium suitable for storing electronic instructions.

[0057] Although the present invention has been described in terms of a limited number of embodiments, those skilled in the art will be able to see many modifications and variations therefrom. The appended claims are intended to cover all such modifications and variations that fall within the true spirit and scope of the present invention.

Claims

1. Card edge connector, A housing having an opening into which a first circuit board is inserted, A plurality of pins, each having a first end and a second end, the plurality of pins extending from within the opening through the bottom surface of the housing, and the first end of the plurality of pins mating with corresponding contacts on the first circuit board, A plurality of ball grid array (BGA) solder balls, each fitted to the second end of a corresponding pin among the plurality of pins, wherein the plurality of pins mate with corresponding conductive regions of a second circuit board through which the card edge connector mates, At least a first portion of the plurality of pins is coupled to a first corresponding conductive region of the second circuit board to which the heel-routed signal line is connected. A card edge connector in which at least a second portion of the plurality of pins is coupled to a second corresponding conductive region of the second circuit board to which a tow-routed signal line is connected.

2. The card edge connector according to claim 1, wherein the card edge connector includes a BGA connector.

3. The card edge connector according to claim 2, wherein the BGA connector includes a PCIe connector that receives the first circuit board, which includes a PCIe (Peripheral Component Interconnect Express) circuit board.

4. The card edge connector according to claim 1, wherein the card edge connector is fitted to the edge portion of the second circuit board, and the second circuit board includes a motherboard.

5. The card edge connector according to claim 1, wherein the card edge connector enables communication between at least one memory device fitted to the first circuit board and a processor fitted to the second circuit board.

6. A processor fitted onto a circuit board, The circuit board includes a first connection region on its surface, and the circuit board further includes a plurality of signal lines for coupling the processor to one or more devices on the first circuit board, A card edge connector, wherein the card edge connector is fitted to a first connection area of ​​the circuit board via a plurality of solder balls on the bottom surface of the card edge connector, and the card edge connector has a housing having an opening into which the first circuit board is inserted, At least a first portion of the multiple pins is coupled to a first corresponding conductive pad in the first connection region to which a first signal line from inside the footprint of the card edge connector, defined by the collection of conductive pads in the first connection region, is connected. A system in which at least a second portion of the plurality of pins is coupled to a second corresponding conductive pad in the first connection area to which a second signal line from outside the footprint of the card edge connector is connected.

7. The system according to claim 6, wherein the card edge connector further includes a plurality of pins, each having a first end and a second end, the plurality of pins extending from within the opening through the bottom surface, and the first ends of the plurality of pins mating with corresponding contacts on the first circuit board.

8. The system according to claim 7, wherein the plurality of solder balls include a plurality of ball grid array (BGA) solder balls, each fitted to the second end of a corresponding pin among the plurality of pins, and each of the plurality of pins is coupled to a corresponding conductive pad in the first connection area via one of the plurality of BGA solder balls.

9. The system according to claim 6, wherein the card edge connector communicates signals at a data rate of at least 64 gigabits per second.

10. The system according to claim 6, further comprising one or more memory devices fitted to the first circuit board.

11. The system according to claim 6, wherein the card edge connector includes a ball grid array (BGA) PCIe (Peripheral Component Interconnect Express) connector, and the first circuit board includes a PCIe circuit board.

12. The system according to claim 6, wherein the first circuit board includes a network interface circuit.

13. The system according to any one of claims 6 to 12, wherein the card edge connector is fitted to the edge portion of the circuit board, and the circuit board includes a motherboard.

14. It is a CEM (card electromechanical) connector, A housing having an opening for receiving a first circuit board, A plurality of pins, each having a first end and a second end, the plurality of pins extending from within the opening through the bottom surface of the housing, and the first end of each of the plurality of pins mating with a corresponding contact of the first circuit board, A plurality of solder balls, each fitted to the second end of a corresponding pin among the plurality of pins, the plurality of pins mating with a corresponding conductive region on the motherboard through which the CEM connector mates, At least a first portion of the plurality of pins is coupled to a first corresponding conductive region on the motherboard to which the heel-routed signal line is connected. A CEM connector in which at least a second portion of the plurality of pins is coupled to a second corresponding conductive region on the motherboard to which a tow-routed signal line is connected.

15. The CEM connector according to claim 14, wherein the CEM connector includes a PCIe connector that receives the first circuit board, which includes a PCIe (Peripheral Component Interconnect Express) circuit board.

16. The CEM connector according to claim 15, wherein the plurality of solder balls include ball grid array solder balls.

17. The CEM connector according to any one of claims 14 to 16, wherein the CEM connector enables the signal integrity of a first signal communicated via the heel-routed signal line to be at least substantially equal to the signal integrity of a second signal communicated via the toe-routed signal line.

18. It is a device, A housing means having an opening into which a first circuit board is inserted, A plurality of pin means, each having a first end and a second end, the plurality of pin means extending from within the opening through the bottom surface of the housing means, and the first end of the plurality of pin means mating with corresponding contacts of the first circuit board, A plurality of ball grid array (BGA) soldering means, each fitted to the second end of a corresponding pin means among the plurality of pin means, the plurality of pin means comprising a plurality of BGA soldering means that mate with corresponding conductive regions of a second circuit board with which the device mates via the plurality of BGA soldering means. At least a first portion of the plurality of pin means is coupled to a first corresponding conductive region of the second circuit board to which the heel-routed signal line is connected, Apparatus, wherein at least a second portion of the plurality of pin means is coupled to a second corresponding conductive region of the second circuit board to which a tow-routed signal line is connected.

19. The apparatus according to claim 18, wherein the apparatus includes a card edge connector.

20. The apparatus according to claim 19, wherein the apparatus includes a PCIe connector for receiving the first circuit board which includes a PCIe (Peripheral Component Interconnect Express) circuit board.

21. The apparatus according to any one of claims 18 to 20, wherein the apparatus is fitted to the edge portion of the second circuit board, and the second circuit board includes a motherboard.

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