Semiconductor equipment

Abstract

To provide a semiconductor device capable of reducing degradation of a forward voltage and a loss at turn-on.SOLUTION: A vertical MOSFET comprises: a semiconductor substrate 2 of a first conductivity type; a first semiconductor layer 1 of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; a first trench 31 and a second trench 32; and an active region 40 in which current flows when a gate electrode provided via a gate insulation film inside the first trench 31 and a Schottky electrode provided inside the second trench 32 are in the on state. The second trench 32 is also provided in a connection region 41 between the active region 40 and an edge region 42 surrounding the active region 40 and holding a breakdown voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, in power semiconductor devices, vertical MOSFETs (Metal Oxied Semiconductor Field Effect Transistors) with a trench structure have been fabricated to reduce the on-resistance of the device. In vertical MOSFETs, a trench structure in which the channel is formed perpendicular to the substrate surface can increase the cell density per unit area compared to a planar structure in which the channel is formed parallel to the substrate surface, thus increasing the current density per unit area and offering cost advantages.

[0003] Vertical MOSFETs incorporate a parasitic pn diode formed from a p-type base layer and an n-type drift layer as a body diode between the source and drain. This eliminates the need for a freewheeling diode (FWD) used in inverters, contributing to cost reduction and miniaturization. However, when using a silicon carbide substrate as the semiconductor substrate, the parasitic pn diode has a higher built-in potential compared to when using a silicon (Si) substrate, resulting in higher on-resistance of the parasitic pn diode and increased losses. Furthermore, when the parasitic pn diode is turned on and current is supplied, its bipolar operation causes its characteristics to change over time (aging degradation), leading to forward degradation and increased turn-on losses.

[0004] To address this problem, a Schottky barrier diode (SBD) can be connected in parallel with the MOSFET in the circuit. During freewheeling, current flows through the SBD, preventing current from flowing through the parasitic pn diode. However, this requires approximately the same number of SBD chips as MOSFETs, increasing costs.

[0005] Therefore, a technique has been proposed in which a contact trench is formed on the substrate surface that penetrates the p-type channel portion, an SBD is embedded in the inner wall of the trench, and the current during recirculation is passed through the built-in SBD instead of the PiN diode (see, for example, Patent Document 1 below).

[0006] Figure 16 is a top view showing the structure of a conventional silicon carbide semiconductor device with a built-in SBD. Figure 17 is a cross-sectional view of the C-C' portion of Figure 16 showing the structure of a conventional silicon carbide semiconductor device with a built-in SBD. Figure 18 is a cross-sectional view of the B-B' portion of Figure 16 showing the structure of a conventional silicon carbide semiconductor device with a built-in SBD. As shown in Figure 16, the silicon carbide semiconductor device 150 with a built-in SBD includes an active region 140 through which current flows when the element structure is formed and the device is in the ON state, an edge region 142 surrounding the active region 140 and maintaining the breakdown voltage, and a connecting region 141 between the active region 140 and the edge region 142. The active region 140 is the area enclosed by the black line in Figure 16.

[0007] As shown in Figure 16, the active region 140 is provided with alternating stripe-shaped trench gates 131 and stripe-shaped trench SBDs 132. The connecting region 141 is provided with gate contacts 143 that electrically connect the trench gates 131 and gate electrode pads 145, surrounding the active region 140. The trench gates 131 and gate contacts 143 are electrically connected by polysilicon 144 provided in the connecting region 141.

[0008] Furthermore, as shown in Figure 17, the silicon carbide semiconductor device 150 with a built-in SBD is equipped with a MOS gate with a general trench gate structure on the front side (the side facing the p-type base layer 116, which will be described later) of the semiconductor substrate made of silicon carbide (hereinafter referred to as the silicon carbide substrate). The silicon carbide substrate (semiconductor chip) is made of n + Mold support substrate (hereinafter referred to as n + (The silicon carbide substrate is 102) n - The silicon carbide layers, which form the n-type drift layer 101, the n-type region 115 which is a current diffusion region, and the p-type base layer 116, are sequentially epitaxially grown.

[0009] n + An n-type drift layer 101 is epitaxially grown on an n-type silicon carbide substrate 102, and an n-type layer is epitaxially grown on the front surface (the surface on the side of the n-type drift layer 101) of the n-type silicon carbide substrate 102. A MOS gate structure including a p-type base layer 116, an n-type source region 117, a trench gate 131, a gate insulating film 119, and a gate electrode 120 is provided. Also, reference numerals 118, 121, and 122 denote a p-type contact region, an interlayer insulating film, and a source electrode, respectively. - 型ドリフト層101となるn - 型層をエピタキシャル成長させて、n + 型炭化珪素基板102のおもて面(n - 型ドリフト層101側の面)側に、p型ベース層116、n + 型ソース領域117、トレンチゲート131、ゲート絶縁膜119およびゲート電極120からなるMOSゲート構造が設けられている。また、符号118、121および122は、それぞれp ++ 型コンタクト領域、層間絶縁膜およびソース電極である。

[0010] In the n-type region 115, a first p-type region 103 is selectively provided so as to cover the entire bottom surface of the trench gate 131. Also, in the n-type region 115, a first p-type region 103 is selectively provided so as to cover the entire bottom surface of the trench SBD 132. The first p-type region 103 is provided at a depth that does not reach the n-type drift layer 101. Also, as shown in FIG. 18, in the edge region 142, a second p-type region 104 is provided on the entire surface of the first p-type region 103. + 型領域103が選択的に設けられている。また、n型領域115には、トレンチSBD132の底面全体を覆うように第1p + 型領域103が選択的に設けられている。第1p + 型領域103は、n - 型ドリフト層101に達しない深さで設けられている。また、図18に示すように、エッジ領域142では、第1p + 型領域103の全面上に第2p + 型領域104が設けられている。

[0011] Also, the trench SBD 132 is a trench in which the inner wall is covered with a Schottky metal 126 connected to the source electrode 122, and a Schottky contact is formed between the semiconductor region exposed on the inner wall and the Schottky metal 126. Thus, in FIG. 17, a parasitic Schottky diode (built-in SBD) is provided in parallel with a parasitic pn diode between the source and the drain.

[0012] It should be noted that the translation is based on the understanding of the original text. If there are specific requirements or corrections, please feel free to let me know.In a MOSFET with an integrated SBD on the same semiconductor substrate, the integrated SBD, which has a lower forward voltage than the parasitic diode (body diode) formed at the pn junction between the MOSFET's base region and drift region, operates preferentially during MOSFET switching operation. This reduces the reverse recovery loss of the parasitic diode.

[0013] A positive voltage is applied to the source electrode 122, n + When a negative voltage is applied to the drain electrode (not shown) provided on the back surface of the silicon carbide substrate 102 (when the MOSFET is off), the p-type base layer 116 and n - The pn junction between the MOSFET and the drift layer 101 is forward-biased. In Figure 17, by designing the parasitic Schottky diode to turn on before the parasitic pn diode turns on when the MOSFET is turned off, the bipolar operation of the parasitic pn diode can be suppressed, and degradation due to bipolar operation over time can be prevented.

[0014] Furthermore, a semiconductor device is known that includes a Schottky diode in its outer voltage-bearing portion, which has a trench and a Schottky electrode provided within the trench and electrically connected to a drift layer (see, for example, Patent Document 2 below). [Prior art documents] [Patent Documents]

[0015] [Patent Document 1] Japanese Patent Application Publication No. 8-204179 [Patent Document 2] Japanese Patent Publication No. 2012-79795 [Overview of the Initiative] [Problems that the invention aims to solve]

[0016] Here, as shown in Figure 18, in the connecting region 141, the first p + The second p is located on type region 103. + A mold region 104 is provided. In addition, the surface layer of the p-type base layer 116 is in contact with the trench SBD 132.++ A type contact region 118 is provided. Therefore, in the connecting region 141, the trench SBD 132 is surrounded by a p-type region (p-type base layer 116, p ++ Type contact area 118, 1p + Type region 103 and 2p + It has a structure enclosed by type region 104).

[0017] In the junction region 141, reverse recovery losses occur due to the parasitic pn diode. As a result, in the junction region 141, the trench SBD 132 does not function as a parasitic Schottky diode and cannot suppress the bipolar operation of the parasitic pn diode. When the parasitic pn diode is turned on and current is applied, the bipolar operation of the parasitic pn diode causes a Hall current to flow as shown in path D in Figure 18, and the energy generated by the recombination of the Hall current and electron current causes stacking faults to occur and expand.

[0018] Therefore, the bridging region 141 experiences changes in characteristics over time (aging degradation) due to the bipolar operation of the parasitic pn diode, resulting in issues such as forward degradation and increased turn-on losses, compared to the interior of the active region 140.

[0019] This invention aims to provide a semiconductor device that can reduce reverse recovery loss, forward voltage degradation, and turn-on losses in order to overcome the problems of the conventional technology described above. [Means for solving the problem]

[0020] To solve the above-mentioned problems and achieve the objectives of the present invention, the semiconductor device according to this invention has the following features: A first semiconductor layer of a first conductivity type with a lower impurity concentration than the semiconductor substrate is provided on the front surface of a first conductivity type semiconductor substrate. A second semiconductor layer of a second conductivity type is provided on the side of the first semiconductor layer opposite to the semiconductor substrate side. A first semiconductor region of a first conductivity type with a higher impurity concentration than the semiconductor substrate is selectively provided inside the second semiconductor layer. A first trench and a second trench are provided that penetrate the first semiconductor region and the second semiconductor layer and reach the first semiconductor layer. A gate electrode is provided inside the first trench via a gate insulating film. A Schottky electrode is provided inside the second trench. These are provided in an active region through which current flows when the device is ON. The second trench is also provided in a connecting region between the active region and an edge region that surrounds the active region and maintains its breakdown voltage. Polysilicon connected to the gate electrode is wired between the second trench provided in the connecting region and the second trench. The polysilicon is provided on the surface of the second semiconductor layer opposite to the semiconductor substrate side, via an insulating film.

[0021] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the longitudinal direction of the second trench provided in the connecting region is parallel to the longitudinal direction of the second trench provided in the active region.

[0022] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the longitudinal direction of the second trench provided in the connecting region is perpendicular to the longitudinal direction of the second trench provided in the active region.

[0023] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the spacing between the second trenches provided in the connecting region is greater than or equal to the spacing between the second trenches provided in the active region.

[0024] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the second trench provided in the connecting region is provided in multiple locations in the longitudinal direction of the second trench provided in the active region.

[0025] According to the invention described above, a trench SBD is placed in the junction region. This allows the trench SBD to function as a parasitic Schottky diode even in the junction region. Therefore, when a negative bias is applied to the drain side of a silicon carbide semiconductor device with a built-in SBD, the operation of the parasitic Schottky diode in the junction region can suppress the bipolar operation of the parasitic pn diode, thereby suppressing forward degradation and increased turn-on losses. By forming the SBD in a trench, the distance between the Schottky junction and the parasitic pn diode can be reduced, allowing for more effective suppression of the parasitic pn diode's operation. Furthermore, reverse recovery losses during MOSFET switching operation can be reduced. [Effects of the Invention]

[0026] The semiconductor device according to the present invention has the effect of reducing reverse recovery losses, forward voltage degradation, and turn-on losses. [Brief explanation of the drawing]

[0027] [Figure 1] This is a top view showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view of part 1 of Figure 1, showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 3] This is a cross-sectional view of part 2 of Figure 1, showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 4] This is a cross-sectional view of section 3 of Figure 1, showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 5] This is a cross-sectional view of section 4 of Figure 1, showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 6]This is a cross-sectional view of section 5 of Figure 1, showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 7] This is a top view showing the source electrode pad of a silicon carbide semiconductor device according to Embodiment 1. [Figure 8] This is a top view showing another structure of the silicon carbide semiconductor device according to Embodiment 1. [Figure 9] This is a cross-sectional view (part 1) showing the state of a silicon carbide semiconductor device during the manufacturing process according to Embodiment 1. [Figure 10] This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 11] This is a cross-sectional view (part 3) showing the silicon carbide semiconductor device in the process of being manufactured according to Embodiment 1. [Figure 12] This is a cross-sectional view (part 4) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 13] This is a cross-sectional view (part 5) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 14] This is a top view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 15] This is a top view showing the source electrode pad of a silicon carbide semiconductor device according to Embodiment 2. [Figure 16] This is a top view showing the structure of a conventional silicon carbide semiconductor device with a built-in SDB. [Figure 17] This is a cross-sectional view of the C-C' portion of Figure 16, which shows the structure of a conventional silicon carbide semiconductor device with a built-in SDB. [Figure 18] This is a cross-sectional view of the B-B' portion of Figure 16, which shows the structure of a conventional silicon carbide semiconductor device with a built-in SDB. [Modes for carrying out the invention]

[0028] Preferred embodiments of the semiconductor device according to this invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these prefixes. In the following description of embodiments and accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. In this specification, in the notation of Miller indices, "-" indicates a bar attached to the exponent immediately following it, and a "-" before the exponent indicates a negative exponent. Furthermore, it is preferable to include up to 5% variation when describing them as the same or equivalent, taking into account manufacturing variations.

[0029] (Embodiment 1) The semiconductor device according to the present invention is constructed using a semiconductor with a wider bandgap than silicon (hereinafter referred to as a wide-bandgap semiconductor). Here, the structure of a semiconductor device using silicon carbide (SiC) as the wide-bandgap semiconductor (silicon carbide semiconductor device) will be described as an example. Figure 1 is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 2 is a cross-sectional view of part 1 of Figure 1 showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 3 is a cross-sectional view of part 2 of Figure 1 showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 4 is a cross-sectional view of part 3 of Figure 1 showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 5 is a cross-sectional view of part 4 of Figure 1 showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 6 is a cross-sectional view of part 5 of Figure 1 showing the structure of the silicon carbide semiconductor device according to Embodiment 1. The cross-sectional view of the active region of the silicon carbide semiconductor device according to Embodiment 1 is the same as that of a conventional silicon carbide semiconductor device with a built-in SDB, so it is omitted from the description.

[0030] As shown in Figure 1, the silicon carbide semiconductor device 50 with a built-in SBD consists of an active region 40 through which the main current flows in the thickness direction of the substrate when the device structure is formed and the device is ON, an edge region 42 surrounding the active region 40 and maintaining the breakdown voltage, and a connecting region 41 between the active region 40 and the edge region 42. The active region 40 is the area enclosed by the black line in Figure 1. The connecting region 41 is the area where the side surface of the trench gate 31, which will be described later, is covered by a p-type region and does not function as a MOS, as shown in Figure 2. Figures 4 and 5 show only one unit cell (functional unit of the device), and other unit cells adjacent to them are omitted from the illustration. The silicon carbide semiconductor device according to the embodiment shown in Figures 1 to 6 is a MOSFET equipped with a MOS gate on the front side (the side facing the p-type base layer 16, which will be described later) of a semiconductor substrate (silicon carbide substrate: semiconductor chip) made of silicon carbide.

[0031] The silicon carbide substrate is made of n + n - Each silicon carbide layer, which will become a p-type drift layer (first semiconductor layer of the first conductivity type) 1 and a p-type base layer (second semiconductor layer of the second conductivity type) 16, is epitaxially grown in sequence. In the active region 40, the MOS gate consists of a p-type base layer 16 and n + It consists of a type source region (first semiconductor region of the first conductivity type) 17, a gate insulating film 19, and a gate electrode 20. Specifically, n - An n-type region 15 may be provided on the source side (source electrode 22 side, described later) of the type drift layer 1 so as to be in contact with the p-type base layer 16. The n-type region 15 is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. This n-type region 15 is provided uniformly in a direction parallel to the substrate surface (the surface of the silicon carbide substrate), for example.

[0032] n-type region 15 (If n-type region 15 is not provided, n - Inside the drift layer 1 (hereinafter referred to as (1)), the first p + Type region 3 is selectively provided. In the active region 40, the first p+ The n-type region 3 is provided so as to be in contact with the bottom surface of the trench gate (first trench) 31, which will be described later, and the bottom surface of the trench SBD (second trench) 32, which will be described later. In addition, the surface layer of the n-type region 15(1) has a second p + Type region 4 is selectively provided. 2p + Type region 4 has a base that is the first p + It is provided so as to be in contact with type region 3.

[0033] If an n-type region 15 is provided, the first p + Type region 3 is located deeper on the drain side than the interface between the p-type base layer 16 and the n-type region 15, and is connected to the n-type region 15 and n - It is provided at a depth that does not reach the interface with the mold drift layer 1. 1p + By providing mold region 3, the first p is located near the bottom surface of the trench gate 31 and trench SBD 32. + A pn junction can be formed between the n-type region 3 and the n-type region 15(1). + Type region 3 and 2p + Type region 4 has a higher impurity concentration than the p-type base layer 16.

[0034] Furthermore, inside the p-type base layer 16, n + A type source region (first semiconductor region of the first conductivity type) 17 is selectively provided. n are arranged in contact with each other. + Type source region 17 and p ++ Each type contact region 18 may be selectively provided. In this case, p ++ The depth of the type contact region 18 is, for example, n + It may be the same depth as the type source area 17, or n + The type source area may be deeper than 17.

[0035] As shown in Figure 1, the trench SBD32 and trench gate 31 are n + Silicon carbide substrate 2 The trench gates are arranged in a stripe pattern in the direction in which the crystal orientation is <11-20>. The trench gates 31 are located from the front surface of the substrate to n +The n-type region 15(1) is reached by penetrating the p-type source region 17 and the p-type base layer 16. Inside the trench gate 31, a gate insulating film 19 is provided along the side walls of the trench gate 31, and a gate electrode 20 is provided inside the gate insulating film 19. The source-side end of the gate electrode 20 may or may not protrude outward from the surface of the substrate. The gate electrode 20 is electrically connected to the gate electrode pad 45. The interlayer insulating film 21 is provided over the entire surface of the surface of the substrate so as to cover the gate electrode 20 embedded in the trench gate 31. Furthermore, since the trench gate 31 does not function as a MOS in the bridging region 41, the side walls and bottom surface of the trench gate 31 are first and second p + It is adjacent to type regions 3 and 4.

[0036] Trench SBD32 is located from the front surface of the substrate n + The n-type region 15(1) is reached by penetrating the p-type source region 17 and the p-type base layer 16. Inside the trench SBD 32, along the side walls of the trench SBD 32, there is a Schottky metal 26 that connects to the source electrode 22, forming a Schottky junction between the semiconductor region exposed on the inner wall and the Schottky metal 26. An oxide film, such as silicon dioxide (SiO2), may also be provided on the inside of the Schottky metal 26.

[0037] In the bridging region 41, a gate contact 43 is provided that electrically connects the trench gate 31 and the gate electrode pad 45, surrounding the active region 40. The trench gate 31 and the gate contact 43 are electrically connected by polysilicon 44 provided in the bridging region 41.

[0038] Here, as shown in Figure 1, the trench SBDs 32 are also arranged in the bridging region 41 with the same cell pitch as in the active region 40. In this way, the trench SBDs 32 have the effect of suppressing parasitic pn diode operation in the bridging region 41 as well as in the active region 40. For this reason, in Embodiment 1, characteristic degradation due to forward current can be suppressed throughout the entire chip. In addition, the spacing between the trench SBDs 32 arranged in the bridging region 41 may be the same as the spacing between the trench SBDs 32 arranged in the active region 40, but it may also be wider.

[0039] Additionally, polysilicon is placed between the trench SBD32 located in the connecting region 41. 44 The wires are connected, electrically linking the trench gate 31 to the gate contact 43 of the edge region 42. 44 The wiring is arranged to extend in a straight line from the end of the silicon carbide semiconductor device 50 with the built-in SBD to the gate contact 43. In this way, by keeping the path from the end of the trench SBD 32 of the silicon carbide semiconductor device 50 with the built-in SBD to the gate contact 43 simple, an increase in gate resistance can be prevented.

[0040] Furthermore, as shown in Figures 4 and 5, in the connecting region 41 as well, in order to suppress the breakdown voltage drop, the JFET width (adjacent 1st p) is reduced. + Width between type regions 3), 1p of the bottom of trench SBD32 + Type area 3, 2nd p + The layout of type region 4 is the same as that of active region 40.

[0041] The source electrode 22 is connected to the interlayer insulating film 21 via a contact hole opened in the interlayer insulating film 21. + It is in contact with the mold source region 17 and is electrically insulated from the gate electrode 20 by the interlayer insulating film 21. ++ When a type contact region 18 is provided, the source electrode 22 is p ++It also contacts the type contact region 18. A barrier metal may be provided between the source electrode 22 and the interlayer insulating film 21 to prevent the diffusion of metal atoms from the source electrode 22 to the gate electrode 20. A source electrode pad 46 is provided on the source electrode 22. Figure 7 is a top view showing the source electrode pad of a silicon carbide semiconductor device according to Embodiment 1. As shown in Figure 7, the source electrode pad 46 is provided on the active region 40 and the connecting region 41 on which the trench SBD 32 is located. The back surface (n + n becomes the type drain region + A drain electrode (not shown) is provided on the back surface of the silicon carbide substrate 1.

[0042] Figure 8 is a top view showing another structure of the silicon carbide semiconductor device according to Embodiment 1. In Figure 8, only a portion of the active region 40 and the connecting region 41 is shown. As shown in Figure 8, the trench SBD 32 of the connecting region 41 may be shortened and divided into multiple sections. In this case, polysilicon 44 is arranged between the multiple trench SBD 32 sections.

[0043] (Method of manufacturing a semiconductor device according to Embodiment 1) Next, a method for manufacturing a semiconductor device according to Embodiment 1 will be described. Figures 9 to 13 are cross-sectional views showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1. First, n + n becomes the type drain region + Prepare a silicon carbide substrate 2. Next, n + On the front surface of the silicon carbide substrate 2, the above-mentioned n - Type drift layer 1 is epitaxially grown. For example, n - The conditions for epitaxial growth to form type drift layer 1 are n - The impurity concentration in the drift layer 1 is 3 × 10 15 / cm 3 You may set it to a certain degree. The state up to this point is shown in Figure 9.

[0044] Next, n -On top of the drift layer 1, the lower n-type region 15a (if n-type region 15 is not formed, n - An n-type layer (hereinafter abbreviated as the n-type layer) with impurities of a similar degree to that of the drift layer 1 is epitaxially grown. For example, the conditions for epitaxial growth to form the lower n-type region 15a are such that the impurity concentration of the lower n-type region 15a is 1 × 10⁻⁶. 17 / cm 3 It may be set to the extent that this is the case. This lower n-type region 15a is part of the n-type region 15. Next, by photolithography and ion implantation of p-type impurities, the surface layer of the lower n-type region 15a (n-type layer) is implanted with the first p + Selectively forms type region 3. For example, the first p + The dose of ion implantation required to form type region 3 is determined when the impurity concentration is 5 × 10⁻⁶. 18 / cm 3 It may be set to the extent that it is. Similarly, in the connecting region 41 and the edge region 42, the first p + Type region 3 is selectively formed. The state up to this point is shown in Figure 10.

[0045] Next, the lower n-type region 15a (n-type layer), the first p + An upper n-type region 15b (n-type layer) is epitaxially grown on top of the n-type region 3. For example, the conditions for epitaxial growth to form the upper n-type region 15b may be set to be approximately the same as the impurity concentration of the lower n-type region 15a. This upper n-type region 15b is part of the n-type region 15, and together with the lower n-type region 15a, the upper n-type region 15b forms the n-type region 15. Next, by photolithography and ion implantation of p-type impurities, a second p-type impurity is implanted in the surface layer of the upper n-type region 15b (n-type layer). + Selectively forms type region 4. For example, 2p + The dose amount during ion implantation to form type region 4 is determined when the impurity concentration is 1p + It may be set to be similar to type region 3. (1st p) + Type region 3 and 2p + The region formed by combining type region 4 and the other region is designated as the 1st and 2nd p. + These are referred to as type regions 3 and 4. Similarly, in the connecting region 41 and edge region 42, the second p +The type 4 region is selectively formed. Second p + When forming the type 4 region, the side wall of the trench SBD32 in the connection region 41 is formed so as not to contact the second p + type 4 region. The state up to this point is described in FIG. 11.

[0046] Next, an epitaxial growth of a p-type base layer 16 is performed on the upper n-type region 15b and the second p + type 4 region. For example, the conditions for epitaxial growth for forming the p-type base layer 16 may be set so that the impurity concentration of the p-type base layer 16 is 4×10 17 / cm 3 or so.

[0047] Next, an n + type source region 17 is selectively formed on the surface layer of the p-type base layer 16 by photolithography and ion implantation of n-type impurities. For example, the dose amount during ion implantation for forming the n + type source region 17 may be set so that the impurity concentration is 3×10 20 / cm 3 or so.

[0048] Next, a p + type contact region 18 may be selectively formed on the surface layer of the p-type base layer 16 so as to contact the n ++ type source region 17 by photolithography and ion implantation of p-type impurities. For example, the dose amount during ion implantation for forming the p ++ type contact region 18 may be set so that the impurity concentration is 3×10 20 / cm 3 or so. The formation order of the n + type source region 17 and the p ++ type contact region 18 may be reversed. Next, a JTE region 43 is formed in the edge region 42 by photolithography and ion implantation of p-type impurities. After all the ion implantations are completed, an activation anneal is performed. The state up to this point is described in FIG. 12.

[0049] Next, by photolithography and etching, n + A trench gate 31 is formed that penetrates the p-type source region 17 and the p-type base layer 16 and reaches the n-type region 15(1). The bottom of the trench gate 31 is the first p + It may reach type region 3, or the p-type base layer 16 and the first p + It may be located within the n-type region 15(1) sandwiched between the mold regions 3. Next, the mask used to form the trench gate 31 is removed. An oxide film is used as the mask during trench formation. After trench etching, isotropic etching may be performed to remove damage to the trench gate 31, or hydrogen annealing may be performed to round the corners of the bottom and opening of the trench gate 31. Either isotropic etching or hydrogen annealing may be performed alone. Alternatively, hydrogen annealing may be performed after isotropic etching.

[0050] Next, by photolithography and etching, n + A trench SBD32 is formed that penetrates the p-type source region 17 and the p-type base layer 16 and reaches the n-type region 15(1). The bottom of the trench SBD32 is the first p + It may reach type region 3, or the p-type base layer 16 and the first p + It may be located within the n-type region 15(1) sandwiched between the mold regions 3. Next, the mask used to form the trench SBD 32 is removed. At this time, the trench SBD 32 is also formed in the connecting region 41. The state up to this point is shown in Figure 13.

[0051] Next, a gate insulating film 19 is formed along the front surface of the silicon carbide substrate and the inner wall of the trench gate 31. Then, polysilicon is deposited, for example, so as to be embedded in the trench gate 31 and etched to leave polysilicon that will become the gate electrode 20 inside the trench gate 31. At this time, etching may be performed to leave the polysilicon inside the substrate surface, or patterning and etching may be performed so that the polysilicon protrudes outside the substrate surface.

[0052] Next, an interlayer insulating film 21 is formed on the entire surface of the silicon carbide substrate so as to cover the gate electrode 20. The interlayer insulating film 21 is formed from, for example, NSG (None-doped Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), HTO (High Temperature Oxide), or a combination thereof. Next, the interlayer insulating film 21 and the gate insulating film 19 are patterned to form a contact hole, n + Expose the type source region 17. ++ When a type contact region 18 is formed, n + Type source region 17 and p ++ The contact area 18 is exposed.

[0053] Next, a barrier metal is formed and patterned to cover the interlayer insulating film 21, n + Type source region 17 and p ++ The contact area 18 is exposed again. Next, n + A source electrode 22 is formed so as to be in contact with the mold source region 17. The source electrode 22 may be formed to cover the barrier metal, or it may be left only within the contact hole.

[0054] Next, a metal film is formed along the inner wall of the trench SBD32, for example, using titanium (Ti). Then, a Schottky junction is formed between the metal film and the semiconductor region on the inner wall of the trench SBD32 by heat treatment (annealing) in a nitrogen (N2) atmosphere at a temperature of approximately 500°C or less.

[0055] Next, a source electrode pad is formed to fill the contact hole. A portion of the metal layer deposited to form the source electrode pad may also be used as the gate electrode pad. +On the back surface of the silicon carbide substrate 2, a metal film such as a nickel (Ni) film or a titanium (Ti) film is formed in the contact area of ​​the drain electrode using sputter deposition or the like. This metal film may be a combination of multiple Ni and Ti films stacked together. Subsequently, annealing such as rapid thermal annealing (RTA) is performed so that the metal film silicides and forms an ohmic contact. After that, a thick film, such as a multilayer film in which a Ti film, Ni film, and gold (Au) are stacked in order, is formed by electron beam (EB) deposition or the like to form the drain electrode.

[0056] In the epitaxial growth and ion implantation described above, n-type impurities (n-type dopants) can be, for example, nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb), which are n-type relative to silicon carbide. For p-type impurities (p-type dopants), for example, boron (B), aluminum (Al), gallium (Ga), indium (In), or thallium (Tl), which are p-type relative to silicon carbide, can be used. In this way, the MOSFETs shown in Figures 1 to 6 are completed.

[0057] As described above, according to Embodiment 1, a trench SBD is placed in the junction region. This allows the trench SBD to function as a parasitic Schottky diode even in the junction region. Therefore, when a negative bias is applied to the drain side of the silicon carbide semiconductor device with an SBD, the operation of the parasitic Schottky diode in the junction region can suppress the bipolar operation of the parasitic pn diode, thereby suppressing forward degradation and increased turn-on loss.

[0058] (Embodiment 2) Next, Embodiment 2 will be described. Figure 14 is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. The difference between the silicon carbide semiconductor device according to Embodiment 2 and the silicon carbide semiconductor device according to Embodiment 1 is that the longitudinal direction of the trench SBD32 provided in the connecting region 41 is perpendicular to the longitudinal direction of the trench SBD32 located in the active region 40.

[0059] Furthermore, the spacing between trench SBDs 32 located in the bridging region 41 may be the same as the spacing between trench SBDs 32 located in the active region 40, but it may also be wider. In Embodiment 2, the trench SBDs 32 also provide the effect of suppressing parasitic pn diode operation in the bridging region 41, similar to the active region 40. Therefore, in Embodiment 2, characteristic degradation due to forward current flow can be suppressed across the entire chip.

[0060] Furthermore, if the trench SBD32 provided in the longitudinal direction of the trench gate 31 is made longer, it will become impossible to connect the polysilicon 44 and the trench gate 31. Therefore, it is preferable that the length of the trench SBD32 be shorter than the distance between the trench gates 31.

[0061] On the other hand, the trench SBD32 provided perpendicular to the longitudinal direction of the trench gate 31 may be long as shown in Figure 14, but it may also be shorter and divided into multiple sections. In this case, polysilicon 44 is placed between the multiple trench SBD32.

[0062] Figure 15 is a top view showing the source electrode pad of a silicon carbide semiconductor device according to Embodiment 2. In Embodiment 2, as in Embodiment 1, the source electrode pad 46 is provided on an active region 40 and a connecting region 41 on which a trench SBD 32 is located.

[0063] The semiconductor device manufacturing method according to Embodiment 2 can be manufactured by changing the longitudinal direction of the trench SBD32 located in the connecting region 41 in the semiconductor device manufacturing method according to Embodiment 1. For this reason, a detailed explanation of the semiconductor device manufacturing method according to Embodiment 2 will be omitted.

[0064] As described above, according to Embodiment 2, the trench SBD32 is arranged in the connecting region 41. This provides the same effects as in Embodiment 1.

[0065] As described above, the present invention can be modified in various ways without departing from the spirit of the invention, and in each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, etc. can be set in various ways according to the required specifications. Furthermore, although the embodiments described above use MOSFETs as examples, the present invention is not limited to MOSFETs and can be broadly applied to various silicon carbide semiconductor devices that conduct and interrupt current by gate drive control based on a predetermined gate threshold voltage. Examples of silicon carbide semiconductor devices that are gate drive controlled include IGBTs (Insulated Gate Bipolar Transistors). Furthermore, although the embodiments described above use silicon carbide as the wide-bandgap semiconductor as an example, the present invention can also be applied to wide-bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Furthermore, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present invention can be similarly applied even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial applicability]

[0066] As described above, the semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable as a silicon carbide semiconductor device with a trench gate structure. [Explanation of Symbols]

[0067] 1, 101 n - Type drift layer 2, 102 n + Silicon carbide substrate 3, 103 1st p. + type area 4, 104 2nd p. + type area 5 p + type area 15, 115 n-type region 15a Lower n-type region 15b Upper n-type region 16, 116 p-type base layer 17, 117 n + Type source area pp. 18, 118 ++ Type Contact Area 19, 119 Gate insulating film 20, 120 gates 21, 121 Interlayer insulating film 22, 122 Source electrodes 26, 126 Schottky metal 31, 131 Trench Gate 32, 132 Trench SBD 40, 140 active area 41, 141 Transition Area 42, 142 edge regions 43, 143 gate contacts 44, 144 Polysilicon 45, 145 Token Pads Silicon carbide semiconductor device with 50 and 150 SBDs

Claims

1. A first-type conductive semiconductor substrate and A first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate is provided on the front surface of the semiconductor substrate, A second semiconductor layer of a second conductivity type is provided on the side of the first semiconductor layer opposite to the semiconductor substrate side, A first semiconductor region of a first conductivity type having a higher impurity concentration than the semiconductor substrate is selectively provided inside the second semiconductor layer, A first trench and a second trench that penetrate the first semiconductor region and the second semiconductor layer and reach the first semiconductor layer, A gate electrode is provided inside the first trench via a gate insulating film, A Schottky electrode provided inside the second trench, When it is in the ON state, it is provided with an active region through which current flows, The second trench is also provided in the connecting region between the active region and the edge region that surrounds the active region and maintains pressure resistance. A polysilicon wire connected to the gate electrode is routed between the second trench and the second trench provided in the connecting region. The semiconductor device is characterized in that the polysilicon is provided on the surface of the second semiconductor layer opposite to the semiconductor substrate side, via an insulating film.

2. The semiconductor device according to claim 1, characterized in that the longitudinal direction of the second trench provided in the connecting region is parallel to the longitudinal direction of the second trench provided in the active region.

3. The semiconductor device according to claim 1, characterized in that the longitudinal direction of the second trench provided in the connecting region is perpendicular to the longitudinal direction of the second trench provided in the active region.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that the distance between the second trenches provided in the connecting region is greater than or equal to the distance between the second trenches provided in the active region.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that the second trench provided in the connecting region is provided in a plurality in the longitudinal direction of the second trench provided in the active region.

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