Silicon carbide semiconductor equipment

Abstract

To provide a silicon carbide semiconductor device capable of improving breakdown resistance.SOLUTION: A drift layer has an SJ construction which is a parallel pn layer 3 formed by an n-type column region and a p-type column region 32 from an active region 10 to an edge termination end region 20. In the active region 10, the p-type column region 32 is constructed by: a long p-type column region 32a of which a length Dp1 of a depth direction Z is similar to the n-type column region; and a short p-type column region 32b of which a length Dp2 of a depth direction Z is shorter than the length p-type column region 32a. A space between the short p-type column region 32b and a n-type buffer region 2 is a n-type column region 33. In the active region 10, the parallel pn layer 3 relatively becomes p-rich on a front surface side of a semiconductor substrate 40 by the short p-type column region 32b, and relatively becomes n-rich on a back surface side of the semiconductor substrate 40 by the n-type column region 33.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field-effect transistors with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) are known, which have a superjunction (SJ) structure in which the drift layer is a parallel pn layer formed by alternately arranging n-type and p-type regions adjacent to each other in a first direction parallel to the main surface of the semiconductor substrate.

[0003] By making the drift layer an SJ structure, n - Compared to a conventional drift layer composed only of mold regions, the impurity concentration of the drift layer can be increased, significantly reducing on-resistance. Furthermore, by using an SJ structure for the drift layer, the increase in on-resistance during high-temperature operation is suppressed. High-temperature operation refers to the operation of a semiconductor device when the semiconductor substrate (semiconductor chip) is at a high temperature due to a high-temperature environment, high voltage application, or high current flow.

[0004] Figure 15 is a plan view showing the layout of a conventional silicon carbide semiconductor device as seen from the front side of the semiconductor substrate. In Figure 15, the number of n-type column regions 131 and p-type column regions 132 is simplified and differs from that in Figure 16. Figures 16-18 are cross-sectional views showing the cross-sectional structure at the cutting lines AA-AA', BB-BB', and CC-CC' in Figure 15, respectively. In Figures 15, 16, and 18, the p-type column regions 132 are indicated by hatching.

[0005] The conventional silicon carbide semiconductor device 150 shown in Figures 15-18 is a trench gate type SiC-MOSFET with an SJ structure, comprising a parallel pn layer 103 acting as a drift layer inside a semiconductor substrate 140 made of silicon carbide (SiC) as the semiconductor material. The semiconductor substrate 140 is made of n +The material is formed by sequentially epitaxially growing parallel pn layers 103 and p-type base regions 104, respectively, on a starting substrate 141.

[0006] The parallel pn layer 103 is formed by alternately arranging n-type regions (hereinafter referred to as n-type column regions) 131 and p-type regions (hereinafter referred to as p-type column regions) 132 adjacent to each other in a first direction X parallel to the main surface of the semiconductor substrate 140. The n-type column regions 131 and p-type column regions 132 extend in a stripe-like manner across the entire area of ​​the semiconductor substrate 140 in a second direction Y parallel to the main surface of the semiconductor substrate 140 and perpendicular to the first direction X.

[0007] The drift layer in both the active region 110 and the edge-terminal region 120 is composed of the same SJ structure. The widths Wn101 and Wp101 of the n-type column region 131 and the p-type column region 132 are uniform in the second direction Y from the active region 110 to the edge-terminal region 120, and are also uniform in the depth direction Z. The width (short-side width) Wn101 of the n-type column region 131 and the width Wp101 of the p-type column region 132 are approximately the same.

[0008] The length Dn101 in the depth direction Z of the n-type column region 131 and the length Dp101 in the depth direction Z of the p-type column region 132 are uniform in the second direction Y from the active region 110 to the edge-terminal region 120. The length Dn101 in the depth direction Z of the n-type column region 131 and the length Dp101 in the depth direction Z of the p-type column region 132 are approximately the same. The impurity concentration of the n-type column region 131 and the impurity concentration of the p-type column region 132 are approximately the same.

[0009] The lengths Dn101 and Dp101 in the depth direction Z of the n-type column region 131 and the p-type column region 132 are the lengths of the n-type column region 131 and the p-type column region 132, respectively. + This is the length from the interface with type regions 111 and 112 to the interface with type n buffer region 102. Approximately the same width, approximately the same depth, and approximately the same impurity concentration mean that they are the same width, the same depth, and the same impurity concentration, respectively, within a range that includes tolerances due to process variations.

[0010] The adjacent n-type column regions 131 and p-type column regions 132 maintain approximately charge balance over the entire semiconductor substrate 140. Charge balance is an index indicating the degree of balance between the charge amount represented by the product of the carrier concentration and width Wn101 of the n-type column region 131 and the charge amount represented by the product of the carrier concentration and width Wp101 of the p-type column region 132.

[0011] In the edge termination region 120, a breakdown voltage structure 121 is disposed between the front surface of the semiconductor substrate 140 and the parallel pn layer 103. In a SiC-MOSFET, it is known that a double-zone junction termination extension (JTE) structure is used as the breakdown voltage structure 121. FIGS. 16 to 18 show the case where a double-zone JTE structure is disposed as the breakdown voltage structure 121.

[0012] The JTE structure is a structure in which a plurality of p-type regions having different impurity concentrations are arranged adjacent to each other concentrically surrounding the active region 110 such that the p-type region having a lower impurity concentration is arranged further away from the active region 110 toward the outside (the end portion (chip end portion) side of the semiconductor substrate 140). The double-zone JTE structure is a JTE structure composed of two p-type regions (p - -type region 122, p -- -type region 123) having different impurity concentrations.

[0013] p + -type regions 111 and 112 are selectively provided on the n + -type drain region 101 side rather than the bottom surface of the gate trench 107 between the parallel pn layer 103 and the p-type base region 104, respectively. The p + -type regions 111 and 112 have a function of relaxing the electric field applied to the gate insulating film 108 on the bottom surface of the gate trench 107. The p + -type regions 111 and 112 are adjacent to the n-type column region 131 and the p-type column region 132 in the depth direction Z, respectively.

[0014] The n-type buffer area 102 is n + Type drain region 101(n + These regions are provided between the n-type starting substrate 141) and the parallel pn layer 103, in contact with these regions. Figures 16-18 show the interface between the n-type buffer region 102 and the parallel pn layer 103 with dashed lines. Reference numerals 105, 106, 109, 114-116 indicate n + Type source area, p ++ These are the contact region, gate electrode, interlayer insulating film, source electrode, and drain electrode.

[0015] As a conventional SJ structure SiC-MOSFET, a device has been proposed in which the n-type column region and p-type column region of the parallel pn layer that serve as the drift layer extend in a stripe-like manner from the active region to the edge termination region, and the p-type column region has a long p-type column region provided to a depth that reaches the n-type buffer region, and a short p-type column region provided to a depth that does not reach the n-type buffer region (see, for example, Patent Document 1 below).

[0016] In Patent Document 1 below, the depth of the p-type column region is made shallower at predetermined intervals in the longitudinal direction, thereby partially arranging short p-type column regions in the active region. The short p-type column regions make the drift layer of the active region n-rich (a state in which the amount of n-type impurities is greater than the amount of p-type impurities), thereby reducing the on-resistance. In addition, the short p-type column regions guide the avalanche generation site to a depth position away from the channel (n-type inversion layer), thereby improving avalanche tolerance.

[0017] As a conventional SiC-MOSFET with a different SJ structure, a device has been proposed in which the n-type column region and p-type column region of the parallel pn layer that serve as the drift layer extend in a stripe shape outward from the active region (towards the edge of the semiconductor substrate), and the depth of each of the n-type column region and p-type column region in the boundary region between the active region and the edge termination region becomes shallower in a stepwise manner towards the outside (see, for example, Patent Document 2 below).

[0018] In the following Patent Document 2, the n-type column region and the p-type column region are adjacent to the outside of the parallel pn layer.- Instead of causing the charge balance disruption due to contact with the high-resistance region to occur at the same location across the entire depth direction parallel to the surface of the semiconductor substrate, the disruption occurs inward (towards the center of the semiconductor substrate) as the depth increases from the surface of the semiconductor substrate, thus distributing the disruption in a stepped manner along the depth direction and suppressing the decrease in breakdown voltage. [Prior art documents] [Patent Documents]

[0019] [Patent Document 1] Japanese Patent Publication No. 2020-191441 [Patent Document 2] Japanese Patent Publication No. 2007-335844 [Overview of the project] [Problems that the invention aims to solve]

[0020] However, as mentioned above, in conventional SJ structure SiC-MOSFETs (see Figures 15-18), the drift layer is composed of the same SJ structure (n-type column region 131 and p-type column region 132) in both the active region 110 and the edge termination region 120. As a result, the breakdown voltage of the edge termination region 120 is lower than that of the active region 110, making it prone to avalanche breakdown in the edge termination region 120. This leads to the problem that the breakdown withstand voltage is lower compared to the case where avalanche breakdown occurs in the active region 110, which has a large area occupying most of the surface area of ​​the semiconductor substrate 140.

[0021] The purpose of this invention is to provide a silicon carbide semiconductor device that can improve fracture resistance in order to solve the problems of the conventional technology described above. [Means for solving the problem]

[0022] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features: A semiconductor substrate made of silicon carbide is provided with an active region and a termination region surrounding the active region. A parallel pn layer is provided inside the semiconductor substrate. The parallel pn layer is formed by alternately and repeatedly arranging a first conductivity type column region and a second conductivity type column region adjacent to each other in a first direction parallel to the first main surface of the semiconductor substrate. A predetermined element structure is provided between the first main surface and the parallel pn layer. A first electrode is provided on the first main surface and electrically connected to the element structure. A second electrode is provided on the second main surface of the semiconductor substrate.

[0023] The first conductivity type column region and the second conductivity type column region extend in a stripe-like manner from the active region to the terminal region in a second direction parallel to the first main surface and perpendicular to the first direction. The impurity concentration in the first conductivity type column region is uniform from the active region to the terminal region. The impurity concentration in the second conductivity type column region is the same as that of the first conductivity type column region and is uniform from the active region to the terminal region. The second conductivity type column region has a short column region in the active region that extends linearly in the second direction and has a shorter length in the depth direction than the other parts. The parallel pn layer is, The short column region and the other portion are regularly arranged throughout the entire active region. A first conductivity type region is located between the short column region and the second main surface, and in the active region, it is relatively p-rich on the first main surface side and relatively n-rich on the second main surface side. The volume of the second conductivity type column region is the total volume of the first conductivity type column region and the first conductivity type region. 50% or more and 70% or less That is the case.

[0024] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the portion of the parallel pn layer on the second main surface side is n-richer in the active region than in the termination region.

[0025] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the short column region is provided in the active region and the termination region, and the length in the depth direction of the active region is shorter than that of the termination region.

[0026] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the above-described invention, the parallel pn layer is relatively p-rich on the first main surface side and relatively n-rich on the second main surface side in the termination region.

[0027] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the second conductivity type column region is formed by repeatedly arranging the short column region and the other portion adjacent to each other in the second direction.

[0028] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the second conductivity type column region is made up of two or more short column regions of different lengths in the depth direction and the other portion arranged regularly in the second direction within the active region.

[0029] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the short column region is adjacent to the short column region of another second conductivity type column region in the first direction.

[0030] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the short column region is adjacent to the other portion of the other second conductivity type column region in the first direction.

[0031] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the other portion of the second conductivity type column region has a narrower width in the short-side direction on the second main surface side than on the first main surface side.

[0032] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, it further comprises a first conductivity type high-concentration region having a higher impurity concentration than the first conductivity type column region, which is provided at the end of the second main surface side of the second conductivity type column region.

[0033] Furthermore, the silicon carbide semiconductor device according to this invention, in the invention described above, the depth direction of the other portion of the second conductivity type column region length The depth direction of the first conductivity type column region length It is characterized by being the same as [the other characteristic].

[0034] Furthermore, in the silicon carbide semiconductor device according to this invention, the device structure comprises a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type, a trench, a gate electrode, a first high-concentration region of a second conductivity type, and a second high-concentration region of a second conductivity type. The first semiconductor region is provided between the first main surface and the parallel pn layer. The second semiconductor region is selectively provided between the first main surface and the first semiconductor region. The trench penetrates the second semiconductor region and the first semiconductor region to reach the first conductivity type column region. The gate electrode is provided inside the trench via a gate insulating film. The first high-concentration region of a second conductivity type is provided between the bottom surface of the trench and the first conductivity type column region, separated from the first semiconductor region.

[0035] The first high-concentration region of the second conductivity type has a higher impurity concentration than the first semiconductor region. The second high-concentration region of the second conductivity type is provided between the first semiconductor region and the second conductivity type column region, in contact with the first semiconductor region and the second conductivity type column region, and separated from the trench and the first high-concentration region of the second conductivity type. The second high-concentration region of the second conductivity type has a higher impurity concentration than the first semiconductor region. The first electrode is electrically connected to the second semiconductor region and the first semiconductor region. The length in the depth direction of the short column region is longer than the length in the depth direction of the first high-concentration region of the second conductivity type.

[0036] According to the invention described above, the breakdown voltage of the active region can be made lower than that of the edge termination region, so avalanche yielding can be performed in the large active region that occupies most of the surface area of ​​the semiconductor substrate. [Effects of the Invention]

[0037] The silicon carbide semiconductor device according to the present invention has the effect of improving fracture resistance. [Brief explanation of the drawing]

[0038] [Figure 1] This is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. [Figure 2] This is a cross-sectional view showing the cross-sectional structure along the cutting line A1-A1' in Figure 1. [Figure 3] This is a cross-sectional view showing the cross-sectional structure along the cutting line A2-A2' in Figure 1. [Figure 4] This is a cross-sectional view showing the cross-sectional structure along the cutting line B-B' in Figure 1. [Figure 5] This is a cross-sectional view showing the cross-sectional structure at the cutting line C-C' in Figure 1. [Figure 6] This is a cross-sectional view showing another example of the cross-sectional structure of the active region (the portion between C1 and C2) at the cutting line C-C' in Figure 1. [Figure 7] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 8] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 9] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 3. [Figure 10] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 3. [Figure 11] This is a cross-sectional view showing another example of a silicon carbide semiconductor device according to Embodiment 3. [Figure 12A]This is a cross-sectional view showing another example of a silicon carbide semiconductor device according to Embodiment 3. [Figure 12B] This is a cross-sectional view showing another example of a silicon carbide semiconductor device according to Embodiment 3. [Figure 13] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 4. [Figure 14] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 4. [Figure 15] This is a plan view showing the layout of a conventional silicon carbide semiconductor device as seen from the front side of the semiconductor substrate. [Figure 16] Figure 15 is a cross-sectional view showing the cross-sectional structure along the cutting line AA-AA'. [Figure 17] Figure 15 is a cross-sectional view showing the cross-sectional structure along the cutting line BB-BB'. [Figure 18] Figure 15 is a cross-sectional view showing the cross-sectional structure along the cutting line CC-CC'. [Modes for carrying out the invention]

[0039] Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0040] (Embodiment 1) The structure of the silicon carbide semiconductor device according to Embodiment 1 will now be described. Figure 1 is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. In Figure 1, the number of n-type column regions 31 and p-type column regions 32 of the parallel pn layer 3 is simplified and differs from that in Figures 2 and 3. Figures 2 to 5 are cross-sectional views showing the cross-sectional structure at the cutting lines A1-A1', A2-A2', B-B', and C-C' in Figure 1, respectively. Figures 2 and 3 show cross-sections of p-type column regions 32 (32a, 32b) with different lengths Dp1 and Dp2 in the depth direction Z, respectively, as seen from the second direction Y (longitudinal direction).

[0041] Figures 4 and 5 show cross-sections of the n-type column region 31 and the p-type column region 32, respectively, viewed from the first direction X (short side). Figure 6 is a cross-sectional view showing another example of the cross-sectional structure of the active region (the portion between C1 and C2) at the cutting line C-C' in Figure 1. In Figure 6, the number of n-type column regions 31 and p-type column regions 32 in the parallel pn layer 3 is simplified and differs from that in Figure 5. In Figures 1-3, 5, and 6, the p-type column region 32 is shown with hatching (the same applies in Figures 7-14). Figures 2-6 show some of the unit cells (elementary components) of multiple unit cells with the same structure that are arranged adjacent to the active region 10 (the same applies in Figures 7-14).

[0042] The silicon carbide semiconductor device 50 according to Embodiment 1 shown in Figures 1 to 5 is a vertical MOSFET with an SJ structure, in which a general trench gate structure (device structure) is provided on the front side (first main surface) of the semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC) in the active region 10, and the drift layer (drift region) is a parallel pn layer 3. As shown in Figure 1, the active region 10 is the region in which the main current flows when the MOSFET is ON, and is located approximately in the center of the semiconductor substrate 40 (center of the chip). In the active region 10, the trench gate structure is arranged between the front surface of the semiconductor substrate 40 and the parallel pn layer 3.

[0043] The edge termination region 20 is the region between the active region 10 and the edge (chip edge) of the semiconductor substrate 40, and surrounds the active region 10. The edge termination region 20 mitigates the electric field on the front side of the semiconductor substrate 40 of the drift layer in the active region 10, thereby maintaining the breakdown voltage. Breakdown voltage is the limit voltage at which leakage current does not increase excessively and the element does not malfunction or break down. The active region 10 is located inside (towards the center of the chip) the outermost gate trench 7 (7a) (see Figures 2 and 3) in the first direction X, and in the second direction Y n + This is the portion inside the edge (not shown) of type source region 5 (see Figures 2 and 3).

[0044] In the edge termination region 20, a breakdown voltage structure 21 (see Figures 2-5) such as a field limiting ring (FLR), mesa structure, junction termination extension (JTE) structure, or field plate is placed between the front surface of the semiconductor substrate 40 and the parallel pn layer 3. Figures 2-5 show a case where almost the entire front surface of the semiconductor substrate 40 in the edge termination region 20 is covered with an interlayer insulating film 14, and a double-zone structure is placed as the breakdown voltage structure 21.

[0045] FLR is a structure in which multiple p-type regions are arranged concentrically around the active region 10, spaced apart from each other. JTE is a structure in which multiple p-type regions with different impurity concentrations are arranged concentrically around the active region 10, adjacent to each other, such that the p-type regions with lower impurity concentrations are located further out from the active region 10. Double-zone JTE is a structure in which two p-type regions with different impurity concentrations (as described later) - type region 22, p -- This is a JTE structure composed of type region 23 (see Figures 2-5).

[0046] The cross-sectional structure of the drift layer's SJ structure differs between the active region 10 and the edge termination region 20. The parallel pn layer 3 is formed by alternately arranging n-type regions (hereinafter referred to as n-type column regions (first conductivity type column regions)) 31 and p-type regions (hereinafter referred to as p-type column regions (second conductivity type column regions)) 32 adjacent to each other in a first direction X parallel to the main surface of the semiconductor substrate 40. The n-type column regions 31 and p-type column regions 32 extend in a stripe-like manner across almost the entire area of ​​the semiconductor substrate 40 in a second direction Y parallel to the main surface of the semiconductor substrate 40 and perpendicular to the first direction X.

[0047] The outermost part of the parallel pn layer 3 in the first direction X is the p-type column region 32. The width Wn1 of the n-type column region 31 in the short direction (first direction X) and the width Wp1 of the p-type column region 32 in the short direction are uniform from the active region 10 to the edge-terminal region 20 (Figure 1), and are also uniform in the depth direction Z (see Figures 2-5). The width Wn1 of the n-type column region 31 in the short direction and the width Wp1 of the p-type column region 32 in the short direction are approximately the same. The adjacent n-type column region 31 and p-type column region 32 extend in the long direction (second direction Y) with approximately the same length.

[0048] The impurity concentration in the n-type column region 31 is uniform from the active region 10 to the edge-terminal region 20. The impurity concentration in the p-type column region 32 is uniform from the active region 10 to the edge-terminal region 20. The impurity concentration in the n-type column region 31 and the impurity concentration in the p-type column region 32 are approximately the same. Approximately the same width, approximately the same depth, and approximately the same impurity concentration means that they are the same width, the same depth, and the same impurity concentration, respectively, within a range that includes tolerances due to process variations.

[0049] As shown in Figures 2-5, the semiconductor substrate 40 is made of n + The semiconductor substrate 40 is formed by sequentially depositing a drift layer and epitaxial layers 42 and 43, which will become the p-type base region 4, on the front surface of the starting substrate 41. The main surface of the p-type epitaxial layer 43 is the front surface of the n + The main surface on the mold starting substrate 41 side is designated as the back surface (second main surface). +The starting substrate 41 is n + This is the n-type drain region 1. The drift layer (n-type epitaxial layer 42) consists of a p-type base region 4 and n + These regions are provided in contact with the drain region 1.

[0050] The drift layer, at least the surface region on the front side of the semiconductor substrate 40, is a parallel pn layer 3. As described above, the parallel pn layer 3 is an SJ structure in which n-type column regions 31 and p-type column regions 32 are alternately and repeatedly arranged adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 40. + The portion between the n-type drain region 1 and the n-type column region 31 may be an n-type buffer region (an n-type region that is not an SJ structure) 2. The impurity concentration in the n-type buffer region 2 is less than or equal to the impurity concentration in the n-type column region 31.

[0051] The n-type column region 31 has an n-type buffer region 2 in the depth direction Z (if n-type buffer region 2 is not provided, then n + It reaches the n-type drain region 1). The length Dn1 in the depth direction Z of the n-type column region 31 is uniform throughout the active region 10 and the edge termination region 20. In the active region 10, the length Dn1 in the depth direction Z of the n-type column region 31 is the length of the n-type column region 31 directly below the gate trench 7 (described later). + p (on the drain region 1 side) + From the interface with type region 11, n-type buffer region 2 (if n-type buffer region 2 is not provided, n + This is the length to the interface with the type drain region 1).

[0052] In the edge termination region 20, the length Dn1 in the depth direction Z of the n-type column region 31 is the pressure-resistant structure 21(p - type region 22, p -- Type region 23) or p described later + From the interface with the extended part 11a, the n-type buffer region 2 (if the n-type buffer region 2 is not provided, then n + This is the length to the interface with the n-type drain region 1). The width Wn1 in the shorter direction of the n-type column region 31 is p +It is wider than the width in the short direction of the type region 11. The n-type column region 31 is between the p gate trenches 7 adjacent to each other, as will be described later. + It may be in contact with type region 12.

[0053] The p-type column region 32 has a portion (hereinafter referred to as the short p-type column region) 32b that extends linearly in the second direction Y in the active region 10, and its length Dp2 in the depth direction Z is shorter than that of the other portion (hereinafter referred to as the long p-type column region) 32a. The long p-type column region 32a has an n-type buffer region 2 in the depth direction Z (if the n-type buffer region 2 is not provided, then n + The drain region 1) is reached. The length Dp1 in the depth direction Z of the long p-type column region 32a is approximately the same as the length Dn1 in the depth direction Z of the n-type column region 31.

[0054] The short p-type column region 32b has an n-type buffer region 2 in the depth direction Z (if an n-type buffer region 2 is not provided, then n + The drain region 1) has not been reached. The short p-type column regions 32b are scattered in the second direction Y in the active region 10. The short p-type column regions 32b may be arranged adjacent to the short p-type column regions 32b of other p-type column regions 32 in the first direction X (see Figure 3), or adjacent to the long p-type column regions 32a of other p-type column regions 32 in the first direction X (not shown).

[0055] Between the short p-type column region 32b and the n-type buffer region 2, an n-type column region 33 is provided, adjacent to these regions, the long p-type column region 32a, and the n-type column region 31. The n-type column region 33 constitutes a parallel pn layer 3. The impurity concentration in the n-type column region 33 is uniform and approximately the same as that of the n-type column region 31. Both the length Dp1 in the depth direction Z of the long p-type column region 32a and the length Dp2 in the depth direction Z of the short p-type column region 32b are p directly below the gate trench 7. + It is longer than the length Dp3 in the depth direction Z of the mold region 11.

[0056] In the active region 10, the length Dp1 in the depth direction Z of the long p-type column region 32a is the length of the p between adjacent gate trenches 7, which will be described later. + From the interface with type region 12, n-type buffer region 2 (if n-type buffer region 2 is not provided, then n + This is the length to the interface with the type drain region 1). The length Dp2 in the depth direction Z of the short p-type column region 32b is the length of the short p-type column region 32b, p + This is the length from the interface with the type region 12 to the interface with the n-type column region 33.

[0057] In the edge termination region 20, the length Dp1 in the depth direction Z of the long p-type column region 32a is the pressure-resistant structure 21 or p of the long p-type column region 32a. + From the interface with the extended part 11a, the n-type buffer region 2 (if the n-type buffer region 2 is not provided, then n + This is the length to the interface with the p-type drain region 1). The width Wp1 (Wp1-1, Wp1-2) in the short direction of the p-type column region 32 is p + The width of the type region 12 in the shorter direction may be approximately the same as p + The length Dp3 in the depth direction Z of the type region 11 is p + Upper end of type region 11 (n + From the end of the source region 5 side to the lower end (n + This is the length to the end of the drain region 1 side.

[0058] The long p-type column region 32a and the short p-type column region 32b are arranged alternately and repeatedly adjacent to each other in the second direction Y within the active region 10 (see Figure 5). The upper end of the long p-type column region 32a and the upper end of the short p-type column region 32b are located at approximately the same depth. The lower end of the long p-type column region 32a is n greater than the lower end of the short p-type column region 32b. + It reaches a deep position on the drain region 1 side. The width Wp1-1 in the short direction of the long p-type column region 32a and the width Wp1-2 in the short direction of the short p-type column region 32b are approximately the same.

[0059] The longitudinal width Wp11 of the long p-type column region 32a can be set as appropriate and may be approximately the same as the longitudinal width Wp12 of the short p-type column region 32b, or approximately the same as the short width Wp1-1 of the long p-type column region 32a. The thickness of the parallel pn layer 3 is determined by the length Dp1 of the long p-type column region 32a in the depth direction Z. When an n-type buffer region 2 is present, the long p-type column region 32a is n greater than the n-type column region 31 in the depth direction Z. + It may reach a deep position on the drain region 1 side.

[0060] Thus, in the active region 10, the p-type column region 32 has a shorter length in the depth direction Z in the cross-section parallel to the first direction X and passing through the short p-type column region 32b (cutting line A2-A2') compared to the cross-section parallel to the first direction X and passing through the long p-type column region 32a (cutting line A1-A1'). In the active region 10, the p-type column region 32 has a comb-like cross-sectional shape when viewed from the short side (cutting line C-C') due to the difference in length in the depth direction Z between the long p-type column region 32a and the short p-type column region 32b.

[0061] On the other hand, the length Dn1 in the depth direction Z of the n-type column region 31 is uniform throughout the entire active region 10. Therefore, in the active region 10, the parallel pn layer 3 is on the front side (n) of the semiconductor substrate 40. + The short p-type column region 32b, located only on the source region 5 side, makes the front side of the semiconductor substrate 40 relatively p-rich, and the back side (n + On the drain region 1 side, an n-type column region 33 is positioned opposite the short p-type column region 32b in the depth direction Z, resulting in a relatively n-rich surface on the back side of the semiconductor substrate 40.

[0062] In the active region 10, p-rich means that the charge amount, represented by the product of the carrier concentration in the p-type column region 32 (long p-type column region 32a and short p-type column region 32b) and the width in the short direction Wp1, is greater than the charge amount, represented by the product of the carrier concentration in the n-type column regions 31 and 33 and the width in the short direction Wn1. n-rich means that the charge amount, represented by the product of the carrier concentration in the n-type column regions 31 and 33 and the width in the short direction Wn1, is greater than the charge amount, represented by the product of the carrier concentration in the p-type column region 32 (long p-type column region 32a and short p-type column region 32b) and the width in the short direction Wp1.

[0063] Furthermore, in the active region 10, both the long p-type column region 32a and the short p-type column region 32b have approximately the same widths Wp1-1 and Wp1-2 in the shorter direction. Therefore, in the parallel pn layer 3 in the active region 10, the charge balance between the n-type column region 31 and the p-type column region 32 is generally maintained from the front side of the semiconductor substrate 40 to the interface between the short p-type column region 32b and the n-type column region 33, while the back side of the semiconductor substrate 40 from the interface between the short p-type column region 32b and the n-type column region 33 is relatively n-rich.

[0064] In the edge-terminal region 20, the p-type column region 32 consists only of the long p-type column region 32a. The width Wp1-1 in the short direction and the length Dp1 in the depth direction Z of the long p-type column region 32a are approximately the same as the width Wn1 in the short direction and the length Dn1 in the depth direction Z of the n-type column region 31, respectively. Therefore, the charge balance between the n-type column region 31 and the p-type column region 32 is generally maintained in the edge-terminal region 20. For this reason, the back side of the semiconductor substrate 40 of the parallel pn layer 3 is n-rich in the active region 10 compared to the edge-terminal region 20.

[0065] In the active region 10, charge balance is an indicator of the degree of balance between the charge amount, which is expressed as the product of the carrier concentration and width Wn1 in the n-type column regions 31 and 33, and the charge amount, which is expressed as the product of the carrier concentration and width Wp1 in the p-type column region 32. In the edge-terminal region 20, charge balance is an indicator of the degree of balance between the charge amount, which is expressed as the product of the carrier concentration and width Wn1 in the n-type column region 31, and the charge amount, which is expressed as the product of the carrier concentration and width Wp1 in the p-type column region 32.

[0066] The charge balance between the n-type column regions 31, 33 and the p-type column region 32 in the active region 10 is adjusted by changing the length Dp2 in the depth direction Z of the short p-type column region 32b, or the width Wp11 in the longitudinal direction of the long p-type column region 32a, or both. By making the parallel pn layers 3 in the active region 10 relatively p-rich on the front side of the semiconductor substrate 40, the breakdown voltage of the active region 10 can be reduced compared to the conventional structure (see Figures 15-18). This makes it possible to lower the breakdown voltage of the active region 10 to lower than the breakdown voltage of the edge termination region 20. In addition, the breakdown voltage margin of the active region 10 can be widened.

[0067] Furthermore, in the active region 10, the long p-type column region 32a and the short p-type column region 32b are arranged alternately and repeatedly adjacent to each other in the second direction Y. This is equivalent to a state in which a normal SJ structure, in which the length Dp1 in the depth direction Z of the p-type column region 32 (long p-type column region 32a) is approximately the same as the length Dn1 in the depth direction Z of the n-type column region 31, and a short SJ structure, in which the length Dp2 in the depth direction Z of the p-type column region 32 (short p-type column region 32b) is shorter than the length Dn1 in the depth direction Z of the n-type column region 31, are connected in parallel in the second direction Y. This makes it possible to achieve both the reduction of on-resistance with the normal SJ structure and the improvement of switching characteristics with the short SJ structure.

[0068] The length Dp2 in the depth direction Z of the short p-type column region 32b is the length of p directly below the gate trench 7. +The length of the p-type column region 32 (long p-type column region 32a and short p-type column region 32b) should be longer than the length Dp3 in the depth direction Z of the type region 11, and may be as short as, for example, 3% of the length Dp1 in the depth direction Z of the long p-type column region 32a. The volume of the p-type column region 32 (long p-type column region 32a and short p-type column region 32b) is preferably 20% or more and less than 90% of the total volume of the n-type column regions 31 and 33, and more preferably 50% or more and 70% of the total volume of the n-type column regions 31 and 33.

[0069] If the volume ratio of the p-type column region 32 to the total volume of the n-type column regions 31 and 33 is less than 20%, the parallel pn layer 3 in the active region 10 becomes excessively n-rich, which reduces pressure resistance and is undesirable. On the other hand, if the volume ratio of the p-type column region 32 to the total volume of the n-type column regions 31 and 33 exceeds 90%, the parallel pn layer 3 in the active region 10 becomes excessively p-rich, which reduces pressure resistance and is undesirable. Furthermore, by setting the volume ratio of the p-type column region 32 to the total volume of the n-type column regions 31 and 33 to approximately 50% to 70%, p + This allows for an increase in the pressure resistance margin when the mold region 12 and the p-type column region 32 deviate from a predetermined positional condition in the first direction X.

[0070] The charge balance between the n-type column regions 31, 33 and the p-type column region 32 in the active region 10 may be adjusted by arranging two or more short p-type column regions 32b with different lengths Dp2 in the depth direction Z in the active region 10 (see Figure 6). The long p-type column region 32a and the two or more short p-type column regions 32b are arranged regularly in the second direction Y. Between each of the two or more short p-type column regions 32b and the n-type buffer region 2, an n-type column region 33 is arranged, corresponding to the length in the depth direction from the short p-type column region 32b to the n-type buffer region 2.

[0071] For example, Figure 6 shows the case where two types of short p-type column regions 32b (32b-1, 32b-2) with different lengths Dp2 (Dp2-1, Dp2-2) in the depth direction Z are arranged. An n-type column region 33 (33-1, 33-2) is placed between the short p-type column regions 32b-1, 32b-2 and the n-type buffer region 2, respectively. The lengths Dp2-1 and Dp2-2 in the depth direction Z of the short p-type column regions 32b-1, 32b-2 may be approximately 1 / 3 and 2 / 3 of the length Dp1 in the depth direction Z of the long p-type column region 32a, respectively.

[0072] The trench gate structure consists of a p-type base region (first semiconductor region) 4, n + Type source region (second semiconductor region) 5, p ++ It consists of a p-type contact region 6, a gate trench (trench) 7, a gate insulating film 8, and a gate electrode 9. The p-type base region 4 is provided between the front surface of the semiconductor substrate 40 and the parallel pn layer 3. The p-type base region 4 is the n of the p-type epitaxial layer 43. + Type source region 5 and p ++ This is the portion excluding the type contact region 6. The p-type base region 4 extends outward from the active region 10 to the step 44, which will be described later.

[0073] n + Type source region 5 and p ++ The type contact region 6 is selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 4 in the active region 10. + Type source region 5 and p ++ The p-type contact region 6 is in contact with the p-type base region 4 and is exposed on the front surface of the semiconductor substrate 40. Exposure to the front surface of the semiconductor substrate 40 means n + Type source region 5 and p ++ The contact area 6 is in contact with the source electrode (first electrode) 15, which will be described later, on the first surface 40a of the front surface of the semiconductor substrate 40.

[0074] n + Type source region 5 and p ++The type contact region 6 extends linearly in the second direction Y, for example, along the side wall of the gate trench 7. + Type source area 5 is p ++ It is positioned on the gate trench 7 side of the type contact region 6 and faces the gate electrode 9 via the gate insulating film 8 of the side wall of the gate trench 7. ++ The type contact area 6 does not need to be provided. In this case, p ++ Instead of the type contact region 6, the p-type base region 4 is exposed on the first surface 40a of the semiconductor substrate 40, which will be described later.

[0075] Between the p-type base region 4 and the parallel pn layer 3, + Type regions (first and second second conductivity type high concentration regions) 11 and 12 are selectively provided, respectively. + The n-type regions 11 and 12 are diffusion regions formed inside the n-type epitaxial layer 42 by ion implantation. + The type regions 11 and 12 are electrically connected to the source electrode 15 and have the function of depleting when the MOSFET is off, thereby mitigating the electric field near the bottom surface of the gate trench 7. + The mold regions 11 and 12 extend in a stripe-like manner in the second direction Y along the side wall of the gate trench 7.

[0076] p + An n-type column region 31 extends between type regions 11 and 12. + Between type regions 11 and 12, the n-type column region 31 extends to the p-type base region 4 and is in contact with the p-type base region 4. + The type region 11 is positioned separately from the p-type base region 4 and faces the bottom surface of the gate trench 7 in the depth direction Z. + Type region 11 is p in the part omitted from the illustration. + It is connected to type region 12. + The type region 11 is in contact with the n-type column region 31 opposite it in the depth direction Z. + The mold region 11 may be in contact with the gate insulating film 8 at the bottom surface of the gate trench 7.

[0077] outermost p +The mold region 11 extends beyond the step 44, which will be described later, and is exposed on the second surface 40b of the front surface of the semiconductor substrate 40, which will be described later. Exposure to the second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40, as described later, means contact with the interlayer insulating film 14 on the front surface of the semiconductor substrate 40. + The type region 12 is in contact with the p-type base region 4 between adjacent gate trenches 7, and p + It is located away from the mold region 11 and the gate trench 7. + The type region 12 is in contact with the p-type column region 32 in the depth direction Z.

[0078] Between adjacent gate trenches 7, p + An n-type current diffusion region (not shown) may be provided between the type regions 11, 12, the p-type base region 4, and the n-type column region 31, in contact with these regions and reaching the side wall of the gate trench 7 in the first direction X. The n-type current diffusion region is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. The impurity concentration of the n-type current diffusion region is equal to or greater than the impurity concentration of the n-type column region 31.

[0079] The gate trench 7 extends from the first surface 40a of the semiconductor substrate 40 (described later) in the depth direction Z to n + It penetrates the p-type source region 5 and the p-type base region 4 to reach the n-type column region 31 (or the n-type current diffusion region if an n-type current diffusion region is provided). The bottom surface of the gate trench 7 is p + The gate trench 7 may terminate inside the mold region 11. The gate trench 7 extends in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 40 (here, the second direction Y). Inside the gate trench 7, a gate electrode 9 is provided via a gate insulating film 8.

[0080] The interlayer insulating film 14 is provided over the entire surface of the front surface of the semiconductor substrate 40 and covers the gate electrode 9. The source electrode 15 makes ohmic contact with the first surface 40a of the front surface of the semiconductor substrate 40, which will be described later, at the contact hole of the interlayer insulating film 14, and the p-type base region 4, n +The n-type source region 5 and the p ++ -type contact region 6 are electrically connected. The drain electrode (second electrode) 16 is provided on the entire back surface (n + -type starting substrate 41) of the semiconductor substrate 40 and is electrically connected to the n + -type drain region 1.

[0081] The portion of the p-type epitaxial layer 43 in the edge termination region 20 is removed by etching, and a step 44 is formed on the front surface of the semiconductor substrate 40. The front surface of the semiconductor substrate 40 is recessed on the side of the edge termination region 20 (second surface) 40b with respect to the portion on the active region 10 side (first surface) 40a with this step 44 as a boundary, on the n + -type drain region 1 side. The second surface 40b of the front surface of the semiconductor substrate 40 is the exposed surface of the n-type epitaxial layer 42 exposed by removing the p-type epitaxial layer 43.

[0082] At the portion (third surface: mesa edge of step 44) 40c connecting the first surface 40a and the second surface 40b of the front surface of the semiconductor substrate 40, the active region 10 and the edge termination region 20 are element-separated. In the edge termination region 20, a field oxide film may be provided between the front surface of the semiconductor substrate 40 and the interlayer insulating film 14. In the edge termination region 20, on the surface region of the front surface of the semiconductor substrate 40, from the active region 10, the p-type base region 4 and the p + -type region 11 facing the bottom surface of the outermost gate trench 7 (7a) extend.

[0083] Hereinafter, the portions of the p-type base region 4 and the p + -type region 11 extending into the edge termination region 20 are respectively referred to as a p-type base extension portion 4a and a p + -type extension portion 11a. The p-type base extension portion 4a and the p + -type extension portion 11a surround the periphery of the active region 10. A p ++ -type outer peripheral contact region (not shown) may be provided between the first surface 40a of the front surface of the semiconductor substrate 40 and the p-type base extension portion 4a. p ++The outer peripheral contact region of the mold and the p-type base extension portion 4a are electrically connected to the source electrode 15 at the contact holes of the interlayer insulating film 14.

[0084] p + The extended portion 11a extends along the boundary between the active region 10 and the edge termination region 20, surrounding the active region 10. + The type extension portion 11a is provided between the p-type base extension portion 4a and the parallel pn layer 3, in contact with them. + The type extension portion 11a contains all p of the active region 10. + The ends of type regions 11 and 12 are connected. Also, p + The mold extension portion 11a extends outward beyond the step 44 on the front surface of the semiconductor substrate 40 and is exposed on the second surface 40b of the front surface of the semiconductor substrate.

[0085] A gate runner (not shown) is provided between the active region 10 and the breakdown structure 21. The gate runner includes a gate polysilicon wiring layer provided on the first surface 40a of the front surface of the semiconductor substrate 40 via a field oxide film (not shown). The gate polysilicon wiring layer is covered with an interlayer insulating film 14. Each gate electrode 9 of all unit cells of the active region 10 is connected to the gate polysilicon wiring layer. The gate runner electrically connects the gate electrode 9 to the gate pad (electrode pad: not shown).

[0086] In the surface region of the second surface 40b of the front surface of the semiconductor substrate 40, a plurality of p-type regions constituting the breakdown structure 21 are selectively provided inside the n-type epitaxial layer 42, and outside of that, separated from the breakdown structure 21, n + A p-type channel stopper region 24 is selectively provided. The pressure-resistant structure 21 has, for example, two p-type regions (p - type region 22, p -- This is a double-zone JTE structure in which the p-type regions (23) are arranged concentrically around the active region 10, adjacent to each other, such that the p-type regions have lower impurity concentrations as they move away from the active region 10.

[0087] The innermost of the multiple p-type regions that constitute the pressure-resistant structure 21 - The mold region 22 is oriented in a direction parallel to the front surface of the semiconductor substrate 40, p + It is in contact with the extended part 11a. The multiple p-type regions constituting the pressure-resistant structure 21 are p + The potential of the source electrode 15 is fixed via the type extension portion 11a and the p-type base extension portion 4a. Multiple p-type regions and n-type regions constitute the breakdown structure 21. + The n-type channel stopper region 24 is a diffusion region formed by ion implantation into the n-type epitaxial layer 42 and is exposed on the second surface 40b of the front surface of the semiconductor substrate 40.

[0088] n + Instead of the type channel stopper region 24, p + A channel stopper region (not shown) may be provided. Pressure-resistant structure 21 and n + The area between the n-type channel stopper region 24 and the n-type drift region 34 is a normal n-type drift region 34, which does not have an SJ structure. The normal n-type drift region 34 is exposed on the second surface 40b of the front surface of the semiconductor substrate 40 and on the side surface of the semiconductor substrate 40. The normal n-type drift region 34 is in contact with the parallel pn layer 3 and surrounds the parallel pn layer 3. The impurity concentration of the normal n-type drift region 34 is less than or equal to the impurity concentration of the n-type column region 31.

[0089] A method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1 will be described. First, n + n becomes type drain region 1 + A drift layer including parallel pn layers 3 is formed on the front surface of a starting substrate (semiconductor wafer) 41. At this time, for example, using a multi-stage epitaxial method, the n-type epitaxial layer 42 that will become the drift layer is divided into multiple stages (multiple times) and epitaxially grown in multiple stages, and each time p-type impurities such as aluminum (Al) are ion-implanted into each n-type epitaxial layer, the portion that will become the p-type column region 32 (long p-type column region 32a and short p-type column region 32b) of the parallel pn layers 3 is selectively formed.

[0090] The portion of the n-type epitaxial layer 42 that remains n-type without ion implantation between adjacent p-type column regions 32 becomes the n-type column region 31 of the parallel pn layer 3. The portion of the n-type epitaxial layer 42 that remains below the short p-type column region 32b becomes the n-type column region 33 of the parallel pn layer 3. + The entire area between the starting substrate 41 and the parallel pn layer may be left as an n-type buffer region 2 without ion implantation. The following explanation will use the case where an n-type buffer region 2 is provided as an example. The portion between the parallel pn layer 3 and the chip edge (the edge of the part that will become a semiconductor chip) that is not ion implanted and remains n-type becomes a normal n-type drift region 34.

[0091] The n-type column regions 31 and 33 may be formed by ion implantation of n-type impurities. In this case, instead of the n-type epitaxial layer 42, an undoped epitaxial layer or n - The n-type epitaxial layer is grown epitaxially in multiple stages. When an undoped epitaxial layer is grown epitaxially in multiple stages, the n-type buffer region 2 and the n-type drift region 34 are formed by ion implantation of n-type impurities. - When multiple n-type epitaxial layers are epitaxially grown, it is possible to form n-type buffer regions 2 and n-type drift regions 34 with lower impurity concentrations than the n-type column region 31.

[0092] Next, by ion implantation, p is implanted adjacent to the n-type column region 31 and the p-type column region 32 in the depth direction Z, respectively, in the surface region of the n-type epitaxial layer 42. + Selectively forms type regions 11 and 12. Also, p + Type region 11 and simultaneously p + A type extension portion 11a is formed. In the uppermost n-type epitaxial layer of the multi-stage epitaxially grown n-type epitaxial layer 42, n-type column region 31 and p-type column region 32 are not formed, p + Type regions 11, 12 and p + Only the mold extension portion 11a is formed, and adjacent p +An n-type current diffusion region (not shown) may be formed between type regions 11 and 12 by ion implantation.

[0093] Next, a p-type epitaxial layer 43, which will become the p-type base region 4, is epitaxially grown on the n-type epitaxial layer 42. + Epitaxial layers 42 and 43 are sequentially stacked on a starting substrate 41 to create a semiconductor substrate (semiconductor wafer) 40 that includes a parallel pn layer 3 in the n-type epitaxial layer 42. Next, the edge termination region 20 of the p-type epitaxial layer 43 is removed by etching to form a step 44 on the front surface of the semiconductor substrate 40, with the portion on the edge termination region 20 side (second surface 40b) being lower than the portion on the active region 10 side (first surface 40a).

[0094] An n-type epitaxial layer 42 is exposed on the second surface 40b, which has newly become the front surface of the semiconductor substrate 40 in the edge termination region 20. The portion of the front surface of the semiconductor substrate 40 between the first surface 40a and the second surface 40b (third surface 40c) may, for example, form an obtuse angle (inclined surface) with respect to the first and second surfaces 40a and 40b, or it may form a nearly right angle (vertical surface). The second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40 have a p-type base region 4 and p + The mold extension portion 11a is exposed. The etching that forms this step 44 may remove a small portion of the n-type epitaxial layer 42 along with the p-type epitaxial layer 43.

[0095] Next, by ion implantation, n + Type source area 5, p ++ Multiple p-type regions (p) of the pressure-resistant structure 21, including the type contact region 6. - type region 22, p -- Type region 23), and n + Each type channel stopper region 24 is selectively formed. + Type source region 5 and p ++ The type contact regions 6 are selectively formed on the surface regions of the p-type epitaxial layer 43. ++ Type contact area 6 and simultaneously p ++A type outer peripheral contact region may be formed. n of the p-type epitaxial layer 43 + Type source area 5, p ++ Type contact area 6 and p ++ The portion excluding the outer peripheral contact area of ​​the mold becomes the p-type base region 4 and the p-type base extension portion 4a.

[0096] Multiple p-type regions and n of the pressure-resistant structure 21 + The n-type channel stopper region 24 is selectively formed on the surface region of the n-type epitaxial layer 42 exposed on the second surface 40b of the front surface of the semiconductor substrate 40 in the edge termination region 20. + Type source area 5, p ++ Type contact area 6, p ++ The outer peripheral contact area of ​​the type, multiple p-type regions of the pressure-resistant structure 21, and n + The formation order of the channel stopper region 24 can be changed. Also, before forming the step 44 on the front surface of the semiconductor substrate 40, + Type source area 5, p ++ Type contact area 6 and p ++ A contact region may be formed on the outer periphery of the mold.

[0097] Next, a heat treatment is performed to activate the ion-implanted impurities in the epitaxial layers 42 and 43. This heat treatment may be performed each time a diffusion region is formed by ion implantation. Next, from the front surface of the semiconductor substrate 40, n + The source region 5 and the base region 4 of type p penetrate through, + A gate trench 7 is formed opposite the mold region 11. Next, the gate insulating film 8, gate electrode 9, interlayer insulating film 14, source electrode 15, and drain electrode 16 are formed by a general method. After that, the semiconductor wafer (semiconductor substrate 40) is diced (cut) into individual chips to complete the silicon carbide semiconductor device 50 shown in Figures 1-5.

[0098] In the manufacturing method of the silicon carbide semiconductor device 50 according to Embodiment 1 described above, the parallel pn layer 3 may be formed using a trench-embedded epitaxial method instead of the multi-stage epitaxial method. When using the trench-embedded epitaxial method, trenches (SJ trenches) with the same depth as the length Dp1 in the depth direction Z of the long p-type column region 32a and SJ trenches with the same depth as the length Dp2 in the depth direction Z of the short p-type column region 32b are formed in the n-type epitaxial layer 42, leaving portions that become n-type column regions 31 and 33. These SJ trenches are then filled with a p-type epitaxial layer that becomes the p-type column region 32 to form the parallel pn layer 3.

[0099] As described above, according to Embodiment 1, by providing a short p-type column region in a part of the p-type column region of the parallel pn layer in the active region, which has a shorter length in the depth direction than the other part (long p-type column region), the parallel pn layer in the active region can be made relatively p-rich on the front side of the semiconductor substrate and relatively n-rich on the back side of the semiconductor substrate. By making the front side of the semiconductor substrate relatively p-rich in the parallel pn layer in the active region, the electric field concentration at the bottom of the short p-type column region in the active region can be increased, so that the breakdown voltage of the active region can be made lower than the breakdown voltage of the edge termination region.

[0100] This allows avalanche breakdown to occur in a large active region that occupies most of the surface area of ​​the semiconductor substrate, improving fracture tolerance compared to conventional structures where avalanche breakdown occurs in the edge termination region. Relatively speaking, on the front side of the semiconductor substrate, the parallel pn layers in the active region... p By enriching the column, switching characteristics can be improved. Furthermore, according to Embodiment 1, it is possible to achieve both the reduction in on-resistance obtained with a normal SJ structure using a long p-type column region and the improvement in switching characteristics obtained with a short SJ structure using a short p-type column region.

[0101] (Embodiment 2) Next, the structure of the silicon carbide semiconductor device according to Embodiment 2 will be described. Figures 7 and 8 are cross-sectional views showing the structure of the silicon carbide semiconductor device according to Embodiment 2. The layout of the silicon carbide semiconductor device 51 according to Embodiment 2, as viewed from the front side of the semiconductor substrate (semiconductor chip) 40, is the same as in Embodiment 1 (see Figure 1). Figures 7 and 8 show the cross-sectional structure at the cutting lines A1-A1' and C-C' in Figure 1, respectively. Figure 7 shows a cross-section of the narrow p-type column region 61 as viewed from the second direction Y. Figure 8 shows a cross-section of the p-type column region 32 as viewed from the first direction X.

[0102] In the silicon carbide semiconductor device 51 according to Embodiment 2, the cross-section of the short p-type column region 32b viewed from the second direction Y is the same as in Embodiment 1 (see Figure 3), the cross-section of the n-type column region 31 viewed from the first direction X is the same as in Embodiment 1 (see Figure 4), and the configuration of the edge termination region 20 is the same as in Embodiment 1. The difference between the silicon carbide semiconductor device 51 according to Embodiment 2 and the silicon carbide semiconductor device 50 according to Embodiment 1 (Figures 1-5) is that in the active region 10, the width Wp22 in the short direction is relatively narrowed by a part (hereinafter referred to as the narrow p-type column region) 61 that extends linearly in the second direction Y in the p-type column region 32 of the parallel pn layer 60.

[0103] Specifically, in Embodiment 2, the parallel pn layer 60 is composed of n-type column regions 31, 33, 62 and p-type column regions 32 (narrow p-type column region 61 and short p-type column region 32b of the active region 10, and long p-type column region 32a of the edge-termination region 20). The parallel pn layer 60 is an SJ structure in which n-type column regions 31 and p-type column regions 32 are alternately and repeatedly arranged adjacently in a first direction X parallel to the front surface of the semiconductor substrate 40, similar to the parallel pn layer 3 of Embodiment 1. The configuration of the n-type column regions 31, 33 and the long p-type column region 32a of the edge-termination region 20 is the same as in Embodiment 1.

[0104] In the active region 10, the p-type column region 32 is formed by alternately arranging narrow p-type column regions 61 and short p-type column regions 32b adjacent to each other in the second direction Y. The narrow p-type column region 61 has a width Wp21 that is approximately the same as the width Wp1-2 in the short direction of the short p-type column region 32b in the front-side portion 61b of the semiconductor substrate 40, and a width Wp22 that is narrower than the width Wp1-2 in the short direction of the short p-type column region 32b in the back-side portion 61a of the semiconductor substrate 40. The longitudinal width Wp23 of the narrow p-type column region 61 is approximately the same in both the front-side portion 61b and the back-side portion 61a of the semiconductor substrate 40. The configuration of the narrow p-type column region 61, other than the widths Wp21 and Wp22 in the short direction, is the same as that of the long p-type column region 32a in Embodiment 1 (see Figures 2 and 3).

[0105] The configuration of the short p-type column region 32b is as follows in Embodiment 1. Short p-type column region 32b It is similar to this. Between the narrow p-type column region 61 and the n-type column region 31 are these regions and the n-type buffer region 2 (if the n-type buffer region 2 is not provided, then n + An n-type column region 62 is provided adjacent to the n-type drain region 1). By relatively narrowing the width Wp22 in the short direction of the portion 61a on the back side of the semiconductor substrate 40 of the narrow p-type column region 61, the parallel pn layer 60 in the active region 10 can be made relatively p-rich on the front side of the semiconductor substrate 40 and relatively n-rich on the back side of the semiconductor substrate 40.

[0106] The relatively narrow portion 61a of the narrow p-type column region 61 in the short-side width Wp22 on the back side of the semiconductor substrate 40 is located deeper on the back side of the semiconductor substrate 40 than the interface between the short p-type column region 32b and the n-type column region 33. Therefore, similar to Embodiment 1, in the active region 10, the charge balance between the n-type column region 31 and the p-type column region 32 is generally maintained in the portion of the parallel pn layer 60 on the front side of the semiconductor substrate 40 from the interface between the short p-type column region 32b and the n-type column region 33, and it is relatively n-rich on the back side of the semiconductor substrate 40 than the interface between the short p-type column region 32b and the n-type column region 33.

[0107] The method for manufacturing the silicon carbide semiconductor device 51 according to Embodiment 2 is obtained by appropriately changing the opening pattern of the ion implantation mask for forming the p-type column region 32 in the method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1.

[0108] As described above, according to Embodiment 2, by relatively narrowing the width of a part of the p-type column region (the narrow portion in the short direction of the narrow p-type column region), the parallel pn layer can be made relatively p-rich on the front side of the semiconductor substrate and relatively n-rich on the back side of the semiconductor substrate. This makes it possible to adjust the charge balance between the n-type column region and the p-type column region in the active region, thereby obtaining the same effects as in Embodiment 1.

[0109] (Embodiment 3) Next, the structure of the silicon carbide semiconductor device according to Embodiment 3 will be described. Figures 9 and 10 are cross-sectional views showing the structure of the silicon carbide semiconductor device according to Embodiment 3. The layout of the silicon carbide semiconductor device 52 according to Embodiment 3, as viewed from the front side of the semiconductor substrate (semiconductor chip) 40, is the same as in Embodiment 1 (see Figure 1). Figures 9 and 10 show the cross-sectional structure at the cutting lines A1-A1' and C-C' in Figure 1, respectively. Figure 9 shows a cross-section of the long p-type column regions 32a and 71 as viewed from the second direction Y. Figure 10 shows a cross-section of the p-type column region 32 as viewed from the first direction X.

[0110] In the silicon carbide semiconductor device 52 according to Embodiment 3, the cross-section of the short p-type column region 32b viewed from the second direction Y is the same as in Embodiment 1 (see Figure 3), the cross-section of the n-type column region 31 viewed from the first direction X is the same as in Embodiment 1 (see Figure 4), and the configuration of the edge termination region 20 is the same as in Embodiment 1. The difference between the silicon carbide semiconductor device 52 according to Embodiment 3 and the silicon carbide semiconductor device 50 according to Embodiment 1 (see Figures 1-5) is that in the active region 10, directly below the p-type column region 32 of the parallel pn layer 70, there is an n-type column region adjacent to the p-type column region 32. + The point is that the type region (first conductivity type high concentration region) 72 is located there.

[0111] In Embodiment 3, the parallel pn layer 70 is composed of n-type column regions 31, 33 and p-type column regions 32 (long p-type column region 71 and short p-type column region 32b of the active region 10, and long p-type column region 32a of the edge-termination region 20). The parallel pn layer 70 is an SJ structure in which n-type column regions 31 and p-type column regions 32 are alternately and repeatedly arranged adjacently in a first direction X parallel to the front surface of the semiconductor substrate 40, similar to the parallel pn layer 3 of Embodiment 1. The configuration of the n-type column regions 31, 33, the short p-type column region 32b of the active region 10, and the long p-type column region 32a of the edge-termination region 20 is the same as in Embodiment 1.

[0112] n + The type region 72 is the long p-type column region 71 and the n-type buffer region 2 in the active region 10 (if the n-type buffer region 2 is not provided, then n + They are provided in contact with these regions between the drain region 1) and the second direction Y, and are scattered in the second direction Y. + The width in the short direction and the width in the long direction of type region 72 are approximately the same as the width in the short direction Wp1-1 and the width in the long direction Wp11 of the long p-type column region 71, respectively. + The type region 72 is in contact with the n-type column regions 31 and 33. The configuration of the long p-type column region 71 in the active region 10, other than its length Dp11 in the depth direction Z, is the same as that of the long p-type column region 32a in the edge-terminal region 20.

[0113] The length Dp11 of the long p-type column region 71 in the depth direction Z in the active region 10 is n + The length Dp12 of the length Z in the depth direction of the type region 72 is shorter than the length Dp1 of the length Z in the depth direction of the long p-type column region 32a in the edge terminal region 20. The length Dp11 of the length Z in the depth direction of the long p-type column region 71 is the length of the p-type column region 71. + From the interface with type region 12, n + This is the length to the interface with type region 72. + The length Dp12 in the depth direction Z of the type region 72 is n +From the interface of the type region 72 with the long p-type column region 71, the n-type buffer region 2 (if the n-type buffer region 2 is not provided, then n + This is the length to the interface with the type drain region 1).

[0114] The manufacturing method for the silicon carbide semiconductor device 52 according to Embodiment 3 is the same as the manufacturing method for the silicon carbide semiconductor device 50 according to Embodiment 1, but before forming the long p-type column region 71 in the n-type epitaxial layer 42 using a multi-stage epitaxial method, the n-type epitaxial layer 42 is subjected to ion implantation. + The type region 72 can be selectively formed. Alternatively, when forming a parallel pn layer 70 in an n-type epitaxial layer 42 using a trench-embedded epitaxial method, before embedding the p-type epitaxial layer which will become the long p-type column region 71 in the SJ trench, the surface region of the bottom of the SJ trench can be ion-implanted to form n + A type region 72 should be formed.

[0115] Figures 11, 12A, and 12B are cross-sectional views showing another example of the silicon carbide semiconductor device according to Embodiment 3. Figure 11 shows the cross-sectional structure along the cutting line A2-A2' in Figure 1. Figures 12A and 12B show another example of the cross-sectional structure along the cutting line C-C' in Figure 1. The difference between the silicon carbide semiconductor device 53 according to Embodiment 3 shown in Figures 11, 12A, and 12B and the silicon carbide semiconductor device 52 according to Embodiment 3 shown in Figures 9 and 10 is that n + The type region 72 is positioned between the short p-type column region 32b and the n-type column region 33. + The type region 72 is located between the short p-type column region 32b and the n-type column region 33, adjacent to these regions, and is scattered in the second direction Y.

[0116] n directly below the short p-type column region 32b + The type region 72 has widths in the short direction and long direction that are approximately the same as the widths in the short direction Wp1-2 and long direction Wp12 of the short p-type column region 32b, respectively, and is in contact with the long p-type column region 71. +The type region 72 may be located only directly below the short p-type column region 32b (see Figures 11, 12A), or it may be located both directly below the long p-type column region 71 and directly below the short p-type column region 32b (see Figures 9, 11, 12B). + When the type region 72 is not placed directly below the long p-type column region 71 (Figure 12A), the length Dp11 in the depth direction Z of the long p-type column region 71 of the active region 10 is approximately the same as the length Dp1 in the depth direction Z of the long p-type column region 32a of the edge-terminal region 20.

[0117] Furthermore, in the silicon carbide semiconductor device 52, 53 according to Embodiment 3 (see Figures 9-11, 12A, 12B), n directly below the long p-type column region 71 + The n-type region 72 protrudes to the back side of the semiconductor substrate 40 and forms an n-type buffer region 2 (if an n-type buffer region 2 is not provided, then n + The drain region 1) may be terminated inside (not shown). Alternatively, the narrow p-type column region 61 of Embodiment 2 (see Figures 7 and 8) may be applied to the silicon carbide semiconductor device 52 and 53 according to Embodiment 3, so that the long p-type column region 71 is a narrow p-type column region in which the width in the short direction is relatively narrower on the back side of the semiconductor substrate 40 than on the front side of the semiconductor substrate 40.

[0118] As explained above, according to Embodiment 3, n is located directly below the p-type column region. + By arranging the n-type region, the parallel pn layer can be made relatively p-rich on the front side of the semiconductor substrate and relatively n-rich on the back side of the semiconductor substrate. This allows for adjustment of the charge balance between the n-type column region and the p-type column region in the active region, thereby achieving the same effects as in Embodiments 1 and 2.

[0119] (Embodiment 4) Next, the structure of the silicon carbide semiconductor device according to Embodiment 4 will be described. Figures 13 and 14 are cross-sectional views showing the structure of the silicon carbide semiconductor device according to Embodiment 4. The layout of the silicon carbide semiconductor device 54 according to Embodiment 4, as viewed from the front side of the semiconductor substrate (semiconductor chip) 40, is the same as in Embodiment 1 (see Figure 1). Figures 13 and 14 show the cross-sectional structure at the cutting lines A2-A2' and C-C' in Figure 1, respectively. Figure 13 shows a cross-section of the short p-type column regions 32b and 81 as viewed from the second direction Y. Figure 14 shows a cross-section of the p-type column region 32 as viewed from the first direction X.

[0120] In the silicon carbide semiconductor device 54 according to Embodiment 4, the cross-section of the long p-type column region 32a viewed from the second direction Y is the same as in Embodiment 1 (see Figure 2), the cross-section of the n-type column region 31 viewed from the first direction X is the same as in Embodiment 1 (see Figure 4), and the configuration of the active region 10 is the same as in Embodiment 1. The difference between the silicon carbide semiconductor device 54 according to Embodiment 4 and the silicon carbide semiconductor device 50 according to Embodiment 1 (see Figures 1-5) is that in the p-type column region 32 of the parallel pn layer 80, the length Dp22 in the depth direction Z is shorter in a part (short p-type column region 81, described later) that extends linearly in the second direction Y at the edge termination region 20 than in the other part (long p-type column region 32a).

[0121] In Embodiment 4, the parallel pn layer 80 is composed of n-type column regions 31, 33, 82 and p-type column regions 32 (long p-type column region 32a and short p-type column region 32b of the active region 10, and long p-type column region 32a and short p-type column region 81 of the edge-terminal region 20). The parallel pn layer 80 is an SJ structure in which n-type column regions 31 and p-type column regions 32 are alternately and repeatedly arranged adjacently in a first direction X parallel to the front surface of the semiconductor substrate 40, similar to the parallel pn layer 3 of Embodiment 1. The n-type column regions 31, 33 and the long p-type column region 32a and short p-type column region 32b of the active region 10 are the same as in Embodiment 1.

[0122] In the edge termination region 20, the p-type column region 32 is formed by repeatedly arranging long p-type column regions 32a and short p-type column regions 81 adjacent to each other in the second direction Y. The short p-type column region 81 has an n-type buffer region 2 in the depth direction Z (if an n-type buffer region 2 is not provided, then n + The drain region 1) has not been reached. Between the short p-type column region 81 and the n-type buffer region 2, an n-type column region 82 is provided in contact with these regions, the long p-type column region 32a, and the n-type column region 31. The length Dp22 in the depth direction Z of the short p-type column region 81 is longer than the length Dp2 in the depth direction Z of the short p-type column region 32b of the active region 10.

[0123] In the edge termination region 20, the length Dp22 in the depth direction Z of the short p-type column region 81 is the pressure-resistant structure 21 or p of the short p-type column region 81. + This is the length from the interface with the type extension portion 11a to the interface with the n-type column region 82. The width in the short direction and the width in the long direction of the short p-type column region 81 are the same as the width in the short direction Wp1-2 and the width in the long direction Wp12 of the short p-type column region 32b of the active region 10, respectively. The configuration of the long p-type column region 32a of the edge termination region 20 is the same as the configuration of the long p-type column region 32a of the active region 10. The upper end of the long p-type column region 32a and the upper end of the short p-type column region 81 are located at approximately the same depth.

[0124] In the edge termination region 20, the parallel pn layer 80 is relatively p-rich on the front side of the semiconductor substrate 40 due to the short p-type column region 81 located only on the front side of the semiconductor substrate 40, and relatively n-rich on the back side of the semiconductor substrate 40 due to the n-type column region 82 located opposite the short p-type column region 81 in the depth direction Z on the back side of the semiconductor substrate 40. The charge balance between the n-type column region 31 and the p-type column region 32 in the edge termination region 20 is adjusted by changing the length Dp22 in the depth direction Z of the short p-type column region 81, or the longitudinal width Wp11 of the long p-type column region 32a, or both.

[0125] In the edge-terminal region 20 of Embodiment 4, p-rich means that the charge amount, represented by the product of the carrier concentration in the p-type column region 32 (long p-type column region 32a and short p-type column region 81) and the width in the short direction Wp1, is greater than the charge amount, represented by the product of the carrier concentration in the n-type column regions 31 and 82 and the width in the short direction Wn1. n-rich means that the charge amount, represented by the product of the carrier concentration in the n-type column regions 31 and 82 and the width in the short direction Wn1, is greater than the charge amount, represented by the product of the carrier concentration in the p-type column region 32 (long p-type column region 32a and short p-type column region 81) and the width in the short direction Wp1.

[0126] By making the parallel pn layer 80 in the edge termination region 20 relatively p-rich on the front side of the semiconductor substrate 40, the breakdown voltage of the edge termination region 20 can be reduced compared to the case where the p-type column region 32 in the edge termination region 20 is composed only of long p-type column regions 32a, thereby widening the breakdown voltage margin of the edge termination region 20. By making the length Dp22 in the depth direction Z of the short p-type column region 81 in the edge termination region 20 longer than the length Dp2 in the depth direction Z of the short p-type column region 32b in the active region 10, the portion of the parallel pn layer 80 on the back side of the semiconductor substrate 40 becomes n-richer in the active region 10 than in the edge termination region 20.

[0127] Furthermore, by making the length Dp22 in the depth direction Z of the short p-type column region 81 in the edge-terminal region 20 longer than the length Dp2 in the depth direction Z of the short p-type column region 32b in the active region 10, the length in the depth direction Z of the portion where the charge balance between the n-type column region 31 and the p-type column region 32 of the parallel pn layer 80 is generally maintained becomes longer in the edge-terminal region 20 than in the active region 10. For this reason, even if a short p-type column region 81 is provided in the p-type column region 32 of the edge-terminal region 20, the pressure resistance of the active region 10 can be made lower than the pressure resistance of the edge-terminal region 20, similar to Embodiment 1.

[0128] The method for manufacturing the silicon carbide semiconductor device 54 according to Embodiment 4 is obtained by appropriately changing the opening pattern of the ion implantation mask for forming the p-type column region 32 in the method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1.

[0129] Embodiment 4 may be applied to the silicon carbide semiconductor devices 51-53 (Figures 7-11, 12A, 12B) according to Embodiments 2 and 3, and the parallel pn layers 60 and 70 in the edge termination region 20 may be configured with a long p-type column region 32a and a short p-type column region 81.

[0130] As described above, according to Embodiment 4, the same effects as in Embodiment 1 can be obtained, and the withstand voltage margin in the edge termination region can be widened.

[0131] In summary, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the invention. For example, it can be applied not only to MOSFETs, but also to silicon carbide semiconductor devices with various configurations equipped with a trench gate structure. Furthermore, the present invention also holds true when the conductivity type (n-type, p-type) is reversed. [Industrial applicability]

[0132] As described above, the silicon carbide semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices, power supply devices for various industrial machines, and the like. [Explanation of Symbols]

[0133] 1 n + Type drain region 2 n-type buffer area 3,60,70,80 parallel pn layers 4 p-type base region 4a p type base extension 5 n + Type source area 6 p ++ Type Contact Area 7 Gate Trench 8 gate insulating film 9. Postal Service 10 Active area 11 p directly below the gate trench + type area 11a p + Mold extension 12 p between adjacent gate trenches + type area 14 Interlayer insulating film 15 Source electrodes 16 Drain electrode 20 Edge Termination Region 21 Pressure-resistant structure 22 pages - type area 23 pages -- type area 24 n + Type channel stopper region 31,33,62,82 n-type column regions 32 p-type column regions 32a,71 Long p-type column region 32b, 32b-1, 32b-2, 81 Short p-type column region 34 Normal n-type drift region 40 Semiconductor substrates 40a~40c Front side of semiconductor substrate 41 n + Mold starting substrate 42 n-type epitaxial layer 43 p-type epitaxial layer 44 Steps on the front surface of the semiconductor substrate 50-54 Silicon Carbide Semiconductor Equipment 61 Narrow p-type column region 61a, 61b Part of the narrow p-type column region 72 n directly below the p-type column region + type area Dn1 n-type column region depth Dp1, Dp11 Length in the depth direction of the long p-type column region Dp2, Dp2-1, Dp2-2, Dp22: Depth of the short p-type column region Dp3 p directly below the gate trench + Length of the depth Z of the mold region n immediately beneath the long p-type column region of Dp12 + Length in the depth direction of the mold region Wn1 n-type column region width in the short direction Wp1 p-type column region width in the short direction Wp1-1 Width in the short direction of the long p-type column region Wp1-2 Short p-type column region width in the short direction Wp11 Long p-type column region longitudinal width Wp12 Short p-type column region longitudinal width Wp21, Wp22 Width in the short direction of the narrow p-type column region Wp23 Narrow p-type column region longitudinal width X First direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z-direction (depth)

Claims

1. An active region provided on a semiconductor substrate made of silicon carbide, A terminal region surrounding the active region, A parallel pn layer is provided inside the semiconductor substrate, in which a first conductivity type column region and a second conductivity type column region are arranged alternately and repeatedly adjacent to each other in a first direction parallel to the first main surface of the semiconductor substrate. A predetermined element structure is provided between the first main surface and the parallel pn layer, A first electrode provided on the first main surface and electrically connected to the element structure, A second electrode provided on the second main surface of the semiconductor substrate, Equipped with, The first conductivity type column region and the second conductivity type column region extend in a stripe-like manner from the active region to the terminal region in a second direction parallel to the first main surface and perpendicular to the first direction. The impurity concentration in the first conductivity type column region is uniform from the active region to the terminal region. The impurity concentration in the second conductivity type column region is the same as the impurity concentration in the first conductivity type column region, and is uniform from the active region to the terminal region. The second conductive column region has a short column region in the active region that extends linearly in the second direction and has a shorter length in the depth direction than the other portion. The parallel pn layer has the short column region and the other portion regularly arranged throughout the entire active region, and has a first conductivity type region between the short column region and the second main surface, and in the active region, it is relatively p-rich on the first main surface side and relatively n-rich on the second main surface side. A silicon carbide semiconductor device characterized in that the volume of the second conductivity type column region is 50% or more and 70% or less of the total volume of the first conductivity type column region and the first conductivity type region.

2. The silicon carbide semiconductor device according to claim 1, characterized in that the portion of the parallel pn layer on the second main surface side is n-richer in the active region than in the termination region.

3. The aforementioned short column region is The active region and the terminal region are provided, The silicon carbide semiconductor device according to claim 1 or 2, characterized in that the length in the depth direction of the active region is shorter than that of the termination region.

4. The silicon carbide semiconductor device according to claim 3, characterized in that the parallel pn layer is relatively p-rich on the first main surface side and relatively n-rich on the second main surface side in the termination region.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that the second conductive column region is formed by repeatedly arranging the short column region and the other portion adjacent to each other in the second direction.

6. The silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that the second conductive column region is formed by regularly arranging two or more short column regions of different lengths in the depth direction and the other portion in the second direction within the active region.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that the short column region is adjacent to the short column region of another second conductivity type column region in the first direction.

8. The silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that the short column region is adjacent to the other portion of the other second conductivity type column region in the first direction.

9. The silicon carbide semiconductor device according to any one of claims 1 to 8, characterized in that the other portion of the second conductive column region has a narrower width in the short direction on the second main surface side than on the first main surface side.

10. The silicon carbide semiconductor device according to any one of claims 1 to 9, further comprising a first conductivity type high-concentration region having a higher impurity concentration than the first conductivity type column region, provided at the end of the second main surface side of the second conductivity type column region.

11. The silicon carbide semiconductor device according to any one of claims 1 to 10, characterized in that the length in the depth direction of the other portion of the second conductivity type column region is the same as the length in the depth direction of the first conductivity type column region.

12. The aforementioned device structure is A first semiconductor region of a second conductivity type is provided between the first main surface and the parallel pn layer, A second semiconductor region of a first conductivity type is selectively provided between the first main surface and the first semiconductor region, A trench that penetrates the second semiconductor region and the first semiconductor region and reaches the first conductivity type column region, A gate electrode is provided inside the trench via a gate insulating film, Between the bottom surface of the trench and the first conductivity type column region, a first second conductivity type high-concentration region is provided, separated from the first semiconductor region, and having a higher impurity concentration than the first semiconductor region. Between the first semiconductor region and the second conductivity type column region, there is a second second conductivity type high-concentration region having a higher impurity concentration than the first semiconductor region, which is in contact with the first semiconductor region and the second conductivity type column region, and is separated from the trench and the first second conductivity type high-concentration region. The first electrode is electrically connected to the second semiconductor region and the first semiconductor region. The silicon carbide semiconductor device according to any one of claims 1 to 11, characterized in that the length in the depth direction of the short column region is longer than the length in the depth direction of the first second conductivity type high concentration region.

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