Semiconductor equipment

Abstract

To suppress wiring resistance from increasing.SOLUTION: Electric conductive members 60 are arranged at wiring parts of circuit patterns 32, 31 respectively. Currents flowing at the wiring parts flow through even an electric conductive member 60. Consequently, the wiring parts decrease in wiring resistances and also decrease in loss to reduce heat generation by Joule heat. Namely, semiconductor chips 40b, 40d can be arranged nearby the circuit patterns 32, 31 having a risk of heat generation, and the semiconductor chips 40b, 40d increase in degree of freedom of arrangement. Further, even if a region where wiring resistance is improved is formed by reducing the volume of circuit patterns 31 to 36, heat generation can be reduced by providing an electric conductive members 60 in such an area. Consequently, a semiconductor module can be made compact while maintaining its reliability.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Semiconductor devices include power devices and are used as power conversion devices. Power devices include semiconductor chips. Semiconductor chips are, for example, IGBTs (Insulated Gate Bipolar Transistors) or power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Such semiconductor devices include at least a semiconductor chip and an insulating circuit board on which the semiconductor chip is disposed. At this time, the semiconductor chip is joined to a circuit pattern included in the insulating circuit board via a joining member (e.g., solder).

[0003] In addition, semiconductor devices are being miniaturized. In order to achieve miniaturization of semiconductor devices, for example, it is necessary to reduce the size of the insulating circuit board included in the semiconductor device. Reducing the size of the insulating circuit board requires reducing the area of the circuit pattern.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when the area of the circuit pattern is reduced, the wiring resistance with respect to the current flowing through the circuit pattern increases. Further, when the wiring resistance increases, Joule heat is generated in that portion. If a semiconductor chip is disposed near the heat-generating portion, the temperature of the semiconductor chip may rise and the chip may malfunction.

[0006] Alternatively, increasing the number of semiconductor chips placed on an insulated circuit board requires sufficient area for the circuit pattern. Furthermore, increasing the number of semiconductor chips increases the total current output and input from all semiconductor chips. In this case, if the circuit pattern does not have sufficient area, the wiring resistance to the current flowing through the circuit pattern may increase. This, too, can lead to failure due to heat generation at the points of increased wiring resistance, similar to the above-mentioned issue.

[0007] This invention has been made in view of these points, and aims to provide a semiconductor device in which the increase in wiring resistance is suppressed. [Means for solving the problem]

[0008] According to one aspect of the present invention, Semiconductor devices are A semiconductor chip having a first main electrode on its back surface and a second main electrode on its front surface, and a wiring layer electrically connected to at least one of the first or second main electrodes, with a conductive member disposed on the front surface. Furthermore, the wiring layer includes a first portion including a chip region on its front surface to which the back surface of the semiconductor chip is joined, a second portion including a terminal region on its front surface to which external connection terminals are joined, and a wiring portion connecting the first portion and the second portion and on which the conductive member is arranged on its front surface. The conductive member includes a flat plate portion that is flat in shape along the wiring portion and has a width in a direction perpendicular to the conductive direction of the wiring portion in a plan view, the flat plate portion is provided with a gap between it and the front surface of the wiring portion, and the conductive member further includes a pair of legs that connect both ends of the flat plate portion to the front surface of the wiring portion, and the conductive member is stacked with gaps between it in a direction in which the flat plate portion moves away from the front surface of the wiring portion. [Effects of the Invention]

[0009] The semiconductor device with the above configuration can suppress the increase in wiring resistance, thereby preventing failures and preventing a decrease in reliability. [Brief explanation of the drawing]

[0010] [Figure 1] This is a plan view of a semiconductor module according to the first embodiment. [Figure 2] This is a plan view of an insulating circuit board included in the semiconductor module of the first embodiment. [Figure 3] This is a cross-sectional view (part 1) of the semiconductor module according to the first embodiment. [Figure 4] This is a cross-sectional view (part 2) of the semiconductor module according to the first embodiment. [Figure 5] This is a cross-sectional view (part 1) of the main part of the semiconductor module of the first embodiment (modified example 1-1). [Figure 6] This is a cross-sectional view (part 2) of the main part of the semiconductor module of the first embodiment (modified example 1-1). [Figure 7] This is a cross-sectional view of the main part of a semiconductor module according to the first embodiment (modified example 1-2). [Figure 8] This is a cross-sectional view of the main part of a semiconductor module according to the first embodiment (modified example 1-3). [Figure 9] This is a cross-sectional view (part 1) of the main part of the semiconductor module according to the second embodiment. [Figure 10] This is a cross-sectional view (part 2) of the main part of the semiconductor module according to the second embodiment. [Figure 11] This is a cross-sectional view (part 1) of the main part of the semiconductor module of the second embodiment (modified example 2-1). [Figure 12] This is a cross-sectional view (part 2) of the main part of the semiconductor module of the second embodiment (modified example 2-1). [Figure 13] This is a cross-sectional view of the main part of a semiconductor module according to the second embodiment (modified example 2-2). [Modes for carrying out the invention]

[0011] The embodiments will be described below with reference to the drawings. In the following description, "front surface" and "top surface" refer to the semiconductor shown in the figure. Module 1In this case, it represents the X-Y plane facing the upper side (+Z direction). Similarly, "upper" represents the upper side (+Z direction) in the semiconductor module 1 in the figure. "Back surface" and "lower surface" represent the X-Y plane facing the lower side (-Z direction) in the semiconductor module 1 in the figure. Similarly, "lower" represents the lower side (-Z direction) in the semiconductor module 1 in the figure. The same directionality is meant in other drawings as necessary. "Higher position" represents the position on the upper side (+Z side) in the semiconductor module 1 in the figure. Similarly, "lower position" represents the position on the lower side (-Z side) in the semiconductor module 1 in the figure. "Front surface", "upper surface", "upper", "back surface", "lower surface", "lower", "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical idea of the present invention. For example, "upper" and "lower" do not necessarily mean the vertical direction with respect to the ground. That is, the directions of "upper" and "lower" are not limited to the gravitational direction. Also, in the following description, "main component" means when it contains 80 vol% or more. The substantially right angle and the substantially vertical direction mean that the angle formed by two objects is in the range of 85° or more and 95° or less.

[0012] [First Embodiment] The semiconductor module of the first embodiment will be described with reference to FIGS. 1 to 4. FIG. 1 is a plan view of the semiconductor module of the first embodiment, and FIG. 2 is a plan view of the insulating circuit board included in the semiconductor module of the first embodiment. FIGS. 3 and 4 are cross-sectional views of the semiconductor module of the first embodiment. Note that the description of the sealing member 9 is omitted in the semiconductor module 1 of FIG. 1. FIG. 3 is a cross-sectional view taken along the dashed line Y-Y in FIG. 1. FIG. 4 is a cross-sectional view taken along the dashed line X-X in FIG. 1.

[0013] The semiconductor device of the first embodiment includes an equivalent circuit that constitutes an inverter circuit. Such a semiconductor device includes a plurality of single semiconductor modules 1. For example, the semiconductor device has three semiconductor modules 1 arranged side by side in the X direction in the order of U phase, V phase, and W phase.

[0014] Such a semiconductor module 1 includes a semiconductor unit 10, a base substrate 8 on which the semiconductor unit 10 is disposed, and a case 2 disposed on the base substrate 8 for housing the semiconductor unit 10. Further, the semiconductor module 1 includes a sealing member 9 filled in the case 2 for sealing the semiconductor unit 10.

[0015] The case 2 includes an outer frame 3, an output terminal 5, a positive terminal 6, and a negative terminal 7. The outer frame 3 has a substantially rectangular shape in plan view and includes a pair of long sides 3a, 3c and a pair of short sides 3b, 3d. The outer frame 3 includes a storage portion 3e surrounded by the pair of long sides 3a, 3c and the pair of short sides 3b, 3d. The semiconductor unit 10 is stored in the storage portion 3e and sealed by the sealing member 9.

[0016] The output terminal 5 is disposed on the short side 3b of the outer frame 3. The output terminal 5 has a U-shaped configuration in plan view. That is, the output terminal 5 branches into two and includes internal joints 5a, 5b at its tip. The internal joints 5a, 5b of the output terminal 5 are directly connected to circuit patterns 34, 33.

[0017] The positive terminal 6 and the negative terminal 7, which are input terminals, are disposed on the short side 3d with the storage portion 3e interposed therebetween with respect to the output terminal 5. The positive terminal 6 has a U-shaped configuration in plan view. That is, the positive terminal 6 branches into two and includes internal joints 6a, 6b at its tip. The internal joints 6a, 6b of the positive terminal 6 are directly connected to circuit patterns 32, 31. The negative terminal 7 has a U-shaped configuration in plan view. That is, the negative terminal 7 branches into two and includes internal joints 7a, 7b at its tip. The internal joints 7a, 7b of the negative terminal 7 are directly connected to circuit patterns 36, 35.

[0018] The internal joints 5a, 6a, 7a, 5b, 6b, and 7b may be joined to the circuit patterns 31-36 by a joining member or by ultrasonic bonding. The joining member may be solder or a sintered material. Lead-free solder may be used. Lead-free solder mainly consists of an alloy containing at least two of the following: tin, silver, copper, zinc, antimony, indium, and bismuth. In addition, the solder may contain additives. Examples of additives include nickel, germanium, cobalt, or silicon. The inclusion of additives in the solder improves wettability, gloss, and bonding strength, thereby improving reliability. For sintered materials, metallic materials containing silver, copper, or an alloy containing at least one of these may be used.

[0019] Furthermore, with the internal junctions 5a, 6a, 7a, 5b, 6b, and 7b joined in this manner, the output terminal 5, the positive terminal 6, and the negative terminal 7 are electrically connected to the semiconductor chips 40a, 40b, 40c, and 40d of the semiconductor unit 10 housed in the housing 3e. Specifically, the positive terminal 6 (internal junctions 6a and 6b) is electrically connected to the input electrodes of the semiconductor chips 40c and 40a, respectively, via circuit patterns 32 and 31.

[0020] The negative terminals 7 (internal junctions 7a, 7b) are electrically connected to the output electrodes of semiconductor chips 40d, 40b, respectively, via circuit patterns 36, 35 and lead frames 50d, 50b.

[0021] The output terminals 5 (internal junctions 5a, 5b) are electrically connected to the input electrodes of semiconductor chips 40d, 40b, respectively, via circuit patterns 34, 33. Furthermore, the output terminals 5 (internal junctions 5a, 5b) are electrically connected to the output electrodes of semiconductor chips 40c, 40a, respectively, via circuit patterns 34, 33 and lead frames 50c, 50a.

[0022] The output terminal 5, the positive terminal 6, and the negative terminal 7 are made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or alloys containing at least one of these. The surfaces of the output terminal 5, the positive terminal 6, and the negative terminal 7 may be plated to improve corrosion resistance. Examples of plating materials in this case include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0023] The sealing member 9 seals the semiconductor unit 10 located within the storage section 3e. The sealing member 9 may be a thermosetting resin. Examples of thermosetting resins include epoxy resin, phenolic resin, maleimide resin, and polyester resin. Epoxy resin is preferred. Furthermore, the sealing member 9 may contain a filler. The filler is a ceramic material that is insulating and has high thermal conductivity. Examples of such fillers include silicon oxide, aluminum oxide, boron nitride, or aluminum nitride. The filler content is 10% to 70% by volume relative to the total volume of the sealing member 9.

[0024] The base substrate 8 is flat and rectangular in shape when viewed from above. The base substrate 8 may also cover the storage compartment 3e of the case 2 (outer frame 3) from the back when viewed from above. Such a base substrate 8 is made of a metal with excellent thermal conductivity. Examples of such materials include aluminum, iron, silver, copper, or alloys containing at least one of these. Examples of such alloys include metal composites such as aluminum-silicon nitride (Al-SiC) or magnesium-silicon nitride (Mg-SiC). The surface of the base substrate 8 may be plated, for example, with a plating material to improve corrosion resistance. Examples of such plating materials include nickel and nickel alloys.

[0025] Furthermore, a cooling unit (not shown) can be attached to the back surface of the base substrate 8. In this case, the cooling unit is made of, for example, a metal with excellent thermal conductivity. The metal may be aluminum, iron, silver, copper, or an alloy containing at least one of these. The cooling unit may also be a heat sink or water-cooled jacket with one or more fins. The base substrate 8 may also be integrated with such a cooling unit.

[0026] The semiconductor unit 10 includes an insulating circuit board 20, semiconductor chips 40a to 40d, and lead frames 50a to 50d. The insulating circuit board 20 is rectangular in plan view. The insulating circuit board 20 has an insulating plate 21, a wiring layer formed on the front surface of the insulating plate 21, and a metal plate 22 formed on the back surface of the insulating plate 21. The wiring layer is, for example, a plurality of circuit patterns 31 to 36, 37a to 37c. The outer shapes of the plurality of circuit patterns 31 to 36, 37a to 37c and the metal plate 22 are smaller than the outer shape of the insulating plate 21 in plan view and are formed inside the insulating plate 21. Note that the shape, number, and size of the plurality of circuit patterns 31 to 36, 37a to 37c are examples.

[0027] The insulating plate 21 has a rectangular shape when viewed from above. The corners of the insulating plate 21 may also be chamfered. For example, they may be C-chamfered or R-chamfered. The insulating plate 21 is surrounded on all four sides by its outer perimeter, which consists of long sides 21a, short sides 21b, long sides 21c, and short sides 21d. The insulating plate 21 also includes corners 21e, 21f, 21g, and 21h. Corner 21e is composed of long side 21a and short side 21b. Corner 21f is composed of short side 21b and long side 21c. Corner 21g is composed of long side 21c and short side 21d. Corner 21h is composed of short side 21d and long side 21a. Such an insulating plate 21 is made of a ceramic with good thermal conductivity. The ceramic is made of a material mainly composed of, for example, aluminum oxide, aluminum nitride, or silicon nitride. Furthermore, the thickness of the insulating plate 21 is between 0.2 mm and 2.0 mm.

[0028] The metal plate 22 has a rectangular shape when viewed from above. Its corners may be chamfered, for example, with a C-chamfer or R-chamfer. The metal plate 22 is smaller than the insulating plate 21 and covers the entire back surface of the insulating plate 21, excluding the edges. The metal plate 22 is mainly composed of a metal with excellent thermal conductivity. The metal is, for example, copper, aluminum, or an alloy containing at least one of these. The thickness of the metal plate 22 is between 0.1 mm and 2.0 mm. Plating may be performed to improve the corrosion resistance of the metal plate. Examples of plating materials used include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0029] The circuit patterns 31-36, 37a-37c are formed over the entire surface of the insulating plate 21, excluding the edges. Preferably, in a plan view, the edges of the circuit patterns 31-36, 37a-37c facing the outer periphery of the insulating plate 21 overlap with the outer periphery edge of the metal plate 22 facing the insulating plate 21. This maintains a stress balance between the insulating circuit board 20 and the metal plate 22 on the back surface of the insulating plate 21. Excessive warping, cracking, and other damage to the insulating plate 21 are suppressed. The dashed lines in circuit pattern 31 represent the chip areas 31a1 of the two semiconductor chips 40a, respectively. The dashed lines in circuit pattern 32 represent the chip areas 32a1 of the two semiconductor chips 40c, respectively. The thickness of the circuit patterns 31-36, 37a-37c is, for example, 0.1 mm or more and 2.0 mm or less. Circuit patterns 31-36, 37a-37c are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or alloys containing at least one of these. In addition, the surfaces of circuit patterns 31-36, 37a-37c may be plated to improve corrosion resistance. The plating material used in this case is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0030] The circuit pattern 31 is formed on the long side 21a of the insulating plate 21, extending along the long side 21a from the short side 21b to the short side 21d. The circuit pattern 31 includes a first part 31a, a second part 31b, and a wiring part 31c.

[0031] The first part 31a is along the longer side 21a short It is located on the side 21b. The first portion 31a has a chip area 31a1 where the semiconductor chip 40a is placed, which is set along the longer side 21a. The number of chip areas 31a1 is arbitrary, and Figure 2 shows two cases. The chip areas 31a1 are set apart from the shorter side 21b relative to the first portion 31a.

[0032] The second part 31b is along the longer side 21a short It is located on the side 21d. The terminal region 31b1 to which the internal junction 6b of the positive terminal 6 is joined is set on the short side 21d. The widths of the first portion 31a and the second portion 31b in the ±X direction are approximately equal.

[0033] The wiring portion 31c connects the first portion 31a and the second portion 31b and is provided along the long side 21a, on the long side 21a side. The width of the wiring portion 31c in the ±X direction is narrower than the width of the first portion 31a and the second portion 31b in the ±X direction.

[0034] The circuit pattern 32 is approximately symmetrical to the circuit pattern 31 with respect to a straight line in the ±Y direction. The circuit pattern 32 is formed on the long side 21c side of the insulating plate 21, along the long side 21c, from the short side 21b to the short side 21d. The circuit pattern 32 includes a first part 32a, a second part 32b, and a wiring part 32c.

[0035] Part 1 32a is along the longer side 21c short It is provided on the side 21b. The first portion 32a has a chip area 32a1 where the semiconductor chip 40c is placed, which is set along the long side 21c. The number of chip areas 32a1 is arbitrary, and Figure 2 shows two cases. The chip area 32a1 is set apart from the short side 21b of the first portion 32a. In addition, a notched area is formed at the corner on the short side 21b of the first portion 32a, in the -X direction.

[0036] Part 2, 32b, is along the longer side 21c. short It is located on the side 21d. The terminal region 32b1 to which the internal junction 6a of the positive terminal 6 is joined is set on the short side 21d. The widths of the first portion 32a and the second portion 32b in the ±X direction are approximately equal.

[0037] The wiring portion 32c connects the first portion 32a and the second portion 32b and is provided along the long side 21c, on the long side 21c side. The width of the wiring portion 32c in the ±X direction is narrower than the width of the first portion 32a and the second portion 32b in the ±X direction.

[0038] Circuit pattern 33 is adjacent to the first portion 31a of circuit pattern 31 and extends in the -Y direction from the short side 21b along the long side 21a. The -Y end of circuit pattern 33 is spaced apart from the short side 21d. The side of circuit pattern 33 on the long side 21c is recessed midway.

[0039] Circuit pattern 34 is approximately symmetrical to circuit pattern 33 with respect to a straight line in the ±Y direction. Circuit pattern 34 is adjacent to the first portion 32a of circuit pattern 32 and extends from the short side 21b in the -Y direction along the long side 21c. The -Y end of circuit pattern 34 is spaced apart from the short side 21d. The side of circuit pattern 34 on the long side 21a is recessed midway. In addition, a notched region is formed at the corner on the short side 21b of circuit pattern 34, on the +X direction side.

[0040] Although semiconductor chips 40b and 40d are also placed in circuit patterns 33 and 34, the chip areas are not shown in the diagram. The semiconductor chips 40b and 40d are placed in the positions shown in Figure 1 in circuit patterns 33 and 34.

[0041] Circuit pattern 35 is located in the region enclosed by the second portion 31b and wiring portion 31c of circuit pattern 31, the short side 21d, and circuit pattern 33. In other words, circuit pattern 35 is roughly L-shaped.

[0042] Circuit pattern 36 is approximately symmetrical to circuit pattern 35 with respect to a straight line in the ±Y direction. Circuit pattern 36 is located in the region enclosed by the second part 32b and wiring part 32c of circuit pattern 32, the short side 21d, and circuit pattern 34. In other words, circuit pattern 36 is roughly L-shaped.

[0043] Circuit pattern 37a is I-shaped in plan view and is positioned on the side of circuit pattern 33, along the long side 21a, within the region enclosed by the recesses of circuit patterns 33 and 34. Circuit pattern 37b is L-shaped in plan view and is positioned on the side of circuit pattern 34, along the long side 21c, within the region enclosed by the recesses of circuit patterns 33 and 34. Circuit pattern 37b is positioned to surround circuit pattern 37a. Circuit pattern 37c is I-shaped in plan view and is positioned between circuit patterns 33 and 34, along the long sides 21a and 21c.

[0044] As the insulating circuit board 20 having such a configuration, for example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazed) board may be used. The insulating circuit board 20 dissipates heat generated by the semiconductor chips 40a to 40d, which will be described later, by conducting it to the back side of the insulating circuit board 20 via the circuit patterns 31 to 34, the insulating plate 21, and the metal plate 22.

[0045] Furthermore, the insulating circuit board 20 includes a conductive member 60. In the first embodiment, the conductive member 60 is in the shape of a flat plate. Such a conductive member 60 is provided on the front surface of the wiring portions 31c and 32c of the circuit patterns 31 and 32. The width of the conductive member 60 in the ±X direction may be the same as, or narrower than, the width of the wiring portions 31c and 32c in the ±X direction. The conductive member 60 is arranged from the connection point with the first portion 31a and 32a of the wiring portions 31c and 32c to the connection point with the second portion 31b and 32b. The height of the conductive member 60 may be about the same as the thickness of the semiconductor chips 40a to 40d. As will be described later, the current that conducts through the wiring portions 31c and 32c also conducts through the conductive member 60. Therefore, the wiring resistance of the wiring portions 31c and 32c is reduced. The current flowing through the conductive member 60 is biased towards the underside of the conductive member 60 (the side of the circuit patterns 31 and 32). Therefore, there is no need to make the conductive member 60 too thick. The conductive member 60 is mainly composed of a material having electrical conductivity and thermal conductivity equal to or greater than that of the wiring portions 31c and 32c. Such a material is, for example, copper or a copper alloy. The conductive member 60 is joined to the front surface of the wiring portions 31c and 32c of the circuit patterns 31 and 32 by a joining member. The joining member is either solder or a sintered material. Lead-free solder is used. Lead-free solder is mainly composed of an alloy containing at least two of the following: tin, silver, copper, zinc, antimony, indium, and bismuth. Furthermore, the solder may contain additives. Additives are, for example, nickel, germanium, cobalt, or silicon. The inclusion of additives in the solder improves wettability, gloss, and bonding strength, thereby improving reliability. Sintered materials may include, for example, metallic materials containing silver or silver alloys.

[0046] The semiconductor chips 40a to 40d are power devices made of silicon carbide. An example of such a power device is a power MOSFET. These semiconductor chips 40a to 40d have a drain electrode as the input electrode (main electrode) on the back surface, and a gate electrode as the control electrode 41a to 41d and a source electrode as the output electrode (main electrode) on the front surface.

[0047] Furthermore, the semiconductor chips 40a to 40d may be power devices made of silicon. In this case, the power device is, for example, an RC (Reverse Conducting)-IGBT. An RC-IGBT is a chip in which an IGBT, which is a switching element, and an FWD (Free Wheeling Diode), which is a diode element, are configured on a single chip. Such semiconductor chips 40a to 40d have, for example, a collector electrode as an input electrode (main electrode) on the back surface, and a gate electrode as a control electrode and an emitter electrode as an output electrode (main electrode) on the front surface.

[0048] As shown in Figure 1, multiple semiconductor chips 40a to 40d are arranged on each of the circuit patterns 31, 33, 32, and 34. In the first embodiment, two of each are shown. In this case, each semiconductor chip 40a to 40d is arranged so that its control electrodes 41a to 41d face each other. The semiconductor chips 40a to 40d are also bonded to the circuit patterns 31, 33, 32, and 34 by the bonding member described above.

[0049] The lead frames 50a to 50d electrically connect the output electrodes on the front surface of the semiconductor chips 40a to 40d to the circuit patterns 33 to 36. For example, as shown in Figure 3, the lead frames 50b and 50d include pattern joints 51b and 51d, first vertical linkages 52b and 52d, horizontal linkages 53b and 53d, second vertical linkages 54b and 54d, and chip joints 55b and 55d. The pattern joints 51b and 51d are joined to the circuit patterns 35 and 36. The first vertical linkages 52b and 52d are connected to the ends of the pattern joints 51b and 51d and extend vertically. The horizontal linkages 53b and 53d extend from the ends of the first vertical linkages 52b and 52d toward the semiconductor chips 40b and 40d, respectively. The second vertical linkage sections 54b and 54d extend vertically from the ends of the horizontal linkage sections 53b and 53d toward the semiconductor chips 40b and 40d. The chip bonding sections 55b and 55d are bonded to the output electrodes of the semiconductor chips 40b and 40d, respectively, and their ends are connected to the second vertical linkage sections 54b and 54d.

[0050] Similarly, lead frames 50a and 50c also include a pattern joint, a first vertical linkage, a horizontal linkage, a second vertical linkage, and a tip joint. Figure 4 shows the pattern joint 51a and the first vertical linkage 52a included in lead frame 50a. However, details of lead frames 50a and 50c are omitted.

[0051] The chip bonding portions of each lead frame 50a to 50d can use the aforementioned bonding members for the output electrodes of semiconductor chips 40a to 40d. Furthermore, the pattern bonding portions of each lead frame 50a to 50d can use the aforementioned bonding members for the circuit patterns 33, 35, 34, and 36, or ultrasonic bonding can be performed.

[0052] The lead frames 50a to 50d are made of a material with excellent electrical and thermal conductivity. Examples of such materials include copper, aluminum, or alloys containing at least one of these. In addition, the surfaces of the lead frames 50a to 50d may be plated to improve corrosion resistance. Examples of plating materials in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0053] Although not shown in the diagram, the control electrodes 41a and 41c of semiconductor chips 40a and 40c are connected to circuit patterns 37a and 37b, respectively, by wiring components. The control electrodes 41b and 41d of semiconductor chips 40b and 40d are connected to circuit pattern 37c, respectively, by wiring components. Control signals are input to circuit patterns 37a, 37b, and 37c from an external source.

[0054] A semiconductor module 1 having such a configuration operates when high-potential and low-potential terminals are connected externally to the positive terminal 6 and negative terminal 7, respectively, and a control signal is input. In particular, in response to the on / off state of the control signal to semiconductor chips 40a to 40d, current flows from the internal junctions 6a and 6b of the positive terminal 6 to the circuit patterns 32 and 31. The current flowing into the circuit patterns 32 and 31 flows from the second parts 32b and 31b through the wiring parts 32c and 31c to the semiconductor chips 40 of the first parts 32a and 31a. c ,40 a The current is input to the input electrodes. At this time, the wiring portions 32c and 31c are considerably narrower than the width of the first portions 32a and 31a and the second portions 32b and 31b. Therefore, the wiring portions 32c and 31c may generate heat due to Joule heating. For example, the wiring portions 32c and 31c have a width of 2.6 mm (in the ±X direction), a thickness of 0.4 mm, and carry a current of 600 A. In this case, if there is no conductive material 60, 60 W will be lost in the wiring portions 32c and 31c, and the temperature will rise by more than 30°C. When the temperature rises in this way, the semiconductor chips 40b and 40d located near the wiring portions 32c and 31c may not be sufficiently cooled even if the heat is dissipated towards the base substrate 8 below, and may fail.

[0055] In the first embodiment, conductive members 60 are placed in the wiring portions 32c and 31c of the circuit patterns 32 and 31, respectively. The current flowing through the wiring portions 32c and 31c also flows through the conductive members 60. As a result, the wiring resistance of the wiring portions 32c and 31c is reduced, losses are reduced, and heat generation due to Joule heating can be reduced. In other words, it becomes possible to place semiconductor chips 40b and 40d near the circuit patterns 32 and 31 where heat generation may occur, improving the flexibility of the placement of semiconductor chips 40b and 40d. Furthermore, even if reducing the volume of the circuit patterns 31 to 36 results in areas where wiring resistance increases, heat generation can be reduced by providing conductive members 60 in such areas. As a result, miniaturization can be achieved while maintaining the reliability of the semiconductor module 1. Note that the reduction in volume of the circuit patterns 31 to 36 refers to a reduction in the width perpendicular to the direction of conduction in a plan view, and a reduction in the thickness in a cross-sectional view.

[0056] Alternatively, instead of using such a conductive member 60, it is also conceivable to bond one or more wires to the wiring portions 32c and 31c of the circuit patterns 32 and 31. However, when wires are bonded to the wiring portions 32c and 31c, there is a risk that the bonded area may peel off from the wiring portions 32c and 31c. On the other hand, with the conductive member 60, the occurrence of peeling, as seen when using wires, is suppressed.

[0057] Alternatively, one could consider making only the wiring portions 32c and 31c of circuit patterns 32 and 31 thicker than the rest. However, in this case, it is difficult to process only specific parts of circuit patterns 32 and 31 to be thicker than the rest. Furthermore, if only specific parts of circuit patterns 32 and 31 are made thicker than the rest, the thickness is limited, and it may not be possible to adequately suppress heat generation.

[0058] Furthermore, in the first embodiment, the case in which the conductive member 60 is placed in the wiring portions 32c and 31c of the circuit patterns 32 and 31 is given as an example. The conductive member 60 may be placed in parts other than the wiring portions 32c and 31c of the circuit patterns 32 and 31, or in other circuit patterns, as long as there is a risk of the temperature rising due to heat generation. Examples of locations where the temperature tends to rise when current is applied include the circuit patterns 31 to 36 that are electrically connected to the input and output electrodes of the semiconductor chips 40a to 40d. The conductive member 60 may be placed in such circuit patterns 31 to 36 (and the region containing the circuit patterns 31 to 36).

[0059] Furthermore, the shape of the conductive member 60 in plan view corresponds to the shape of the wiring portions 32c and 31c of the circuit patterns 32 and 31. Since the wiring portions 32c and 31c of the circuit patterns 32 and 31 in the first embodiment are linear, the conductive member 60 is also linear. If the shape of the wiring portions 32c and 31c in plan view is, for example, L-shaped or crank-shaped, the conductive member 60 will have a similar shape.

[0060] The conductive member 60 is not limited to a flat plate shape. Various modified forms of the conductive member 60 are described below. Note that in each of the following modified forms, only the form of the conductive member 60 differs; the other components of the semiconductor module 1 are the same as in Figures 1 to 4.

[0061] [Variation 1-1] A modified example 1-1 of the first embodiment will be described with reference to Figures 5 and 6. Figures 5 and 6 are cross-sectional views of the main part of the semiconductor module of the first embodiment (modified example 1-1). Figures 5 and 6 correspond to Figures 3 and 4, and are enlarged cross-sectional views of the main part of the conductive member 60a. Figure 5 is a cross-sectional view taken along the dashed line YY in Figure 6.

[0062] The conductive member 60a of the modified example 1-1 includes a flat plate portion 61 and a support portion 62. The flat plate portion 61 is flat. In this case, the width of the flat plate portion 61 in the ±X direction may be the same as, or narrower than, the width of the wiring portions 31c and 32c in the ±X direction. The support portion 62 is columnar. The length of the support portion 62 in the ±Y direction may be approximately the same as the length of the wiring portions 32c and 31c in the ±Y direction. The width of the support portion 62 in the ±X direction may be narrower than the width of the flat plate portion 61 in the ±X direction. The cross-section of the conductive member 60a of this modified example 1-1 in the ±X direction is T-shaped.

[0063] The conductive member 60a has a support portion 62 connected to the back surface of the flat plate portion 61 and is joined to the wiring portions 32c and 31c of the circuit patterns 32 and 31 by the aforementioned joining member. Therefore, the current that conducts through the wiring portions 32c and 31c of the circuit patterns 32 and 31 also conducts through the conductive member 60a. As a result, similar to the first embodiment, the wiring resistance of the wiring portions 32c and 31c is reduced, losses are also reduced, and heat generation due to Joule heating can be reduced. In other words, it becomes possible to place semiconductor chips 40b and 40d near the circuit patterns 32 and 31 where heat generation may occur, improving layout flexibility. Furthermore, even if regions where wiring resistance improves occur by reducing the volume of the circuit patterns 31 to 36, the conductive member 60 can be placed in such regions. a By providing this feature, heat generation can be reduced. Therefore, the reliability of the semiconductor module 1 can be maintained while achieving miniaturization.

[0064] Furthermore, the conductive member 60a is T-shaped. Therefore, when the conductive member 60a is sealed with the sealing member 9, the sealing member 9 also penetrates the back surface of the flat plate portion 61. The conductive member 60a provides an anchoring effect to the sealing member 9, suppressing the peeling of the sealing member 9.

[0065] [Variation 1-2] A modified example 1-2 of the first embodiment will be described with reference to Figure 7. Figure 7 is a cross-sectional view of the main part of the semiconductor module of the first embodiment (modified example 1-2). Note that Figure 7 corresponds to Figure 3 and is an enlarged cross-sectional view of the main part of the conductive member 60b.

[0066] The conductive member 60b in modified example 1-2 includes a flat plate portion 61, a support portion 62, and a flat plate portion 63. That is, the conductive member 60b has an additional flat plate portion 63 provided below the support portion 62 of the conductive member 60a in modified example 1-1. The cross-section of the conductive member 60b in the ±X direction has an H-shape turned on its side.

[0067] The width of the flat plate portion 63 in the ±X direction may be the same as, or narrower than, the width of the wiring portions 31c and 32c in the ±X direction. The flat plate portion 63 is positioned between the connection points of the first portions 31a and 32a of the wiring portions 31c and 32c and the connection points of the second portions 31b and 32b. The flat plate portion 61 may be the same as the flat plate portion 63.

[0068] Similar to conductive member 60a, when conductive member 60b is attached to the wiring portions 32c and 31c of the circuit patterns 32 and 31 by the aforementioned bonding member, the wiring resistance of the wiring portions 32c and 31c is reduced, losses are reduced, and heat generation due to Joule heating can be reduced. Furthermore, conductive member 60b has a gap between the flat plate portions 61 and 63. Therefore, when conductive member 60a is sealed with the sealing member 9, the sealing member 9 also penetrates the back surface of the flat plate portion 61. Conductive member 60a provides an anchoring effect to the sealing member 9, suppressing peeling of the sealing member 9. Moreover, conductive member 60b has a flat plate portion 63 that is wider than the support portion 62 of conductive member 60a, which is bonded to the wiring portions 32c and 31c of the circuit patterns 32 and 31. Therefore, conductive member 60b is bonded to the wiring portions 32c and 31c of the circuit patterns 32 and 31 more stably than conductive member 60a.

[0069] [Modifications 1-3] Modification 1-3 of the first embodiment will be described with reference to Figure 8. Figure 8 is a cross-sectional view of the main part of the semiconductor module of the first embodiment (modification 1-3). Note that Figure 8 corresponds to Figure 3 and is an enlarged cross-sectional view of the main part of the conductive member 60c.

[0070] The conductive member 60c in Modification 1-3 includes a flat plate portion 61 and a plurality of groove portions 64. The flat plate portion 61 is the same as in Modification 1-1. The plurality of groove portions 64 are formed on the front surface of the flat plate portion 61 along the long side of the flat plate portion 61. The depth of the groove portions 64 extends from the front surface of the flat plate portion 61 to a maximum of 50% of the thickness of the flat plate portion 61. The cross-sectional shape of the groove portions 64 in the ±X direction may be, for example, U-shaped or V-shaped.

[0071] Such conductive member 60c, like conductive member 60, when attached to the wiring portions 32c and 31c of the circuit patterns 32 and 31 by the aforementioned bonding member, reduces the wiring resistance of the wiring portions 32c and 31c, reduces losses, and reduces heat generation due to Joule heating. Furthermore, conductive member 60c has multiple grooves 64 formed therein. Therefore, conductive member 60 c When the sealing member 9 is applied, the sealing member 9 also enters into the multiple grooves 64 of the flat plate portion 61. The multiple grooves 64 of the conductive member 60c provide an anchoring effect to the sealing member 9, suppressing the peeling of the sealing member 9.

[0072] Furthermore, instead of the multiple grooves 64 formed in the flat plate portion 61 of the conductive member 60c, a similar anchoring effect can be achieved by forming multiple protrusions on the entire surface of the flat plate portion 61. The protrusions may be, for example, prismatic, cylindrical, conical, or frustoconical. Alternatively, instead of the multiple grooves 64, multiple depressions may be formed on the entire surface of the flat plate portion 61. Such multiple grooves 64 (and protrusions) may be formed on the surface of the flat plate portion 61 in the modified examples 1-1 and 1-2.

[0073] [Second Embodiment] In the second embodiment, a case in which a conductive member of a different form than the conductive member 60 of the first embodiment is used will be described with reference to Figures 9 and 10. Figures 9 and 10 are cross-sectional views of the main part of the semiconductor module of the second embodiment. Figures 9 and 10 correspond to Figures 4 and 3, and are enlarged cross-sectional views of the main part of the conductive member 60d. Figure 10 is a cross-sectional view of the main part along the dashed line YY in Figure 9. In the second embodiment, only the conductive member 60 differs from that of the first embodiment, and the other configurations of the semiconductor module 1 are the same as in Figures 1 to 4. Plan views and cross-sectional views of the semiconductor module 1 can be found in Figures 1, 3 and 4.

[0074] The conductive member 60d of the second embodiment includes a flat plate portion 61 and leg portions 65a and 65b formed at both ends of the flat plate portion 61 in the longitudinal direction. That is, the conductive member 60d has a shape (bridge type) that bridges the ±Y ends of the wiring portions 32c and 31c of the circuit patterns 32 and 31. In other words, the flat plate portion 61 is spaced apart from the front surface of the circuit patterns 32 and 31 in the +Z direction, leaving a gap.

[0075] The flat plate portion 61 is the same as the flat plate portion 61 of the first embodiment. That is, the width of the flat plate portion 61 in the ±X direction may be the same as, or narrower than, the width of the wiring portions 31c and 32c in the ±X direction. The length of the flat plate portion 61 is less than or equal to the length between the connection point with the first portions 31a and 32a of the wiring portions 31c and 32c and the connection point with the second portions 31b and 32b. Preferably, the length of the flat plate portion 61 is the length between the connection point with the first portions 31a and 32a of the wiring portions 31c and 32c and the connection point with the second portions 31b and 32b.

[0076] The legs 65a and 65b are integrally formed at both ends of the flat plate portion 61 in the ±Y direction, respectively. The leg 65a is joined to the first portion 31a and 32a side from the connection point between the wiring portions 31c and 32c and the first portion 31a and 32a. The leg 65b is joined to the second portion 31b and 32b side from the connection point between the wiring portions 31c and 32c and the second portion 31b and 32b. As a result, the flat plate portion 61 faces the wiring portions 31c and 32c directly, and the joining area of ​​the legs 65a and 65b to the circuit patterns 32 and 31 is secured. The legs 65a and 65b are joined by the joining member described above or by ultrasonic bonding. The legs 65a and 65b only need to have a shape that can be joined to the wiring portions 32c and 31c of the circuit patterns 32 and 31. Such a shape is, for example, L-shaped when viewed from the side (see Figure 9). Also, the height of the legs 65a and 65b from the circuit patterns 32 and 31 may be about the same as the thickness of the semiconductor chips 40a to 40d.

[0077] Even with such a conductive member 60d, if it is placed in the wiring portions 32c and 31c of the circuit patterns 32 and 31, the current that flows through the wiring portions 32c and 31c will be transmitted through the conductive member 60 d Also conducts electricity. As a result, the wiring resistance of the wiring sections 32c and 31c is reduced, losses are also reduced, and heat generation due to Joule heating can be reduced. In other words, it becomes possible to place semiconductor chips 40b and 40d near circuit patterns 32 and 31 where heat generation may occur, improving layout flexibility. Furthermore, even if regions where wiring resistance improves occur by reducing the volume of circuit patterns 31 to 36, conductive members 60 can be placed in such regions. d By providing this feature, it becomes possible to reduce heat generation.

[0078] Furthermore, semiconductor chips 40a to 40d (or a part of semiconductor chips 40a to 40d) may be positioned in the gap between such bridge-shaped conductive member 60d and the wiring portions 32c and 31c of the circuit patterns 32 and 31. Figure 9 shows the case where the semiconductor chip 40b is located in the gap between the conductive member 60d and the circuit pattern 31.However, in this case, it is necessary to maintain a certain level of insulation distance between the conductive member 60d and the semiconductor chips 40a to 40d. Therefore, the degree of freedom in arranging the semiconductor chips 40a to 40d is further improved. Also, even if regions where wiring resistance improves occur due to the reduction in volume of the circuit patterns 31 to 36, it is possible to reduce heat generation by providing the conductive member 60d in such regions. As a result, further miniaturization can be achieved while maintaining the reliability of the semiconductor module 1.

[0079] The conductive member 60d includes one flat plate portion 61, and the flat plate portion 61 is not limited to being flat. Various modified forms of the conductive member 60d are described below. Note that in each of the following modified forms, only the form of the conductive member 60d differs; the other components of the semiconductor module 1 are the same as in Figures 1 to 4.

[0080] [Modification 2-1] A modified example 2-1 of the second embodiment will be described using Figures 11 and 12. Figures 11 and 12 are cross-sectional views of the main part of the semiconductor module of the second embodiment (modified example 2-1). Figures 11 and 12 correspond to Figures 4 and 3, and are enlarged cross-sectional views of the main part of the conductive member 60e. Figure 12 is a cross-sectional view of the main part along the dashed line YY in Figure 11.

[0081] The conductive member 60e of modified example 2-1 includes two flat plate portions 61 and 63 and leg portions 65a and 65b. The flat plate portion 63 is provided in the -Z direction of the flat plate portion 61. That is, in the conductive member 60d, the flat plate portion 63 is provided with a gap between it and the flat plate portion 61. In other words, both ends of the flat plate portions 61 and 63 in the ±Y direction are connected by the leg portions 65a and 65b. Note that the leg portions 65a and 65b can have any shape as long as they can connect the flat plate portions 61 and 63. As an example, Figure 11 shows the case where the conductive member 60d of Figure 9 is superimposed in the Z direction. In the modified example 2-1, semiconductor chips 40a to 40d (or a portion of semiconductor chips 40a to 40d) may also be located in the gap between the conductive member 60e and the wiring portions 32c and 31c of the circuit patterns 32 and 31. Figure 11 shows the case where semiconductor chip 40b is located in the gap between the conductive member 60e and the circuit pattern 31.

[0082] In this conductive member 60e, as in the second embodiment, the wiring resistance of the wiring portions 32c and 31c is reduced, losses are also reduced, and heat generation due to Joule heating can be reduced. Furthermore, in the conductive member 60d of the second embodiment, there is a risk that differences in the current flowing through it (current imbalance) may occur depending on the difference in wiring resistance between the conductive member 60d and the wiring portions 32c and 31c of the circuit patterns 32 and 31. The conductive member 60e of Modification 2-1 has two flat plate portions 61 and 63, which can suppress such current imbalance.

[0083] The conductive member 60e in Modification 2-1 is described using the example of two flat plate sections 61 and 63. The conductive member 60e is not limited to two; it may consist of three or more flat plate sections stacked with gaps between them. Furthermore, the cross-sectional area of ​​such multiple flat plate sections may increase as they move away from the circuit pattern. This makes it possible to further suppress current imbalance.

[0084] [Modification 2-2] Modification 2 of the second embodiment 2 This will be explained using Figure 13. Figure 13 is a cross-sectional view of the main part of the semiconductor module of the second embodiment (modified example 2-2). Note that Figure 13 corresponds to Figure 4 and is an enlarged cross-sectional view of the main part of the conductive member 60f. For example, Figure 11 can be used to refer to the view of Figure 13 in the +X direction. Therefore, Figure 13 can also be used as a cross-sectional view of the main part along the dashed line YY in Figure 11.

[0085] The conductive member 60f in Modification 2-2 includes multiple cylindrical sections 66 and leg sections 65a and 65b. In Figure 13, the leg section 65b is shown. The number of cylindrical sections 66 increases as you move in the +Z direction. In Modification 2-2, one cylindrical section 66 is provided, and two parallel cylindrical sections 66 are provided on top of it. Leg sections 65a and 65b are provided at one end and the other end of the cylindrical section 66 in the longitudinal direction, similar to Modification 2-1.

[0086] In this conductive member 60f, as in the modified example 2-1, the wiring resistance of the wiring portions 32c and 31c is reduced, losses are also reduced, and heat generation due to Joule heating can be reduced. Furthermore, the conductive member 60f of modified example 2-2 has multiple cylindrical portions 66, which can suppress such current imbalance. In particular, the skin effect is observed in the cylindrical portions 66 of the conductive member 60f. As a result, the resistance to current flowing through the cylindrical portions 66 is reduced, making it easier to conduct electricity. Also, variation 2- 2 The following describes the case where the number of cylindrical sections 66 increases in the +Z direction. However, the cross-sectional area of ​​the cylindrical sections 66 may also be increased by stacking the cylindrical sections 66 one by one in the +Z direction with gaps between them. [Explanation of Symbols]

[0087] 1. Semiconductor module 2 cases 3 Outer frame 3a, 3c, 21a, 21c Longer side 3b,3d,21b,21d Short side 3e Storage compartment 5 Output terminals 5a,5b,6a,6b,7a,7b Internal joints 6. Positive terminal 7 Negative terminal 8 Base board 9 Sealing member 10 Semiconductor Units 20 Insulated circuit board 21 Insulating board 21e,21f,21g,21h corner 22 Metal plate Circuit patterns 31, 32, 33, 34, 35, 36, 37a, 37b, 37c 31a,32a 1st part 31a1, 32a1 Chip area 31b,32b 2nd part 31b1,32b1 Terminal area 31c,32c wiring part 40a, 40b, 40c, 40d semiconductor chips 41a, 41b, 41c, 41d control electrodes 50a, 50b, 50c, 50d lead frames 51a, 51b, 51d Pattern joint 52a, 52b, 52d First vertical linkage section 53b, 53d Horizontal linkage section 54b, 54d Second vertical linkage section 55b, 55d Chip joint 60, 60a, 60b, 60c, 60d, 60e Conductive material 61,63 Flat plate part 62 Support part 64 groove 65a,65b Legs 66. Cylindrical section

Claims

1. A semiconductor chip having a first main electrode on the back side and a second main electrode on the front side, A wiring layer is electrically connected to at least one of the first main electrode or the second main electrode, and a conductive member is disposed on its front surface. The aforementioned wiring layer is It includes a first portion on the front surface which includes a chip region to which the back surface of the semiconductor chip is bonded, a second portion on the front surface which includes a terminal region to which external connection terminals are bonded, and a wiring portion which connects the first portion and the second portion and on the front surface which the conductive member is arranged. The conductive member has a width in a direction perpendicular to the conductive direction of the wiring portion in a plan view, and includes a flat plate portion that forms a flat plate shape along the wiring portion. The flat plate portion is provided with a gap between it and the front surface of the wiring portion. The conductive member further comprises a pair of legs that connect both ends of the flat plate portion to the front surface of the wiring portion, The conductive member is arranged in such a way that multiple flat plate portions are stacked with gaps between them, in a direction that separates them from the front surface of the wiring portion. Semiconductor equipment.

2. The cross-sectional area of ​​each of the multiple flat plate portions increases as they move away from the front surface of the wiring portion. The semiconductor device according to claim 1.

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