Semiconductor equipment

Abstract

To provide a semiconductor device capable of improving manufacturing efficiency and manufacturing quality by suppressing the vibrations and positional deviation of a lead frame.SOLUTION: A semiconductor device comprises a plurality of integrated circuits, an IC frame that is loaded with the plurality of integrated circuits, and a sealing material. The IC frame has a first protrusion that extends in the longitudinal direction of the IC frame, a second protrusion that is positioned on the opposite side to the first protrusion in the first frame and that extends in the opposite direction to the first protrusion, and a third protrusion that extends in the short direction of the IC frame and that is built in the sealing material.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a technology related to a lead frame on which chips of two integrated circuits (ICs) are mounted. This lead frame has one protrusion that supports an IC die bonding portion in the process of IC die bonding or wire bonding.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Since the above-mentioned lead frame mounts two chips, by widening the IC die bonding portion, the area and weight of the IC die bonding portion have increased. As a result, during IC die bonding or wire bonding, vibration or displacement of the lead frame is likely to occur.

[0005] However, since the above-mentioned lead frame has only one protrusion that supports the IC die bonding portion, vibration and displacement cannot be sufficiently suppressed. As a result, there has been a problem that the manufacturing efficiency and manufacturing quality deteriorate due to the poor accuracy of IC die bonding and wire bonding.

[0006] An object of this disclosure is to provide a semiconductor device that can improve manufacturing efficiency and manufacturing quality by suppressing vibration and displacement of a lead frame in order to solve the above problems.

Means for Solving the Problems

[0007] A preferred aspect of the present disclosure is a semiconductor device comprising a plurality of integrated circuits, an IC frame on which the plurality of integrated circuits are mounted, and a encapsulating material, wherein the IC frame has a first projection extending in the longitudinal direction of the IC frame, a second projection located on the opposite side of the first projection in the IC frame and extending in the opposite direction to the first projection, and a third projection extending in the short direction of the IC frame and embedded in the encapsulating material. [Effects of the Invention]

[0008] Aspects of the present disclosure include a plurality of integrated circuits, an IC frame on which the plurality of integrated circuits are mounted, and a encapsulating material, wherein the IC frame has a first projection extending in the longitudinal direction of the IC frame, a second projection located on the opposite side of the IC frame from the first projection and extending in the opposite direction from the first projection, and a third projection extending in the short direction of the IC frame and embedded in the encapsulating material. Furthermore, multiple integrated circuits are actually two integrated circuits, and a third protrusion is located at a position that is the same distance from each of the two integrated circuits. It is preferable that it be a semiconductor device. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing a semiconductor device according to Embodiment 1 of the present disclosure. [Figure 2] This is a plan view showing a semiconductor device according to Embodiment 2 of the present disclosure. [Figure 3] This is a plan view showing a semiconductor device according to Embodiment 3 of the present disclosure. [Figure 4] This is a plan view showing a semiconductor device according to Embodiment 4 of the present disclosure. [Figure 5] This is a plan view showing a comparative example with the semiconductor device according to Embodiment 4 of this disclosure. [Figure 6] This is a plan view showing a semiconductor device according to Embodiment 5 of the present disclosure. [Modes for carrying out the invention]

[0010] Embodiment 1 Figure 1 is a plan view showing a semiconductor device according to Embodiment 1 of the present disclosure. The semiconductor device 100 comprises an IC frame 1. The IC frame 1 is a conductive lead frame having a longitudinal direction in the first direction 50.

[0011] IC frame 1 has an IC die bond portion 1a, indicated by a dotted line. LVIC2 and HVIC3 are bonded to the IC die bond portion 1a, aligned in the first direction 50. LVIC2 is a control IC. HVIC3 is a control IC to which a higher voltage than that of LVIC2 is input.

[0012] LVIC2 is electrically connected to the semiconductor element 4 bonded to the low-side frame 7 via LVIC wiring 9. Similarly, HVIC3 is electrically connected to the semiconductor element 4 bonded to the high-side frame 8 via HVIC wiring 10. The IC die bond portion 1a, LVIC2, HVIC3, and semiconductor element 4 are covered with an insulating encapsulant.

[0013] The IC die bond portion 1a has a first projection 5a and a second projection 5b extending in the first direction 50, and a third projection 5c extending in the second direction 60. The second direction 60 is perpendicular to the first direction 50. The entire third projection 5c is embedded in the encapsulating material 6. The third projection 5c is also provided on the side edge opposite to the semiconductor element 4. Here, the third projection 5c is shown to be located near the HVIC3, but it may also be located near the LVIC2.

[0014] The wire bonding process for the semiconductor device 100 is described below. In the wire bonding process, the LVIC 2 and the semiconductor element 4 are bonded via the LVIC wiring 9. In addition, the HVIC 3 and the semiconductor element 4 are bonded via the HVIC wiring 10. At this time, the semiconductor device 100 is fixed in place by pressing the first projection 5a, the second projection 5b, and the third projection 5c with a jig provided by the bonding apparatus.

[0015] The IC die bonding part 1a is configured to have a large area in order to accommodate two types of control ICs, namely the LVIC 2 and the HVIC 3. Therefore, during wire bonding, vibration and displacement of the IC frame 1 are likely to occur. However, with only one point of the first protrusion 5a, or only two points of the first protrusion 5a and the second protrusion 5b fixed, only the direction of the first direction 50 can be fixed, so vibration cannot be completely suppressed.

[0016] Therefore, a third protrusion 5c extending in the second direction 60 is added and fixed at three points. As a result, it is possible to hold the vicinity of the center of the longitudinal direction where the fixation is weak, so that the vibration and displacement of the IC frame 1 can be sufficiently suppressed. As a result, stable wire bonding becomes possible, improving the manufacturing efficiency and quality of the semiconductor device 100.

[0017] Therefore, a third protrusion 5c extending in the second direction 60 is added and fixed at three points. By this direction it is possible to hold the vicinity of the center of the longitudinal direction where the fixation is weak, so that the vibration and displacement of the IC frame 1 can be sufficiently suppressed. As a result, stable wire bonding becomes possible, improving the manufacturing efficiency and quality of the semiconductor device 100.

[0018] Embodiment 2 FIG. 2 is a plan view showing a semiconductor device according to Embodiment 2 of the present disclosure. The semiconductor device 200 according to Embodiment 2 is different from Embodiment 1 in that the point where the third protrusion 5c is at the same distance from the LVIC 2 and the HVIC 3.

[0019] The IC die bonding portion 1a has a third protrusion 5c. The third protrusion 5c is positioned such that the distances from the LVIC 2 and the HVIC 3 are the same in the first direction 50. Thereby, the IC frame 1 can be stably fixed as compared with the case where the third protrusion 5c is positioned closer to the LVIC 2 or the HVIC 3. That is, since the vibration and displacement of the IC frame 1 can be suppressed to a minimum, stable wire bonding becomes possible, and the manufacturing efficiency and manufacturing quality of the semiconductor device 200 can be improved.

[0020] Embodiment 3 FIG. 3 is a plan view showing a semiconductor device according to Embodiment 3 of the present disclosure. The semiconductor device 300 according to Embodiment 3 is different from Embodiment 1 in that the IC die bonding portion 1a has a plated region between the LVIC 2 and the HVIC 3.

[0021] The IC die bonding portion 1a has a plating portion 11. The plating portion 11 is located between the LVIC 2 and the HVIC 3. Thereby, since the wirings from the LVIC 2 and the HVIC 3 can be wire-bonded to the plating portion 11, the wirings can be shortened. That is, in the manufacturing process, since the wiring flow when injecting the sealing material can be suppressed, the manufacturing quality of the semiconductor device 300 can be improved.

[0022] Also, when the area of the plating portion 11 is set to a size that enables a plurality of wirings, a plurality of wirings from the LVIC 2 and the HVIC 3 can be wire-bonded. Thereby, the functionality of the semiconductor device 300 can be improved.

[0023] Embodiment 4 FIG. 4 is a plan view showing a semiconductor device according to Embodiment 4 of the present disclosure. The semiconductor device 400 according to Embodiment 4 is different from Embodiment 1 in that it has two types of semiconductor elements.

[0024] The low-side frame 7 has semiconductor elements 4a and 4b. The high-side frame 8 also has semiconductor elements 4a and 4b. As a result, the number of wirings for LVIC wiring 9 and HVIC wiring 10 increases.

[0025] However, in the semiconductor device 400, the IC die bond portion 1a has a first projection 5a, a second projection 5b, and a third projection 5c. Therefore, the LVIC2 and HVIC3 can take on a long shape in the first direction 50. In other words, even if the number of wirings for the LVIC 9 and HVIC 10 increases, the wiring itself can be shortened by optimizing its arrangement.

[0026] This improves the manufacturing quality of the semiconductor device 400. Furthermore, by incorporating two types of semiconductor elements, the functionality of the semiconductor device 400 can be enhanced.

[0027] Figure 5 is a plan view showing a comparative example with a semiconductor device according to Embodiment 4 of the present disclosure. In semiconductor device 400a, the IC die bond portion 1b has only the first projection 5a and the second projection 5b, and does not have a third projection 5c. Therefore, LVIC2a and HVIC3a cannot take an elongated shape in the first direction 50. In other words, even if the number of wirings for LVIC wiring 9a and HVIC wiring 10a increases, their arrangement cannot be optimized, and the wiring itself cannot be shortened.

[0028] Comparing semiconductor device 400 with semiconductor device 400a, it can be seen that the wiring itself can be shortened by optimizing the arrangement of the LVIC wiring 9 and HVIC wiring 10. In other words, it can be seen that the manufacturing quality of semiconductor device 400 can be improved by having three protrusions, including the third protrusion 5c, in the IC die bond portion 1a.

[0029] Embodiment 5 Figure 6 is a plan view showing a semiconductor device according to Embodiment 5 of the present disclosure. The semiconductor device 500 according to Embodiment 5 differs from Embodiment 1 in that it has wiring between LVIC2 and HVIC3.

[0030] The IC die bond section 1a has wiring 12. Wiring 12 connects LVIC2 and HVIC3. Although this example shows four wires 12, the number of wires is not limited to this; one or more wires are acceptable.

[0031] Wiring 12 allows the wiring from the control-side lead frame to be directly connected from LVIC2 to HVIC. This shortens the overall wiring. In other words, it suppresses the flow of wiring when injecting the encapsulating material during the manufacturing process, thereby improving the manufacturing quality of the semiconductor device 500.

[0032] Furthermore, the wiring 12 allows the functions of LVIC2 and HVIC3 to be combined. This improves the functionality of the semiconductor device 500.

[0033] Embodiment 6 The semiconductor device according to Embodiment 6 has the same configuration as semiconductor device 100. However, it differs from Embodiment 1 in that the semiconductor elements connected to LVIC2 and HVIC3 are wide-bandgap semiconductors.

[0034] The low-side frame 7 and high-side frame 8 have semiconductor elements 4c. Furthermore, the semiconductor elements 4c are wide-bandgap semiconductors such as silicon carbide, gallium nitride-based materials, or diamond. This allows for improved electrical characteristics, such as reduced power loss in the semiconductor device. Additionally, wide-bandgap semiconductors are easier to miniaturize compared to semiconductor elements such as Si. Therefore, it is possible to miniaturize the entire semiconductor device.

[0035] The aspects of this disclosure are summarized below as an appendix.

[0036] (Note 1) The IC comprises multiple integrated circuits, an IC frame on which the multiple integrated circuits are mounted, and a sealing material. The aforementioned IC frame, The IC frame has a first projection extending in the longitudinal direction, In the IC frame, a second projection is located on the opposite side of the first projection and extends in the opposite direction to the first projection, A third projection extends in the shorter direction of the IC frame and is embedded in the sealing material. Semiconductor device. (Note 2) The aforementioned plurality of integrated circuits are two integrated circuits, The third projection is located at a position that is the same distance from each of the two integrated circuits. The semiconductor device described in Appendix 1. (Note 3) The aforementioned plurality of integrated circuits are two integrated circuits, The IC frame has a plated region between the two integrated circuits. Semiconductor device as described in Appendix 1 or 2. (Note 4) The IC frame further comprises a group of semiconductor elements located on the opposite side of the third protrusion and arranged in parallel in the longitudinal direction of the IC frame, The group of semiconductor elements comprises multiple types of semiconductor elements. A semiconductor device as described in any one of the appendices 1 to 3. (Note 5) The plurality of integrated circuits are connected to each other by wiring. A semiconductor device as described in any one of the appendices 1 to 4. (Note 6) The semiconductors constituting the aforementioned group of semiconductor elements are formed from wide-bandgap semiconductors. Semiconductor device as described in Appendix 4 or 5. (Note 7) The wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond. Semiconductor device as described in Appendix 6. [Explanation of Symbols]

[0037] 4 Semiconductor elements 4a Semiconductor device 4b Semiconductor element 4c semiconductor device 5a First protrusion 5b Second protrusion 5c third protrusion 6. Sealing material 12 Wiring 100 Semiconductor Equipment 200 Semiconductor Equipment 300 semiconductor equipment 400 semiconductor devices 400a Semiconductor 500 Semiconductor Equipment

Claims

1. The IC comprises multiple integrated circuits, an IC frame on which the multiple integrated circuits are mounted, and a sealing material. The aforementioned IC frame, The IC frame has a first projection extending in the longitudinal direction, In the IC frame, a second projection is located on the opposite side of the first projection and extends in the opposite direction to the first projection, A third projection extends in the short direction of the IC frame and is embedded in the sealing material. It has, The aforementioned plurality of integrated circuits are two integrated circuits, The third projection is located at a position that is the same distance from each of the two integrated circuits. Semiconductor equipment.

2. The aforementioned plurality of integrated circuits are two integrated circuits, The IC frame has a plating region between the two integrated circuits. The semiconductor device according to claim 1.

3. The IC frame further comprises a group of semiconductor elements located on the opposite side of the third protrusion and arranged in parallel in the longitudinal direction of the IC frame, The group of semiconductor elements comprises multiple types of semiconductor elements. The semiconductor device according to claim 1.

4. The plurality of integrated circuits are connected to each other by wiring. The semiconductor device according to claim 1.

5. The semiconductors constituting the aforementioned group of semiconductor elements are formed from wide-bandgap semiconductors. The semiconductor device according to claim 3.

6. The wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond. The semiconductor device according to claim 5.

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