Integrated circuits, power supply circuits

Abstract

To provide an integrated circuit that can further reduce power consumption.SOLUTION: An integrated circuit includes a first terminal to which an external circuit that sets the operating mode is connected, and a mode selection circuit that selects whether the integrated circuit is to operate in a shutdown mode in which no switching operation is performed, a normal mode in which continuous switching operation is performed, or a low standby power mode in which switching operation periods and shutdown operation periods are alternately repeated on the basis of the voltage level of the first terminal, and the mode selection circuit operates the integrated circuit in the shutdown mode when the voltage level of the first terminal is in a first voltage range, operates the integrated circuit in the normal mode when the voltage level is in a second voltage range different from the first voltage range, and operates the integrated circuit in the low standby power mode when the voltage level is in a third voltage range different from the first and second voltage ranges.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to an integrated circuit and a power supply circuit.

Background Art

[0002] There are integrated circuits that control a power supply circuit (for example, Patent Documents 1 to 7).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, there is an integrated circuit that changes an operation mode according to the state of a load of a power supply circuit.

[0005] In such an integrated circuit, generally, a load detection circuit that detects the state of a load is always operating. Therefore, even if the load becomes a no-load state, it is difficult to reduce the power consumption of the integrated circuit because the integrated circuit continues to consume a certain amount of power.

[0006] This invention has been made in view of the above-mentioned conventional problems, and aims to provide an integrated circuit that can further reduce power consumption. [Means for solving the problem]

[0007] A first embodiment of the main integrated circuit of the present invention that solves the aforementioned problems is an integrated circuit that drives a transistor of a power supply circuit to generate an output voltage of a target level in the power supply circuit, comprising: a first terminal to which a first switch that is turned on or off based on an instruction signal indicating the operating mode of the integrated circuit is connected; a first determination circuit that determines whether to operate the integrated circuit in a first mode or in a second mode which consumes more power than the first mode, based on the voltage level of the first terminal; a first power supply voltage generation circuit that stops generating a first power supply voltage when the integrated circuit is operated in the first mode and generates the first power supply voltage when the integrated circuit is operated in the second mode; and a drive circuit to which the first power supply voltage is supplied and drives the transistor.

[0008] The main power supply circuit of the present invention that solves the aforementioned problems is a power supply circuit that generates an output voltage of a target level, comprising: a transistor; an integrated circuit that drives the transistor; and a first switch that turns on and off based on an instruction signal that indicates the operating mode of the integrated circuit, wherein the integrated circuit includes: a first terminal to which the first switch is connected; a first determination circuit that determines, based on the voltage level of the first terminal, whether to operate the integrated circuit in a first mode or in a second mode which consumes more power than the first mode; a first power supply voltage generation circuit that stops generating a first power supply voltage when the integrated circuit is operated in the first mode, and generates the first power supply voltage when the integrated circuit is operated in the second mode; and a drive circuit to which the first power supply voltage is supplied and drives the transistor.

[0009] A second aspect of the main integrated circuit of the present invention that solves the aforementioned problems is an integrated circuit that switches-drives a power transistor of a power supply circuit in order to generate an output voltage of a target level in the power supply circuit, comprising: a first terminal to which an external circuit for setting the operating mode of the integrated circuit is connected; and a mode selection circuit that selects whether to operate the integrated circuit in one of the following modes based on the voltage level of the first terminal: a cutoff mode in which no switching operation is performed, a normal mode in which switching operation is performed continuously, or a low standby power mode in which a switching operation period and a switching stop period are alternately repeated. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide an integrated circuit that can further reduce power consumption. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows an example of a power supply unit 10. [Figure 2] This diagram shows an overview of the AC-DC converter 12. [Figure 3] This figure shows an example of a DC-DC converter 13. [Figure 4] This figure shows an example of the control IC 50. [Figure 5] This figure shows an example of the setting circuit 76. [Figure 6] This diagram shows the relationship between the resistance value of resistor Rstb and the method used to switch the drive pattern of control IC 50. [Figure 7] This figure shows an example of the drive signals Vdr1 and Vdr2 in "normal mode". [Figure 8] This figure shows an example of drive signals Vdr1 and Vdr2 in "low standby power mode". [Figure 9] This figure shows an example of an interface (IF) circuit 18a. [Figure 10] This diagram shows the relationship between the logic levels of the Wakeup and ExtSTB signals and the voltage Vstb. [Figure 11] It is a diagram showing the relationship between the logic levels of signal Wakeup and signal ExtSTB and the operation mode of control IC50. [Figure 12] It is a diagram showing an example of the power factor improvement circuit 22. [Figure 13] It is a diagram showing an example of the power factor improvement IC175. [Figure 14] It is a diagram showing an example of the operation of control IC50. [Figure 15] It is a diagram showing an example of the interface (IF) circuit 18b. [Figure 16] It is a diagram showing the relationship between the logic level of signal Wakeup and the voltage Vstb. [Figure 17] It is a diagram showing the relationship between the logic level of signal Wakeup and the operation modes of control IC50 and power factor improvement IC155. [Figure 18] It is a diagram showing an example of the operation of control IC50 and power factor improvement IC175.

Embodiments of the Invention

[0012] From the descriptions in this specification and the accompanying drawings, at least the following matters become clear.

[0013] =====This Embodiment===== <<<Overview of the Power Supply Device 10>>> FIG. 1 is a diagram showing an example of the power supply device 10. The power supply device 10 is, for example, a device incorporated in a television, generates an output voltage Vout2 from a commercial AC voltage Vac, and supplies power to a predetermined load 14. The power supply device 10 is composed of a switch 11, an AC-DC converter 12, a DC-DC converter 13, a microcontroller (MCU) 15a, a capacitor 16, a photodiode 17, and an interface (IF) circuit 18a. The switch 11 is provided between node N2 and node N3 and is turned on and off by a signal SW_sig from the microcontroller 15a.

[0014] When switch 11 is turned on, the AC-DC converter 12 generates an output voltage Vout1 from the AC voltage Vac applied to nodes N1 and N2. On the other hand, when switch 11 is turned off, the AC-DC converter 12 does not generate an output voltage Vout1 because no AC voltage Vac is applied.

[0015] The DC-DC converter 13 generates output voltage Vout2 from output voltage Vout1 applied to nodes N4 and N5. Load 14 is connected to nodes N6 and N7 and operates when output voltage Vout2 is applied and load current Iout is supplied. Load 14 is, for example, an electronic device included in a television that operates on DC voltage. Here, "connected" means electrically connected unless otherwise specified, that is, connected via a resistor.

[0016] The microcontroller 15a controls the power supply unit 10 based on instructions from the user. The microcontroller 15a operates on a voltage Vdd from a power supply circuit (not shown) that operates on a commercial AC voltage Vac, and the capacitor 16 is placed between terminal VDD and ground to stabilize the voltage Vdd.

[0017] Furthermore, the photodiode 17 is provided between terminal RCV and ground, and receives signals using infrared light from, for example, a television remote control (not shown). The microcontroller 15a controls the operation of the power supply unit 10 and various television components (not shown) based on the signals received by the photodiode 17.

[0018] Furthermore, when the microcontroller 15a receives a signal from the remote control to turn on the load 14 via the photodiode 17, it sends a signal SW_sig to turn on the switch 11, which acts as a relay. As a result, the switch 11 turns on, and an AC voltage Vac is applied to the AC-DC converter 12. The AC-DC converter 12 then generates an output voltage Vout1.

[0019] Also, at this time, the microcontroller 15a outputs a signal Wakeup for starting the DC-DC converter 13 to the interface circuit 18a.

[0020] Then, the DC-DC converter 13 starts based on the voltage Vstb from the interface circuit 18a and supplies power to the load 14. Incidentally, the microcontroller 15a also outputs a signal ExtSTB for changing the operation mode of the DC-DC converter 13 in a predetermined case, but the details will be described later.

[0021] On the other hand, when the microcontroller 15a receives a signal transmitted from the remote control for the photodiode 17 to turn off the load 14, it sends a signal SW_sig for turning off the switch 11. As a result, since the switch 11 is turned off, the supply of the AC voltage Vac to the AC-DC converter 12 is stopped.

[0022] Also, at this time, the microcontroller 15a outputs a signal Wakeup for stopping the DC-DC converter 13 to the interface circuit 18a. Thereby, the interface circuit 18a generates a voltage Vstb at a level higher than a predetermined level, although the details will be described later. Also, the DC-DC converter 13 stops generating the output voltage Vout2 in response to the voltage Vstb, stops supplying power to the load 14, the load current Iout flowing through the load 14 becomes zero, and the load 14 is in a so-called no-load state.

[0023] Also, the interface circuit 18a realizes a change in the operation of the control IC50 and a cooperation function between the control IC50 and the power factor correction IC175 in accordance with the signal Wakeup and the signal ExtSTB from the microcontroller 15a. The details of the interface circuit 18a will be described later. Also, the interface circuit 18a corresponds to an "external circuit".

[0024] <<<Overview of the AC-DC Converter>>> FIG. 2 is a diagram showing the configuration of the AC-DC converter 12 included in the power supply device 10 of the present invention. The AC-DC converter 12 is a power supply circuit that generates an output voltage Vout1 at a target level from the AC voltage Vac of a commercial power supply.

[0025] The AC-DC converter 12 includes diodes 20, 21 and a power factor correction circuit 22. The diodes 20, 21 full-wave rectify the AC voltage Vac from the nodes N1, N3 and apply it as a rectified voltage Vrec1 to a control IC50 described later.

[0026] The power factor correction circuit 22 generates an output voltage Vout1 at a target level from the AC voltage Vac of the commercial power supply based on the voltage Sig from the interface circuit 18a and applies it to the nodes N4, N5. Details of the power factor correction circuit 22 will be described later.

[0027] <<<Overview of the DC-DC converter 13>>> FIG. 3 is a diagram showing the configuration of the DC-DC converter 13 included in the power supply device 10 of the present invention. The DC-DC converter 13 is an LLC current resonance type power supply circuit that generates an output voltage Vout2 at a target level (for example, 15V) for the load 14 from a predetermined input voltage Vout1 (for example, 400V).

[0028] The DC-DC converter 13 includes capacitors 30, 31, 42, NMOS transistors 32, 33, a transformer 34, a control block 35, diodes 40, 41, a constant voltage circuit 43, and a light emitting diode 44.

[0029] The capacitor 30 stabilizes the voltage between the power supply line to which the input voltage Vout1 is applied and the ground line on the ground side and removes noise and the like. The input voltage Vout1 is a DC voltage at a predetermined level.

[0030] NMOS transistor 32 is the high-side power transistor, and NMOS transistor 33 is the low-side power transistor. In this embodiment, NMOS transistors 32 and 33 are used as switching elements, but PMOS transistors or bipolar transistors may also be used, for example.

[0031] The transformer 34 is equipped with a primary coil L1, secondary coils L2 and L3, and an auxiliary coil L4, and the primary coil L1, secondary coils L2 and L3, and auxiliary coil L3 are insulated from each other. In the transformer 34, a voltage is generated in the secondary coils L2 and L3 on the secondary side in response to a change in the voltage across the primary coil L1 on the primary side, and a voltage is generated in the auxiliary coil L4 on the primary side in response to a change in the voltage of the secondary coils L2 and L3.

[0032] Furthermore, the primary coil L1 has the source of NMOS transistor 32 and the drain of NMOS transistor 33 connected to one end, and the source of NMOS transistor 33 connected to the other end via capacitor 31.

[0033] Therefore, when the switching of NMOS transistors 32 and 33 begins, the voltages across the secondary coils L2 and L3 and the auxiliary coil L4 will change. Note that the primary coil L1 and the secondary coils L2 and L3 are electromagnetically coupled with the same polarity, and the secondary coils L2 and L3 and the auxiliary coil L4 are also electromagnetically coupled with the same polarity.

[0034] Control block 35 is a circuit block for controlling the switching of NMOS transistors 32 and 33, and its details will be described later.

[0035] Diodes 40 and 41 rectify the voltages across the secondary coils L2 and L3, and capacitor 42 smooths the rectified voltage. As a result, capacitor 42 generates a smoothed output voltage Vout2. The output voltage Vout2 is a DC voltage of the desired level.

[0036] The constant voltage circuit 43 is a circuit that generates a constant DC voltage, and is constructed, for example, using a shunt regulator.

[0037] The light-emitting diode 44 is an element that emits light of an intensity corresponding to the difference between the output voltage Vout2 and the output of the constant voltage circuit 43, and together with the phototransistor 62, which will be described later, it constitutes a photocoupler. In this embodiment, as the level of the output voltage Vout2 increases, the intensity of the light from the light-emitting diode 44 increases.

[0038] ===Control Block 35=== The control block 35 includes a control IC 50, a diode 60, capacitors 61, 63, 64, 67, 68, 154, a phototransistor 62, and resistors 65, 66.

[0039] The control IC 50 is an integrated circuit that controls the switching of NMOS transistors 32 and 33 according to the state of terminal STB, as described later, and has terminals VCC, GND, STB, REG, FB, IS, CA, HO, LO, and VH.

[0040] Terminal VCC is the terminal to which the voltage Vcc required to operate the control IC 50 is applied. The cathode of diode 60 and capacitor 61, with one end grounded, are connected to terminal VCC. Therefore, capacitor 61 is charged by the current from the control IC 50's startup circuit 70 (described later) or the current from diode 60, and the charging voltage of capacitor 61 becomes the voltage Vcc required to operate the control IC 50.

[0041] Terminal GND is a terminal to which the ground voltage is applied, and is connected, for example, to the casing of a device in which the power supply unit 10 is installed.

[0042] Terminal STB is a terminal that receives the voltage generated by interface circuit 18a or the terminal that control IC 50 uses to output a signal to power factor correction IC 175, which will be described later. Further details will be provided later.

[0043] Terminal REG is the terminal that outputs the output voltage of the internal power supply (REG1) 92 (described later) built into the control IC 50. As will be explained in more detail later, a capacitor 154 is provided between terminal REG and ground, as shown in Figure 7 below, in order to stabilize the output voltage of the internal power supply 92.

[0044] Terminal FB is the terminal to which a feedback voltage Vfb_a corresponding to the output voltage Vout2 is generated, and a phototransistor 62 and a capacitor 63 are connected. The phototransistor 62 flows a bias current I1, whose magnitude corresponds to the light intensity from the light-emitting diode 44, from terminal FB to ground, and the capacitor 63 is provided to remove noise between terminal FB and ground. Therefore, the phototransistor 62 operates as a transistor that generates sink current.

[0045] Terminal IS is a terminal to which a voltage corresponding to the resonant current of the DC-DC converter 13 is applied. Here, a voltage corresponding to the resonant current of the primary coil L1 is generated at the node to which capacitor 64 and resistor 65 are connected. The resistor 66 and capacitor 67 constitute a low-pass filter. Therefore, a voltage from which noise components have been removed is applied to terminal IS, corresponding to the resonant current of the primary coil L1.

[0046] Furthermore, the resonant current value increases in accordance with the input power of the DC-DC converter 13, and the input power of the DC-DC converter 13 increases in accordance with the power consumed by the load 14. Therefore, the voltage applied to terminal IS will be a voltage corresponding to the power consumed by the load 14.

[0047] Terminal CA applies a voltage to capacitor 68 that changes according to the voltage applied to terminal IS. Specifically, when the power consumption of load 14 increases, that is, when load 14 is in a heavy load state, the voltage applied to capacitor 68 increases. On the other hand, when the power consumption of load 14 decreases, that is, when load 14 is in a light load state, the voltage applied to capacitor 68 decreases.

[0048] Note that "the state of load 14 is heavy load" refers to a case where, for example, the load current Iout flowing through load 14 is greater than a predetermined value (for example, 1A). Conversely, "the state of load 14 is light load" refers to a case where, for example, the load current Iout flowing through load 14 is less than a predetermined value (for example, 1A).

[0049] Terminal VH is the terminal to which the rectified voltage Vrec1 is applied. The control IC 50 includes a startup circuit 70 (described later) that charges the voltage Vcc to start up the control IC 50 when the rectified voltage Vrec1 is applied via terminal VH, and after startup, it operates based on the voltage Vcc.

[0050] Terminal HO is the terminal to which the drive signal Vdr1, which drives the NMOS transistor 32, is output, and the gate of the NMOS transistor 32 is connected to it.

[0051] Terminal LO is the terminal to which the drive signal Vdr2, which drives the NMOS transistor 33, is output, and the gate of the NMOS transistor 33 is connected to it.

[0052] Note that terminal STB corresponds to the "first terminal," terminal VH corresponds to the "second terminal," terminal VCC corresponds to the "third terminal," and terminal REG corresponds to the "fourth terminal."

[0053] <<<Details of Control IC 50>>> Figure 4 shows the configuration of the control IC 50. The control IC 50 is an integrated circuit that controls an LLC current resonant type power supply circuit. The control IC 50 consists of a startup circuit 70, a current source 71, a Zener diode 72, a determination circuit 73, resistors 74, 75, a setting circuit 76, a reset circuit (RESET) 90, an undervoltage protection circuit (UVLO) 91, an internal power supply (REG1) 92, an internal power supply (REG2) 93, a load detection circuit 100, an oscillation circuit 101, and a drive circuit 102. The determination circuit 73 corresponds to the "first determination circuit" or the "first mode determination circuit".

[0054] ===Startup Circuit 70=== The startup circuit 70 generates the power supply voltage Vcc for the operation of the control IC 50 based on the rectified voltage Vrec1 when the control IC 50 is started up. Specifically, when the control IC 50 is started up, the startup circuit 70 charges the capacitor 61 in Figure 3 with the voltage generated from the rectified voltage Vrec1 applied via terminal VH, based on the voltage Vcc at terminal VCC, thereby generating the voltage Vcc.

[0055] Furthermore, once the control IC 50 has finished starting up, the voltage Vcc becomes sufficiently high and the capacitor 61 is charged by the current from the auxiliary coil L4, the starting circuit 70 stops charging the capacitor 61.

[0056] Here, "startup" refers to the operation from the time the AC voltage Vac is applied to the power supply 10, through the output of the signal rst1 (described later) that activates the digital circuit of the control IC 50, until the output of the signal rst2 (described later) that starts switching.

[0057] The "startup" of the control IC 50 includes the operations shown in the following steps (1) and (2). Step (1) is when the AC voltage Vac is applied to the power supply 10, and then a "state setting period" elapses during which the various circuits of the control IC 50 are initialized. Step (2) is when, after step (1) has elapsed, the startup circuit 70 charges the capacitor 61 and sets the voltage Vcc level to a level at which the control IC 50 starts switching the NMOS transistors 32 and 33 (for example, a predetermined level Vccon, which will be described later). Details of steps (1) and (2) will be described later. The startup circuit 70 in this embodiment is composed of a constant voltage source 80, a control circuit 81, and a charging circuit 82.

[0058] <<Constant voltage source 80>> The constant voltage source 80 generates a constant voltage Vstartup (e.g., 30V) based on the rectified voltage Vrec1. Specifically, the constant voltage source 80 generates a constant voltage Vstartup based on the rectified voltage Vrec1 applied via terminal VH, regardless of the operating mode of the control IC 50.

[0059] Furthermore, the constant voltage source 80 applies the constant voltage Vstartup to the control circuit 81, the charging circuit 82, the current source 71, and the determination circuit 73 while the rectified voltage Vrec1 is applied to terminal VH. Note that the constant voltage Vstartup corresponds to a "predetermined voltage".

[0060] <<Control circuit 81>> The control circuit 81 controls the charging circuit 82 and causes the charging circuit 82 to generate a voltage Vcc. In addition, the control circuit 81 controls the charging circuit 82 during steps (1) to (2) when the control IC 50 described above is activated.

[0061] Specifically, when the determination circuit 73 outputs a signal Sb indicating that the switching of NMOS transistors 32 and 33 in Figure 3 should be started, the control circuit 81 outputs a signal Pon that controls the charging circuit 82 according to the voltage value of voltage Vcc. Furthermore, the signal Sb indicating that the switching of NMOS transistors 32 and 33 should be started will be referred to as the "switching signal Sb" below.

[0062] On the other hand, when the determination circuit 73 outputs a signal Sb indicating that the switching of NMOS transistors 32 and 33 should be stopped, the control circuit 81 outputs a signal Pon to the charging circuit 82 to stop generating voltage Vcc. The signal Sb used when the switching of NMOS transistors 32 and 33 should be stopped is referred to as the "signal Sb indicating that switching should be stopped." Details of the signal Pon will be described later.

[0063] During the state setting period, if the voltage Vcc level is lower than a predetermined level Vston (for example, 9V), the control circuit 81 outputs a signal Pon to the charging circuit 82 to charge the capacitor 61. On the other hand, when the voltage Vcc level reaches a predetermined level Vstoff (for example, 10V), the control circuit 81 outputs a signal Pon to the charging circuit 82 to stop charging the capacitor 61.

[0064] Furthermore, when the voltage Vcc level drops from a predetermined level Vstoff to a predetermined level Vston, the control circuit 81 outputs a signal Pon to the charging circuit 82 to charge the capacitor 61 again. After the state setting period is complete, the control circuit 81 outputs a signal Pon to the charging circuit 82 to charge the capacitor 61 until the voltage Vcc level reaches a predetermined level Vccon.

[0065] Then, once the control IC 50 has finished starting up, the voltage Vcc level becomes sufficiently high and the capacitor 61 is charged by the current from the auxiliary coil L4, the control circuit 81 outputs a signal Pon to the charging circuit 82 to stop charging the capacitor 61. After the signal Pon to stop charging the capacitor 61 is output to the charging circuit 82, the constant voltage source 80 no longer needs to supply the constant voltage Vstartup, and the current generated by the generation of this constant voltage Vstartup becomes almost zero. Therefore, the power consumption of the constant voltage source 80 is almost eliminated. Note that capacitor 61 corresponds to the "first capacitor".

[0066] <<Charging circuit 82>> The charging circuit 82 operates based on the voltage Vstartup, charging the capacitor 61 via terminal VCC and generating the voltage Vcc. Specifically, when the control circuit 81 outputs a signal Pon indicating that the capacitor 61 should be charged, the charging circuit 82 charges the capacitor 61 via terminal VCC based on the voltage Vstartup. On the other hand, when the control circuit 81 outputs a signal Pon indicating that the charging of the capacitor 61 should be stopped, the charging circuit 82 stops charging the capacitor 61.

[0067] ===Current source 71=== The current source 71 is a circuit that causes terminal STB to generate a voltage corresponding to the state of the interface circuit 18a connected to terminal STB. As will be described in detail later, the control IC 50 can operate in an operating mode corresponding to the signal from the microcontroller 15a depending on the level of the voltage Vstb at terminal STB. In this embodiment, the current source 71 supplies current Ia to terminal STB when the control IC 50 is in a predetermined state, based on the signal Sa (described later) from the setting circuit 76. Specifically, when a signal Sa instructing the current source 71 to supply current Ia is input during a period other than the state setting period, the current source 71 supplies current Ia to terminal STB.

[0068] The current Ia is the current used to charge the capacitor 150 in the interface circuit 18a shown in Figure 9, which will be described later. When the microcontroller 15a outputs the Wakeup signal to stop the DC-DC converter 13, the level of the voltage Vstb generated across the capacitor 150 rises and becomes higher than the predetermined level Vstop (for example, 5.0V).

[0069] On the other hand, when the microcontroller 15a outputs the Wakeup signal to operate the DC-DC converter 13, the capacitor 150 discharges through the resistor 151 (described later) in Figure 9, causing the voltage Vstb level to decrease and fall below the predetermined level Vstop. In this way, the control IC 50 can operate in response to instructions from the microcontroller 15a by changing the voltage Vstb level at terminal STB according to the current Ia. Details of the interface circuit 18a will be described later.

[0070] ===Zener Diode 72=== The Zener diode 72 is placed between terminal STB and ground and functions to prevent the voltage Vstb at terminal STB from exceeding a predetermined level (e.g., 5.9V) (i.e., to clamp it). The Zener diode 72 corresponds to a "clamping element".

[0071] ===Judgment circuit 73=== The determination circuit 73 determines whether the voltage Vstb level at terminal STB exceeds a predetermined level Vstop for determining the operating mode of the control IC 50. Specifically, if the voltage Vstb level is lower than the predetermined level Vstop, the determination circuit 73 outputs a signal Sb to be switched. The operating mode of the control IC 50 in this case is referred to as the "powered-on mode". When the control IC 50 is operating in the "powered-on mode", the control IC 50 switches the NMOS transistors 32 and 33 after step (2) described above.

[0072] On the other hand, if the voltage Vstb level becomes higher than the predetermined level Vstop, the determination circuit 73 outputs a signal Sb indicating that switching should be stopped. The operating mode of the control IC 50 in this case is referred to as the "cutoff mode". When the control IC 50 is in "cutoff mode", the control IC 50 does not switch the NMOS transistors 32 and 33. The "energized mode" corresponds to the "first mode", and the "cutoff mode" corresponds to the "second mode". The predetermined level Vstop corresponds to the "first voltage level".

[0073] ===Resistance 74, 75=== Resistors 74 and 75 generate a voltage Vh from the rectified voltage Vrec1 to detect the RMS value of the AC voltage Vac. Specifically, resistors 74 and 75 are connected in series between the node to which the rectified voltage Vrec1 is applied and ground, generating a voltage Vh at the connection point of resistors 74 and 75.

[0074] ===Setting Circuit 76=== Figure 5 shows an example of the setting circuit 76. The setting circuit 76 outputs various signals for setting the operation of the control IC 50. Specifically, the setting circuit 76 outputs a signal Sa to supply or stop current Ia to the current source 71.

[0075] Furthermore, when the drive pattern is changed in “external mode” (described later), the setting circuit 76 detects the change in the level of the voltage Vstb and outputs a signal Sc to the oscillation circuit 101 (described later) to instruct the drive pattern of the NMOS transistors 32 and 33. The setting circuit 76 also outputs a signal Sd indicating the completion of the state setting period and a signal Se indicating the method of changing the drive pattern of the NMOS transistors 32 and 33. The setting circuit 76 is composed of a digital section 110 consisting of digital circuits (logic circuits) and an analog section 111 consisting of analog circuits.

[0076] ====Digital Section 110==== The digital unit 110 is comprised of a control circuit 120 and a determination circuit 121.

[0077] =====Control circuit 120===== The control circuit 120 controls the current source 71, control circuit 81, internal power supply 92 in Figure 4, and various circuits within the analog section 111 in Figure 5. Note that the control circuit 120 corresponds to the "control circuit".

[0078] =====Judgment circuit 121===== The determination circuit 121 determines the method for changing the driving pattern of the NMOS transistors 32 and 33 based on the signal from the control circuit 120 and the conversion result (digital value Dvstb) of the analog-to-digital converter (ADC) 132 (described later).

[0079] Furthermore, when the control circuit 120 outputs a signal S3 indicating the timing for acquiring the conversion result, the determination circuit 121 acquires a digital value Dvstb, which is obtained by converting the voltage Vstb corresponding to the resistance value Rstb of the resistor 151 (described later) into a digital value. Then, the determination circuit 121 outputs a signal Se indicating whether to change the drive pattern in "external mode" or "internal mode" according to the digital value Dvstb.

[0080] Here, "external mode" refers to a mode in which the comparator 134, described later, determines the level of the voltage Vstb output by the interface circuit 18a according to the logic level of the signal ExtSTB, and changes the drive pattern depending on whether it is higher than a predetermined level Vthstb, described later.

[0081] On the other hand, the “internal mode” is a mode in which the drive pattern is changed based on the voltage Vca output by the load detection circuit 100, which will be described later, i.e., the state of the load 14. The determination circuit 121 corresponds to the “second determination circuit”.

[0082] ====Analog Section 111==== The analog section 111 consists of analog circuits and includes a discharge circuit 130, a current source 131, an analog-to-digital converter (ADC) 132, a clamp circuit 133, a comparator 134, and a communication circuit 135. The discharge circuit 130, current source 131, and analog-to-digital converter 132 of the analog section 111 operate during the state setting period to determine how to change the driving pattern of the NMOS transistors 32 and 33 shown in Figure 3 based on the resistance value Rstb of the resistor 151 shown in Figure 9, which will be described later.

[0083] =====Discharge circuit 130===== During the state setting period, the discharge circuit 130 discharges the capacitor 150 (described later) shown in Figure 9 in order to accurately determine the voltage corresponding to the resistance value Rstb of the resistor 151. Specifically, when the control circuit 120 outputs a signal S1 to discharge the capacitor 150, the discharge circuit 130 discharges the terminal STB to which the capacitor 150 is connected. On the other hand, when the control circuit 120 outputs a signal S1 to stop the discharge of the capacitor 150, the discharge circuit 130 stops discharging the terminal STB to which the capacitor 150 is connected.

[0084] =====Current source 131===== The current source 131 supplies current Ib to terminal STB in order to measure the resistance value Rstb of resistor 151 shown in Figure 9, which will be described later, in order to set the method for changing the drive pattern. Specifically, when the control circuit 120 outputs a signal S2 instructing the supply of current Ib, the current source 131 supplies current Ib to resistor 151 via terminal STB. This allows the control IC 50 to determine the resistance value Rstb of resistor 151.

[0085] As will be explained in more detail later, when the user sets the method for changing the drive pattern to "external mode," the resistance value Rstb becomes the resistance value Ra, and when it sets it to "internal mode," the resistance value Rstb becomes the resistance value Rb.

[0086] Furthermore, the determination circuit 121 outputs a signal Se indicating that the drive pattern will be changed in "external mode" if the resistance value Rstb is equal to the resistance value Ra. The signal Se that indicates the drive pattern will be changed in "external mode" is referred to as the "signal Se indicating 'external mode'".

[0087] On the other hand, the determination circuit 121 outputs a signal Se indicating that the drive pattern will be changed in "internal mode" if the resistance value Rstb is Rb. The signal Se that indicates the drive pattern will be changed in "internal mode" is referred to as the "signal Se indicating "internal mode".

[0088] =====Analog-to-Digital Converter (ADC) 132===== The analog-to-digital converter (ADC) 132 converts the voltage value of voltage Vstb into a digital value Dvstb. In this embodiment, the control circuit 120 outputs a signal S2 instructing the supply of current Ib and a signal S3 indicating the timing for acquiring the digital value Dvstb. Subsequently, the determination circuit 121 outputs a signal Se based on the digital value Dvstb. At this time, the analog-to-digital converter 132 converts the voltage value of the voltage generated across resistor 151 into a digital value Dvstb and outputs it to the determination circuit 121.

[0089] =====Clamping Circuit 133===== The clamp circuit 133 generates a voltage to maintain the level of the voltage Vstb at terminal STB at a predetermined level Vnorm.

[0090] The clamp circuit 133 comprises an operational amplifier 140, a PMOS transistor 141, and a resistor 142. The operational amplifier 140 drives the PMOS transistor 141 to reduce its on-resistance when the level of the voltage Vstb input to the non-inverting input terminal is lower than a predetermined level Vnorm input to the inverting input terminal.

[0091] Meanwhile, the operational amplifier 140 drives the PMOS transistor 141 to increase its on-resistance when the voltage Vstb level is higher than a predetermined level Vnorm. The resistor 142 then generates a voltage that sets the voltage Vstb level to the predetermined level Vnorm, while limiting the current according to the voltage Vreg2 and the on-resistance of the PMOS transistor 141.

[0092] Furthermore, the driving capability of the clamp circuit 133 that drives terminal STB is smaller than that of the discharge circuit 130 and the communication circuit 135 (described later). When these circuits are not operating and no external ground voltage is applied to terminal STB, the clamp circuit 133 generates a voltage such that the level of voltage Vstb is set to a predetermined level Vnorm.

[0093] =====Comparator 134===== The comparator 134 determines whether to operate the control IC 50 in "normal mode" or "low standby power mode" based on the ExtSTB signal from the microcontroller 15a.

[0094] Here, "normal mode" refers to the operating mode in which the control IC 50 continuously switches the NMOS transistors 32 and 33, as shown in Figure 7, when the load condition is not light load.

[0095] On the other hand, the "low standby power mode" is an operating mode in which, when the load is light, the control IC 50 switches in a so-called burst mode, alternating between a switching operation period in which it continuously switches the NMOS transistors 32 and 33, as shown in Figure 8, and a stop operation period in which it intermittently stops switching.

[0096] Note that "Normal Mode" and "Low Standby Power Mode" are modes that indicate the drive patterns of NMOS transistors 32 and 33 when the control IC 50 is operating in "Powered-On Mode".

[0097] Specifically, when the signal Se indicating "external mode" is output, the comparator 134, upon detecting a voltage Vstb at a level higher than a predetermined level Vthstb, outputs a signal Sc indicating "normal mode," causing the oscillator circuit 101 (described later) to output an oscillation signal Vosc that switches the NMOS transistors 32 and 33 in "normal mode."

[0098] On the other hand, when comparator 134 detects a voltage Vstb lower than a predetermined level Vthstb, it outputs a signal Sc indicating "low standby power mode," causing the oscillation circuit 101 to output an oscillation signal Vosc that switches the NMOS transistors 32 and 33 in "low standby power mode." Comparator 134 corresponds to either the "first signal output circuit" or the "second mode determination circuit," and signal Sc corresponds to the "second signal." Furthermore, the predetermined level Vthstb corresponds to the "second voltage level," and the determination circuit 73 and comparator 134 correspond to the "mode selection circuit."

[0099] =====Communication Circuit 135===== The communication circuit 135 outputs a pulse signal to terminal STB in order to enable cooperation with the power factor correction IC 175. Specifically, in order to transmit the effective value of the AC voltage Vac to the power factor correction IC 175, the communication circuit 135 receives a voltage Vh for determining the effective value of the AC voltage Vac based on the rectified voltage Vrec1 applied to terminal VH, and generates and outputs a pulse signal to terminal STB based on this voltage Vh. The pulse signal has an amplitude level lower than a predetermined level Vstop and higher than a predetermined level Vthstb.

[0100] This operation is performed when the communication circuit 135 receives a voltage Vh, generates a pulse signal indicating whether the effective value of the AC voltage Vac is high (e.g., 200V) or low (e.g., 100V), and outputs it to the power factor correction IC 175 via the interface circuit 18a (18b).

[0101] Furthermore, when the signal Se indicating "internal mode" is output, the communication circuit 135 outputs a pulse signal having a pulse width corresponding to the state of the load 14. Note that the communication circuit 135 corresponds to the "second signal output circuit" or "signal output circuit," and the pulse signal corresponds to the "third signal."

[0102] ===Reset Circuit (RESET) 90=== Returning to Figure 4, the reset circuit (RESET) 90 resets the digital circuit of the control IC 50 when the voltage Vcc is low, stopping the operation of the digital circuit of the control IC 50. Specifically, the reset circuit 90 outputs a signal rst1 to reset the digital circuit of the control IC 50 when the voltage Vcc level falls below a predetermined level Vccrst.

[0103] On the other hand, when the voltage Vcc level exceeds a predetermined level Vccrst, the reset circuit 90 outputs a signal rst1 that starts the operation of the digital circuit of the control IC 50. In this embodiment, when the voltage Vcc rises and the reset circuit 90 releases the reset of the digital circuit, the state setting described above is performed.

[0104] ===Low Voltage Protection Circuit (UVLO) 91=== The undervoltage protection circuit (UVLO) 91 resets the load detection circuit 100, the oscillator circuit 101, and the drive circuit 102 (described later) when the voltage Vcc is low, and stops the operation of the load detection circuit 100, the oscillator circuit 101, and the drive circuit 102. Specifically, the undervoltage protection circuit 91 outputs a signal rst2 to reset the load detection circuit 100, the oscillator circuit 101, and the drive circuit 102 when the power supply voltage Vcc level falls below a predetermined level Vccon.

[0105] On the other hand, when the voltage Vcc level exceeds a predetermined level Vccon, the low-voltage protection circuit 91 outputs a signal rst2 that starts the operation of the load detection circuit 100, the oscillation circuit 101, and the drive circuit 102. In this embodiment, when the voltage Vcc rises and the low-voltage protection circuit 91 releases the reset of the various circuits, the control IC 50 starts switching operation.

[0106] ===Internal power supply (REG1)92=== When the control IC 50 is started, the internal power supply (REG1) 92 generates voltage Vreg1 for the drive signals Vdr1 and Vdr2 output by the drive circuit 102 (described later) when the voltage Vcc level rises. Specifically, when the signal Sb to be switched is output by the determination circuit 73 and the voltage Vcc level rises from the ground level, the internal power supply 92 gradually generates voltage Vreg1 internally.

[0107] Subsequently, when the setting circuit 76 outputs a signal Sd indicating the completion of the state setting period, the internal power supply 92 outputs a voltage Vreg1 to terminal REG. Also, when the control IC 50 is operating in "powered-on mode", when the low-voltage protection circuit 91 outputs the above-mentioned signal rst2, the drive circuit 102 starts switching the NMOS transistors 32 and 33.

[0108] Furthermore, when the determination circuit 73 outputs a signal Sb indicating that switching should be stopped, the internal power supply 92 stops generating the voltage Vreg1. As a result, when the control IC 50 is in "cutoff mode", the drive circuit 102 stops switching the NMOS transistors 32 and 33. The internal power supply 92 corresponds to the "first power supply voltage generation circuit", and the voltage Vreg1 corresponds to the "first power supply voltage".

[0109] ===Internal power supply (REG2)93=== The internal power supply (REG2) 93 generates a voltage Vreg2, which is used as the power supply for various circuits that perform state setting, when the voltage Vcc rises during the startup of the control IC 50. Specifically, when the signal Sb to be switched is output by the determination circuit 73 and the level of voltage Vcc rises above ground level, the internal power supply 93 generates a voltage Vreg2. As a result, the various circuits of the control IC 50 (for example, the control circuit 120, the discharge circuit 130, and the current source 131) operate by receiving a supply of voltage Vreg2 when the control IC 50 is operating in "energized mode".

[0110] Furthermore, when the determination circuit 73 outputs a signal Sb indicating that switching should be stopped, the internal power supply 93 stops generating the voltage Vreg2. As a result, the various circuits of the control IC 50 do not operate when the control IC 50 is in "shut-off mode". The internal power supply 93 corresponds to the "second power supply voltage generation circuit," and the voltage Vreg2 corresponds to the "second power supply voltage."

[0111] ===Load detection circuit 100=== The load detection circuit 100 detects whether the load 14 is a light load or a heavy load based on a voltage applied to terminal IS and corresponding to the power consumption of the load 14. The load detection circuit 100 outputs a voltage Vca indicating the state of the load 14 to the oscillator circuit 101 and the communication circuit 135.

[0112] Here, the power consumption of load 14 is greater when load 14 is under heavy load conditions than when it is under light load conditions. Therefore, the voltage Vis applied to terminal IS indicates a voltage corresponding to the power consumption of load 14. Consequently, when the voltage Vis is lower than a predetermined value, the load detection circuit 100 outputs a voltage Vca indicating that load 14 is under light load conditions.

[0113] On the other hand, the load detection circuit 100 outputs a voltage Vca indicating that the load 14 is under heavy load conditions when the voltage Vis is higher than a predetermined value. The voltage Vca increases as the load 14 becomes under heavier load conditions. The voltage Vca corresponds to the "first signal".

[0114] ===Oscillator Circuit 101=== The oscillator circuit 101 is a voltage-controlled oscillator circuit that outputs an oscillation signal Vosc for switching the NMOS transistors 32 and 33 in Figure 3 based on the input feedback voltage Vfb_a.

[0115] Furthermore, when the voltage Vfb_a level of the oscillator circuit 101 decreases, it outputs a high-frequency oscillation signal Vosc. When the load 14 becomes a light load, the output voltage Vout2 rises above the target level. As a result, the internal input to the constant voltage circuit 43, which is composed of a shunt regulator as shown in Figure 3, increases, and in order to keep the output constant, more current flows to the transistor inside the shunt regulator (not shown).

[0116] As a result, a large current flows through the light-emitting diode 44. Then, the phototransistor 62 flows a bias current I1, whose magnitude corresponds to the amplification of the light from the light-emitting diode 44, from terminal FB to ground, thereby lowering the feedback voltage Vfb_a.

[0117] Furthermore, when the low-voltage protection circuit 91 outputs the signal rst2 that starts the operation of the oscillator circuit 101, the oscillator circuit 101 outputs an oscillation signal Vosc to the control IC 50 that switches the NMOS transistors 32 and 33 in "normal mode" or "low standby power mode" based on the signal Sc or voltage Vca.

[0118] Furthermore, when the oscillator circuit 101 outputs a signal Se indicating "external mode," it operates based on the logic level of the signal Sc from the setting circuit 76.

[0119] On the other hand, when the oscillator circuit 101 outputs a signal Se indicating the “internal mode”, it operates based on the voltage level of the voltage Vca from the load detection circuit 100.

[0120] <<Changes to the drive pattern in "internal mode">> Then, when the signal Se indicating "internal mode" is output, and a voltage Vca higher than a predetermined level Vcastb is output by the load detection circuit 100, the oscillation circuit 101 switches the NMOS transistors 32 and 33 in "normal mode".

[0121] On the other hand, when the load detection circuit 100 outputs a voltage Vca lower than a predetermined level Vcastb, the oscillation circuit 101 switches the NMOS transistors 32 and 33 in "low standby power mode".

[0122] Note that the oscillator circuit 101 corresponds to the "oscillating circuit," the "normal mode" corresponds to the "third mode," the "low standby power mode" corresponds to the "fourth mode," and the oscillation signal Vosc corresponds to the "drive signal."

[0123] ===Drive Circuit 102=== The drive circuit 102 is supplied with voltage Vreg1 and switches-drives the NMOS transistors 32 and 33 at the frequency of the oscillation signal Vosc. Specifically, the drive circuit 102 outputs pulsed drive signals Vdr1 and Vdr2, which have the frequency of the oscillation signal Vosc and a duty cycle that is generally constant (for example, 50%), to the NMOS transistors 32 and 33, respectively, as shown in Figures 7 and 8. The drive circuit 102 also varies the drive signals Vdr1 and Vdr2 complementaryly, while providing a dead time to prevent the NMOS transistors 32 and 33 from turning on simultaneously.

[0124] In this case, during "normal mode" operation, if the level of the output voltage Vout2 rises above the target level, the feedback voltage Vfb_a decreases, and the frequency of the oscillation signal Vosc increases. As a result, the output voltage Vout2 of the DC-DC converter 13, which is an LLC current resonant power supply circuit, decreases.

[0125] On the other hand, when the output voltage Vout2 level falls below the target level, the feedback voltage Vfb_a increases, and the frequency of the oscillation signal Vosc decreases. As a result, the output voltage Vout2 of the DC-DC converter 13 increases. Therefore, in "normal mode" operation, the DC-DC converter 13 can generate an output voltage Vout2 at the target level.

[0126] <<<Configuration and Operation of Interface Circuit 18a>>> Figure 9 shows an example of the interface circuit 18a. As described above, the interface circuit 18a enables changes in the operation of the control IC 50 and coordination between the control IC 50 and the power factor correction IC 175 in response to the Wakeup and ExtSTB signals from the microcontroller 15a in Figure 1.

[0127] Furthermore, the interface circuit 18a is composed of capacitors 150, 154, 159, 162, resistors 151, 155, 156, 158, 161, and NMOS transistors 152, 153, 157, 160.

[0128] As will be explained in more detail below, capacitors 150 and 154, resistors 151, 155 and 156, and NMOS transistors 152, 153 and 157 set the level of the voltage Vstb at terminal STB of control IC 50. On the other hand, resistors 158 and 161, capacitors 159 and 162, and NMOS transistor 160 realize the coordination function between control IC 50 and power factor correction IC 175.

[0129] ===Circuit for setting the level of the voltage Vstb at terminal STB=== <Configuration of circuits related to the Wakeup signal> Capacitor 150 is located between the signal line L1, which is connected to terminal STB of the control IC 50, and ground, and is charged by the current Ia from the current source 71 of the control IC 50. Capacitor 150 corresponds to the "second capacitor," and signal line L1 corresponds to the "first signal line."

[0130] Resistor 151 has a resistance value Rstb, with one end connected to signal line L1 and the other end connected to ground via NMOS transistor 152. As mentioned above, the resistance value RStb is set to cause the control IC 50 to determine whether it is in "external mode" or "internal mode".

[0131] The NMOS transistor 152 is a switch whose gate electrode is turned on and off based on the Wakeup signal from the microcontroller 15a in Figure 1. The NMOS transistor 152 is connected in series with the resistor 151.

[0132] ==Operation when the Wakeup signal is at a low level (hereinafter referred to as "L" level)== When the NMOS transistor 152 receives a "L" level signal Wakeup that stops the DC-DC converter 13, it turns off and disconnects the resistor 151 from ground. In this case, the capacitor 150 is not discharged through the resistor 151 and is charged by the current Ia from the current source 71, and the voltage Vstb level becomes higher than the predetermined level Vstop, as shown in Figure 10. As a result, the determination circuit 73 determines that the control IC 50 should be put into "cutoff mode".

[0133] In other words, the interface circuit 18a puts the control IC 50 into "cutoff mode" as shown in the stage where the Wakeup signal in Figure 11 is "L". Note that when the Wakeup signal is at the "L" level, the NMOS transistor 153, described later, is disconnected from ground, so the level of voltage Vstb is not affected by the ExtSTB signal.

[0134] ==Operation when the Wakeup signal is at a high level (hereinafter referred to as "H" level)== On the other hand, when the NMOS transistor 152 receives a Wakeup signal (i.e., a "H" level signal) to operate the DC-DC converter 13, it turns on and connects the resistor 151, which is connected in series with the NMOS transistor 152, to ground. As a result, the capacitor 150 discharges through the resistor 151, and the voltage Vstb level falls below the predetermined level Vstop, as shown in Figure 10. As a result, the determination circuit 73 determines that the control IC 50 should be put into "powered mode".

[0135] As a result, the control IC 50 operates in "energized mode" as shown in Figure 11 when the Wakeup signal is "H". Note that resistor 151 corresponds to a "resistor", NMOS transistor 152 corresponds to a "first switch", and the Wakeup signal corresponds to an "instruction signal". Also, current source 71 corresponds to a "current source".

[0136] Then, when the control IC 50 is started up and the control IC 50 is in the state setting period, current Ib flows from the current source 131, which has received a signal S2 instructing the supply of current Ib, and a predetermined voltage Vstb is generated at terminal STB. As a result, the analog-to-digital converter 132 converts this predetermined voltage into a digital value Dvstb.

[0137] Subsequently, the determination circuit 121 outputs a signal Se indicating whether the drive pattern should be changed to "external mode" or "internal mode" depending on the digital value Dvstb. Specifically, if the resistance value Rstb of resistor 151 is Ra, the determination circuit 121 outputs a signal Se indicating "external mode" as shown in Figure 6.

[0138] On the other hand, if the resistance value Rstb of resistor 151 is Rb, the determination circuit 121 outputs a signal Se indicating the "internal mode" as shown in Figure 6.

[0139] <Configuration of circuits related to the ExtSTB signal> NMOS transistor 153 is a switch that changes the level of voltage Vstb based on the signal ExtSTB, and is located between NMOS transistor 157 (described later) and NMOS transistor 152. NMOS transistor 153 receives the signal ExtSTB from microcontroller 15a at its gate electrode.

[0140] Before explaining what level of voltage Vstb the interface circuit 18a outputs depending on the logic level of the signal EXtSTB, we will first explain the relationship between terminal REG and the NMOS transistor 157, which will be described later.

[0141] <Circuit configuration related to terminal REG> Capacitor 154 is placed between terminal REG and ground to stabilize the output voltage Vreg1 of the internal power supply 92.

[0142] Resistors 155 and 156 divide the voltage Vreg1, generating the voltage Vreg1_div at their connection point.

[0143] NMOS transistor 157 receives the gate electrode voltage Vreg1_div, is placed between signal line L1 and NMOS transistor 153, and is connected to ground via NMOS transistors 152 and 153. NMOS transistors 153 and 157 are also connected in parallel to resistor 151.

[0144] Then, the internal power supply 92 stops the output of voltage Vreg1 until the state setting period of the control IC 50 is complete, so the NMOS transistor 157 is turned off. As a result, the NMOS transistor 157 eliminates the influence that the NMOS transistor 153, which receives the signal ExtSTB, has on the level of voltage Vstb. The NMOS transistor 157 corresponds to the "second switch," and the NMOS transistor 153 corresponds to the "third switch."

[0145] Specifically, the internal power supply 92 outputs a voltage Vreg1, which is the ground voltage, until the state setting period of the control IC 50 is completed. This turns off the NMOS transistor 157, eliminating the influence of the NMOS transistor 153 during the state setting period.

[0146] Subsequently, when the state setting period of the control IC 50 is complete, the internal power supply 92 outputs voltage Vreg1, and the NMOS transistor 157 turns on. When the NMOS transistor 157 turns on, the NMOS transistor 152 is also on, so the level of voltage Vstb changes due to the on / off switching of the NMOS transistor 153, and the control IC 50 changes its operating mode according to the signal ExtSTB.

[0147] Then, when the signal ExtSTB, which instructs the driving pattern of NMOS transistors 32 and 33 in Figure 3, is output, NMOS transistor 153 turns on and off, setting the voltage Vstb lower or higher than the voltage Vthstb as shown in Figure 10.

[0148] Furthermore, when the Wakeup signal is at a low level and the control IC 50 is in "off mode," the NMOS transistor 153 is disconnected from ground, and therefore the level of voltage Vstb is not affected by the ExtSTB signal. Therefore, the following describes what level of voltage Vstb the interface circuit 18a outputs in response to the ExtSTB signal when the Wakeup signal is at a high level ("H") and the control IC 50 is in "on mode."

[0149] ==Operation when signal ExtSTB is at “H” level== Specifically, when the signal ExtSTB, which switches NMOS transistors 32 and 33 in "low standby power mode" (i.e., at the "H" level), is output, NMOS transistor 153 turns on. At this time, regardless of the operation of the clamp circuit 133 in Figure 5, the voltage Vstb level becomes lower than the predetermined level Vthstb, as shown in Figure 10.

[0150] At this time, the comparator 134 outputs a signal Sc indicating "low standby power mode," causing the oscillator circuit 101 to output an oscillation signal Vosc that switches the NMOS transistors 32 and 33 in "low standby power mode."

[0151] As a result, the interface circuit 18a causes the control IC 50 to intermittently switch the NMOS transistors 32 and 33, as shown in the stage where the signal ExTSTB in Figure 11 is at the "H" level.

[0152] ==Operation when signal ExtSTB is at “L” level== On the other hand, when the signal ExtSTB, which switches NMOS transistors 32 and 33 in "normal mode" (i.e., at the "L" level), is output, NMOS transistor 153 turns off. At this time, as shown in Figure 10, the level of voltage Vstb becomes higher than the predetermined level Vthstb.

[0153] At this time, the comparator 134 outputs a signal Sc indicating "normal mode," causing the oscillator circuit 101 to output an oscillation signal Vosc that switches the NMOS transistors 32 and 33 in "normal mode."

[0154] As a result, the interface circuit 18a causes the control IC 50 to continuously switch NMOS transistors 32 and 33, as shown in the stage where the signal ExTSTB in Figure 11 is at the "L" level. The coordination function of the interface circuit 18a will be described later.

[0155] ==Power Factor Correction IC175 Side Circuit== As described above, resistors 158 and 161, capacitors 159 and 162, and NMOS transistor 160 enable the coordinated function between the control IC 50 and the power factor correction IC 175.

[0156] The resistor 158 and capacitor 159 constitute a low-band-pass filter that removes noise from the pulse signal output by the communication circuit 135 in Figure 5. The pulse signal is configured to output two pulses of period T1 when the effective value of the AC voltage Vac is 100V, and to output one pulse of period T1 when the effective value of the AC voltage Vac is 200V.

[0157] The NMOS transistor 160 is switched on and off in response to the output of the low-band-pass filter, and outputs a voltage Sig corresponding to the pulse signal output by the communication circuit 135 to the power factor correction IC 175.

[0158] Resistor 161 is placed between terminal RT and ground, and lowers the voltage at terminal RT when the NMOS transistor 160 is turned off.

[0159] Capacitor 162 is placed between terminal RT and ground to stabilize the voltage at terminal RT.

[0160] <<<Overview of Power Factor Correction Circuit 22>>> Figure 12 shows the configuration of the power factor correction circuit 22. The power factor correction circuit 22 is a boost chopper type power supply circuit that generates an output voltage Vout1 of the desired level from the AC voltage Vac of the commercial power supply.

[0161] The power factor correction circuit 22 consists of a full-wave rectifier circuit 170, capacitors 171, 174, 183, 184, transformer 172, diode 173, power factor correction IC 175, NMOS transistor 176, and resistors 180-182.

[0162] The full-wave rectifier circuit 170 applies a rectified voltage Vrec2, obtained by full-wave rectifying a predetermined AC voltage Vac, to the capacitor 171 and the main coil L5 of the transformer 172. Here, the AC voltage Vac is, for example, a voltage with a frequency of 50 to 60 Hz and a value of 100 to 240 V.

[0163] Capacitor 171 is an element that smooths the rectified voltage Vrec2, and transformer 172 has a main coil L5 and an auxiliary coil L6 that is magnetically coupled to the main coil L5. In this embodiment, the auxiliary coil L6 is wound such that the voltage generated in the auxiliary coil L6 has the opposite polarity to the voltage generated in the main coil L5. The voltage Vzcd generated in the auxiliary coil L6 is then applied to terminal ZCD.

[0164] The rectified voltage Vrec2 is applied directly to the main coil L5, but it may also be applied to the main coil L5 via an element such as a resistor (not shown).

[0165] Furthermore, the main coil L5, together with the diode 173, capacitor 174, and NMOS transistor 176, constitutes a boost chopper circuit. Therefore, the charging voltage of capacitor 174 becomes the DC output voltage Vout1. The output voltage Vout1 is, for example, 400V.

[0166] The power factor correction IC 175 is an integrated circuit that controls the switching of the NMOS transistor 176 so that the output voltage Vout1 level reaches a target level (e.g., 400V) while improving the power factor of the AC-DC converter 12. Specifically, the power factor correction IC 175 drives the NMOS transistor 176 based on the inductor current IL flowing through the main coil L5 and the output voltage Vout1.

[0167] Details of the power factor correction IC175 will be described later, but the power factor correction IC175 is provided with terminals VH, VCC, RT, FB, ZCD, COMP, and OUT. In addition to the seven terminals VH, VCC, RT, FB, ZCD, COMP, and OUT mentioned above, the power factor correction IC175 is also provided with other terminals, but these are omitted here for convenience.

[0168] The NMOS transistor 176 is a transistor for controlling the power from the AC-DC converter 12 to the DC-DC converter 13. In this embodiment, the NMOS transistor 176 is a MOS (Metal Oxide Semiconductor) transistor, but it is not limited to this. The NMOS transistor 176 may be any transistor capable of controlling power, such as a bipolar transistor. The gate electrode of the NMOS transistor 176 is connected to be driven by a signal from terminal OUT.

[0169] Resistors 180 and 181 form a voltage divider circuit that divides the output voltage Vout1, generating the feedback voltage Vfb_b used when switching the NMOS transistor 176. The feedback voltage Vfb_b generated at the node to which resistors 180 and 181 are connected is applied to terminal FB.

[0170] Resistor 182 and capacitors 183 and 184 are phase compensation elements for the feedback-controlled power factor correction IC 175, as will be described in detail later. Resistor 182 and capacitor 183 are connected in series between terminal COMP and ground, and capacitor 184 is connected in parallel with them.

[0171] Additionally, a pulse signal from interface circuit 18a is input to terminal RT.

[0172] <<<Details of the power factor correction IC175>>> Figure 13 shows an example of the configuration of the power factor correction IC 175. The power factor correction IC 175 consists of a drive circuit 190, a signal detection circuit 191, and a resistor 192. In Figure 13, for convenience, the terminals are drawn in different positions than in Figure 12, but the wiring, components, etc. connected to each terminal are the same in Figures 12 and 13.

[0173] ===Drive Circuit 190=== The drive circuit 190 is a circuit that generates a drive signal Vdr to turn the NMOS transistor 176 on and off based on a feedback voltage Vfb_b corresponding to the output voltage Vout1. The drive circuit 190 is composed of a zero current detection circuit 200, a delay circuit 201, a pulse circuit 202, a turn-on timer circuit 203, OR circuits 204, 213, an error amplification circuit 210, an oscillator circuit 211, a comparator 212, an SR flip-flop 220, and a buffer circuit 221.

[0174] ====Zero Current Detection Circuit 200==== The zero current detection circuit 200 is a circuit that detects whether the current value of the inductor current IL is approximately zero, represented by a "current value Ia" (hereinafter, for convenience, "approximately zero" will simply be referred to as zero), based on the voltage Vzcd at terminal ZCD. In this embodiment, the zero current detection circuit 200 outputs a high-level signal Vz when it detects that the current value of the inductor current IL is "zero," which is "current value Ia." The zero current detection circuit 200 also includes a comparator (not shown) that compares a predetermined voltage across the auxiliary coil L6 when the inductor current IL is "current value Ia" with the voltage Vzcd.

[0175] ====Delay Circuit 201==== The delay circuit 201 outputs a signal Vz at the "H" level after delaying it for a predetermined time when the zero current detection circuit 200 outputs it.

[0176] ====Pulse Circuit 202===== When the delay circuit 201 outputs a high-level signal Vz, the pulse circuit 202 outputs a high-level pulse signal Vp1.

[0177] ====Turn-on timer circuit 203==== The turn-on timer circuit 203 outputs a pulse signal Vp2 to turn on the NMOS transistor 176 when the power factor correction IC 175 is started up or when the AC voltage Vac is interrupted and the pulse signal Vp1 is not output. Specifically, if the pulse signal Vp1 is not output for a predetermined period of time, it outputs a pulse signal Vp2 at a "H" level at predetermined intervals.

[0178] ====OR Circuit 204==== The OR circuit 204 calculates and outputs the logical OR of pulse signals Vp1 and Vp2. Therefore, in this embodiment, either pulse signal Vp1 or pulse signal Vp2 is output as signal Vp3 from the OR circuit 204.

[0179] ====Error Amplifier Circuit 210==== The error amplification circuit 210 is a circuit that amplifies the error between the feedback voltage Vfb_b applied to terminal FB and a predetermined reference voltage VREF0 or VREF1. Based on the reference voltage VREF0, the ratio of resistors 180 and 181 is adjusted so that the output voltage Vout1 becomes the desired voltage.

[0180] Furthermore, the reference voltages VREF0 and VREF1 are selected based on the signal enb from the signal detection circuit 191 described later. Reference voltage VREF1 is the reference voltage used to generate an output voltage Vout1 at a predetermined level lower than the target level when the AC input is high (e.g., 200V).

[0181] Furthermore, between the output of the error amplifier circuit 210 and ground, a phase compensation resistor 182 and capacitors 183 and 184 are connected via terminal COMP. Here, the voltage at the node where the output of the error amplifier circuit 210 and terminal COMP are connected is denoted as voltage Ve.

[0182] ====Oscillator Circuit 211==== The oscillator circuit 211 outputs a ramp wave Vr whose amplitude gradually increases each time it receives a high-level signal Vp1 from the SR flip-flop 220.

[0183] ====Comparator 212===== The comparator 212 compares the magnitudes of the voltage Ve and the ramp wave Vr, and outputs a signal Vc1 as a result of the comparison. Here, the voltage Ve is applied to the inverting input terminal of the comparator 212, and the ramp wave Vr is applied to the non-inverting input terminal of the comparator 212. Therefore, when the level of the ramp wave Vr is lower than the level of the voltage Ve, the signal Vc1 becomes "L" level, and when the level of the ramp wave Vr is higher than the level of the voltage Ve, the signal Vc1 becomes "H" level.

[0184] ====OR Circuit 213==== The OR circuit 213 calculates and outputs the logical OR of signal Vc1 and signal Vsb from signal detection circuit 191. Therefore, when signal Vc1 or signal Vsb reaches a "H" level, the OR circuit 213 outputs a "H" level signal Vp4.

[0185] ====SR Flip-Flop 220==== The S input of the SR flip-flop 220 receives signal Vp3, and the R input receives signal Vp4. Therefore, the drive signal Vq1, which is the Q output of the SR flip-flop 220, becomes high when signal Vp3 is high. On the other hand, when signal Vp4 is high, the drive signal Vq1 becomes low. The SR flip-flop 220 operates with reset priority, and when signal Vp4 is high, it always outputs a low signal Vq1 regardless of signal Vp3.

[0186] ====Buffer Circuit 221==== The buffer circuit 221 drives the NMOS transistor 176 based on the drive signal Vq1. Specifically, the buffer circuit 221 drives the NMOS transistor 176, which has a large gate capacitance, etc., with a signal Vdr of the same logic level as the input signal. In addition, the buffer circuit 221 turns on the NMOS transistor 176 based on the "H" level drive signal Vq1 and turns off the NMOS transistor 176 based on the "L" level drive signal Vq1.

[0187] ===Signal detection circuit 191=== The signal detection circuit 191 implements the main functions when the control IC 50 operates in "internal mode" and controls the power factor correction IC 175. This embodiment also describes the case when the control IC 50 operates in "external mode".

[0188] Therefore, in this embodiment, when the determination circuit 121 outputs a signal Se indicating “external mode”, the communication circuit 135 in Figure 5 outputs a pulse signal to the power factor correction IC 175 via the interface circuit 18a indicating whether the effective value of the AC voltage Vac is high (e.g., 200V) or low (e.g., 100V).

[0189] The signal detection circuit 191 then detects whether the AC input is 100V or 200V based on the pulse signal input via terminal RT, and outputs a signal enb indicating whether the AC input is 100V or 200V. A resistor 192 is connected to terminal RT to pull it up to the power supply voltage Vdd from the internal power supply (not shown). Other functions of the signal detection circuit 191 will be described later.

[0190] <<<Operation of Control IC 50>>> Figure 14 shows an example of the operation of the control IC 50. Note that Figure 14 shows an example of the operation of the control IC 50 when it changes the drive pattern in "external mode" after startup. Furthermore, it is assumed that before time t0, the microcontroller 15a outputs a Wakeup signal (i.e., at an "L" level) to stop the DC-DC converter 13. Also, at this time, the control IC 50 is in "cutoff mode". The effective value of the AC voltage Vac (i.e., AC input) is assumed to be 100V.

[0191] At time t0, when the microcontroller 15a in Figure 1 outputs a Wakeup signal (i.e., a "H" level signal) to activate the DC-DC converter 13, the NMOS transistor 152 in Figure 9 turns on. The capacitor 150 discharges through the resistor 151, and the voltage Vstb at terminal STB begins to decrease.

[0192] At time t1, when the voltage Vstb decreases and reaches the predetermined level Vstop, the determination circuit 73 outputs a switching signal Sb. As a result, the control circuit 81 outputs a signal Pon to the charging circuit 82 to start charging the capacitor 61 in Figure 3. Then, the voltage Vcc begins to rise. At this time, the control IC 50 switches to "power-on mode". However, since the control IC 50 has not yet completed its initial setup, the NMOS transistors 32 and 33 are not switched.

[0193] At time t2, when the voltage Vcc reaches a predetermined level Vccrst, the reset circuit 90 outputs a signal rst1 that starts the operation of the various circuits of the control IC 50. Then, the state setting period begins, and the control circuit 120 in Figure 5 outputs a signal S1 to discharge the capacitor 150, and the discharge circuit 130 discharges the capacitor 150. As a result, the voltage Vstb becomes the ground voltage.

[0194] At time t3, when the voltage Vcc reaches a predetermined level Vstoff, the control circuit 81 outputs a signal Pon to the charging circuit 82 to stop charging the capacitor 61. Thereafter, until time t6 as described later, when the voltage Vcc reaches a predetermined level Vston, the control circuit 81 causes the charging circuit 82 to start charging the capacitor 61 shown in Figure 3, and outputs a signal Pon to stop charging when the voltage Vcc reaches a predetermined level Vstoff.

[0195] At time t4, when the control circuit 120 outputs a signal S1 to stop the discharge of capacitor 150 and a signal S2 to instruct the supply of current Ib, the current source 131 in Figure 5 supplies current Ib to resistor 151 via terminal STB. As a result, the voltage Vstb becomes a voltage corresponding to the resistance value Rstb of resistor 151. In this embodiment, the resistance value Rstb of resistor 151 is assumed to be the resistance value Ra shown in Figure 6.

[0196] At time t5, when the control circuit 120 outputs a signal S3 indicating the timing to acquire the digital value Dvstb, the determination circuit 121 acquires the digital value Dvstb of the voltage Vstb. As a result, the determination circuit 121 determines that it is in "external mode" and outputs a signal Se indicating "external mode".

[0197] Subsequently, the control circuit 120 outputs a signal S1 to discharge the capacitor 150, and the discharge circuit 130 discharges the capacitor 150. As a result, the voltage Vstb becomes the ground voltage.

[0198] At time t6, when the state setting period is completed, the control circuit 120 outputs a signal Sd indicating the completion of the state setting period for initializing the various circuits of the control IC 50. At this time, the control circuit 81 causes the charging circuit 82 to charge the capacitor 61 until the voltage Vcc reaches a predetermined level Vccon. The internal power supply 92 also outputs a voltage Vreg1 to terminal REG.

[0199] Then, when the control circuit 120 outputs a signal S1 to stop the discharge of capacitor 150, the discharge circuit 130 stops the discharge of capacitor 150. As a result, the clamp circuit 133 begins to maintain the voltage Vstb at voltage Vnorm.

[0200] At time t7, when the voltage Vcc exceeds a predetermined level Vccon, the undervoltage protection circuit 91 outputs a signal rst2 that starts the operation of the load detection circuit 100, the oscillation circuit 101, and the drive circuit 102 shown in Figure 4. Also, since the voltage Vcc has reached the predetermined level Vccon, the control circuit 81 outputs a signal Pon to the charging circuit 82 that stops charging the capacitor 61.

[0201] Furthermore, when the oscillator circuit 101 receives the signal Sc indicating "normal mode" and the signal Se indicating "external mode", it outputs an oscillation signal Vosc to the drive circuit 102 to cause the NMOS transistors 32 and 33 to be continuously switched.

[0202] Then, the control IC 50 starts switching the NMOS transistors 32 and 33 in Figure 3, and thereafter, the capacitor 61 is charged by the current from the auxiliary coil L4. Also, since the AC input is 100V, the communication circuit 135 outputs a pulse signal to the power factor correction IC 175 via terminal STB, indicating that the effective value of the AC voltage Vac is low.

[0203] At time t8, when the microcontroller 15a outputs a signal ExtSTB to the control IC 50 that switches the NMOS transistors 32 and 33 in "low standby power mode" (i.e., at the "H" level), the voltage Vstb level becomes lower than a predetermined level Vthstb. As a result, the comparator 134 outputs a signal Sc that indicates "low standby power mode".

[0204] Then, when the oscillation circuit 101 receives the signal Sc indicating "low standby power mode" and the signal Se indicating "external mode", it outputs an oscillation signal Vosc to the drive circuit 102 to cause intermittent switching of the NMOS transistors 32 and 33.

[0205] At time t9, when the microcontroller 15a outputs a signal ExtSTB to the control IC 50 that switches the NMOS transistors 32 and 33 in "normal mode" (i.e., at the "L" level), the voltage Vstb level becomes higher than the predetermined level Vthstb. As a result, the comparator 134 outputs a signal Sc that indicates "normal mode".

[0206] Then, when the oscillator circuit 101 receives the signal Sc indicating "normal mode" and the signal Se indicating "external mode", it outputs an oscillation signal Vosc to the drive circuit 102 to cause continuous switching of the NMOS transistors 32 and 33.

[0207] At time t10, similar to time t7, the communication circuit 135 outputs a pulse signal to the power factor correction IC 175 via terminal STB, indicating that the effective value of the AC voltage Vac is low because the AC input is 100V.

[0208] The above describes an embodiment in which the control IC 50 changes the drive pattern in "external mode". Furthermore, the control IC 50 can change its operating mode between a "shut-off mode" which stops circuits other than the start circuit 70, and a "power-on mode" which operates the circuit including the start circuit 70, depending on the logic level of the Wakeup signal.

[0209] In this embodiment, the configuration of the interface circuit 18a allows the control IC 50 to appropriately switch the NMOS transistors 32 and 33 in "normal mode" or "low standby power mode" according to the logic level of the signal ExtSTB after startup.

[0210] As a result, when the control IC 50 is in "off mode," the control IC 50 can reduce its own power consumption. Furthermore, even when the control IC 50 is operating in "powered mode," it can change its drive pattern to "normal mode" or "low standby power mode" depending on the logic level of the signal ExtSTB, thereby reducing the power consumption of the DC-DC converter 13. Moreover, the power consumption of the control IC 50 when it is in "off mode" is less than the power consumption when the control IC 50 is operating in "normal mode" or "low standby power mode."

[0211] <<<Configuration and Operation of Interface Circuit 18b>>> Figure 15 shows an example of interface (IF) circuit 18b. Interface circuit 18b is used when changing the drive pattern in “internal mode”, and is a circuit obtained by removing NMOS transistors 153, 157 and resistors 155, 156 from interface circuit 18a in Figure 9. Therefore, the details of the configuration of interface circuit 18b will not be explained.

[0212] <<Operation when the Wakeup signal is at the "L" level>> Also, similar to the case in Figure 9, when the microcontroller 15b outputs a Wakeup signal (i.e., at the "L" level) to stop the DC-DC converter 13, the voltage Vstb at terminal STB rises above the predetermined level Vstop, as shown in Figure 16. As a result, the interface circuit 18b puts the control IC 50 into "cutoff mode," as shown in the stage where the Wakeup signal is "L" in Figure 17.

[0213] <<Operation when the Wakeup signal is at the "H" level>> On the other hand, when the microcontroller 15b outputs a Wakeup signal (i.e., a "H" level signal) to operate the DC-DC converter 13, the level of voltage Vstb becomes lower than the predetermined level Vstop, as shown in Figure 16. As a result, the interface circuit 18b operates the control IC 50 in "powered-on mode," as shown in the stage where the Wakeup signal is "H" in Figure 17.

[0214] <Explanation of the coordination function between control IC 50 and power factor correction IC 175> Furthermore, when the drive pattern is changed in “internal mode”, the communication circuit 135 in Figure 5 outputs a pulse signal to the power factor correction IC 175 according to the AC input and the operating mode of the control IC 50, as shown in Figure 17, in order to realize a cooperative function between the control IC 50 and the power factor correction IC 175.

[0215] Specifically, as shown in Figure 17, the communication circuit 135 changes the number of pulses included in the pulse signal in response to the AC input (see, for example, pulses (a) and (c)), and changes the pulse width of the pulse in response to the operating mode of the control IC 50 (see, for example, pulses (a) and (b)).

[0216] Furthermore, the power factor correction IC175 detects that (a) when it receives a pulse signal with a pulse width of T1 and 2 pulses, the AC input is 100V and the operating mode should be changed to continuous switching. Also, the power factor correction IC175 detects that (b) when it receives a pulse signal with a pulse width of T2 and 2 pulses, the AC input is 100V and the operating mode should be changed to intermittent switching.

[0217] Furthermore, the power factor correction IC175 detects that (c) when it receives a pulse signal with a pulse width of T1 and one pulse, the AC input is 200V and the operating mode should be changed to continuous switching. Also, the power factor correction IC175 detects that (d) when it receives a pulse signal with a pulse width of T2 and one pulse, the AC input is 200V and the operating mode should be changed to intermittent switching.

[0218] Furthermore, the power factor correction IC175 (e) stops switching while receiving a pulse signal that is a continuous pulse with a pulse width of T3. Also, the power factor correction IC175 stops if the control IC50 is in "cutoff mode". Note that the relationship between pulse widths T1 to T3 is T2 > T1 > T3.

[0219] <Details of signal detection circuit 191> The signal detection circuit 191 in Figure 13 detects the voltage Sig at terminal RT, which receives the pulse signal from the control IC 50, and detects the AC input and switching instructions based on the number of pulses and pulse width of the pulse signal. Specifically, as described above, the signal detection circuit 191 detects that the AC input is 100V if the pulse signal contains two pulses.

[0220] The signal detection circuit 191 then detects that the AC input is 200V if the pulse signal contains one pulse. As a result, the power factor correction IC 175 can change its operation according to the type of AC input indicated by the pulse signal without having to detect the AC input itself.

[0221] Furthermore, the signal detection circuit 191 detects that the control IC 50 has instructed the power factor correction IC 175 to perform "continuous switching" when the pulse width of the pulse signal is pulse width T1. In this case, the signal detection circuit 191 outputs a "L" level signal Vsb to the OR circuit 213. Then, the power factor correction IC 175 sets the signal Vdr to a "L" level based on the signal Vc1 output by the comparator 212.

[0222] Furthermore, the signal detection circuit 191 detects that the control IC 50 has instructed the power factor correction IC 175 to perform "intermittent switching" when the pulse width of the pulse signal is pulse width T2. In this case, the signal detection circuit 191 outputs an "H" level signal Vsb when the voltage Vfb_b reaches a predetermined level V1, and outputs an "L" level signal Vsb when the voltage Vfb_b drops to a predetermined level V2.

[0223] Therefore, when the voltage Vfb_b reaches a predetermined level V1, the signal detection circuit 191 sets the signal Vdr to the "L" level and turns off the NMOS transistor 176 of the power factor correction IC 175. On the other hand, when the voltage Vfb_b decreases to a predetermined level V2, the signal detection circuit 191 drives the NMOS transistor 176 of the power factor correction IC 175 based on the signal Vc1.

[0224] Furthermore, the signal detection circuit 191 detects that if the pulse width of the pulse signal is pulse width T3, the control IC 50 has instructed the power factor correction IC 175 to stop switching while outputting the pulse signal. In this case, the signal detection circuit 191 outputs a "H" level signal Vsb while the pulse signal is input, setting the signal Vdr to a "L" level and causing the power factor correction IC 175 to turn off the NMOS transistor 176.

[0225] <<<Coordinated operation of control IC 50 and power factor correction IC 175>>> Figure 18 shows an example of the operation of the control IC 50 and the power factor correction IC 155. Note that Figure 18 also shows an example of the operation of the control IC 50 when it changes the drive pattern in "internal mode" after being started up.

[0226] Furthermore, prior to time t20, the microcontroller 15b outputs a Wakeup signal (i.e., an "L" level signal) that stops the DC-DC converter 13. At this time, the control IC 50 is in "cutoff mode". The effective value of the AC voltage Vac (i.e., the AC input) is assumed to be 100V.

[0227] Furthermore, since the signal ExtSTB and voltage Vreg1_div are not used as inputs in interface circuit 18b, they are not shown in Figure 18. Also, the operation of control IC 50 from time t20 to time t27 in Figure 18 corresponds to the operation of control IC 50 from time t0 to time t7 in Figure 14, except for the following points.

[0228] Furthermore, at time t25, the determination circuit 121 determines that it is in "internal mode" and outputs a signal Se indicating "internal mode".

[0229] Furthermore, the power factor correction IC175 shall stop switching before time t21 when the control IC50 is in "off mode". Also, the power factor correction IC175 shall stop switching from time t21 when the control IC50 transitions to "on mode" until time t27 when the state setting period is completed and continuous switching begins. Based on the above, the operation of the control IC50 and power factor correction IC155 after time t27 will be explained below.

[0230] At time t27, when the voltage Vcc level exceeds a predetermined level Vccon, the undervoltage protection circuit 91 outputs a signal rst2 that starts the operation of the load detection circuit 100, the oscillation circuit 101, and the drive circuit 102 shown in Figure 4. Also, because the voltage Vcc level becomes the predetermined level Vccon, the control circuit 81 outputs a signal Pon to the charging circuit 82 that stops charging the capacitor 61.

[0231] Furthermore, the oscillator circuit 101 operates in the same manner as at time t7 in Figure 14. And, as at time t7 in Figure 14, the capacitor 61 is subsequently charged by the current from the auxiliary coil L4. Also, the communication circuit 135 operates in the same manner as at time t7 in Figure 14.

[0232] Furthermore, the power factor correction IC175 starts continuous switching when the voltage Vcc level exceeds a predetermined level Vccon.

[0233] At time t28, the load detection circuit 100 in Figure 4 indicates that the load 14 in Figure 1 is a light load and outputs a voltage Vca at a level lower than the predetermined level Vcastb. As a result, when the oscillation circuit 101 receives the voltage Vca indicating that the load 14 is a light load and the signal Se indicating "internal mode", it outputs an oscillation signal Vosc to the drive circuit 102 to intermittently switch the NMOS transistors 32 and 33 in Figure 3. Then, the communication circuit 135 in Figure 5 outputs a pulse signal containing two pulses with a pulse width of T2.

[0234] At time t29, the power factor correction IC175 detects, based on the pulse signal, that the AC input is 100V and that intermittent switching should be performed. Therefore, the power factor correction IC175 starts intermittent switching.

[0235] At time t30, the load detection circuit 100 in Figure 4 indicates that the load 14 in Figure 1 is a heavy load and outputs a voltage Vca at a level higher than the predetermined level Vcastb. As a result, when the oscillation circuit 101 receives the voltage Vca indicating that the load 14 is a heavy load and the signal Se indicating the "internal mode", it outputs an oscillation signal Vosc to the drive circuit 102 to cause continuous switching of the NMOS transistors 32 and 33.

[0236] At time t31, the communication circuit 135 in Figure 5 outputs a pulse signal containing two pulses with a pulse width of T1.

[0237] At time t32, the power factor correction IC175 detects, based on the pulse signal, that the AC input is 100V and that continuous switching should be performed. Therefore, the power factor correction IC175 starts continuous switching.

[0238] The above describes an embodiment in which the control IC 50 changes the drive pattern in "internal mode". Furthermore, the control IC 50 can change its operating mode between a "shut-off mode" that stops circuits other than the startup circuit 70 and a "power-on mode" that operates the circuit including the startup circuit 70, depending on the logic level of the Wakeup signal.

[0239] In this embodiment, the configuration of the interface circuit 18b allows the control IC 50 to appropriately switch the NMOS transistors 32 and 33 in "normal mode" or "low standby power mode" depending on the state of the load 14 after startup.

[0240] As a result, when the control IC 50 is in "off-mode," the control IC 50 can reduce its own power consumption. Furthermore, even when the control IC 50 is operating in "on-mode," it can change its drive pattern to "normal mode" or "low standby power mode" depending on the state of the load 14, thereby reducing the power consumption of the DC-DC converter 13. Moreover, the power consumption when the control IC 50 is in "off-mode" is less than the power consumption when the control IC 50 is operating in "normal mode" or "low standby power mode." In addition, the control IC 50 can work in conjunction with the power factor correction IC 175 to reduce the overall power consumption of the power supply unit 10.

[0241] ===Summary=== The power supply unit 10 of this embodiment has been described above. The control IC 50 comprises a terminal STB, a determination circuit 73, an internal power supply 92, and a drive circuit 102. The control IC 50 also controls the internal power supply 92 based on the voltage level of terminal STB (voltage Vstb), and when operating in "cut-off mode", it can stop the internal power supply 92 from generating voltage Vreg1. When the internal power supply 92 stops generating voltage Vreg1, the control IC 50 can stop the operation of circuits that operate by receiving voltage Vreg1. This makes it possible to provide an integrated circuit that can further reduce power consumption.

[0242] Furthermore, the control IC 50 includes terminal VH, a constant voltage source 80, and a current source 71. As a result, the control IC 50 can supply the voltage Vstartup to the current source 71 and the determination circuit 73 even when the control IC 50 is in "cutoff mode" while the rectified voltage Vrec1 is applied to terminal VH.

[0243] Furthermore, the control IC 50 includes a terminal VCC. This allows the internal power supply 92 to operate based on the voltage Vcc, and the control IC 50 facilitates the internal power supply 92 to stop generating the voltage Vreg1 when the voltage Vcc drops in “cutoff mode”.

[0244] Furthermore, the control IC 50 includes a charging circuit 82. As a result, the charging circuit 82 stops charging the capacitor 61, and the control IC 50 facilitates the internal power supply 92 to stop generating voltage Vreg1 by causing a drop in voltage Vcc when in “cutoff mode”.

[0245] Furthermore, the control IC 50 includes a load detection circuit 100, an oscillation circuit 101, a determination circuit 121, and a comparator 134. This allows the control IC 50 to change the drive pattern of the NMOS transistors 32 and 33 in either "external mode" or "internal mode".

[0246] Furthermore, the control IC 50 includes a communication circuit 135. This allows the control IC 50 to output a pulse signal to the power factor correction IC 175 when changing the drive pattern in "internal mode," enabling it to operate in coordination with the power factor correction IC 175.

[0247] Furthermore, the control IC 50 includes a terminal REG. This prevents the control IC 50 from malfunctioning even if the ExtSTB signal is mistakenly input from the microcontroller 15a during the state setting period.

[0248] Furthermore, the control IC 50 includes a discharge circuit 130 and a control circuit 120. This allows the control IC 50 to accurately determine the voltage corresponding to the resistance value Rstb of the resistor 151 during the state setting period.

[0249] Furthermore, the control IC 50 includes an internal power supply 93. This allows the control IC 50 to shut down a circuit that operates when supplied with voltage Vreg2 when it is in "shut-off mode".

[0250] Furthermore, the control IC 50 includes a Zener diode 72. As a result, even if the capacitor 150 is charged by the current source 71, the voltage Vstb will not exceed a predetermined level.

[0251] Furthermore, the control IC 50 includes a terminal STB and a mode selection circuit (decision circuit 73 and comparator 134). The control IC 50 can also operate in one of three modes: "cutoff mode," "normal mode," or "low standby power mode," based on the voltage level of terminal STB (voltage Vstb). This allows the control IC 50 to further reduce power consumption.

[0252] Furthermore, the mode selection circuit can change the operating mode of the control IC 50 based on the voltage level of terminal STB. This allows the operating mode of the control IC 50 to be changed simply by detecting the voltage level of terminal STB.

[0253] Furthermore, the mode selection circuit includes a determination circuit 73 that operates even in "off mode" and a comparator 134 that does not operate in "off mode". As a result, the control IC 50 can suppress power consumption in "off mode" while operating in either "normal mode" or "low standby power mode" in "powered mode".

[0254] Furthermore, the control IC 50 includes a load detection circuit 100, an oscillation circuit 101, and a setting circuit 76. This allows the control IC 50 to change the drive pattern of the NMOS transistors 32 and 33 in either "external mode" or "internal mode".

[0255] Further, the control IC 50 includes a communication circuit 135. The communication circuit 135 outputs a pulse signal that is lower than a predetermined level Vstop and higher than a predetermined level Vthstb. Thereby, even if the voltage level of the terminal STB changes due to the pulse signal, it does not affect the change of the operation mode of the control IC 50.

[0256] Also, the control IC 50 includes an internal power supply 92 and a drive circuit 102. The control IC 50 controls the internal power supply 92 based on the voltage level (voltage Vstb) of the terminal STB, and when operating in the "cut-off mode", it can stop the generation of the voltage Vreg1 in the internal power supply 92. Then, when the internal power supply 92 stops generating the voltage Vreg1, the control IC 50 can stop the operation of the circuit that operates by receiving the supply of the voltage Vreg1.

[0257] Also, the DC-DC converter 13 includes an interface circuit 18a. The interface circuit 18a includes a resistor 151 and NMOS transistors 152, 153, 157. Thereby, the interface circuit 18a can apply a voltage for setting the operation mode of the control IC 50 to the terminal STB by turning on and off the NMOS transistors 152, 153, 157.

[0258] Also, by turning on and off the NMOS transistor 152, the interface circuit 18a can operate the control IC 50 in the "cut-off mode" or the "power-on mode".

[0259] Also, by turning on and off the NMOS transistors 153, 157, the interface circuit 18a can operate the control IC 50 in the "normal mode" or the "low standby power mode".

[0260] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. Furthermore, the present invention may be modified or improved without departing from its spirit, and it goes without saying that equivalents thereof are included. [Explanation of Symbols]

[0261] 10 Power supply 11 switches 12 AC-DC Converters 13 DC-DC Converters 14 load 15a, 15b Microcontroller 16,30,31,42,61,63,64,67,68,150,154,159,162,171,174,183,184 Capacitors 17 Photodiode 18a, 18b Interface Circuit 20, 21, 40, 41, 60, 173 diodes 22 Power Factor Correction Circuit 32, 33, 152, 153, 157, 160, 176 NMOS transistors 34,172 transformers 35 Control Block 43 Constant Voltage Circuit 44 Light-emitting diodes 62 Phototransistors 65, 66, 74, 75, 142, 151, 155, 156, 158, 161, 180, 181, 182 resistors 70 Startup Circuit 71,131 current source 72 Zener diodes 73 Judgment circuit 76 Setting Circuit 80 Constant voltage source 81,120 Control circuits 82 Charging circuit 90 Reset circuit 91 Low-voltage protection circuit 92,93 Internal power supply 100 Load detection circuit 101,211 Oscillation circuit 102,190 Drive circuit 110 Digital section 111 Analog section 121 Judgment circuit 130 Discharge circuit 132 Analog-to-digital converter 133 Clamp circuit 134,212 Comparator 135 Communication circuit 140 Operational amplifier 141 PMOS transistor 170 Full-wave rectifier circuit 191 Signal detection circuit 200 Zero-current detection circuit 201 Delay circuit 202 Pulse circuit 203 Turn-on timer circuit 204,213 OR circuit 210 Error amplification circuit 220 SR flip-flop 221 Buffer circuit

Claims

1. An integrated circuit for switching-driving the power transistors of a power supply circuit in order to generate an output voltage of a target level in the power supply circuit, A first terminal to which an external circuit for setting the operating mode of the integrated circuit is connected, A mode selection circuit that selects whether to operate the integrated circuit in one of the following modes based on the voltage level of the first terminal: a shut-off mode in which no switching operation is performed, a normal mode in which switching operation is performed continuously, or a low standby power mode in which switching operation periods and shut-off operation periods are alternately repeated. Equipped with, The mode selection circuit is, An integrated circuit that operates in the cutoff mode when the voltage level of the first terminal is within a first voltage range, operates in the normal mode when the voltage level is within a second voltage range different from the first voltage range, and operates in the low standby power mode when the voltage level is within a third voltage range different from the first and second voltage ranges.

2. The integrated circuit according to claim 1, The voltage level in the first voltage range is higher than the voltage level in the second voltage range. The voltage level in the second voltage range is higher than the voltage level in the third voltage range. Integrated circuit.

3. The integrated circuit according to claim 2, The mode selection circuit is, A first mode determination circuit that determines whether to operate the integrated circuit in the cutoff mode when the voltage level is within the first voltage range, A second mode determination circuit determines whether to operate the integrated circuit in the normal mode if the voltage level is within the second voltage range, and whether to operate the integrated circuit in the low standby power mode if the voltage level is within the third voltage range. An integrated circuit equipped with the following features.

4. An integrated circuit according to claim 2 or claim 3, An oscillator circuit that outputs an oscillation signal corresponding to the operating mode of the integrated circuit, A load detection circuit for detecting the load state of the power supply circuit, During a state setting period in which the integrated circuit starts up and sets the state of the oscillator circuit, a setting circuit sets the state of the oscillator circuit based on the voltage level so that the oscillator circuit operates in either an external mode that operates based on the voltage level or an internal mode that operates based on the output from the load detection circuit. Equipped with, The oscillation circuit outputs an oscillation signal corresponding to the voltage level when the oscillation circuit is operating in the external mode, and outputs an oscillation signal corresponding to the output from the load detection circuit when the oscillation circuit is operating in the internal mode. Integrated circuit.

5. The integrated circuit according to claim 4, A signal output circuit that outputs a signal of amplitude level within the second voltage range to the first terminal, An integrated circuit equipped with the following features.

6. An integrated circuit according to any one of claims 1 to 5, When the integrated circuit is operated in the cutoff mode, the generation of the first power supply voltage is stopped, and when the integrated circuit is operated in the normal mode or the low standby power mode, the first power supply voltage generation circuit generates the first power supply voltage, The first power supply voltage is supplied, and the drive circuit drives the power transistor using the switching mechanism, An integrated circuit equipped with the following features.

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