DML driver

Abstract

A DML driver configured from: a transistor (M1p) in which a gate is connected to a bias voltage (V2) and in which a source is connected to a power supply voltage (V1); a transistor (M1n) in which a drain is connected to an anode of an LD (1) and in which a source is connected to ground; an inductor (L1) in which an RF input signal (Vin) is inputted to one end and in which the other end is connected to the gate of the transistor (M1n); an inductor (L2) in which one end is connected to the drain of the transistor (M1p) and in which the other end is connected to the anode of the LD (1); and a resistor (Rin) in which one end is connected to a bias voltage (V4) and in which the other end is connected to the inductor (L1).

Description

[Technical Field]

[0001] This invention relates to a technology for driving a directly modulated laser (DML), and more particularly to a DML driver having a frequency peaking function. [Background technology]

[0002] In recent years, the remarkable development of SNS (Social Networking Services) has led to a year-on-year increase in global communication traffic. Further increases in traffic are expected with the advancement of IoT (Internet of Things) and cloud computing technologies. To support this enormous volume of traffic, there is a need for increased communication capacity both within and outside data centers.

[0003] With increasing data capacity, the Ethernet® standard, a key component of network specifications, has completed standardization for 100GbE, and standardization for 400GbE, aiming for even greater capacity, is currently being discussed. For application to 400GbE, drivers using DML are attracting attention from the perspective of low power consumption (see Non-Patent Document 1).

[0004] Figure 11 is a circuit diagram showing the configuration of a conventional DML driver. The DML driver consists of a PMOS transistor M, whose gate is connected to a bias voltage V2, whose source is connected to a power supply voltage V1, and whose drain is connected to the anode of a laser diode (LD) 1. 1p Then, the RF input signal V is sent to the gate. in An NMOS transistor M is input and its source is connected to ground. 1n The gate is connected to the bias voltage V3, and the drain is connected to the PMOS transistor M. 1p The drain and anode of LD1 are connected, and the source is an NMOS transistor M 1n NMOS transistor M connected to the drain 2nand a resistor R having one end connected to the bias voltage V4 and the other end connected to the gate of the NMOS transistor M 1n is composed of in .

[0005] The NMOS transistors M 1n and M 2n are cascode-connected. By being cascode-connected, the frequency characteristics of the NMOS transistor M 1n are improved compared to when it is alone. Also, even when the operating voltage of LD1 exceeds the breakdown voltage of a single NMOS transistor, it is voltage-divided by the cascode connection, so breakdown of the breakdown voltages of the NMOS transistors M 1n , M 2n can be prevented. The resistor R in is a resistor for impedance matching.

[0006] As shown in FIG. 11, in the configuration of the conventional driver circuit, there was no function to compensate for the band of the LD in the driver section, so there was a problem that the band of the transmission front end composed of the DML driver and the LD was limited by the band of the LD.

Prior Art Documents

Non-Patent Documents

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] The present invention was made to solve the above problems and aims to provide a DML driver capable of compensating for the bandwidth of an LD. [Means for solving the problem]

[0009] The DML driver of the present invention is characterized by comprising: a first transistor whose gate or base is connected to a first bias voltage and whose source or emitter is connected to a first power supply voltage; a second transistor whose drain or collector is connected to the anode of a laser diode and whose source or emitter is connected to a second power supply voltage; a first inductor to which an RF input signal is input and whose other end is connected to the gate or base of the second transistor; a second inductor to which one end is connected to the drain or collector of the first transistor and whose other end is connected to the anode of the laser diode; and a first resistor to which one end is connected to a second bias voltage and whose other end is connected to the terminal of the first inductor opposite to the gate or base of the second transistor. [Effects of the Invention]

[0010] According to the present invention, the bandwidth of the LD can be compensated by the high-frequency peaking effect of the first and second inductors. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a circuit diagram showing the configuration of a DML driver according to a first embodiment of the present invention. [Figure 2] Figure 2 is a diagram illustrating the characteristics of the DML driver according to the first embodiment of the present invention. [Figure 3] Figure 3 shows the results of simulations to determine the EO response characteristics of the DML driver and LD for a conventional configuration and the first embodiment of the present invention. [Figure 4A-4B] Figures 4A and 4B show the optical output waveforms of the LD for a conventional configuration and a first embodiment of the present invention. [Figure 5] Figure 5 is a circuit diagram showing the configuration of a DML driver according to a second embodiment of the present invention. [Figure 6] Figure 6 is a circuit diagram showing the configuration of a DML driver according to a third embodiment of the present invention. [Figure 7] Figure 7 is a circuit diagram showing the configuration of a DML driver according to a fourth embodiment of the present invention. [Figure 8] Figure 8 is a circuit diagram showing the configuration of a DML driver according to the fifth embodiment of the present invention. [Figure 9] Figure 9 is a circuit diagram showing the configuration of a DML driver according to the sixth embodiment of the present invention. [Figure 10] Figure 10 is a circuit diagram showing the configuration of a DML driver according to the seventh embodiment of the present invention. [Figure 11] Figure 11 is a circuit diagram showing the configuration of a conventional DML driver. [Modes for carrying out the invention]

[0012] [First Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Figure 1 is a circuit diagram showing the configuration of a DML driver according to the first embodiment of the present invention. The DML driver 10 of this embodiment is a PMOS transistor M whose gate is connected to a bias voltage V2 (first bias voltage) and whose source is connected to a power supply voltage V1 (first power supply voltage). 1p Then, an NMOS transistor M whose source is connected to ground (second power supply voltage) 1n The gate is connected to bias voltage V3 (third bias voltage), the drain is connected to the anode of LD1, and the source is the NMOS transistor M 1n NMOS transistor M connected to the drain 2n And, an RF input signal V is connected to one end. in A (modulated signal) is input, and the other end is connected to an NMOS transistor M 1n An inductor L1 connected to the gate, and a PMOS transistor M with one end connected to the gate. 1pInductor L2 is connected to the drain and the other end is connected to the anode of LD1, and one end is connected to the bias voltage V4 (second bias voltage) and the other end is connected to one of the two terminals of inductor L1, the NMOS transistor M 1n Resistor R connected to the gate and the terminal opposite it in And one end is a PMOS transistor M 1p Capacitor C connected to the source f And one end is a capacitor C f It is connected to the other end, and the other end is a PMOS transistor M 1p Resistor R connected to the drain f It is composed of the following.

[0013] The relative magnitudes of the voltages are V1 > V2 > V3 > V4 > GND (ground). In this embodiment, the RF input signal V in and NMOS transistor M 1n An inductor L1 is inserted between the gates of the PMOS transistor M 1p The drain and NMOS transistor M 2n An inductor L2 is inserted between the drains of the PMOS transistor M 1p A capacitor C is connected in parallel with it. f and resistor R f By connecting these elements in series, it is possible to suppress excessive overshoot and undershoot of the optical waveform while simultaneously activating a high-frequency peaking function to compensate for the bandwidth of LD1.

[0014] PMOS transistor M 1p The RF input signal V in The modulation section to which the input is received is an NMOS transistor M 1n It is responsible for supplying current to LD1 and can be considered a constant current source. PMOS transistor M 1p When considering the constant current source, the resistor R is as shown in Figure 2. 1p It can be replaced with an NMOS transistor M 1n The gate-source resistance and capacitance components can be represented as shown in Figure 2. NMOS transistor M 1nLet R1 be the gate-source resistance, C1 be the gate-source capacitance, and V be the gate voltage. G Therefore, |V G / V in | can be expressed by the following equation (1).

[0015]

number

[0016] In equation (1), ω is the angular frequency. Also, the NMOS transistor M 1n The transconductance of g m Therefore, the gain A of the DML driver v This can be expressed by the following equation (2).

[0017]

number

[0018] Regarding equation (1), 1-ω 2 When C1L1=0, |V G / V in If |>1 is satisfied, a frequency peaking effect can be obtained, so the following equations (3) and (4) must be satisfied.

[0019]

number

[0020] From equation (2), the gain A increases as the frequency increases. v It can be seen that it increases. Therefore, |V| in equation (1) G / V in Gain A is calculated from the frequency at which the value of | begins to decrease. v The inductor L2 and capacitor C increase as the value increases. f and resistor R f By setting this value, it becomes possible to compensate for the bandwidth of LD1 while suppressing excessive overshoot and undershoot of the optical waveform.

[0021] Furthermore, the larger the value of the inductor L2, the greater the gain A. v This increases the bandwidth of the transmit front end, which consists of the DML driver and LD1. However, LD1 has a characteristic where the group delay increases at its relaxation oscillation frequency. Therefore, there is a trade-off between the bandwidth of the transmit front end and the group delay characteristics of LD1, and the value of inductor L2 must be determined considering the group delay characteristics of LD1.

[0022] Figure 3 shows the results of simulations of the Electrical-to-Optical (EO) response characteristics of the DML driver and LD1 for the conventional configuration and this embodiment. In Figure 3, 100 shows the EO response characteristics of the conventional configuration shown in Figure 11, and 101 shows the EO response characteristics of this embodiment. When the EO response exceeds 0 dB, the group delay increases, so by maintaining 0 dB as much as possible and achieving a flat frequency response, it is possible to suppress excessive overshoot and undershoot. Furthermore, it can be seen that the EO response bandwidth of this embodiment is improved by 3 dB compared to the conventional configuration.

[0023] Figure 4A shows the results of a simulation of the optical output waveform of LD1 for a conventional configuration, and Figure 4B shows the results of a simulation of the optical output waveform of LD1 for the configuration of this embodiment. The examples in Figures 4A and 4B show the case where an NRZ (Non Return to Zero) signal light with a signal speed of 32 Gbps is output from LD1. The amplitude scale on the vertical axis is 200 μW / div, and the time scale on the horizontal axis is 20 ps / div. Comparing Figures 4A and 4B, it can be seen that in the configuration of this embodiment, the eye aperture is improved in both the horizontal axis (time) and vertical axis (amplitude) directions, as a peaking effect at high frequencies is obtained while suppressing excessive overshoot and undershoot of the optical waveform.

[0024] [Second Example] Figure 5 is a circuit diagram showing the configuration of a DML driver according to a second embodiment of the present invention. The DML driver 10a of this embodiment is connected to capacitor C from the DML driver 10 of the first embodiment. f and resistor R f This is the version with the element removed.

[0025] There is variation in the characteristics of commercially available LDs, and some have narrow bandwidths. When using such a narrow-bandwidth LD1, the capacitor C from the first embodiment onwards... f and resistor R f A circuit configuration that removes the frequency peaking and strongly applies it can compensate the bandwidth of LD1 without degrading the group delay characteristics. Therefore, from the first embodiment, capacitor C f and resistor R f This embodiment, in which the [specific component] has been removed, can be an effective circuit configuration when the bandwidth of LD1 is narrow.

[0026] [Third embodiment] Figure 6 is a circuit diagram showing the configuration of a DML driver according to a third embodiment of the present invention. The DML driver 10b of this embodiment is connected to an NMOS transistor M 2n Omitting the NMOS transistor M 1n This is a configuration where the drain of the transistor is connected to the anode of LD1. In this case, the bias voltage V3 is not required. NMOS transistor M 1n If the voltage rating is high, it is possible to reduce the number of power supply terminals by not using a cascode configuration for the NMOS transistors. Furthermore, similar to the second embodiment, the DML driver 10b is connected to the capacitor C f and resistor R f You may remove it.

[0027] [Fourth embodiment] Figure 7 is a circuit diagram showing the configuration of a DML driver according to a fourth embodiment of the present invention. The DML driver 10c in this embodiment is a PMOS transistor M 1p And, NMOS transistor M 1n And, resistor R in ,R fand inductors L1, L2, and capacitor C f and PMOS transistors M, with their gates connected to bias voltages V5-1 to V5-x (the fourth bias voltage), and cascode-connected between the power supply voltage V1 and the sources of PMOS transistors M 1p from 1 to a plurality of PMOS transistors M 2p -1 to M 2p and NMOS transistors M, with their gates connected to bias voltages V3-1 to V3-y (the third bias voltage), and cascode-connected between the anode of LD1 and the drains of NMOS transistors M 1n from 1 to a plurality of NMOS transistors M 2n -1 to M 2n -y.

[0028] The magnitude relationship of each voltage is V1 > V5-x > ··· > V5-1 > V2 > V3-y > ··· > V3-1 > V4 > GND (ground). The cascode connection of PMOS transistors M 2p -1 to M 2p -x can be achieved by connecting the source to the power supply voltage V1 or the drain of the upper PMOS transistor, and connecting the drain to the source of the lower PMOS transistor. The cascode connection of NMOS transistors M 2n -1 to M 2n -y can be achieved by connecting the source to the drain of the lower NMOS transistor, and connecting the drain to the source of the upper NMOS transistor or the anode of LD1.

[0029] In this way, a multi-stage circuit configuration can be adopted for both PMOS and NMOS transistors to prevent breakdown voltage destruction. This is effective because at the most advanced nodes, the breakdown voltage per transistor decreases. Here, the PMOS transistors M 1p cascoded with PMOS transistors M 2p -1 to M 2p -x are x stages, and the NMOS transistors M 1n cascoded with NMOS transistors M 2n -1 to M 2n -y are y stages. Both x and y are set to be 1 or more.

[0030] Note that, similar to the second embodiment, the capacitor C f and the resistor R f may be removed. Also, in the second embodiment, the PMOS transistor M 1p to which the PMOS transistor M 2p -1 to M 2p -x are provided in x stages (x is an integer of 1 or more), and instead of the NMOS transistor M 2n , a plurality of stages of NMOS transistors M 1n -1 to M 2n -y may be connected (y ≧ 2).

[0031] [The Fifth Embodiment] FIG. 8 is a circuit diagram showing the configuration of a DML driver according to the fifth embodiment of the present invention. The DML driver 10d of this embodiment includes a PMOS transistor M 1p whose gate is connected to the bias voltage V2 and whose source is connected to the power supply voltage V1, an NMOS transistor M 1n whose gate is connected to the bias voltage V4 and whose source is connected to the ground, an NMOS transistor M 1n whose drain is connected to the anode of LD1 and whose source is connected to the drain of the NMOS transistor M 2n , an inductor L1 to which an RF input signal V in (modulation signal) is input at one end and the other end is connected to the gate of the NMOS transistor M 2n , an inductor L2 whose one end is connected to the drain of the PMOS transistor M 1p and the other end is connected to the anode of LD1, a resistor R 2n whose one end is connected to the bias voltage V3 and the other end is connected to the terminal on the opposite side of the two terminals of the inductor L1 from the gate of the NMOS transistor M in , a capacitor C 1p whose one end is connected to the source of the PMOS transistor M f , and a capacitor C f whose one end is connected to the other end of the capacitor C 1p ​​Resistor R connected to the drain f It is composed of the following.

[0032] In the first embodiment, an NMOS transistor M is connected via an inductor L1. 1n RF input signal V at the gate in The input was... In this example, an NMOS transistor M was connected via inductor L1. 2n RF input signal V at the gate in This is input. As a result, in this embodiment, the NMOS transistor M 1n By adjusting the bias voltage V4 applied to the gate of the PMOS transistor M, 1p From NMOS transistor M 2n M 1n The current flowing through it can be adjusted.

[0033] Furthermore, similar to the second embodiment, the DML driver 10d is connected to capacitor C f and resistor R f The PMOS transistor M may be removed. Also, similar to the fourth embodiment, the PMOS transistor M 1p A PMOS transistor M is connected in cascode. 2p -1~M 2p You may also set up x rows of -x (where x is an integer greater than or equal to 1).

[0034] Furthermore, in this embodiment, the NMOS transistor M 1n NMOS transistor M connected in cascode 2n Although this was set as one stage (y=1), as explained in the fourth embodiment, multiple stages of NMOS transistors M 2n -1~M 2n -y may be connected (y≧2). In this case, multiple stages of NMOS transistors M 2n -1~M 2n -y one of the NMOS transistors M 2n RF input signal V through inductor L1 to the gate of -k (where k is one of 1 to y) in Input the NMOS transistor M 2nThe bias voltage V3-k to be applied to -k, and the NMOS transistor M, one of the two terminals of inductor L1. 2n A resistor R is placed between the gate and the opposite terminal of -k. in Just connect it.

[0035] [Sixth embodiment] Figure 9 is a circuit diagram showing the configuration of a DML driver according to the sixth embodiment of the present invention. The DML driver 10e of this embodiment has an NMOS transistor M compared to the DML driver 10 of the first embodiment. 1n A resistor R is placed between the source and ground. s This is an insertion. As a result, in this embodiment, the linearity of the DML driver 10e can be improved, and the RF input signal V in This allows the DML driver 10e to operate more linearly.

[0036] In Figure 9, the resistor R is shown in the first embodiment. s Although this is applied, resistor R is used in the second to fifth embodiments. s The following may also be applied. Furthermore, similar to the second embodiment, the DML driver 10e is connected to the capacitor C f and resistor R f You may remove it.

[0037] [Seventh Embodiment] Figure 10 is a circuit diagram showing the configuration of a DML driver according to the seventh embodiment of the present invention. The DML driver 10f of this embodiment has a resistor R compared to the DML driver 10e of the sixth embodiment. s capacitor C in parallel with it s This is a connection made. As a result, in this embodiment, the high-frequency bandwidth of the transmitting front end, which consists of the DML driver 10f and LD1, can be improved compared to the sixth embodiment. In Figure 10, the resistor R is shown in the first embodiment. s and capacitor C s Although this is applied, resistor R is used in the second to fifth embodiments. s and capacitor C s You may apply this.

[0038] Furthermore, if there is no problem with the voltage rating of the NMOS transistor, in the first, second, fourth, sixth, and seventh embodiments, the NMOS transistor M 2n M 2n -1~M 2n -y is omitted, NMOS transistor M 1n The drain of the LD1 may be connected to the anode of the LD1. In this case, the bias voltages V3, V3-1 to V3-y become unnecessary.

[0039] Furthermore, in the fourth embodiment, if there is no problem with the breakdown voltage of the PMOS transistor, the PMOS transistor M 2p -1~M 2p -x is omitted, PMOS transistor M 1p The source and power supply voltage V1 may be connected. In this case, the bias voltages V5-1 to V5-x become unnecessary.

[0040] In the first to seventh embodiments, transistor M 1p M 2p -1~M 2p -x,M 1n M 2n M 2n -1~M 2n The example shows a MOS transistor used as -y, but transistor M 1p M 2p -1~M 2p -x is a PNP bipolar transistor, and transistor M 1n M 2n M 2n -1~M 2n An NPN bipolar transistor may be used as -y. When using a bipolar transistor, in the descriptions of the first to seventh embodiments, the gate should be replaced with the base, the drain with the collector, and the source with the emitter.

[0041] Some or all of the above examples may also be described as follows, but are not limited to the following:

[0042] (Note 1) The DML driver of the present invention comprises: a first transistor whose gate or base is connected to a first bias voltage and whose source or emitter is connected to a first power supply voltage; a second transistor whose drain or collector is connected to the anode of a laser diode and whose source or emitter is connected to a second power supply voltage; a first inductor to which an RF input signal is input and whose other end is connected to the gate or base of the second transistor; a second inductor to which one end is connected to the drain or collector of the first transistor and whose other end is connected to the anode of the laser diode; and a first resistor to which one end is connected to a second bias voltage and whose other end is connected to the terminal of the first inductor opposite to the gate or base of the second transistor.

[0043] (Note 2) The DML driver described in Note 1 further comprises a third transistor whose gate or base is connected to a third bias voltage and which is cascode-connected between the anode of the laser diode and the drain or collector of the second transistor.

[0044] (Note 3) The DML driver described in Note 1 further comprises a fourth transistor whose gate or base is connected to a fourth bias voltage and which is cascode-connected between the first power supply voltage and the source or emitter of the first transistor.

[0045] (Note 4) The DML driver of the present invention comprises: a first transistor whose gate or base is connected to a first bias voltage and whose source or emitter is connected to a first power supply voltage; a second transistor whose gate or base is connected to a second bias voltage and whose source or emitter is connected to a second power supply voltage; a third transistor cascode-connected between the anode of a laser diode and the drain or collector of the second transistor; a first inductor to which an RF input signal is input and whose other end is connected to the gate or base of the third transistor; a second inductor to which one end is connected to the drain or collector of the first transistor and whose other end is connected to the anode of the laser diode; and a first resistor to which one end is connected to a third bias voltage and whose other end is connected to the terminal of the first inductor opposite to the gate or base of the third transistor.

[0046] (Note 5) The DML driver described in Note 4 further comprises a fourth transistor whose gate or base is connected to a fourth bias voltage and which is cascode-connected between the first power supply voltage and the source or emitter of the first transistor.

[0047] (Note 6) The DML driver described in any one of Notes 1 to 5 further comprises a first capacitor, one end of which is connected to the source or emitter of the first transistor, and a second resistor, one end of which is connected to the other end of the first capacitor and the other end of which is connected to the drain or collector of the first transistor.

[0048] (Note 7) The DML driver described in any one of Notes 1 to 5 further comprises a second resistor inserted between the source or emitter of the second transistor and the second power supply voltage.

[0049] (Note 8) The DML driver described in Note 7 further comprises a first capacitor connected in parallel with the second resistor. [Industrial applicability]

[0050] This invention can be applied to techniques for directly modulating the optical output of an LD. [Explanation of Symbols]

[0051] 1...LD, 10,10a~10f...DML driver, M 1p M 2p -1~M 2p -x...PMOS transistor, M 1n M 2n M 2n -1~M 2n -y...NMOS transistor, L1,L2...inductor, R in ,R f ,R s …Resistance, C f ,C s ...capacitor.

Claims

1. A first transistor having its gate or base connected to a first bias voltage and its source or emitter connected to a first power supply voltage, A second transistor whose drain or collector is connected to the anode of a laser diode and whose source or emitter is connected to a second power supply voltage, A first inductor, to which an RF input signal is input at one end and which is connected to the gate or base of the second transistor at the other end, A second inductor, one end of which is connected to the drain or collector of the first transistor and the other end of which is connected to the anode of the laser diode, A DML driver characterized by comprising a first resistor, one end of which is connected to a second bias voltage, and the other end of which is connected to one of the two terminals of the first inductor, the terminal opposite to the gate or base of the second transistor.

2. In the DML driver according to claim 1, A DML driver further comprising a third transistor whose gate or base is connected to a third bias voltage and which is cascode-connected between the anode of the laser diode and the drain or collector of the second transistor.

3. In the DML driver according to claim 1, A DML driver further comprising a fourth transistor whose gate or base is connected to a fourth bias voltage and which is cascode-connected between the first power supply voltage and the source or emitter of the first transistor.

4. A first transistor having its gate or base connected to a first bias voltage and its source or emitter connected to a first power supply voltage, A second transistor whose gate or base is connected to a second bias voltage and whose source or emitter is connected to a second power supply voltage, A third transistor is cascode-connected between the anode of the laser diode and the drain or collector of the second transistor, A first inductor has an RF input signal at one end and the other end is connected to the gate or base of the third transistor, A second inductor, one end of which is connected to the drain or collector of the first transistor and the other end of which is connected to the anode of the laser diode, A DML driver characterized by comprising a first resistor, one end of which is connected to a third bias voltage, and the other end of which is connected to one of the two terminals of the first inductor, the terminal opposite to the gate or base of the third transistor.

5. In the DML driver according to claim 4, A DML driver further comprising a fourth transistor whose gate or base is connected to a fourth bias voltage and which is cascode-connected between the first power supply voltage and the source or emitter of the first transistor.

6. In the DML driver according to any one of claims 1 to 5, A first capacitor, one end of which is connected to the source or emitter of the first transistor, A DML driver further comprising a second resistor, one end of which is connected to the other end of the first capacitor and the other end of which is connected to the drain or collector of the first transistor.

7. In the DML driver according to any one of claims 1 to 5, A DML driver further comprising a second resistor inserted between the source or emitter of the second transistor and the second power supply voltage.

8. In the DML driver according to claim 7, A DML driver further comprising a first capacitor connected in parallel with the second resistor.

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