Semiconductor equipment

Abstract

The present invention prevents decreases in heat dissipation.　A semiconductor device (1) includes: an insulating circuit board (20) having a lower surface (23a); a heat dissipation base plate (40) including a front surface (40a), and having a placement region (40b) where the lower surface (23a) of the insulating circuit board (20) is placed on the front surface (40a) via a solder (27); a plating film (41) which is formed on the front surface (40a) of the heat dissipation base plate (40) except for at a solder region where the solder (27) is spread over the placement region (40b) of the front surface (40a); and an alloy layer which is included between the solder (27) and the placement region (40b) of the heat dissipation base plate (40), and contains solder components contained in the solder (27). In particular, in the semiconductor device (1), the plating film (41) is formed on the entire surface of the heat dissipation base plate (40) excluding an open region (41a) that surrounds the outer perimeter of the periphery of the placement region (40b) where the insulating circuit board (20) is placed via the solder (27).

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] A semiconductor device includes a metal base and an insulating substrate provided via solder on the metal base (see, for example, Patent Document 1). As another example, it includes a collector lead frame and a semiconductor element provided via solder on the collector lead frame (see, for example, Patent Document 2). Further, a concave depression is formed on the upper surface of the base material, a plating layer is formed on the upper surface including the depression, and the lower surface of the base material and the upper surface on which the plating layer is formed are polished. Thereby, the plating layer filled in the depression of the base material functions as a through electrode (see, for example, Patent Document 3). Also, a resist pattern formed on the base substrate can be used as a plating prevention film, and a copper plating film can be formed in the pattern formation region by electroless reduction plating (see, for example, Patent Document 4). Further, the plating film can be peeled off by irradiating with a laser (see, for example, Patent Document 5). <000​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​The present invention aims to provide a semiconductor device in which a decrease in heat dissipation performance is prevented. [Means for solving the problem]

[0005] According to one aspect of the present invention, the present invention includes a substrate including a lower surface and a placement region including a main surface on which the lower surface of the substrate is placed via solder. and contains copper A heat dissipation base plate, and the main surface of the heat dissipation base plate, formed on the arrangement area of ​​the main surface, excluding the solder area where the solder has spread. It is composed mainly of nickel. A first plating film, an alloy layer contained between the solder and the arrangement region of the heat dissipation base plate, and containing the solder components contained in the solder, The first plating film formed on the main surface has a thickness of less than 0.2 μm. We provide semiconductor devices.

[0006] Furthermore, the alloy layer may further contain the first metallic material contained in the heat dissipation base plate, along with the solder component. Furthermore, the first metal material may contain copper.

[0007] Ma Furthermore, the outer perimeter of the arrangement area may be located inside the outer perimeter of the substrate in a plan view. Furthermore, the first plating film may be formed on the main surface of the heat dissipation base plate, excluding the opening region that surrounds the entire periphery of the solder area.

[0008] Furthermore, the arrangement area may be recessed in a concave shape relative to the main surface excluding the arrangement area. Furthermore, the solder may include a fillet portion that extends outward from the lower surface of the substrate in a plan view. Furthermore, the outer edge of the fillet portion of the solder may be located outside the arrangement area in a plan view.

[0009] The substrate comprises an insulating plate, a conductive pattern formed on the front surface of the insulating plate, and the insulating plate on the back The device comprises a metal plate formed on a surface, including the lower surface, wherein the second plating film may be formed on the side surface of the metal plate, except for the lower surface, surrounding the entire circumference of the outer edge of the lower surface.

[0010] Further, the metal plate may be composed mainly of copper. Further, the second plating film may be composed mainly of nickel. Further, the heat dissipation base plate of A resist material may be formed surrounding the entire circumference of the opening edge of the first plating film formed on the mounting surface.

[0011] Further, the alloy layer may further contain a second metal material constituting the first plating film together with the solder component and the first metal material. Further, the second metal material may contain nickel.

[0012] Further, the first plating film is further formed on the surface of the heat dissipation base plate excluding the main surface, and the thickness of the first plating film formed on the main surface may be thinner than the thickness of the first plating film formed on the surface excluding the main surface. 。

[0013] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub - combinations of these feature groups can also be inventions.

Effects of the Invention

[0014] According to the disclosed technology, a decrease in heat dissipation can be prevented and a decrease in reliability can be suppressed. The above and other objects, features, and advantages of the present invention will become apparent from the following description in connection with the accompanying drawings that represent preferred embodiments of the present invention as examples.

Brief Description of the Drawings

[0015] [Figure 1] It is a cross - sectional view of a semiconductor device of the first embodiment. [Figure 2] [[ID=,44]]It is a plan view of a main part of a semiconductor device of the first embodiment (without a sealing member). [Figure 3] It is a flowchart showing a manufacturing method of a semiconductor device of the first embodiment. [Figure 4] It is a plan view showing a manufacturing process of a heat radiation unit (preparation of a heat radiation base plate) included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] It is a plan view showing a manufacturing process of a heat radiation unit (plating process) included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] It is a plan view showing a manufacturing process of a heat radiation unit (grinding process) included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] It is a cross-sectional view showing a manufacturing process of a heat radiation unit (grinding process) included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] It is a plan view showing a manufacturing process of a heat radiation unit (mask setting) included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] It is a plan view showing a manufacturing process of a heat radiation unit (plating process) included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] It is a plan view showing a manufacturing process of a heat radiation unit (mask removal) included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] It is a cross-sectional view showing a manufacturing process of a heat radiation unit (mask removal) included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] It is a cross-sectional view showing an arrangement process included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] It is a schematic cross-sectional view showing an atomic arrangement in an arrangement process included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] It is a cross-sectional view showing a bonding process included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] It is a schematic cross-sectional view showing an atomic arrangement in a bonding process included in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] It is a cross-sectional view showing an arrangement process included in a method for manufacturing a semiconductor device according to a reference example. [Figure 17]This is a schematic cross-sectional diagram showing the arrangement of atoms in the arrangement process included in the manufacturing method of a semiconductor device as an example. [Figure 18] This is a schematic cross-sectional diagram showing the arrangement of atoms during the bonding process (during heating) included in the manufacturing method of the semiconductor device in the reference example. [Figure 19] This is a second schematic cross-sectional diagram showing the arrangement of atoms during the bonding process (during heating) included in the manufacturing method of the semiconductor device in the reference example. [Figure 20] This is a schematic diagram of the third cross-section showing the arrangement of atoms during the bonding process (during heating) included in the manufacturing method of the semiconductor device in the reference example. [Figure 21] This is a cross-sectional view showing the bonding process (after bonding) included in the manufacturing method of the semiconductor device in the reference example. [Figure 22] This is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 23] This is a rear view perspective of an insulating circuit board included in the semiconductor device of the second embodiment. [Figure 24] This is a plan view of the main part of the semiconductor device of the third embodiment (without sealing member). [Figure 25] This is a cross-sectional view of a semiconductor device according to the fourth embodiment. [Figure 26] This is a flowchart showing the manufacturing method of a semiconductor device according to the fourth embodiment. [Figure 27] This is a cross-sectional view showing the manufacturing process (plating treatment) of a heat dissipation unit included in the manufacturing method of a semiconductor device according to the fourth embodiment. [Figure 28] This is a cross-sectional view showing the manufacturing process (thinning treatment) of a heat dissipation unit included in the manufacturing method of a semiconductor device according to the fourth embodiment. [Figure 29] This is a cross-sectional view showing the arrangement step included in the manufacturing method of a semiconductor device according to the fourth embodiment. [Figure 30] This is a schematic cross-sectional view showing the arrangement of atoms in the arrangement step included in the manufacturing method of a semiconductor device according to the fourth embodiment. [Figure 31] This is a cross-sectional view showing a bonding process included in the manufacturing method of a semiconductor device according to the fourth embodiment. [Figure 32]This is a schematic cross-sectional diagram showing the arrangement of atoms in the bonding process included in the manufacturing method of a semiconductor device according to the fourth embodiment. [Modes for carrying out the invention]

[0016] The embodiments will be described below with reference to the drawings. In the following description, "front surface" and "top surface" refer to the XY plane facing upwards (+Z direction) in the semiconductor device 1 of Figure 1. Similarly, "up" refers to the upward direction (+Z direction) in the semiconductor device 1 of Figure 1. "Back surface" and "bottom surface" refer to the XY plane facing downwards (-Z direction) in the semiconductor device 1 of Figure 1. Similarly, "down" refers to the downward direction (-Z direction) in the semiconductor device 1 of Figure 1. The same directionality will be used in other drawings as needed. "High position" and "upper position" refer to the upper position (+Z direction) in the semiconductor device 1 of Figure 1. Similarly, "low position" and "lower position" refer to the upper position (+Z direction) in Figure 1. 1 In semiconductor device 1, this refers to the position on the lower side (-Z direction). "Front surface," "top surface," "upper" and "back surface," "bottom surface," "down" and "side" are merely convenient expressions to specify the relative positional relationship and do not limit the technical concept of the present invention. For example, "upper" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "upper" and "down" are not limited to the direction of gravity. Also, in the following explanation, "main component" refers to a case where it contains 80 vol% or more (if filler is included, it is the percentage excluding the filler). Also, "approximately the same" means that it is within a range of ±10%. Also, "perpendicular," "orthogonal," and "parallel" mean that it is within a range of ±10°.

[0017] [First Embodiment] The semiconductor device will be described using Figures 1 and 2. Figure 1 is a cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 is a plan view of the main part of the semiconductor device according to the first embodiment (without the sealing member). Note that Figure 2 shows an enlarged view of the semiconductor chip 25, excluding the sealing member 50 and wire 51 from the semiconductor device 1 of Figure 1. Therefore, since Figure 2 shows an enlarged view of the main part inside case 3 of Figure 1, the description of case 3 is omitted. Figure 1 is a cross-sectional view along the dashed line YY in Figure 2, including case 3.

[0018] As shown in Figure 1, the semiconductor device 1 includes a semiconductor unit 2, a heat dissipation unit 4 on which the semiconductor unit 2 is positioned, and a case 3 provided on the outer edge of the heat dissipation unit 4 for housing the semiconductor unit 2. The inside of the case 3 of the semiconductor device 1 is sealed by a sealing member 50.

[0019] The sealing member 50 may be, for example, a silicone gel. Alternatively, the sealing member 50 may be a thermosetting resin mixed with a filler. In this case, the thermosetting resin may be, for example, an epoxy resin, a phenolic resin, a maleimide resin, or a polyester resin. The filler is a ceramic that is insulating and has high thermal conductivity. Examples of such fillers include silicon oxide, aluminum oxide, boron nitride, or aluminum nitride. The filler content may be 10% or more and 70% or less by volume relative to the total amount of the sealing member 50.

[0020] The semiconductor unit 2 includes an insulating circuit board 20 and a semiconductor chip 25 disposed on the front surface of the insulating circuit board 20 via solder 26. The insulating circuit board 20 includes an insulating plate 21, a plurality of conductive patterns 22 provided on the front surface of the insulating plate 21, and a metal plate 23 provided on the back surface of the insulating plate 21. The insulating plate 21 and the metal plate 23 are rectangular in plan view. The corners of the insulating plate 21 and the metal plate 23 may be rounded (R-chamfered) or chamfered (C-chamfered). The size of the metal plate 23 is smaller than the size of the insulating plate 21 in plan view and is formed inside the insulating plate 21.

[0021] The insulating plate 21 may be, for example, a ceramic substrate. The ceramic substrate is made of ceramics with good thermal conductivity. The ceramics are made of materials mainly composed of aluminum oxide, aluminum nitride, and silicon nitride. Furthermore, such an insulating plate 21 has a rectangular shape when viewed from above.

[0022] A semiconductor chip 25 is placed on the upper surface 22a of the conductive pattern 22. The conductive pattern 22 is formed over the entire surface of the insulating plate 21, excluding the edges. Preferably, in a plan view, the end of the conductive pattern 22 facing the outer periphery of the insulating plate 21 overlaps with the outer periphery end of the metal plate 23. As a result, the insulating circuit board 20 maintains a stress balance between the conductive pattern 22 and the metal plate 23 on the back surface of the insulating plate 21. As a result, Excessive warping, cracking, and other damage to the insulating plate 21 are suppressed. The conductive pattern 22 is made of a material with excellent conductivity. Such materials include, for example, copper, aluminum, or an alloy containing at least one of these. It is also possible to plate the conductive pattern 22 with a material with excellent corrosion resistance. Such materials include, for example, nickel, nickel-phosphorus alloy, and nickel-boron alloy. The thickness of the plating film is 10 μm or less. The conductive pattern 22 on the insulating plate 21 is obtained by forming a metal plate on the front surface of the insulating plate 21 and performing an etching or other treatment on this metal plate. Alternatively, the conductive pattern 22 cut out from a metal plate in advance may be joined to the front surface of the insulating plate 21. Note that the conductive pattern 22 included in the semiconductor device 1 of this embodiment is merely an example. The number, shape, size, etc. of the conductive patterns may be appropriately selected as needed. Note that the upper surface 22a of the conductive pattern 22 is also the upper surface 22a of the insulating circuit board 20.

[0023] The metal plate 23 has its lower surface 23a positioned on the heat dissipation unit 4. The metal plate 23 is made of a metal with excellent thermal conductivity. Such materials include, for example, copper, aluminum, or an alloy containing at least one of these. In this case, copper is included. In addition, the surface of the metal plate 23 may be plated to improve corrosion resistance. In this case, the plating material contains nickel. Such plating materials include, for example, nickel, nickel-phosphorus alloy, and nickel-boron alloy. The thickness of the plating film is 3 μm or more and 7 μm or less. The lower surface 23a of the metal plate 23 is also the lower surface 23a of the insulating circuit board 20. Another form of the plating film formed on the metal plate 23 will be described in the second embodiment.

[0024] As the insulating circuit board 20 having such a configuration, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used. Alternatively, a resin insulating substrate may be used. The insulating circuit board 20 dissipates heat generated by the semiconductor chip 25, which will be described later, by conducting it to the back side of the insulating circuit board 20 via the conductive pattern 22, insulating plate 21, and metal plate 23.

[0025] The semiconductor chip 25 includes a switching element, for example, which is mainly composed of silicon. The switching element is, for example, an RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). An RC-IGBT is a semiconductor element in which an IGBT and an FWD (Free Wheeling Diode) are configured in antiparallel within a single chip.

[0026] The semiconductor chip 25 has a collector electrode as an input electrode on its back surface, and a gate electrode as a control electrode and an emitter electrode as an output electrode on its front surface. The control electrode may be located at the center of one side of the front surface of the semiconductor chip 25. Alternatively, the control electrode does not necessarily have to be located at the center of one side of the front surface of the semiconductor chip 25, and may be offset from the center in the ±X direction.

[0027] Another switching element may be a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) composed mainly of silicon carbide. In the power MOSFET, the body diode may function as the FWD. Such a semiconductor chip 25 has, for example, an input electrode (drain electrode) which is the main electrode on its back surface, and an output electrode (source electrode) and a control electrode (gate electrode), which are the main electrodes, on its front surface.

[0028] Alternatively, instead of semiconductor chip 25, a semiconductor chip mainly composed of silicon and containing a pair of switching elements and diode elements may be used. Examples of switching elements include power MOSFETs and IGBTs. A semiconductor chip containing switching elements may have, for example, an input electrode (drain electrode in the case of a power MOSFET, collector electrode in the case of an IGBT) as the main electrode on its back surface, and a gate electrode as the control electrode and an output electrode as the main electrode (source electrode in the case of a power MOSFET, emitter electrode in the case of an IGBT) on its front surface. Diode elements may include, for example, SBDs (Schottky Barrier Diodes) and PiN (P-intrinsic-N) diodes used as FWDs. A semiconductor chip containing diode elements may have an output electrode (cathode electrode) as the main electrode on its back surface and an input electrode (anode electrode) as the main electrode on its front surface.

[0029] The semiconductor chip 25 is joined to a conductive pattern 22 on its back side by solder 26. The solder 26 is composed of solder components. The solder components are substances that make up the solder and include lead-free solder mainly composed of a predetermined alloy. The predetermined alloy contains tin. Such alloys are, for example, at least one of the following: a tin-silver alloy, a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, a tin-silver-indium-bismuth alloy, or a tin-antimony alloy. Furthermore, such solder components may contain additives. Examples of additives include nickel, germanium, cobalt, or silicon. Therefore, the solder components may include, for example, tin along with at least one of silver, zinc, copper, bismuth, indium, and antimony. Furthermore, the solder components may include, for example, at least one of nickel, germanium, cobalt, and silicon. The solder components in subsequent embodiments are the same as in the first embodiment. Also, a sintered body may be used instead of solder 26. When joining parts using a sintered body, the sintered material can be, for example, powders of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum. Note that here, solder 26 is composed of the same solder as solder 27, which will be described later.

[0030] Case 3 includes a frame portion 31 and an external connection terminal 32 embedded in the frame portion 31. The frame portion 31 has a rectangular shape in plan view and forms a frame shape surrounding the storage area 31f. The storage area 31f extends from the upper opening 31a on the front surface of Case 3 to the lower opening 31b on the back surface. to This is the area that is opened. The area of ​​the upper opening 31a may be larger than the area of ​​the lower opening 31b. A heat dissipation unit 4, which will be described later, is attached to the step on the back of the frame 31 to close the storage area 31f.

[0031] Furthermore, the upper inner wall 31c of the frame portion 31 surrounds the upper part of the storage area 31f on all four sides, forming an upper opening 31a leading to the storage area 31f. The lower inner wall 31e of the frame portion 31 surrounds the lower part of the storage area 31f on all four sides, forming a lower opening 31b leading to the storage area 31f. In a plan view, the frame portion 31 has steps 31d between the upper inner wall 31c and the lower inner wall 31e on the shorter side. The upper inner wall 31c is positioned approximately perpendicular to the front surface of the frame portion 31. The steps 31d are positioned approximately perpendicular to the upper inner wall 31c. The lower inner wall 31e is positioned approximately perpendicular to the steps 31d. From the above, in a plan view, the lower inner wall 31e on the shorter side protrudes from the upper inner wall 31c towards the storage area 31f by the amount of the steps 31d.

[0032] Such a frame portion 31 is formed by injection molding using a thermoplastic resin containing a filler. Examples of such resins include polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, or polyamide (PA) resin. The filler consists of, for example, glass fibers, glass beads, calcium carbide, talc, magnesium oxide, or aluminum hydroxide.

[0033] The external connection terminal 32 is flat and, in side view, forms an L-shape. The external connection terminal 32 is integrally molded with the frame portion 31. The external connection terminal 32 includes an internal wiring portion 32a and an external wiring portion 32b provided substantially perpendicular to the internal wiring portion 32a. The internal wiring portion 32a is included in the frame portion 31 parallel to its front surface. One end of the internal wiring portion 32a extends substantially perpendicularly from the upper inner wall 31c toward the storage area 31f, with the front surface of this end exposed from the step 31d. The external wiring portion 32b is included in the frame portion 31 substantially parallel to the upper inner wall 31c. The other end of the external wiring portion 32b extends substantially perpendicularly to the front surface of the frame portion 31. One end of the external wiring portion 32b is integrally connected to the other end of the internal wiring portion 32a within the frame portion 31.

[0034] Such external connection terminals 32 are made of a material with excellent conductivity. Such materials include, for example, copper, aluminum, or an alloy containing at least one of these. The external connection terminals 32 have a uniform thickness throughout. It is also possible to plate the external connection terminals 32 with a material that has excellent corrosion resistance. Such materials include, for example, aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, silver, platinum, palladium, or an alloy containing at least one of these.

[0035] In this case 3, the outer edge of the front surface of the heat dissipation unit 4, to which the semiconductor unit 2 is attached, is bonded to the back surface of the frame portion 31 on the lower opening 31b side using an adhesive (not shown). As a result, the semiconductor unit 2 is housed in the storage area 31f of the frame portion 31. Although not shown, a lid (not shown) may be bonded to the front surface of the frame portion 31 on the upper opening 31a side using an adhesive. For example, a thermosetting resin adhesive or an elastomer adhesive can be used. Thermosetting resin adhesives mainly consist of epoxy resin and phenolic resin, for example. Elastomer adhesives mainly consist of silicone rubber and chloroprene rubber, for example.

[0036] The junction region exposed from the step 31d of the internal wiring section 32a is electrically connected to the conductive pattern 22 of the insulating circuit board 20 and the semiconductor chip 25 by a wiring member. The wiring member is, for example, the wire 51 shown in Figure 1. The wire 51 is made of a material with excellent conductivity. This material is, for example, gold, silver, copper, aluminum, or an alloy containing at least one of these. Note that such a wiring member is not limited to a wire 51; a lead frame may also be used.

[0037] The heat dissipation unit 4 includes a heat dissipation base plate 40 and a plating film 41. The heat dissipation base plate 40 is mainly composed of copper. The heat dissipation base plate 40 includes a placement area 40b on its front surface 40a where the lower surface 23a of the insulating circuit board 20 is placed via solder 27. The placement area 40b is the area where the metal plate 23 of the insulating circuit board 20 is placed on the heat dissipation base plate 40. In plan view, the placement area 40b is rectangular, similar to the insulating circuit board 20. The size of the placement area 40b may be less than or equal to the size of the insulating plate 21 and greater than or equal to the size of the metal plate 23, in plan view. Here, the case where the size of the placement area 40b is the same as the size of the metal plate 23 is shown. The thickness of the heat dissipation base plate 40 depends on the size of the semiconductor device 1, but may be, for example, 2.5 mm or more and 3.5 mm or less. The plating film 41 is formed on the front surface 40a of the heat dissipation base plate 40, excluding the opening region 41a that surrounds the entire outer periphery of the placement region 40b. The thickness of the portion of the plating film 41 excluding the opening region 41a may be, for example, a commonly used thickness, such as 1 μm or more and 10 μm or less.

[0038] The arrangement area 40b may be rectangular in shape in a plan view, similar to the insulating circuit board 20. metal plate 23 It is larger in size than the other. The placement area 40b only needs to include the insulating circuit board 20 in a plan view and does not necessarily have to be rectangular. Also, the corners of the placement area 40b do not necessarily have to be right angles in a plan view and may form rounded surfaces.

[0039] The placement area 40b may be recessed in the -Z direction relative to the front surface 40a of the heat dissipation base plate 40 excluding the placement area 40b. Here, the placement area 40b is smoothly connected to the front surface 40a of the heat dissipation base plate 40 excluding the placement area 40b. In this case, the depth of the deepest part of the placement area 40b may be deeper than the thickness of the plating film 24, which will be described later. The placement area 40b may be on the same plane as the front surface 40a of the heat dissipation base plate 40 excluding the placement area 40b.

[0040] The solder 27 is provided in the placement area 40b and joins the insulating circuit board 20 and the front surface 40a of the heat dissipation base plate 40, as shown in Figures 1 and 2. The thickness of the solder 27 is 100 μm or more and 500 μm or less. In a plan view, the solder 27 extends to the outside of the lower surface 23a of the insulating circuit board 20 (metal plate 23) and includes a fillet portion 27b provided outside the placement area 40b.

[0041] The fillet portion 27b (outer edge of the solder 27) may extend outward from the outer edge of the insulating circuit board 20 (insulating plate 21) in a plan view. However, it is preferable that the fillet portion 27b be located inside the outer edge of the insulating plate 21. In Figure 2, the outer edge of the solder 27 is shown extending outward from the outer edge of the insulating circuit board 20 (insulating plate 21) simply to clarify the position of the solder 27 relative to the insulating circuit board 20 and the plating film 41. The area on the placement area 40b of the front surface 40a of the heat dissipation base plate 40 in this way is called the solder area (the reference numeral is omitted here; see the solder area 41b in Figure 25). The size of the solder area may be wider than the size of the placement area 40b in a plan view, and may include the placement area 40b.

[0042] The opening region 41a of the plating film 41 surrounding the placement region 40b includes a region where the plating film 41 is not provided, in order to prevent the solder 27 from spreading beyond the placement region 40b. The opening region 41a may be rectangular, similar to the placement region 40b, and is wider than the placement region 40b. It is desirable that this opening region 41a is at least 1 mm away from the placement region 40b. The opening region 41a may coincide with the solder region or extend beyond the solder region.

[0043] The plating film 41 is formed by plating on the surface of the heat dissipation base plate 40, excluding the placement area 40b. The plating film 41 improves the corrosion resistance of the heat dissipation base plate 40. The plating material of the plating film 41 contains nickel. Examples of such plating materials include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0044] Alternatively, a cooling unit (not shown) may be attached to the back surface of the case 3, which includes the heat dissipation unit 4, via a thermally conductive member. The thermally conductive member is a thermal interface material (TIM). Examples of TIMs include thermally conductive grease, elastomer sheets, RTV (Room Temperature Vulcanization) rubber, gel, phase change material, solder, and silver solder. Includes, etc. A general term for various materials That is This improves the heat dissipation of the semiconductor device 1. In this case, the cooling unit is made of, for example, a metal with excellent thermal conductivity. The metal is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these. The cooling unit is also, for example, a heat sink with one or more fins or a water-cooled cooling device.

[0045] Next, the manufacturing method of the semiconductor device 1 will be explained using Figure 3. Figure 3 is a flowchart of the manufacturing method of the semiconductor device according to the first embodiment. Note that the flowchart showing the manufacturing method in Figure 3 is just one example. The semiconductor device 1 includes a heat dissipation unit 4 to which the semiconductor unit 2 is bonded, and other than the flowchart in Figure 3, the semiconductor device 1 can also be manufactured in any other way. The method But it can be manufactured.

[0046] First, a preparation process is carried out to prepare the components of the semiconductor device 1 (step S1 in Figure 3). The components prepared at this stage include, for example, an insulating circuit board 20, a semiconductor chip 25, a case 3, and a heat dissipation unit 4. Other components necessary for the semiconductor device 1 are also prepared. Furthermore, manufacturing equipment used in the production of the semiconductor device 1 may also be prepared.

[0047] Two methods of manufacturing the heat dissipation unit 4 are possible. First, the manufacturing method of the heat dissipation unit 4 included in the semiconductor device 1 shown in Figure 1 (steps S10, S11a, S12a, S14 in Figure 3) will be explained using Figures 4 to 7. Figure 4 is a plan view showing the manufacturing process of the heat dissipation unit (preparation of the heat dissipation base plate) included in the manufacturing method of the semiconductor device of the first embodiment. Figure 5 is a plan view showing the manufacturing process of the heat dissipation unit (plating process) included in the manufacturing method of the semiconductor device of the first embodiment. Figure 6 is a plan view showing the manufacturing process of the heat dissipation unit (grinding process) included in the manufacturing method of the semiconductor device of the first embodiment, and Figure 7 is a cross-sectional view showing the manufacturing process of the heat dissipation unit (grinding process) included in the manufacturing method of the semiconductor device of the first embodiment. Note that Figure 7 is a cross-sectional view along the dashed line XX in Figure 6. Also, Figure 1 shows the heat dissipation base plate 40 (heat dissipation unit 4) of Figures 4 to 7 as viewed in the +Y direction.

[0048] First, a heat dissipation base plate 40 is prepared (step S10 in Figure 3). For example, a metal plate is sheared to obtain a heat dissipation base plate 40 of a size corresponding to the heat dissipation unit 4 of the semiconductor device 1, as shown in Figure 4. Shearing can be done, for example, by pressing machine A cutting tool may be used. Such a heat dissipation base plate 40 is a flat plate that forms a rectangular shape in plan view. The front surface 40a of the heat dissipation base plate 40 is substantially smooth. Also, placement areas 40b are set on the front surface 40a of the heat dissipation base plate 40. The placement areas 40b are the placement areas where the metal plates 23 of the insulating circuit boards 20 are placed. The placement areas 40b are set according to the number of insulating circuit boards 20 included in the semiconductor device 1. Here, two placement areas 40b are set side by side on the front surface 40a of the heat dissipation base plate 40.

[0049] Next, the heat dissipation base plate 40 is subjected to plating (step S11a in Figure 3). A plating film 41 is formed on the entire surface of the heat dissipation base plate 40, including the front surface 40a, as shown in Figure 5. The plating process may be a generally known method, such as electroplating or electroless plating.

[0050] Next, the heat dissipation base plate 40 on which the plating film 41 is formed is subjected to grinding (step S12a in Figure 3). The plating film 41 corresponding to the opening region 41a including the placement region 40b of the heat dissipation base plate 40 on which the plating film 41 is formed is ground and removed. As shown in Figure 6, the plating film 41 is removed to form an opening region 41a that is wider than the placement region 40b. Note that the plating film 41 is formed on the heat dissipation base plate 40 in areas other than the opening region 41a. When the plating film 41 corresponding to the opening region 41a including the placement region 40b of the heat dissipation base plate 40 is removed by grinding, the plating film 41 on the placement region 40b is removed, and the front surface 40a of the heat dissipation base plate 40 in the placement region 40b is also ground. Therefore, as shown in Figure 7, the placement region 40b is recessed compared to the front surface 40a excluding the placement region 40b. Furthermore, if the front surface 40a of the heat dissipation base plate 40 is ground, the bottom surface of the recess and the front surface 40a are connected by a smooth surface. Thus, the heat dissipation unit 4 shown in Figure 1 can be prepared (step S14 in Figure 3).

[0051] Furthermore, the heat dissipation unit 4 can also be manufactured by the following manufacturing method. The manufacturing method in this case (steps S10, S11b, S12b, S13b, S14 in Figure 3) will be explained with reference to Figures 8 to 11, along with Figure 4. Figure 8 is a plan view showing the manufacturing process (mask setting) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the first embodiment. Figure 9 is a plan view showing the manufacturing process (plating treatment) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the first embodiment. Figure 10 is a plan view showing the manufacturing process (mask removal) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the first embodiment, and Figure 11 is a cross-sectional view showing the manufacturing process (mask removal) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the first embodiment. Note that Figure 11 is a cross-sectional view taken along the dashed line XX in Figure 10.

[0052] Here again, first, the heat dissipation base plate 40 is prepared (step S10 in Figure 3). Step S10 is as previously described. Next, the mask is set on the heat dissipation base plate 40 (step S11b in Figure 3). As shown in Figure 8, the mask 42 is set in the placement area 40b on the front surface 40a of the heat dissipation base plate 40. The mask 42 used has the same shape as the placement area 40b in plan view, but is slightly larger in size than the placement area 40b.

[0053] Next, the heat dissipation base plate 40 is plated (step S12b in Figure 3). The entire surface of the heat dissipation base plate 40, including the front surface 40a, is plated in the same manner as in step S11a to form a plating film 41. On the front surface 40a of the heat dissipation base plate 40 that has been plated, the plating film 41 is formed in the area excluding the mask 42.

[0054] Next, the mask 42 is removed (step S13b in Figure 3). After step S12b, the mask 42 is removed. As shown in Figure 10, the plating film 41 is formed on the front surface 40a of the heat dissipation base plate 40, excluding the opening region 41a which includes the placement region 40b. Also, as shown in Figure 11, the placement region 40b on the front surface 40a of the heat dissipation base plate 40 is not removed, and the placement region 40b is coplanar with the front surface 40a. With the above steps, the heat dissipation unit 4 shown in Figure 1 can be prepared (step S14 in Figure 3).

[0055] Next, a placement process is performed in which the heat dissipation unit 4, the insulating circuit board 20, and the semiconductor chip 25 are placed in order (step S2 in Figure 3). The placement process will be explained using Figures 12 and 13. Figure 12 is a cross-sectional view showing the placement process included in the manufacturing method of the semiconductor device of the first embodiment. Figure 13 is a schematic cross-sectional view showing the arrangement of atoms in the placement process included in the manufacturing method of the semiconductor device of the first embodiment. Note that Figure 13 schematically shows the arrangement of atoms in the area B enclosed by the dashed line in Figure 12. Also, Figure 13 only schematically shows the arrangement of atoms, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer. Furthermore, Figure 13 only shows tin, which is a constituent element of the solder component. The solder component may contain elements other than tin, and the description of those elements is omitted. Also, not only in Figure 13, but in subsequent schematic cross-sectional views showing the arrangement of atoms, only tin, which is a constituent element of the solder component, is shown. These cross-sectional schematic diagrams also show that the solder components may include elements other than tin, and the names of those elements are omitted.

[0056] The insulating circuit boards 20 are placed in the placement area 40b within the opening area 41a of the plating film 41 formed on the heat dissipation unit 4, via a solder plate 27a. The solder plate 27a is made of solder 27 that has hardened into a plate shape. The solder plate 27a is placed at the bottom of the recess in the placement area 40b of the heat dissipation unit 4. In plan view, the solder plate 27a may be the same size as, for example, the lower surface 23a of the metal plate 23 of the insulating circuit board 20.

[0057] A semiconductor chip 25 is placed on the upper surface 22a of the conductive pattern 22 of the insulating circuit board 20 via a solder plate 26a. The solder plate 26a is made of solder 26 that has hardened into a plate shape. In plan view, the solder plate 26a may be the same size as, for example, the semiconductor chip 25.

[0058] Through this placement process, as shown in Figure 12, the insulating circuit board 20 is placed in the placement area 40b of the heat dissipation unit 4 via a solder board 27a, and the semiconductor chip 25 is placed on the conductive pattern 22 of the insulating circuit board 20 via a solder board 26a.

[0059] Furthermore, area B in Figure 12 is near the boundary between the heat dissipation base plate 40 and the solder plate 27a in the heat dissipation unit 4. At this boundary in area B, as shown in Figure 13, the copper atoms contained in the heat dissipation base plate 40 and the tin atoms contained in the solder plate 27a are regularly arranged on either side of the boundary L. This boundary L corresponds to the boundary between the solder plate 27a and the placement area 40b of the heat dissipation base plate 40 when the solder plate 27a is placed in the placement area 40b of the heat dissipation unit 4 (heat dissipation base plate 40). Note that since the solder plate 27a is not bonded when it is placed on the heat dissipation base plate 40, air layers contained in the irregularities of the solder plate 27a exist between the solder plate 27a and the metal plate 23, and between the solder plate 27a and the heat dissipation base plate 40, but this is not described here.

[0060] Next, a bonding process is performed between the heat dissipation unit 4 and the insulating circuit board 20, and between the insulating circuit board 20 and the semiconductor chip 25 (step S3 in Figure 3). The bonding process will be explained using Figures 14 and 15. Figure 14 is a cross-sectional view showing the bonding process included in the manufacturing method of the semiconductor device of the first embodiment. Figure 15 is a schematic cross-sectional view showing the arrangement of atoms in the bonding process included in the manufacturing method of the semiconductor device of the first embodiment. Note that Figure 15 schematically shows the arrangement of atoms in the area B enclosed by the dashed line in Figure 14. Also, Figure 15 only schematically shows the arrangement of atoms, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0061] In step S2, the solder plate 27a between the heat dissipation unit 4 and the insulating circuit board 20, and the solder plate 26a between the conductive pattern 22 of the insulating circuit board 20 and the semiconductor chip 25 are heated. Solder plates 26a and 27a melt and transition to solder 26 and 27, respectively.

[0062] When heated in this manner, as shown in Figure 15, copper atoms from the heat dissipation base plate 40 move and diffuse beyond the boundary L into the tin atoms of the solder 27. Conversely, the tin atoms of the solder 27 diffuse beyond the boundary L into the copper atoms of the heat dissipation base plate 40 due to the diffusion of copper atoms. Thus, an alloy layer 44 is formed near the boundary L. This alloy layer 44 contains both copper and tin atoms. This alloy layer 44 is included at the boundary between the solder 27 and the heat dissipation base plate 40, not limited to the area specified by B.

[0063] In this way, the molten solder 26 and 27 from the solder plates 26a and 27a are cooled and hardened. Then, as shown in Figure 14, the insulating circuit boards 20 are joined to the placement area 40b of the heat dissipation unit 4 via the hardened solder 27. Similarly, the semiconductor chip 25 is joined to the upper surface 22a of the insulating circuit board 20 via the hardened solder 26.

[0064] Therefore, a semiconductor unit 2 is formed, which includes an insulating circuit board 20 and a semiconductor chip 25. The semiconductor unit 2 is then joined to the placement area 40b of the heat dissipation unit 4 by solder 27.

[0065] Next, the heat dissipation unit 4 is attached to the lower opening 31b of case 3, and the semiconductor unit 2 is placed in case 3 in a storage process (step S4 in Figure 3). The outer edge of the heat dissipation unit 4 is attached to the step on the back surface of case 3 (frame portion 31) using adhesive (not shown). As a result, the semiconductor unit 2 is placed in the storage area 31f of case 3.

[0066] Next, a wiring process is performed to connect the semiconductor unit 2 housed in case 3 (step S5 in Figure 3). The internal wiring portion 32a of the external connection terminal 32, which is exposed from the upper opening 31a of case 3, is connected to the conductive pattern 22 with a wire 51. In addition, the output electrode of the semiconductor chip 25 is connected to the internal wiring portion 32a of the external connection terminal 32 with a wire 51.

[0067] Next, a sealing process is performed in which the storage area 31f of case 3 is sealed with a sealing member 50 (step S6 in Figure 3). The sealing member 50 is filled from the upper opening 31a of case 3, sealing the semiconductor unit 2 on the heat dissipation unit 4 in the storage area 31f. As a result, the semiconductor device 1 shown in Figure 1 is obtained.

[0068] Here, a reference example semiconductor device (not shown) relative to the semiconductor device 1 of the first embodiment will be described using Figure 3 (and Figures 16 and 17 described later). The reference example semiconductor device (not shown) also includes a heat dissipation unit 4a. The heat dissipation base plate 40 included in the reference example heat dissipation unit 4a has a plating film 41 formed on its entire surface, including the placement area 40b. That is, the plating film 41 in the placement area 40b of the heat dissipation unit 4a is not removed. A semiconductor device including such a heat dissipation unit 4a is also manufactured according to the flowchart in Figure 3.

[0069] First, a preparation process is carried out to prepare the components of the semiconductor device (step S1 in Figure 3). The heat dissipation unit 4a prepared here is manufactured through steps S10, S11a, and S14 in Figure 3. Alternatively, it is manufactured through steps S10, S12b, and S14 in Figure 3.

[0070] Next, a placement process is performed in which the heat dissipation unit 4, the insulating circuit board 20, and the semiconductor chip 25 are placed in order (step S2 in Figure 3). The placement process will be explained using Figures 16 and 17. Figure 16 is a cross-sectional view showing the placement process included in the semiconductor device manufacturing method of the reference example. Figure 17 is a schematic cross-sectional view showing the arrangement of atoms in the placement process included in the semiconductor device manufacturing method of the reference example. Note that Figure 17 schematically shows the arrangement of atoms in the area B enclosed by the dashed line in Figure 16. Also, Figure 17 only schematically shows the arrangement of atoms, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer. In this case as well, since the solder plate 27a is not joined when it is placed on the heat dissipation base plate 40 (plating film 41), air layers contained in the irregularities of the solder plate 27a exist between the solder plate 27a and the metal plate 23, and between the solder plate 27a and the plating film 41, but this description is omitted.

[0071] As shown in Figure 16, the insulating circuit board 20 is placed in the placement area 40b on the heat dissipation unit 4a via a solder board 27a. The semiconductor chip 25 is also placed on the upper surface 22a of the conductive pattern 22 of the insulating circuit board 20 via a solder board 26a. The thickness of the plating film 41 formed on the entire surface of the heat dissipation base plate 40 is a commonly used thickness, similar to the first embodiment, and may be, for example, 1 μm or more and 10 μm or less.

[0072] Furthermore, area B in Figure 16 is near the boundary between the heat dissipation base plate 40, on which the plating film 41 is formed, and the solder plate 27a in the heat dissipation unit 4a. At this boundary in area B, as shown in Figure 17, the copper atoms contained in the heat dissipation base plate 40, the nickel atoms contained in the plating film 41, and the tin atoms contained in the solder plate 27a are arranged regularly on either side of boundaries L1 and L2, respectively. Boundary L1 corresponds to the boundary between the solder plate 27a and the plating film 41 when the solder plate 27a is placed in the arrangement area 40b of the heat dissipation unit 4a (heat dissipation base plate 40). Similarly, boundary L2 corresponds to the boundary between the heat dissipation base plate 40 and the plating film 41.

[0073] Next, a bonding process is performed between the heat dissipation unit 4a and the insulating circuit board 20, and between the insulating circuit board 20 and the semiconductor chip 25 (step S3 in Figure 3). The bonding process will be explained using Figures 18 to 20. Figure 18 is a first cross-sectional schematic diagram showing the arrangement of atoms during the bonding process (during heating) included in the semiconductor device manufacturing method of the reference example, Figure 19 is a second cross-sectional schematic diagram showing the arrangement of atoms during the bonding process (during heating) included in the semiconductor device manufacturing method of the reference example, and Figure 20 is a third cross-sectional schematic diagram showing the arrangement of atoms during the bonding process (during heating) included in the semiconductor device manufacturing method of the reference example. Note that Figures 18 to 20 show the atomic arrangement in the area B enclosed by the dashed line in Figure 16, schematically illustrating the change from Figure 17. Also, Figures 18 to 20 only schematically show the arrangement of atoms, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0074] In step S2, the solder plate 27a between the heat dissipation unit 4a and the insulating circuit board 20, and the solder plate 26a between the conductive pattern 22 of the insulating circuit board 20 and the semiconductor chip 25 are heated. Solder plates 26a and 27a melt and transition to solder 26 and 27, respectively.

[0075] When heated in this manner, as shown in Figure 18, nickel atoms from any part of the plating film 41 migrate and diffuse into the tin atoms of the molten solder 27 across the boundary L1. Conversely, tin atoms from any part of the solder 27 diffuse into the nickel atoms of the plating film 41 across the boundary L1. Therefore, near the boundary L1, the formation of an alloy layer containing nickel atoms and tin atoms begins.

[0076] As heating continues, the diffusion of nickel atoms from the plating film 41 into the solder 27 and the diffusion of tin atoms from the solder 27 into the plating film 41 progress, and as shown in Figure 19, the formation of an alloy layer containing nickel atoms and tin atoms near the boundary L1 progresses further. The plating film 41 is thinner than the solder 27. Therefore, the nickel atoms in the plating film 41 decrease and the tin atoms increase in parts. In this way, the plating film 41 is partially replaced by tin atoms instead of nickel atoms, causing solder erosion. If the plating film 41 is sufficiently thin, the plating film 41 will disappear when all the nickel atoms in the plating film 41 are replaced by tin atoms.

[0077] Furthermore, as heating continues, copper atoms with a high diffusion rate in the heat dissipation base plate 40 move beyond the boundary L2 to the area where solder erosion has occurred in the plating film 41 and diffuse into the solder 27. Also, near the boundary L1 27 Tin atoms diffuse beyond the boundary L2 into the heat dissipation base plate 40. In this process, as shown in Figure 20, the traces left by the movement of copper atoms within the heat dissipation base plate 40 become voids (Kirkendal voids). Kirkendal voids often occur in the portion of the heat dissipation base plate 40 below the remaining plating film 41.

[0078] Heat dissipation unit 4: After heating, the molten solder 26 and 27 are hardened by cooling. a The bonding of the insulating circuit board 20 and the semiconductor chip 25 will be explained using Figure 21. Figure 21 is a cross-sectional view showing the bonding process (after bonding) included in the manufacturing method of the semiconductor device of the reference example.

[0079] The molten solders 26 and 27 are then cooled and hardened. As shown in Figure 21, the insulating circuit boards 20 are then joined to the placement area 40b of the heat dissipation unit 4a via the hardened solder 27. Similarly, the semiconductor chip 25 is joined to the upper surface 22a of the insulating circuit board 20 via the hardened solder 26. However, the heat dissipation base plate 40 contains multiple Kirkendal voids (vacancies V).

[0080] Next, the heat dissipation unit 4 is placed in the lower opening 31b of case 3. a The process involves attaching the heat dissipation unit 4a, then sequentially performing a storage process (step S4 in Figure 3) in which the semiconductor unit 2 is housed in the case 3, followed by a wiring process (step S5 in Figure 3) in which wiring is performed to the semiconductor unit 2 housed in the case 3. Finally, a sealing process is performed in which the storage area 31f of the case 3 is sealed with a sealing member 50 (step S6 in Figure 3). Through this process, a semiconductor device including the heat dissipation unit 4a is manufactured.

[0081] In such a heat dissipation unit 4a, as explained in Figure 20, the plating film 41 directly beneath the solder 27 is partially corroded by the solder 27. Also, as shown in Figure 21, multiple Kirkendal voids (vacancies V) are generated beneath the partially remaining plating film 41 of the heat dissipation base plate 40. When multiple Kirkendal voids (vacancies V) are present in the heat dissipation base plate 40, the thermal resistance of the heat dissipation base plate 40 increases. Furthermore, this explanation describes the generation of Kirkendal voids in the heat dissipation unit 4a (heat dissipation base plate 40) due to heating during the bonding process. However, Kirkendal voids can also be generated due to heat generation from long-term operation of the semiconductor device 1. In a semiconductor device containing such a heat dissipation unit 4a, the heat dissipation performance is reduced.

[0082] Therefore, the semiconductor device 1 described above includes an insulating circuit board 20 including a lower surface 23a, a heat dissipation base plate 40 including a front surface 40a and having a placement area 40b on the front surface 40a where the lower surface 23a of the insulating circuit board 20 is placed via solder 27, a plating film 41 formed on the front surface 40a of the heat dissipation base plate 40 excluding the solder area 41b where the solder 27 has spread over the placement area 40b of the front surface 40a, and an alloy layer 44 contained between the solder 27 and the placement area 40b of the heat dissipation base plate 40 and containing the solder components contained in the solder 27. In particular, in the semiconductor device 1, the plating film 41 is formed on the entire surface of the heat dissipation base plate 40 excluding the opening area 41a that surrounds the outer periphery of the placement area 40b where the insulating circuit board 20 is placed via solder 27. That is, the solder 27 that joins the insulating circuit board 20 is joined to the heat dissipation base plate 40 without going through the plating film 41. Therefore, in the placement region 40b of the heat dissipation base plate 40, the plating film 41 is not eroded by the solder 27. Consequently, there is no movement of atoms constituting the heat dissipation base plate 40, and the generation of voids in the heat dissipation base plate 40 is suppressed. Furthermore, the generation of voids is similarly suppressed even with heat generation due to long-term operation of the semiconductor device 1. As a result, the increase in the thermal resistance of the heat dissipation base plate 40 is suppressed, and the decrease in the heat dissipation performance of the semiconductor device 1, including the heat dissipation base plate 40, is suppressed. This also prevents a decrease in the reliability of the semiconductor device 1.

[0083] [Second Embodiment] In the second embodiment, a case in which a plating film is not provided on the lower surface 23a of the insulating circuit board 20 that contacts the solder 27 in the semiconductor device 1 will be described with reference to Figures 22 and 23. Figure 22 is a cross-sectional view of the semiconductor device of the second embodiment. Figure 23 is a rear perspective view of the insulating circuit board included in the semiconductor device of the second embodiment.

[0084] As described in the first embodiment, the surface of the metal plate 23 of the insulating circuit board 20 of the semiconductor device 1 may be plated to improve corrosion resistance. The insulating circuit board 20 is joined to the placement area 40b of the heat dissipation unit 4 via solder 27. The plated metal plate 23 will come into contact with the solder 27 via the plating film. As a result, solder corrosion of the plating film will occur on the metal plate 23 as well.

[0085] Therefore, in the second embodiment, the metal plate 23 of the insulating circuit board 20 has a plating film 24 formed on all surfaces except the bottom surface 23a, as shown in Figures 22 and 23. That is, the metal plate 23 does not have a plating film 24 on the bottom surface 23a, which is placed in the arrangement area 40b of the heat dissipation base plate 40 via solder 27, but the plating film 24 is formed on the sides surrounding the entire circumference of the bottom surface 23a, excluding the bottom surface 23a.

[0086] Therefore, the solder 27 that joins the heat dissipation unit 4 is joined to the metal plate 23 of the insulating circuit board 20 without going through the plating film 24. As a result, the plating film 24 on the lower surface 23a of the metal plate 23 is not corroded by the solder 27. Consequently, there is no movement of atoms constituting the metal plate 23, and the generation of voids in the metal plate 23 is suppressed. Furthermore, the generation of voids is similarly suppressed even with heat generation due to long-term operation of the semiconductor device 1. As a result, the increase in thermal resistance of the metal plate 23 together with the heat dissipation unit 4 is suppressed, the decrease in the heat dissipation performance of the semiconductor device 1 including the heat dissipation unit 4 and the metal plate 23 is suppressed, and the decrease in the reliability of the semiconductor device 1 is also prevented.

[0087] [Third Embodiment] The heat dissipation unit 4 of the third embodiment will be described with reference to Figure 24. Figure 24 is a plan view of the main part of the semiconductor device of the third embodiment (without sealing member). Note that the heat dissipation unit 4 of the third embodiment is included in the semiconductor device 1 of the first embodiment.

[0088] In the third embodiment, a resist film 43 is formed in an annular shape continuously along the opening edge of the opening region 41a of the plating film 41 included in the heat dissipation unit 4. The resist film 43 may be made of epoxy resin or acrylic resin, for example.

[0089] Solder 27 provided between the placement area 40b of the heat dissipation base plate 40 and the insulating circuit board 20 may spread outside the placement area 40b, but the presence of the resist film 43 suppresses the spreading of solder 27. If there is no resist film 43 and the solder 27 spreads outside the placement area 40b, there is a risk that the solder 27 will extend onto the plating film 41 surrounding the placement area 40b. When solder 27 comes into contact with the plating film 41, as described above, voids will be generated in the heat dissipation base plate 40 below the plating film 41. By providing the resist film 43 at the opening edge of the opening area 41a of the plating film 41, the generation of voids in the heat dissipation base plate 40 can be suppressed. In addition, the resist film 43 can narrow the opening area 41a. The area on the heat dissipation base plate 40 that does not have either the plating film 41 or solder 27 can be reduced in size or eliminated.

[0090] The resist film 43 on the opening region 41a of the plating film 41 may be formed by applying it along the opening edge of the opening region 41a of the plating film 41 after performing steps S10, S11a, and S12a in Figure 3. Alternatively, the resist film 43 may be formed on the opening region 41a of the plating film 41 after step S11a, and then step S12a may be performed.

[0091] Alternatively, the resist film 43 may be formed by applying it along the opening edge of the opening region 41a of the plating film 41 after performing steps S10, S11b, S12b, and S13b in Figure 3.

[0092] [Fourth Embodiment] The semiconductor device of the fourth embodiment consists of the semiconductor device 1 of the first embodiment and a heat dissipation unit 4 aExcept for one element, it has a similar configuration. This fourth embodiment of the semiconductor device will be described with reference to Figure 25. Figure 25 is a cross-sectional view of the fourth embodiment of the semiconductor device. Note that Figure 25 corresponds to Figure 1 of the first embodiment.

[0093] As shown in Figure 25, the semiconductor device 1a includes a semiconductor unit 2, a heat dissipation unit 4a on which the semiconductor unit 2 is positioned, and a case 3 provided on the outer edge of the heat dissipation unit 4a for housing the semiconductor unit 2. The inside of the case 3 of the semiconductor device 1a is sealed by a sealing member 50. The semiconductor unit 2, the case 3, and the sealing member 50 have the same configuration as in the first embodiment. The solder 26 and 27 provided on the upper surface 22a and lower surface 23a of the semiconductor unit 2 are also as described in the first embodiment.

[0094] The heat dissipation unit 4a includes a heat dissipation base plate 40 and a plating film 41. The heat dissipation base plate 40 is made of the same material and has the same size as in the first embodiment. The front surface 40a of the heat dissipation base plate 40 also includes a placement area 40b similar to that of the first embodiment, to which the lower surface 23a of the insulating circuit board 20 is joined via solder 27. However, the placement area 40b of the front surface 40a of the heat dissipation base plate 40 in the fourth embodiment is different from that of the first embodiment. , release The front surface 40a of the heat dissipation base plate 40 is not recessed in the -Z direction. That is, the entire surface of the front surface 40a of the heat dissipation base plate 40 in the fourth embodiment is substantially smooth. The front surface 40a of the heat dissipation base plate 40 includes a solder area 41b where the solder 27 is spread over the placement area 40b.

[0095] The plating film 41 is made of the same material as in the first embodiment. The plating film 41 is formed on the front surface 40a of the heat dissipation base plate 40, excluding the solder area 41b. Furthermore, the plating film 41 is also formed on the entire surface of the heat dissipation base plate 40, excluding the front surface 40a. That is, the plating film 41 is formed on the front surface 40a of the heat dissipation base plate 40 excluding the solder area 41b, the back surface 40c on the opposite side of the front surface 40a, and the four side surfaces 40d surrounding the front surface 40a and the back surface 40c.

[0096] Furthermore, the thickness of the plating film 41 formed on the front surface 40a is thinner than the thickness of the plating film 41 formed on the back surface 40c and the side surface 40d. For example, the thickness of the plating film 41 formed on the front surface 40a is 0.2 μm or less.

[0097] An insulating circuit board 20 is joined to the solder region 41b of the heat dissipation base plate 40 included in such a heat dissipation unit 4a via solder 27. The plating film 41 is formed on the surface of the heat dissipation base plate 40, excluding the solder 27 (solder region 41b). Furthermore, an alloy layer containing the solder components contained in the solder 27 is included between the solder 27 and the front surface 40a of the heat dissipation base plate 40. Details of this alloy layer will be described later.

[0098] Next, a method for manufacturing such a semiconductor device 1a will be explained using Figure 26. Figure 26 is a flowchart showing the method for manufacturing a semiconductor device according to the fourth embodiment. Note that the flowchart showing the manufacturing method in Figure 26 is just one example. The semiconductor device 1a includes a heat dissipation unit 4a to which the semiconductor unit 2 is bonded, and other than the flowchart in Figure 26, the semiconductor device 1a can be manufactured in any way. The method However, it can also be manufactured. Furthermore, the steps from step S2 onwards in the flowchart of Figure 26 are the same as the steps from step S2 onwards in the flowchart of Figure 3. For this reason, the explanation of the steps from step S2 onwards may be simplified here.

[0099] First, a preparation process is carried out to prepare the components of the semiconductor device 1a (step S1a in Figure 26). The components to be prepared include, for example, an insulating circuit board 20, a semiconductor chip 25, a case 3, and a heat dissipation unit 4a. Other components necessary for the semiconductor device 1a are also prepared. Manufacturing equipment used to manufacture the semiconductor device 1a may also be prepared.

[0100] Here, the manufacturing method of the heat dissipation unit 4a included in the semiconductor device 1a shown in Figure 25 (steps S10, S11c, S12c, S14 in Figure 26) is shown in Figure 25. 4 This will be explained using Figures 27 and 28. Figure 27 is a cross-sectional view showing the manufacturing process (plating treatment) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the fourth embodiment. Figure 28 is a cross-sectional view showing the manufacturing process (thinning treatment) of the heat dissipation unit included in the manufacturing method of the semiconductor device of the fourth embodiment. Figures 27 and 28 correspond to the cross-sectional areas indicated by the dashed-dotted line XX in Figure 6.

[0101] First, a heat dissipation base plate 40 is prepared, similar to the first embodiment (step S10 in Figure 26). Next, a plating treatment is performed on the entire surface of the heat dissipation base plate 40 to form a plating film 41 (step S11c in Figure 26). For example, as shown in Figure 27, a plating treatment is performed on the front surface 40a, back surface 40c, and side surface 40d of the heat dissipation base plate 40 to form a plating film 41. The plating treatment may be a generally known method, such as electroplating or electroless plating. The thickness of the plating film 41 formed on the entire surface of the heat dissipation base plate 40 may be the same for each surface. In this case, the thickness may be, for example, 1 μm or more and 10 μm or less.

[0102] Next, the plating film 41 on the front surface 40a of the heat dissipation base plate 40 is thinned (step S12c in Figure 26). The plating film 41 on the front surface 40a of the plating film 41 formed on the surface of the heat dissipation base plate 40 is uniformly ground down. As shown in Figure 28, the plating film 41 on the front surface 40a of the heat dissipation base plate 40 is thinned more than on other surfaces, and its thickness becomes 0.2 μm or less. With the above steps, the heat dissipation unit 4a can be prepared (step S14 in Figure 26).

[0103] Furthermore, the heat dissipation unit 4a may also be manufactured by the following method. For example, during the plating process in step S11c of Figure 26, the thickness of the plating film 41 formed on the front surface 40a of the heat dissipation base plate 40 may be made thinner than the thickness of the plating film 41 formed on other surfaces.

[0104] Furthermore, the above example describes a case where the entire plating film 41 on the front surface 40a of the heat dissipation base plate 40 is thinner than on other surfaces. However, it is not limited to this case; only the solder region 41b of the plating film 41 formed on the front surface 40a of the heat dissipation base plate 40 may be thinned. In the same way as in step S11c above, the plating film 41 may be formed on the entire surface of the heat dissipation base plate 40, and then in step S12c, only the plating film 41 in the solder region 41b may be ground down to thin it.

[0105] Alternatively, a plating film 41 may be formed over the entire surface of the heat dissipation base plate 40 to a thickness of at least 0.2 μm, masking may be applied to the solder region 41b of the plating film 41, another plating film 41 may be formed, and the masking may be removed. In this case, the plating film 41 may also be formed on the heat dissipation base plate 40 using an electrolytic plating method or an electroless plating method until the desired thickness is achieved. As a result, only the solder region 41b of the plating film 41 formed on the front surface 40a of the heat dissipation base plate 40 can be made thinner than other parts.

[0106] Alternatively, the thickness of the plating film 41 formed on the entire surface of the heat dissipation base plate 40, including the solder area 41b, may be 0.2 μm or less. In this case as well, the plating film 41 is formed on the heat dissipation base plate 40 using an electrolytic plating method or an electroless plating method until the desired thickness is achieved.

[0107] Next, a placement process is performed in which the heat dissipation unit 4a, the insulating circuit board 20, and the semiconductor chip 25 are placed in order (step S2 in Figure 26). The placement process will be explained using Figures 29 and 30. Figure 29 is a cross-sectional view showing the placement process included in the manufacturing method of the semiconductor device of the fourth embodiment. Figure 30 is a schematic cross-sectional view showing the arrangement of atoms in the placement process included in the manufacturing method of the semiconductor device of the fourth embodiment. Note that Figure 30 schematically shows the arrangement of atoms in the area B enclosed by the dashed line in Figure 29. Also, Figure 30 only schematically shows the arrangement of atoms, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0108] Insulating circuit boards 20 are placed in the arrangement area 40b of the plating film 41 formed on the heat dissipation unit 4a via solder plates 27a. The solder plate 27a is made of solder 27 that has hardened into a plate shape. In this case as well, as in the first embodiment, the solder plate 27a may be the same size as, for example, the lower surface 23a of the metal plate 23 of the insulating circuit board 20 when viewed from above.

[0109] A semiconductor chip 25 is placed on the upper surface 22a of the conductive pattern 22 of the insulating circuit board 20 via a solder plate 26a. The solder plate 26a is made of solder 26 that has hardened into a plate shape. In plan view, the solder plate 26a may be the same size as, for example, the semiconductor chip 25.

[0110] Through this placement process, as shown in Figure 29, the insulating circuit board 20 is placed in the placement area 40b of the heat dissipation unit 4a via a solder board 27a, and the semiconductor chip 25 is placed on the conductive pattern 22 of the insulating circuit board 20 via a solder board 26a.

[0111] Furthermore, area B in Figure 29 is near the boundary between the heat dissipation base plate 40 and the solder plate 27a in the heat dissipation unit 4a. At this boundary in area B, as shown in Figure 30, tin atoms, which are solder components contained in the solder plate 27a, and nickel atoms, which are contained in the plating film 41, are regularly arranged on either side of boundary L1. This boundary L1 corresponds to the boundary between the solder plate 27a and the plating film 41 when the solder plate 27a is placed on the plating film 41. Note that the boundary may contain solder components other than tin, such as silver and zinc. Below, only tin, which is a typical solder component, is described, but other solder components may also be included.

[0112] Furthermore, nickel atoms contained in the plating film 41 and copper atoms contained in the heat dissipation base plate 40 are regularly arranged across a boundary L2. This boundary L2 corresponds to the boundary between the plating film 41 and the placement area 40b of the heat dissipation base plate 40 when the plating film 41 is formed in the placement area 40b of the heat dissipation unit 4a (heat dissipation base plate 40).

[0113] Note that since the solder board 27a is not bonded when it is placed on the heat dissipation base plate 40 (plating film 41), air layers contained in the irregularities of the solder board 27a exist between the solder board 27a and the metal plate 23, and between the solder board 27a and the heat dissipation base plate 40 (plating film 41), but this is omitted from the description.

[0114] Next, a bonding process is performed between the heat dissipation unit 4a and the insulating circuit board 20, and between the insulating circuit board 20 and the semiconductor chip 25 (step S3 in Figure 26). The bonding process will be explained using Figures 31 and 32. Figure 31 is a cross-sectional view showing the bonding process included in the semiconductor device manufacturing method of the fourth embodiment. Figure 32 is a schematic cross-sectional view showing the arrangement of atoms in the bonding process included in the semiconductor device manufacturing method of the fourth embodiment. Note that Figure 32 schematically shows the arrangement of atoms in the area B enclosed by the dashed line in Figure 31. Also, Figure 32 only schematically shows the arrangement of atoms, and the number of stacked atoms does not necessarily represent the thickness of the atomic layer.

[0115] In step S2, the solder plate 27a between the heat dissipation unit 4a and the insulating circuit board 20, and the solder plate 26a between the conductive pattern 22 of the insulating circuit board 20 and the semiconductor chip 25 are heated. Solder plates 26a and 27a melt and transition to solder 26 and 27, respectively.

[0116] When heated in this manner, the tin atoms of the molten solder 27 and the nickel atoms of the plating film 41 move and diffuse across the boundary L1. Also, the copper atoms of the heat dissipation base plate 40 and the nickel atoms of the plating film 41 move and diffuse across the boundary L2. Furthermore, the tin atoms of the molten solder 27 move even further and diffuse into the copper atoms of the heat dissipation base plate 40 across the boundary L2. Also, the copper atoms of the heat dissipation base plate 40 move even further and diffuse into the tin atoms of the molten solder 27 across the boundary L1.

[0117] The plating film 41 on the front surface 40a of the heat dissipation base plate 40 is formed to be sufficiently thin. As a result, nickel atoms are replaced by tin and copper atoms in the plating film 41, causing plating erosion. Consequently, as shown in Figure 32, the plating film 41 is eroded between the solder 27 and the heat dissipation base plate 40 near the boundaries L1 and L2, forming an alloy layer 44. In this case, the traces of copper atom migration within the heat dissipation base plate 40, as shown in Figure 20, do not become voids (Kirkendal voids). This alloy layer 44 contains copper atoms, tin atoms, and nickel atoms. Such an alloy layer 44 may be included at the boundary between the solder 27 and the heat dissipation base plate 40, not limited to the area B.

[0118] The molten solder 26 and 27 are cooled and hardened, and the insulating circuit board 20 is joined to the placement area 40b of the heat dissipation unit 4a (front surface 40a of the heat dissipation base plate 40) via the hardened solder 27. Similarly, the semiconductor chip 25 is joined to the upper surface 22a of the insulating circuit board 20 via the hardened solder 26.

[0119] Therefore, a semiconductor unit 2 is formed, which includes an insulating circuit board 20 and a semiconductor chip 25. The semiconductor unit 2 is then joined to the placement area 40b of the heat dissipation unit 4a by solder 27.

[0120] Subsequently, the following steps are performed in order, similar to the first embodiment: the flowchart storage step (step S4 in Figure 26), the wiring step (step S5 in Figure 26), and the sealing step (step S6 in Figure 26). Through these steps, the semiconductor device 1a shown in Figure 25 is obtained.

[0121] In the semiconductor device 1a described above, the insulating circuit board 20 and the heat dissipation base plate 40 having a plating film 41 on its front surface 40a are joined by a solder plate 27a. As a result, the plating film 41 is consumed in the placement area 40b of the heat dissipation base plate 40. That is, the thickness of the plating film 41 on the front surface 40a of the heat dissipation base plate 40 of the semiconductor device 1a is considerably thinner than in the reference example shown in Figure 16, and disappears during joining. Therefore, an alloy layer 44 is formed that includes the atoms constituting the heat dissipation base plate 40, the tin atoms constituting the solder 27, and the nickel atoms constituting the plating film 41, thereby suppressing the generation of voids in the heat dissipation base plate 40. Furthermore, the generation of voids is similarly suppressed even with heat generation due to long-term operation of the semiconductor device 1a. As a result, the increase in the thermal resistance of the heat dissipation base plate 40 is suppressed, and the decrease in the heat dissipation performance of the semiconductor device 1a including the heat dissipation base plate 40 is suppressed. This also prevents a decrease in the reliability of the semiconductor device 1a.

[0122] The above merely illustrates the principle of the present invention. Furthermore, numerous modifications and changes are possible for those skilled in the art, and the present invention is not limited to the exact configurations and applications shown and described above, and all corresponding modifications and equivalents are considered to be within the scope of the present invention as defined by the appended claims and equivalents. [Explanation of Symbols]

[0123] 1,1a Semiconductor device 2 Semiconductor Units 3 cases 4,4a Heat dissipation unit 20 Insulated Circuit Boards 21 Insulating board 22 Conductive Patterns 22a Top side 23 Metal plate 23a Bottom surface 24 Plating film 25 Semiconductor Chips 26,27 Solder 26a, 27a Solder board 27b Fillet section 31 Frame section 31a Top opening 31b Bottom opening 31c Upper inner wall 31d Step 31e Lower interior wall 31f Storage Area 32 External connection terminals 32a Internal wiring section 32b External wiring section 40 Heat dissipation base plate 40a Front side 40b Placement area 40c back side 40d side view 41 Plating film 41a Opening area 41b Solder area 42 masks 43 Resist film 44 alloy layer 50 Sealing member 51 wire

Claims

1. A substrate including the bottom surface, A heat dissipation base plate containing copper, having a main surface and an arrangement region on the main surface where the lower surface of the substrate is placed via solder, A first plating film is formed on the main surface of the heat dissipation base plate, excluding the solder area where the solder has spread over the arrangement area of ​​the main surface, and is mainly composed of nickel. The solder and the heat dissipation base plate are interposed, and the alloy layer containing the solder components contained in the solder is included between them. The thickness of the first plating film formed on the main surface is less than 0.2 μm. Semiconductor equipment.

2. The alloy layer further comprises the first metallic material contained in the heat dissipation base plate, along with the solder component. The semiconductor device according to claim 1.

3. The first metallic material contains copper. The semiconductor device according to claim 2.

4. The outer perimeter of the aforementioned arrangement area is located inward from the outer perimeter of the substrate in a plan view. The semiconductor device according to claim 1.

5. The first plating film is formed on the main surface of the heat dissipation base plate, excluding the opening region that surrounds the entire periphery of the solder area. The semiconductor device according to claim 1.

6. The arrangement area is recessed in a concave shape relative to the main surface excluding the arrangement area. The semiconductor device according to claim 5.

7. The aforementioned solder, in a plan view, includes a fillet portion that extends outward from the lower surface of the substrate. The semiconductor device according to claim 6.

8. The outer edge of the fillet portion of the solder is located outside the placement area in a plan view. The semiconductor device according to claim 7.

9. The substrate includes an insulating plate, a conductive pattern formed on the front surface of the insulating plate, and a metal plate formed on the back surface of the insulating plate, including the bottom surface. The metal plate, except for the lower surface, has a second plating film formed on its side surface, surrounding the entire circumference of the lower surface. The semiconductor device according to claim 5.

10. The aforementioned metal plate is composed mainly of copper. The semiconductor device according to claim 9.

11. The second plating film is mainly composed of nickel. The semiconductor device according to claim 9.

12. A resist material is formed on the front surface of the heat dissipation base plate, surrounding the entire circumference of the opening edge of the first plating film. The semiconductor device according to claim 5.

13. The alloy layer further comprises the solder component and the first metal material, along with a second metal material constituting the first plating film. The semiconductor device according to claim 2.

14. The second metallic material contains nickel. The semiconductor device according to claim 13.

15. The first plating film is further formed on the surface of the heat dissipation base plate excluding the main surface, and the thickness of the first plating film formed on the main surface is thinner than the thickness of the first plating film formed on the surface excluding the main surface. The semiconductor device according to claim 13.

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