Semiconductor packages

Abstract

A semiconductor package (10) comprising a passive component and an active component is provided with a first component layer having a first principal surface (10A) and a second principal surface (10B) on the opposite side from the first principal surface (10A). The semiconductor package (10) is provided with a first wiring layer adjacent to the first component layer in a direction orthogonal to the first principal surface (10A). The first component layer has a first sealing part (11) containing an inorganic material, and an active component (12A) positioned inside the first sealing part (11). The first component layer has a plurality of first via wires (14) extending in a direction intersecting the first principal surface (10A) inside the first sealing part (11), and having an end exposed from the first sealing part (11) on the first principal surface (10A). The first wiring layer has a first insulating resin part (21) and a first wiring part (22) extending inside the first insulating resin part (21). A connection terminal (13) of the active component (12A) is exposed from the first sealing part (11) on the second principal surface (10B) side of the first sealing part (11).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package.

Background Art

[0002] The electronic component described in Patent Document 1 has a core substrate. The core substrate has an opening penetrating the core substrate. Inside the opening, a magnetic resin is filled. Further, the magnetic resin has a through-hole. Inside the through-hole, a through-hole conductor is located. The electronic component also has an insulating layer and a conductor layer. The insulating layer is located on the main surface of the core substrate. The conductor layer is located on the surface of the insulating layer. The conductor layer forms an inductor together with the above-described through-hole conductor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an electronic component as described in Patent Document 1, the inductor is constituted by a conductor layer and a through-hole conductor. It is difficult to determine whether such an inductor operates normally until the entire electronic component is manufactured and a current is passed through the electronic component. Therefore, in the electronic component described in Patent Document 1, after manufacturing the entire electronic component, a test must be conducted to determine whether the inductor operates normally. Here, although the inductor is taken as an example, even when the electronic component includes a passive component or an active component other than the inductor, similarly, there is a problem that it is difficult to determine whether it operates normally until the entire electronic component is manufactured.

Means for Solving the Problems

[0005] To solve the above problems, one aspect of the present disclosure is a semiconductor package having a passive component and an active component, comprising: a first component layer having a first main surface and a second main surface opposite to the first main surface; and a first wiring layer adjacent to the first component layer in a direction perpendicular to the first main surface; wherein the first component layer comprises a first sealing portion containing an inorganic material, at least one of the active component located inside the first sealing portion, and a plurality of first via wirings extending inside the first sealing portion in a direction intersecting the first main surface, with their ends exposed from the first sealing portion on the first main surface; and the first wiring layer comprises a first insulating resin portion and a first wiring portion extending inside the first insulating resin portion; and the connection terminals of the active component are exposed from the first sealing portion on the second main surface side of the first sealing portion. [Effects of the Invention]

[0006] According to the above configuration, passive components that have passed the safety check can be installed, improving reliability. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic diagram of the semiconductor package according to the first embodiment. [Figure 2] Figure 2 is an explanatory diagram of the manufacturing method for a semiconductor package according to the first embodiment. [Figure 3] Figure 3 is an explanatory diagram of the semiconductor package manufacturing method according to the first embodiment. [Figure 4] Figure 4 is an explanatory diagram of the manufacturing method for a semiconductor package according to the first embodiment. [Figure 5] Figure 5 is an explanatory diagram of the manufacturing method for a semiconductor package according to the first embodiment. [Figure 6] Figure 6 is an explanatory diagram of the semiconductor package manufacturing method according to the first embodiment. [Figure 7] Figure 7 is an explanatory diagram of the semiconductor package manufacturing method according to the first embodiment. [Figure 8] Figure 8 is an explanatory diagram of the method for manufacturing a semiconductor package according to the first embodiment. [Figure 9] Figure 9 is an explanatory diagram of the semiconductor package manufacturing method according to the first embodiment. [Figure 10] Figure 10 is an explanatory diagram of the manufacturing method for a semiconductor package according to the first embodiment. [Figure 11] Figure 11 is an explanatory diagram of the manufacturing method of a semiconductor package according to the first embodiment. [Figure 12] Figure 12 is a schematic diagram of the semiconductor package according to the second embodiment. [Figure 13] Figure 13 is a schematic diagram of the semiconductor package as an example of the modification. [Figure 14] Figure 14 is a schematic diagram of the semiconductor package as an example of the modification. [Figure 15] Figure 15 is a schematic diagram of the semiconductor package as an example of the modification. [Modes for carrying out the invention]

[0008] The following describes one embodiment of a semiconductor package with reference to the drawings. Note that the drawings may show enlarged versions of components for ease of understanding. The dimensional ratios of the components may differ from those in the actual product or those in other drawings. Furthermore, some components are labeled as 1st, 2nd, etc., below. These are for convenience only and do not indicate priority of the components. It is also permissible to interpret the numbers 1st and 2nd as interchangeable.

[0009] (First Embodiment) <About the overall structure> As shown in FIG. 1, the semiconductor package 10 includes a first layer L1. The outer shape of the first layer L1 is generally substantially rectangular parallelepiped. The first layer L1 has a first main surface 10A and a second main surface 10B. The first main surface 10A is one of the surfaces with the largest area among the outer surfaces of the first layer L1. When viewed in the direction orthogonal to the first main surface 10A, the first main surface 10A is rectangular. The second main surface 10B is the surface on the opposite side of the first main surface 10A among the outer surfaces of the first layer L1. The second main surface 10B is parallel to the first main surface 10A. When viewed in the direction orthogonal to the second main surface 10B, the shape of the second main surface 10B is the same as the shape of the first main surface 10A.

[0010] In the following description, the axis orthogonal to the first main surface 10A is defined as the first axis X. And a specific direction among the directions along the first axis X is defined as the first positive direction X1, and the direction opposite to the first positive direction X1 is defined as the first negative direction X2. In the first embodiment, the first positive direction X1 coincides with the direction in which the first main surface 10A faces. The first negative direction X2 coincides with the direction in which the second main surface 10B faces.

[0011] The semiconductor package 10 includes a second layer L2, a third layer L3, a fourth layer L4, and a fifth layer L5 laminated on the first layer L1. When viewed in perspective in the direction along the first axis X, the outer shapes of each of the first layer L1 to the fifth layer L5 are all rectangular. Each layer of the semiconductor package 10 is arranged in the order of the second layer L2, the first layer L1, the third layer L3, the fourth layer L4, and the fifth layer L5 from the first negative direction X2 side to the first positive direction X1 side.

[0012] The first layer L1 has a first sealing portion 11, a plurality of first electronic components 12, a plurality of first via wirings 14, and a plurality of first component external terminals 15. Note that the first layer L1 is a first component layer including the first electronic components 12.

[0013] The outer shape of the first sealing portion 11 is substantially rectangular parallelepiped. The plane facing the first positive direction X1 of the outer surface of the first sealing portion 11 is the first main surface 10A. Also, the plane facing the first negative direction X2 of the outer surface of the first sealing portion 11 is the second main surface 10B. The first sealing portion 11 is TEOS (Tetra EthOxy Silane). That is, the first sealing portion 11 contains an inorganic material. Also, as the material containing the inorganic material applied to the first sealing portion 11, SiO2, TiN, TiO, SiCOH, etc. can be adopted.

[0014] The first electronic component 12 is a passive component or an active component. The passive component is any one of an inductor, a resistor, and a capacitor. The active component is an electronic component that performs active work such as amplification, rectification, and conversion on an electric current. For example, the active component is a diode, a transistor, and an integrated circuit including these. Note that even when the integrated circuit includes an inductor, a resistor, and a capacitor, if it has even one active component, it is treated as an active component. In the following description, "electronic component" also indicates either a passive component or an active component.

[0015] In the example shown in FIG. 1, the first layer L1 has three first electronic components 12. The three first electronic components 12 are two active components 12A and one passive component 12B. That is, at least one of the first electronic components 12 is an active component 12A. Also, one of the first electronic components 12 is a passive component 12B.

[0016] The passive component 12B contains an inorganic material. For example, when the passive component 12B is an inductor, the passive component 12B contains materials such as Fe, FeSi-based, and chromium-zirconium-tantalum alloy as the inorganic material. These materials are contained in the core of the inductor. Also, when the passive component 12B is an inductor, the passive component 12B contains materials such as Cu and Ag as the inorganic material. These materials are contained in the wiring of the inductor.

[0017] Furthermore, if the passive component 12B is a capacitor, it contains inorganic materials such as SiO2, SiN, and barium titanate. These materials are contained in the capacitor core. Also, if the passive component 12B is a capacitor, it contains materials such as Al and Ni. These materials are contained in the electrodes. In both the case of an inductor and a capacitor, the passive component 12B contains organic materials such as epoxy and polyimide resins.

[0018] In the first embodiment, the volume fraction of inorganic material in the passive component 12B is 80 vol% or more. That is, the volume fraction of inorganic material in the passive component 12B is 50 vol% or more.

[0019] Each first electronic component 12 is located inside the first sealing portion 11. Specifically, the three first electronic components 12 are arranged in a direction parallel to the first main surface 10A. Furthermore, each first electronic component 12 is located closer to the second main surface 10B within the first layer L1. Specifically, one main surface of each first electronic component 12 is approximately flush with the second main surface 10B of the first layer L1.

[0020] Of the first electronic components 12, the maximum dimensions of two active components 12A in the direction perpendicular to the first main surface 10A are the same. Also, the maximum dimension of the remaining passive component 12B, which is the remaining first electronic component 12, in the direction perpendicular to the first main surface 10A is greater than the maximum dimension of each active component 12A in the direction perpendicular to the first main surface 10A.

[0021] Each active component 12A comprises a component body 12M, a connection terminal 13, and an internal terminal 13A. The connection terminal 13 functions as an external terminal for connecting to external wiring, etc., of the first electronic component 12. In the example shown in Figure 1, each active component 12A has two connection terminals 13 and two internal terminals 13A. The two connection terminals 13 are exposed toward the first negative direction X2. Specifically, each connection terminal 13 protrudes from the component body 12M. In addition, each connection terminal 13 is exposed from the first sealing portion 11 on the second main surface 10B side of the first sealing portion 11. Note that each of these connection terminals 13 protrudes from the first sealing portion 11.

[0022] On the outer surface of each first electronic component 12's connection terminal 13, the volume fraction of Cu is 50 vol% or more. In the first embodiment, the volume fraction of Cu in the entire connection terminal 13 is 90 vol% or more. Each connection terminal 13 contains small amounts of S, Ni, and O components in addition to the Cu component.

[0023] The two internal terminals 13A are exposed from the component body 12M toward the first positive direction X1. That is, each internal terminal 13A is exposed from the component body 12M on the opposite side from the connection terminal 13 in the direction perpendicular to the first main surface 10A. In the example shown in Figure 1, the internal terminals 13A do not protrude from the component body 12M. In other words, the end face of the internal terminal 13A toward the first positive direction X1 is flush with the component body 12M. That is, the amount of protrusion of the connection terminal 13 is greater than the amount of protrusion of the internal terminals 13A. The material of each internal terminal 13A is the same as the material of the connection terminal 13.

[0024] In the example shown in Figure 1, the passive component 12B of the first electronic component 12 has two connection terminals 13. The material of these two connection terminals 13 is the same as the material of the connection terminals 13 of the active component 12A. The two connection terminals 13 are exposed toward the first negative direction X2. Furthermore, each connection terminal 13 toward the first negative direction X2 is exposed from the first sealing portion 11 on the second main surface 10B side of the first sealing portion 11. Note that each of these connection terminals 13 toward the first negative direction X2 protrudes from the first sealing portion 11. Thus, the connection terminals 13 of each first electronic component 12 are exposed from the first sealing portion 11 only on the second main surface 10B of the first sealing portion 11.

[0025] In the example shown in Figure 1, the first layer L1 has four first via connections 14. Each first via connection 14 is substantially cylindrical. Each first via connection 14 extends within the first sealing portion 11 in a direction intersecting the first main surface 10A. In the first embodiment, each first via connection 14 extends in a direction perpendicular to the first main surface 10A. The first end of each first via connection 14 is connected to the internal terminal 13A of the active component 12A. The second end of each first via connection 14 is exposed from the first sealing portion 11. That is, the ends of the first via connections 14 are exposed from the first sealing portion 11 on the first main surface 10A.

[0026] The first via wiring 14 contains a Cu component. The volume fraction of Cu in the first via wiring 14 is 50 vol% or more. In the first embodiment, the volume fraction of Cu in the first wiring section 22 is 90 vol% or more.

[0027] Multiple first component external terminals 15 protrude from the first sealing portion 11. Specifically, multiple first component external terminals 15 are exposed from the first positive direction X1 side of the first sealing portion 11. Each first component external terminal 15 is connected to the second end of the first via wiring 14. The material of each first component external terminal 15 is the same as the material of the first via wiring 14.

[0028] The second layer L2 is laminated relative to the first layer L1 on the first negative direction X2 side. In other words, the second layer L2 is directly laminated on the second main surface 10B of the first layer L1. Therefore, the second layer L2 is adjacent to the first component layer in a direction perpendicular to the first main surface 10A.

[0029] The second layer L2 has a first insulating resin portion 21, a first wiring portion 22, and a plurality of first external wiring terminals 23. Therefore, the second layer L2 is a first wiring layer including the first wiring portion 22.

[0030] The outer shape of the first insulating resin part 21 is approximately rectangular parallelepiped. The outer shape of the first insulating resin part 21 is approximately the same as the outer shape of the second layer L2. The material of the first insulating resin part 21 is a synthetic resin containing an inorganic filler. The synthetic resin is, for example, an epoxy-based or polyimide-based resin. The first insulating resin part 21 covers the circumferential surface of the connection terminal 13 of the first electronic component 12 that protrudes from the first sealing part 11.

[0031] The first wiring section 22 has a plurality of first columnar wirings 22B extending in a direction intersecting the first main surface 10A, and a plurality of first wirings 22A extending in a direction parallel to the first main surface 10A. The first columnar wirings 22B are connected to the first wirings 22A. These plurality of first columnar wirings 22B and plurality of first wirings 22A are connected to each other. Note that in Figure 1, only some of the first columnar wirings 22B and some of the first wirings 22A are labeled with reference numerals.

[0032] The first wiring section 22 is connected to the connection terminal 13 of the first electronic component 12. The first wiring section 22 extends within the first insulating resin section 21 in an arbitrary pattern. The material of the first wiring section 22 is the same as the material of the first via wiring 14. That is, the volume fraction of Cu in the first wiring section 22 is 50 vol% or more.

[0033] Multiple first wiring external terminals 23 protrude from the first insulating resin portion 21. Specifically, multiple first wiring external terminals 23 are exposed from the first negative direction X2 side of the first insulating resin portion 21. The material of each first wiring external terminal 23 has a three-layer structure consisting of a layer mainly composed of Cu, a layer mainly composed of Ni, and a layer mainly composed of Au, from the first positive direction X1 side. These first wiring external terminals 23 function as external terminals when mounting the semiconductor package 10 onto a substrate or the like. Note that in Figure 1, only some of the first wiring external terminals 23 are labeled with reference numerals.

[0034] The third layer L3 is stacked relative to the first layer L1 on the first positive direction X1 side. In other words, the third layer L3 is stacked on the first main surface 10A of the first layer L1. That is, the third layer L3 is adjacent to the first component layer in a direction perpendicular to the first main surface 10A.

[0035] The third layer L3 has a second insulating resin portion 31, a second wiring portion 32, and a plurality of second external wiring terminals 33. The third layer L3 is a second wiring layer including the second wiring portion 32. The outer shape of the second insulating resin part 31 is approximately rectangular parallelepiped. The outer shape of the second insulating resin part 31 is approximately the same as the outer shape of the third layer L3. The material of the second insulating resin part 31 is a synthetic resin containing an inorganic filler. The second insulating resin part 31 covers the circumferential surface of the first component external terminal 15.

[0036] The second wiring section 32 has a plurality of second wirings 32A extending in a direction parallel to the first main surface 10A, and a plurality of second columnar wirings 32B extending in a direction intersecting the first main surface 10A. The second columnar wirings 32B are connected to the second wirings 32A. These plurality of second columnar wirings 32B and plurality of second wirings 32A are connected to each other. Note that in Figure 1, only some of the second columnar wirings 32B and some of the second wirings 32A are labeled with reference numerals.

[0037] The second wiring section 32 is connected to the first component external terminal 15. That is, the second wiring section 32 is connected to the first via wiring 14 in the first layer L1 via the first component external terminal 15. In other words, the second end of the first via wiring 14 is connected to the second wiring section 32 in the second wiring layer.

[0038] The second wiring section 32 extends within the second insulating resin section 31 in an arbitrary pattern. The material of the second wiring section 32 is the same as that of the first wiring section 22. That is, the volume fraction of Cu in the second wiring section 32 is 50 vol% or more.

[0039] Multiple second external wiring terminals 33 protrude from the second insulating resin part 31. Specifically, multiple second external wiring terminals 33 are exposed from the first positive direction X1 side of the second insulating resin part 31. The material of each second external wiring terminal 33 is the same as the material of the first external terminal 15 of the component.

[0040] The fourth layer L4 is stacked relative to the third layer L3 on the first positive direction X1 side. The fourth layer L4 has a second sealing portion 41, a plurality of second electronic components 42, a second via wiring 44, a plurality of second component external terminals 45, a plurality of connection portions 47, and an underfill 46. Note that the fourth layer L4 is a second component layer including the second electronic components 42.

[0041] The second sealing portion 41 has an outer shape that is approximately rectangular. The outer shape of the second sealing portion 41 is approximately the same as the outer shape of the fourth layer L4. The material of the second sealing portion 41 is a synthetic resin containing an inorganic filler. In the example shown in Figure 1, the fourth layer L4 comprises three second electronic components 42. The second electronic components 42 consist of two active components 42A and one passive component 42B. That is, at least one of the second electronic components 42 is an active component 42A, and one of the second electronic components 42 is a passive component 42B. The volume fraction of inorganic material in the passive component 42B is 80 vol% or more.

[0042] Each second electronic component 42 is located inside the second sealing portion 41. Specifically, the three second electronic components 42 are arranged in a direction parallel to the first main surface 10A. Each second electronic component 42 is provided with a connection terminal 43. The connection terminal 43 functions as an external terminal for connecting the second electronic component 42 to external wiring, etc.

[0043] In the example shown in Figure 1, each second electronic component 42 has two connection terminals 43. Each connection terminal 43 is exposed toward the first negative direction X2. These connection terminals 43 are not covered by the second insulating resin portion 31. The material of the connection terminals 43 of each second electronic component 42 is the same as the material of the connection terminals 43 of the first electronic component 12.

[0044] The second via wiring 44 is substantially cylindrical in shape. The second via wiring 44 extends inside the second sealing portion 41 in a direction intersecting the first main surface 10A. In the first embodiment, the second via wiring 44 extends in a direction perpendicular to the first main surface 10A. The first end of the second via wiring 44 is connected to one of the second external wiring terminals 33. The second end of the second via wiring 44 is exposed from the second sealing portion 41. That is, the end of the second via wiring 44 is exposed from the second sealing portion 41 on the surface facing the first positive direction X1. The material of the second via wiring 44 is the same as the material of the first via wiring 14.

[0045] Multiple second component external terminals 45 protrude from the second sealing portion 41. Specifically, multiple second component external terminals 45 are exposed from the first positive direction X1 side of the second sealing portion 41. One of the second component external terminals 45 is connected to the second end of the second via wiring 44. The material of each second component external terminal 45 is the same as the material of the first component external terminal 15.

[0046] The second external wiring terminals 33 that are not connected to the second via wiring 44 are connected to the connection terminals 43 of the second electronic component 42 via connection parts 47. The connection parts 47 are made of a conductive material such as solder. There are connection parts 47 corresponding to the number of second external wiring terminals 33. Each connection part 47 is applied to the corresponding second external wiring terminal 33. That is, the connection parts 47 cover the first positive X1 side surface of the second external wiring terminal 33.

[0047] The underfill 46 is located inside the second sealing portion 41. The underfill 46 is located in the region from the first positive direction X1 side of the second insulating resin portion 31 to the first positive direction X1 side end of the connection terminal 43. That is, the underfill 46 covers the second wiring external terminal 33, the connection portion 47, and the circumferential surface of the connection terminal 43. The material of the underfill 46 is, for example, epoxy resin. However, the material of the underfill 46 is not limited to epoxy resins, but may also be polyimide resins, liquid crystal polymer resins, acrylic resins, phenolic resins, or combinations thereof. Furthermore, the underfill 46 may contain an inorganic filler such as silica filler.

[0048] The fifth layer L5 is laminated relative to the fourth layer L4 on the first positive direction X1 side. The fifth layer L5 has a third insulating resin portion 51 and a third wiring portion 52. The fifth layer L5 is a third wiring layer including the third wiring portion 52.

[0049] The outer shape of the third insulating resin part 51 is approximately a rectangular parallelepiped. The outer shape of the third insulating resin part 51 is approximately the same as the outer shape of the fifth layer L5. The material of the third insulating resin part 51 is the same as the material of the first insulating resin part 21. The second component external terminal 45 is embedded in the first negative direction X2 side of the third insulating resin part 51.

[0050] The third wiring section 52 has a plurality of third columnar wirings 52B extending in a direction intersecting the first main surface 10A, and a plurality of third wirings 52A extending in a direction parallel to the first main surface 10A. The third columnar wirings 52B are connected to the third wirings 52A. Note that in Figure 1, only some of the third columnar wirings 52B and some of the third wirings 52A are denoted by reference numerals.

[0051] The third wiring section 52 is connected to the second component external terminal 45. The third wiring section 52 extends inside the third insulating resin section 51 in an arbitrary pattern. The material of the third wiring section 52 is the same as the material of the first wiring section 22. That is, the volume fraction of Cu in the third wiring section 52 is 50 vol% or more.

[0052] <About the manufacturing method of semiconductor packages> A method for manufacturing the semiconductor package 10 will be described. Note that in Figures 2 to 11, only some components may be denoted by reference numerals.

[0053] As shown in Figure 2, first, a plate-shaped base substrate BL is prepared. The material of the base substrate BL is silicon. In the following description, it is assumed that the main surface of the base substrate BL is perpendicular to the first axis X. When viewed in the first negative direction X2, the base substrate BL is, for example, rectangular. The dimensions of each side of the base substrate BL are such that multiple semiconductor packages 10 can be accommodated. Next, the first release layer RL1 is applied to the entire top surface of the base substrate BL, on the first positive direction X1 side. The first release layer RL1 is a sheet-like material with adhesive properties, such as an infrared-curable resin tape, an acrylic resin adhesive, or a polyimide adhesive.

[0054] Next, as shown in Figure 3, the first electronic component 12 is placed on the first release layer RL1. Specifically, the first electronic component 12 is placed so that its connection terminals 13 face the first release layer RL1.

[0055] Next, as shown in Figure 4, the first sealing portion 11 is formed. Specifically, first, an insulator is formed from the first positive direction X1 side of each first electronic component 12 and the first release layer RL1 by a known technique such as the CVD method. The material of the insulator is TEOS. Next, a first through hole PO1 is formed in the insulator by a known technique such as the Bosch method. The first through hole PO1 is formed in a position that overlaps with the internal terminal 13A of the first electronic component 12 when viewed in the first negative direction X2.

[0056] Next, as shown in Figure 5, a first via wiring 14 is formed in the first through hole PO1. The first via wiring 14 is formed by known techniques such as the via-fill method. Although not shown in the figure, a seed layer made of Cu is formed during the process of forming the first via wiring 14.

[0057] Next, as shown in Figure 6, the second insulating resin portion 31, the second wiring portion 32, and the second external wiring terminal 33 are formed on the first positive direction X1 side of the first sealing portion 11. The second insulating resin portion 31 is formed by photolithography. The second wiring portion 32 and the second external wiring terminal 33 are formed by known techniques such as the semi-additive method. In this step, the second external wiring terminal 33 may be surface-treated by known methods such as electroless plating or electrolytic plating.

[0058] Next, as shown in Figure 7, the second electronic component 42 is mounted. Specifically, the terminals of the second electronic component 42 are soldered to the second external wiring terminal 33. The soldered portion after connection becomes the connection part 47. In addition, epoxy resin is filled between the second insulating resin part 31 and the second electronic component 42. This forms the underfill 46.

[0059] Next, the second sealing portion 41 is formed. Specifically, an insulator is laminated from the first positive direction X1 side of the second electronic component 42 and the second insulating resin portion 31. The material of the insulator is an organic resin containing an inorganic filler. Next, a laser is irradiated onto the insulator from the first positive direction X1 side. Specifically, the laser is irradiated onto the portion of the insulator on the first positive direction X1 side of the second wiring external terminal 33 that is not connected to the second electronic component 42, and which forms the second via wiring 44. As a result, the insulator is processed and the second through hole PO2 is formed.

[0060] Next, as shown in Figure 8, a second via wiring 44 is formed in the second through hole PO2. The second via wiring 44 is formed by a known technique such as the via-fill method. Although not shown in the figure, a seed layer made of Cu is formed during the process of forming the second via wiring 44. Then, the second sealing portion 41 and a portion of the second via wiring 44 on the first positive direction X1 side are polished to the desired size.

[0061] Next, as shown in Figure 9, the third insulating resin portion 51, the third wiring portion 52, and the second component external terminal 45 are formed. The third insulating resin portion 51 is formed by photolithography. The third wiring portion 52 and the second component external terminal 45 are formed by known techniques such as the semi-additive method. Next, the first release layer RL1 is removed by cutting. Furthermore, the second release layer RL2 is formed on the first positive direction X1 side relative to the third insulating resin portion 51. The second release layer RL2 is formed to cover the entire third insulating resin portion 51. The material of the second release layer RL2 is the same as the material of the first release layer RL1.

[0062] Next, as shown in Figure 10, the first insulating resin portion 21, the first wiring portion 22, and the first external wiring terminal 23 are formed on the first negative direction X2 side of the first sealing portion 11. The first insulating resin portion 21 is formed by photolithography. Parts of the first wiring portion 22 and the first external wiring terminal 23 are formed by known techniques such as the semi-additive method. Furthermore, a layer mainly composed of Ni and a layer mainly composed of Au are formed on a part of the formed first external wiring terminal 23 by known methods such as electroless plating or electrolytic plating. This completes the formation of the first external wiring terminal 23.

[0063] Next, as shown in Figure 11, the semiconductor is diced along the break line DL to obtain the desired size of the semiconductor package 10. Then, the second release layer RL2 is removed by cutting.

[0064] <Regarding the effects of the first embodiment> (1-1) According to the first embodiment described above, the semiconductor package 10 has an active component 12A and a passive component 12B. These active component 12A and passive component 12B are mounted during the process of forming the semiconductor package 10. That is, with the above configuration, only active component 12A and passive component 12B that have been determined to be good in advance can be used. Therefore, it is not necessarily required to perform tests on these active component 12A and passive component 12B to determine whether they are functioning correctly after the entire semiconductor package 10 has been formed. With such a configuration, the good product rate in the semiconductor package 10 can be increased.

[0065] (1-2) In the first embodiment described above, the second layer L2, which is the first wiring layer, is laminated on the second main surface 10B of the first layer L1, which is the first component layer. By laminating the second layer L2 on the first layer L1, the second main surface 10B of the first layer L1 is covered by the second layer L2. With this configuration, the second layer L2 can mitigate external shocks acting on the active component 12A and the passive component 12B included in the first layer L1.

[0066] Furthermore, in the first embodiment described above, the third layer L3, which is the second wiring layer, is laminated on the first main surface 10A of the first layer L1, which is the first component layer. With this configuration, the impact of shocks on the active component 12A and the passive component 12B can be further suppressed.

[0067] (1-3) In the first embodiment described above, the first end of the first via wiring 14 is connected to the first electronic component 12. The second end of the first via wiring 14 is connected to the first wiring section 22 in the first wiring layer. In other words, the first via wiring 14 connects the first electronic component 12 and the first wiring section 22. With this configuration, current can be directly supplied to the first electronic component 12 from a direction perpendicular to the first main surface 10A via the first via wiring 14. In other words, the first electronic component 12 and the first wiring section 22 can be connected without requiring wiring extending parallel to the first main surface 10A and vias extending in a direction intersecting the first main surface 10A within the first layer L1.

[0068] (1-4) In the first embodiment described above, the volume fraction of Cu on the outer surface of the connection terminal 13 of the first electronic component 12 is 50 vol% or more. Also, the volume fraction of Cu in the first wiring section 22 is 50 vol% or more. In the first embodiment described above, the material of the first via wiring 14 connecting the first wiring section 22 and the connection terminal 13 is the same as the material of the first wiring section 22, and contains 50 vol% or more of Cu. That is, since the materials of the interface between the connection terminal 13 and the first via wiring 14 are the same, the connection terminal 13 and the first via wiring 14 are easily integrated. Therefore, the connection strength between the connection terminal 13 and the first via wiring 14 can be improved. Similarly, since the materials of the interface between the first wiring section 22 and the first via wiring 14 are the same, the connection strength between the first wiring section 22 and the first via wiring 14 can be improved. Therefore, the electrical connection between the first electronic component 12 and the first wiring section 22 is easily maintained.

[0069] (1-5) In the first embodiment described above, the passive component 12B contains an inorganic material. The volume fraction of the inorganic material in the passive component 12B is 50 vol% or more. Furthermore, the first sealing portion 11 covering the circumferential surface of the passive component 12B also contains an inorganic material. In other words, with this configuration, the difference between the thermal expansion coefficient of the passive component 12B and the thermal expansion coefficient of the first sealing portion 11 is not extremely large. With such a relationship between thermal expansion coefficients, the amount of deformation of these components due to temperature changes does not diverge significantly, and thus warping in the first layer L1 due to thermal deformation can be suppressed.

[0070] (1-6) In the first embodiment described above, the maximum dimension of the passive component 12B in the direction perpendicular to the first main surface 10A is greater than the maximum dimension of the active component 12A in the direction perpendicular to the first main surface 10A. That is, the thickness dimension of the passive component 12B is considerably large. Therefore, for example, if the passive component 12B is an inductor, it is easy to design a circuit that obtains the desired inductance. Similarly, if the passive component 12B is a capacitor, it is easy to design a circuit that obtains the desired capacitance.

[0071] (1-7) In the first embodiment described above, the amount of protrusion of the connection terminal 13 on the active component 12A of the first electronic component 12 is greater than the amount of protrusion of the internal terminal 13A. The large amount of protrusion of the connection terminal 13 allows the connection terminal 13 to be used as a positioning tool when placing the active component 12A in the semiconductor package manufacturing process 10. In addition, the connection terminal 13 increases the surface area of ​​the face of the first layer L1 facing the first negative direction X2, thereby improving adhesion with the second layer L2. Furthermore, the relatively small amount of protrusion of the internal terminal 13A prevents the dimension of the active component 12A itself in the direction perpendicular to the first main surface 10A from increasing.

[0072] (Second Embodiment) <About the overall structure> The second embodiment of the semiconductor package will be described below.

[0073] As shown in Figure 12, the semiconductor package 10 of the second embodiment comprises a first layer L1 and a second layer L2. The first layer L1 has a first main surface 10A and a second main surface 10B. The first main surface 10A and the second main surface 10B are the same as in the first embodiment. The first axis X, the first positive direction X1, and the first negative direction X2 are also treated the same as in the first embodiment.

[0074] The first layer L1 comprises a first component layer PT1 and two first wiring layers LN1. In the second embodiment, each first wiring layer LN1, which is a separate layer from the first component layer PT1, is embedded inside the first component layer PT1.

[0075] The first component layer PT1 includes a first sealing portion 21, a plurality of first electronic components 22, a plurality of first via connections 24, and a plurality of first component external terminals 25. The outer shape of the first sealing portion 21 is substantially rectangular parallelepiped. The two first wiring layers LN1 described above are located inside the first sealing portion 21. That is, the first wiring layers LN1 are adjacent to the first sealing portion 21 or the first electronic component 22, which is a part of the first component layer PT1, in a direction perpendicular to the first main surface 10A. The material of the first sealing portion 21 is the same as in the first embodiment. That is, the first sealing portion 21 contains an inorganic material.

[0076] In the example shown in Figure 12, the first layer L1 has three first electronic components 22. All three first electronic components 22 are active components; that is, at least one of the first electronic components 22 is an active component.

[0077] Each first electronic component 22 is located inside the first sealing portion 21. Specifically, the three first electronic components 22 are arranged in a direction parallel to the first main surface 10A. Furthermore, each first electronic component 22 is located closer to the second main surface 10B within the first layer L1. Specifically, one main surface of each first electronic component 22 is approximately flush with the second main surface 10B of the first layer L1.

[0078] Two of the three first electronic components 22 are adjacent to different first wiring layers LN1. Specifically, the first wiring layers LN1 are stacked on the first positive direction X1 side of each of the two first electronic components 22. Note that each first wiring layer LN1 is not electrically connected to the others within the first layer L1.

[0079] Each first electronic component 22 is provided with a connection terminal 26. The connection terminal 26 functions as an external terminal for connecting to external wiring, etc., of the first electronic component 22. In the example shown in Figure 12, each first electronic component 22 has a plurality of connection terminals 26. Each connection terminal 26 is exposed toward the first negative direction X2. Each connection terminal 26 is also exposed from the first sealing portion 21 on the second main surface 10B side of the first sealing portion 21. Each connection terminal 26 protrudes from the first sealing portion 21. The volume fraction of Cu on the outer surface of each connection terminal 26 is 50 vol% or more. The material of the connection terminal 26 in the second embodiment is the same as in the first embodiment.

[0080] Each first wiring layer LN1 has a first wiring section 12 and a first insulating resin section 11. Note that in Figure 12, the first wiring section 12 and the first insulating resin section 11 inside the first wiring layer LN1 are not shown. The first wiring section 12 and the first insulating resin section 11 have the same configuration as in the first embodiment. That is, the outer shape of each first insulating resin section 11 is approximately a rectangular parallelepiped. However, the dimension of each first insulating resin section 11 in the direction parallel to the first main surface 10A is smaller than the dimension of the first layer L1 in the direction parallel to the first main surface 10A. Also, the dimension of each first insulating resin section 11 in the direction perpendicular to the first main surface 10A is smaller than the dimension of the first layer L1 in the direction perpendicular to the first main surface 10A. The material of each first insulating resin section 11 is a synthetic resin containing an inorganic filler.

[0081] Each first wiring section 12 extends within each first insulating resin section 11 in an arbitrary pattern. The material of each first wiring section 12 is the same as the material of the first wiring section 12 in the first embodiment. That is, the volume fraction of Cu in the first wiring section 12 is 50 vol% or more.

[0082] Two first electronic components 22 adjacent to the first wiring layer LN1 are provided with through-wiring 23. That is, one or more selected active components are provided with through-wiring 23. Each active component is provided with two through-wiring 23. Each through-wiring 23 is substantially cylindrical. Each through-wiring 23 penetrates the active component in a direction perpendicular to the first main surface 10A. The end of each through-wiring 23 on the first positive direction X1 side is connected to the first wiring section 12 of the first wiring layer LN1. The end of each through-wiring 23 on the first negative direction X2 side is connected to the connection terminal 26.

[0083] In the cross-section shown in Figure 12, the first component layer PT1 has four first via connections 24. Each first via connection 24 is substantially cylindrical. The diameter of each first via connection 24 is greater than the diameter of each through connection 23. In other words, the maximum dimension of the through connection 23 in the direction parallel to the first main surface 10A is smaller than the maximum dimension of the first via connection 24 in the direction parallel to the first main surface 10A. Each first via connection 24 extends in a direction intersecting the first main surface 10A within the first sealing portion 21. In the second embodiment, each first via connection 24 extends in a direction perpendicular to the first main surface 10A.

[0084] Two of the four first via connections 24 extend from the first wiring layer LN1. Specifically, the first end of each first via connection 24 on the first negative direction X2 side is connected to the first wiring portion 12 of the first wiring layer LN1. The second end of each first via connection 24 on the first positive direction X1 side is exposed from the first sealing portion 21 on the first main surface 10A side.

[0085] Furthermore, the first ends of the remaining two first via connections 24 on the first negative direction X2 side are exposed from the first sealing portion 21 on the second main surface 10B side. Also, the second ends of these two first via connections 24 on the first positive direction X1 side are exposed from the first sealing portion 21 on the first main surface 10A side. In other words, the ends of the four first via connections 24 in the second embodiment are exposed from the first sealing portion 21 on the first main surface 10A side.

[0086] The first via wiring 24 contains a Cu component. The volume fraction of Cu in the first via wiring 24 is 50 vol% or more. In the second embodiment, similar to the first embodiment, the volume fraction of Cu in the first via wiring 24 is 90 vol% or more.

[0087] In the cross-section shown in Figure 12, the first layer L1 has 10 first component external terminals 25. Note that the first layer L1 may also have other first component external terminals 25 not shown in the cross-section of Figure 12. Two of these first component external terminals 25 protrude from the first negative direction X2 side of the first sealing portion 21. Each of these first component external terminals 25 is connected to the first end of a first via wiring 24 exposed from the first sealing portion 21 on the second main surface 10B side. The material of these 10 first component external terminals 25 is the same as the material of the connection terminals 26.

[0088] Furthermore, the remaining eight of the first component external terminals 25 shown in the cross-section of Figure 12 are exposed on the first positive direction X1 side of the first sealing portion 21. The circumferential surfaces of these eight first component external terminals 25 are covered by the first sealing portion 21. Four of these first component external terminals 25 are connected to the first positive direction X1 end of the first via wiring 24. The remaining four first component external terminals 25 are directly laminated on the first positive direction X1 side of the first wiring layer LN1. These first component external terminals 25 are electrically connected to the first wiring portion 12 in the first wiring layer LN1. The material of these eight first component external terminals 25 is the same as the material of the first wiring portion 12. Note that in Figure 12, only some of the first component external terminals 25 are labeled with reference numerals.

[0089] The second layer L2 is directly laminated to the first positive direction X1 side of the first layer L1. The second layer L2 comprises a second component layer PT2 and four second wiring layers LN2. Similar to the first layer L1 described above, in the second layer L2, the second wiring layers LN2, which are a separate layer from the second component layer PT2, are embedded inside the second component layer PT2.

[0090] The second component layer PT2 includes a second sealing portion 41, a plurality of second electronic components 42, and a plurality of second component external terminals 43. The outer shape of the second sealing portion 41 is approximately a rectangular parallelepiped. The four second wiring layers LN2 described above are located inside the second sealing portion 41. That is, the second wiring layers LN2 are adjacent to the second sealing portion 41 or the second electronic component 42, which is part of the second component layer PT2, in a direction perpendicular to the first main surface 10A. The material of the second sealing portion 41 is the same as the material of the first sealing portion 21. That is, the second sealing portion 41 contains an inorganic material.

[0091] In the example shown in Figure 12, the second layer L2 has five second electronic components 42. Four of the five second electronic components 42 are active components 42A. The remaining second electronic component 42 is a passive component 42B. That is, at least one of the second electronic components 42 is an active component 42A. At least one of the second electronic components 42 is a passive component 42B.

[0092] Two of the four active components 42A are arranged in a direction parallel to the first main surface 10A. A second wiring layer LN2 is laminated on the first negative direction X2 side of each of these two active components 42A. Furthermore, a second wiring layer LN2 and another active component 42A are laminated on the first positive direction X1 side of the two active components 42A. Thus, these form a laminate consisting of a total of four elements, laminated in the order of second wiring layer LN2, active component 42A, second wiring layer LN2, and active component 42A toward the first positive direction X1. Two sets of these laminates are arranged in a direction parallel to the first main surface 10A. In addition, adjacent second wiring layers LN2 and active components 42A are electrically connected to each other. However, each second wiring layer LN2 is not electrically connected to each other within the second layer L2.

[0093] Here, two active components 42A in a set of laminates stacked in the direction along the first axis X are referred to as the first active component 42A1 and the second active component 42A2, respectively. The first active component 42A1 is located on the first negative direction X2 side relative to the second active component 42A2. The first active component 42A1 and the second active component 42A2 are stacked relative to the first component layer PT1 in a direction perpendicular to the first main surface 10A. Furthermore, there are no electronic components between the first active component 42A1 and the first component layer PT1. That is, the first active component 42A1 and the second active component 42A2 are stacked relative to the first component layer PT1 in a direction perpendicular to the first main surface 10A without any other electronic components in between. The maximum dimension of the first active component 42A1 in the direction perpendicular to the first main surface 10A is the same as the maximum dimension of the second active component 42A2 in the direction perpendicular to the first main surface 10A. The thickness dimension of each active component 42A is the same.

[0094] The passive component 42B in the second electronic component 42 is positioned in a direction parallel to the first main surface 10A with respect to two sets of laminates in which the active component 42A and the second wiring layer LN2 are stacked. The passive component 42B contains an inorganic material. The volume fraction of the inorganic material in the passive component 42B is 80 vol% or more.

[0095] The maximum dimension of the passive component 42B in the direction perpendicular to the first main surface 10A is greater than the sum of the maximum dimension of the first active component 42A1 in the direction perpendicular to the first main surface 10A and the maximum dimension of the second active component 42A2 in the direction perpendicular to the first main surface 10A.

[0096] Each of the second wiring layers LN2 described above has a second wiring section 32 and a second insulating resin section 31. Note that in Figure 12, the second wiring section 32 and the second insulating resin section 31 inside the second wiring layer LN2 are not shown. The second wiring section 32 and the second insulating resin section 31 have the same configuration as the first wiring layer LN1 described above. That is, the outer shape of each second insulating resin section 31 is approximately a rectangular parallelepiped. However, since the second wiring layer LN2 is embedded in the second component layer PT2, the dimension of each second insulating resin section 31 in the direction parallel to the first main surface 10A is smaller than the dimension of the second layer L2 in the direction parallel to the first main surface 10A. Also, the dimension of each second insulating resin section 31 in the direction perpendicular to the first main surface 10A is smaller than the dimension of the second layer L2 in the direction perpendicular to the first main surface 10A. The material of each second insulating resin part 31 is a synthetic resin containing an inorganic filler.

[0097] Each second wiring section 32 extends within each second insulating resin section 31 in an arbitrary pattern. The material of each second wiring section 32 is the same as the material of the second wiring section 32. That is, the volume fraction of Cu in the second wiring section 32 is 50 vol% or more.

[0098] In the cross-section shown in Figure 12, the second layer L2 has eight second component external terminals 43. Note that the second layer L2 may also have other second component external terminals 43 not shown in the cross-section of Figure 12. Seven of the second component external terminals 43 in the cross-section shown in Figure 12 are directly laminated to the second wiring layer LN2 on the first negative direction X2 side. These seven second component external terminals 43 are electrically connected to the second wiring layer LN2. The remaining second component external terminal 43 in the cross-section shown in Figure 12 is directly laminated to the first negative direction X2 side of the passive component 42B of the second electronic component 42.

[0099] The circumferential surfaces of the eight second component external terminals 43 in the cross-section shown in Figure 12 are covered by the second sealing portion 41. Furthermore, the eight second component external terminals 43 are exposed on the first negative direction X2 side of the second sealing portion 41. That is, each second component external terminal 43 is exposed from the side of the second sealing portion 41 facing the first component layer PT1.

[0100] Furthermore, as described above, eight of the first component external terminals 25 in the cross-section shown in Figure 12 are exposed on the first positive direction X1 side of the first sealing portion 21. That is, the first component external terminals 25 are exposed from the surface of the first sealing portion 21 on the second component layer PT2 side. The first component external terminals 25 are connected to the second component external terminals 43 without any other members in between. Similarly, the first sealing portion 21 facing the first positive direction X1 is in contact with the second sealing portion 41 facing the first negative direction X2 without any other members in between.

[0101] Each component of the first layer L1 and the second layer L2 contains an inorganic material. In the second embodiment, the entire semiconductor package 10 is almost entirely made of inorganic material. Specifically, the volume fraction of inorganic material in the entire semiconductor package 10 is 90 vol% or more.

[0102] <Effects of the second embodiment> (2-1) According to the second embodiment described above, the first component layer PT1 has a first electronic component 22. The first electronic component 22 is mounted during the process of forming the semiconductor package 10. That is, with the above configuration, only first electronic components 22 that have been determined to be good in advance can be used. Therefore, it is not necessarily required to perform tests on these first electronic components 22 to determine whether or not they are functioning correctly after the entire semiconductor package 10 has been formed. With such a configuration, the good product rate in the semiconductor package 10 can be increased.

[0103] (2-2) In the second embodiment, one or more selected from the first electronic components 22 are provided with through-wiring 23. The through-wiring 23 is connected to the first wiring section 12. With this configuration, the through-wiring 23 allows current to flow inside the first electronic component 22 in a direction perpendicular to the first main surface 10A. That is, with this configuration, current can flow to the first wiring section 12 via the first electronic component 22, so there is no need to design the wiring pattern to avoid the first electronic component 22, and the complexity of the wiring pattern can be suppressed.

[0104] (2-3) In the second embodiment, the maximum dimension of each through-wiring 23 in the direction parallel to the first main surface 10A is smaller than the maximum dimension of each first via wiring 24 in the direction parallel to the first main surface 10A. With this configuration, a larger current can be passed through the first via wiring 24 than through-wiring 23. That is, a larger current can be supplied to the first component layer PT1 compared to the case where the maximum dimension of the first via wiring 24 in the direction parallel to the first main surface 10A and the maximum dimension of the through-wiring 23 in the direction parallel to the first main surface 10A are the same.

[0105] (2-4) In the second embodiment, the volume fraction of inorganic material in the passive component 42B is 80 vol% or more. Furthermore, the volume fraction of inorganic material in the entire semiconductor package 10 is 90 vol% or more. With this configuration, the coefficient of thermal expansion can be made uniform throughout the entire semiconductor package 10. Therefore, localized thermal deformation in the semiconductor package 10 can be suppressed.

[0106] (2-5) In the second embodiment, the first component external terminal 25 is connected to the second component external terminal 43 without any other components in between. In other words, the second component layer PT2 is connected to the first component layer PT1 without any other wiring such as vias. Therefore, when current flows from the first component layer PT1 to the second component layer PT2, it is possible to suppress an increase in DC resistance at the interface between these components.

[0107] (2-6) In the second embodiment, the maximum dimension of the passive component 42B in the direction perpendicular to the first main surface 10A is greater than the sum of the maximum dimension of the first active component 42A1 in the direction perpendicular to the first main surface 10A and the maximum dimension of the second active component 42A2 in the direction perpendicular to the first main surface 10A. With this configuration, for example, if the passive component 42B is an inductor, the core capacitance can be secured. Therefore, the obtainable inductance can be increased. Furthermore, with this configuration, even if a capacitor is used as the passive component, the capacitance can be increased.

[0108] <Example of changes> The first and second embodiments described above can be implemented with the following modifications. The first and second embodiments and the following modifications can be combined to the extent that they do not contradict the technical standards. In the modifications shown in Figures 13 to 15 below, explanations of parts having the same configuration as the first and second embodiments may be omitted or simplified. In Figures 13 to 15, some reference numerals may be omitted for parts having the same configuration as the first and second embodiments.

[0109] In the second embodiment, a wiring layer may be further laminated on the first component layer PT1. For example, in the example shown in Figure 13, the semiconductor package 10 includes a third layer L3. The third layer L3 is laminated on the first negative direction X2 side relative to the first layer L1. In other words, the third layer L3 is directly laminated on the second main surface 10B of the first layer L1. Therefore, the third layer L3 is adjacent to the first component layer PT1 in a direction perpendicular to the first main surface 10A.

[0110] The third layer L3 has a third insulating resin portion 51, a third wiring portion 52, and a plurality of third external wiring terminals 53. Therefore, the third layer L3 is a third wiring layer LN3 including the third wiring portion 52. The third wiring layer LN3 has the same configuration as the second wiring layer in the first embodiment.

[0111] The third insulating resin part 51 has a roughly rectangular parallelepiped shape. The material of the third insulating resin part 51 is solely organic resin. The third insulating resin part 51 covers the circumferential surfaces of the first component external terminal 25 and the connection terminal 26 that protrude from the first sealing part 21.

[0112] The third wiring section 52 is connected to the first component external terminal 25 or connection terminal 26. The third wiring section 52 extends inside the third insulating resin section 51 in an arbitrary pattern. The material of the third wiring section 52 is the same as the material of the first wiring section 12. That is, the volume fraction of Cu in the third wiring section 52 is 50 vol% or more.

[0113] Multiple third wiring external terminals 53 protrude from the third insulating resin part 51. Specifically, multiple third wiring external terminals 53 are exposed from the first negative direction X2 side of the third insulating resin part 51. The material of each third wiring external terminal 53 has a three-layer structure consisting of a layer mainly composed of Cu, a layer mainly composed of Ni, and a layer mainly composed of Au, from the first positive direction X1 side.

[0114] If the third insulating resin part 51 is composed solely of inorganic materials, a high degree of cleanliness is required in the manufacturing environment of the semiconductor package 10. In the example shown in Figure 13, the material of the third insulating resin part 51 is solely organic resin. Therefore, in the example shown in Figure 13, a higher degree of cleanliness in the manufacturing environment is not required compared to the case where the third insulating resin part 51 is composed solely of inorganic materials, and the increase in manufacturing costs can be suppressed. It should be noted that the same effect is achieved not only when the third insulating resin part 51 is composed solely of organic resin, but also when it is an organic resin containing inorganic fillers.

[0115] In a second embodiment, the semiconductor package 10 may further include a component for connecting to a motherboard. In the example shown in Figure 13, the semiconductor package 10 includes a land portion 54. The land portion 54 is made of a conductive material such as solder. The land portion 54 is applied to some of the third wiring external terminals 53. The land portion 54 covers the first negative direction X2 side surface of the third wiring external terminal 53. That is, the land portion 54 is located on the third wiring external terminal 53 that is on the side facing away from the first component layer PT1 in a direction perpendicular to the first main surface 10A of the third wiring layer LN3. The land portion 54 is a component for connecting to a motherboard mounted on the third wiring layer LN3.

[0116] With this configuration, the presence of the land portion 54 allows the wiring pattern of the third wiring portion 52 to be designed to any desired pattern. In other words, the wiring pattern of the third wiring portion 52 can be designed to be a pattern suitable in consideration of the connection between the motherboard and the first electronic component 22 in the first component layer PT1.

[0117] In the second embodiment, the sizes of the active components 42A laminated on the first component layer PT1 do not all have to be the same. In the example shown in Figure 13, the first positive direction X1 faces of the two active components 42A located furthest towards the first positive direction X1 among the active components 42A of the second component layer PT2 are exposed from the second sealing portion 41. Here, the two active components 42A in the example shown in Figure 13 are referred to as the first active component 42A1 and the second active component 42A2, respectively. The first active component 42A1 and the second active component 42A2 are laminated on the first component layer PT1 in a direction perpendicular to the first main surface 10A. In the example shown in Figure 13, the first active component 42A1 and the second active component 42A2 are laminated on the first component layer PT1 via the second wiring layer LN2 and other active components 42A. The first active component 42A1 and the second active component 42A2 are arranged in a direction parallel to the first main surface 10A, without any other electronic components in between.

[0118] Furthermore, in the example shown in Figure 13, the semiconductor package 10 comprises a third active component 42A3 and a fourth wiring layer LN4. The configuration of the fourth wiring layer LN4 is the same as that of the second wiring layer LN2 in the second embodiment. That is, the fourth wiring layer LN4 has a fourth insulating resin portion 61 and a fourth wiring portion 62. The fourth wiring portion 62 extends in an arbitrary pattern inside the fourth insulating resin portion 61.

[0119] In the example shown in Figure 13, the fourth wiring layer LN4 and the third active component 42A3 are stacked on the first component layer PT1 in a direction perpendicular to the first main surface 10A. Specifically, the third active component 42A3 is stacked on the first active component 42A1 and the second active component 42A2 via the fourth wiring layer LN4 in a direction perpendicular to the first main surface 10A. No other electronic components are interposed between the third active component 42A3 and the first active component 42A1 and the second active component 42A2. When viewed from a direction perpendicular to the first main surface 10A, the third active component 42A3 and the fourth wiring layer LN4 overlap the first active component 42A1 and the second active component 42A2. With this configuration, power is supplied to the third active component 42A3 via the first active component 42A1 and the second active component 42A2. In other words, the semiconductor package 10 includes highly integrated active components 42A.

[0120] In the second embodiment, a wiring layer may be laminated on the first component layer PT1 in the first positive direction X1. Alternatively, multiple wiring layers may be laminated on the first component layer PT1.

[0121] In the example shown in Figure 14, the second layer L2 in the second embodiment consists only of the second wiring layer LN2. Also in the example shown in Figure 14, the semiconductor package 10 includes a fourth layer L4 stacked in the first positive direction X1 relative to the second layer L2. The fourth layer L4 consists only of the fourth wiring layer LN4. Note that in the example shown in Figure 14, the semiconductor package 10 includes a third wiring layer LN3 similar to the example shown in Figure 13.

[0122] The second wiring layer LN2 includes a second insulating resin portion 31, a second wiring portion 32, and a plurality of second external wiring terminals 33. The outer shape of the second insulating resin part 31 is approximately a rectangular parallelepiped. The material of the second insulating resin part 31 is an organic resin containing an inorganic filler. The second wiring part 32 has a plurality of second columnar wirings 32B extending in a direction intersecting the first main surface 10A, and a plurality of second wirings 32A extending in a direction parallel to the first main surface 10A. Each second wiring 32A is connected to each second columnar wiring 32B. Each second columnar wiring 32B is approximately a frustoconical shape. The diameter of each second columnar wiring 32B decreases as it approaches the first positive direction X1. That is, the maximum dimension of each second columnar wiring 32B in the direction parallel to the first main surface 10A decreases as it approaches the fourth wiring layer LN4.

[0123] The second wiring section 32 extends within the second insulating resin section 31 in an arbitrary pattern. The material of the second wiring section 32 is the same as the material of the first wiring section 12. That is, the volume fraction of Cu in the second wiring section 32 is 50 vol% or more.

[0124] In the cross-section shown in Figure 14, the second wiring layer LN2 has 21 second external wiring terminals 33. The material of each second external wiring terminal 33 is the same as the material of the second wiring section 32. Ten of these second external wiring terminals 33 are located on the first negative direction X2 side relative to the second wiring section 32. The circumferential surfaces of these ten second external wiring terminals 33 are covered by the second insulating resin section 31. These ten second external wiring terminals 33 are exposed on the first negative direction X2 side of the second insulating resin section 31. These ten second external wiring terminals 33 are connected to the first external component terminal 25 without any other members in between.

[0125] The remaining 11 second external wiring terminals 33 are located on the first positive direction X1 side relative to the second wiring section 32. These 11 second external wiring terminals 33 are exposed on the first negative direction X2 side of the second insulating resin section 31. Specifically, these 11 second external wiring terminals 33 protrude in the first positive direction X1 relative to the second insulating resin section 31. That is, the second external wiring terminals 33 protrude from the surface of the second insulating resin section 31 on the fourth wiring layer LN4 side. The circumferential surfaces of these 11 second external wiring terminals 33 are not covered by any other material.

[0126] In the example shown in Figure 14, as described above, the fourth layer L4 consists only of the fourth wiring layer LN4. The fourth wiring layer LN4 has a fourth insulating resin portion 61, a fourth wiring portion 62, and a plurality of fourth external wiring terminals 63.

[0127] The outer shape of the fourth insulating resin part 61 is approximately a rectangular parallelepiped. The material of the fourth insulating resin part 61 is an organic resin containing an inorganic filler. The fourth wiring part 62 has a plurality of fourth columnar wirings 62B extending in a direction intersecting the first main surface 10A, and a plurality of fourth wirings 62A extending in a direction parallel to the first main surface 10A. Each fourth wiring 62A is connected to each fourth columnar wiring 62B. Each fourth columnar wiring 62B is approximately a frustoconical shape. The diameter of each fourth columnar wiring 62B decreases as it moves toward the first negative direction X2. That is, the maximum dimension of each fourth columnar wiring 62B in the direction parallel to the first main surface 10A decreases as it moves toward the second wiring layer LN2.

[0128] In the cross-section shown in Figure 14, the fourth wiring layer LN4 has 20 fourth wiring external terminals 63. The material of each fourth wiring external terminal 63 is the same as the material of the fourth wiring section 62. Nine of these fourth wiring external terminals 63 are located on the first positive direction X1 side relative to the fourth wiring section 62. The circumferential surfaces of these nine fourth wiring external terminals 63 are covered by the second insulating resin section 31. These nine fourth wiring external terminals 63 are exposed on the first positive direction X1 side of the fourth insulating resin section 61.

[0129] The remaining 11 fourth external wiring terminals 63 are located on the first negative direction X2 side relative to the fourth wiring section 62. These 11 fourth external wiring terminals 63 are exposed on the first negative direction X2 side of the second insulating resin section 31. Specifically, these 11 fourth external wiring terminals 63 protrude in the first negative direction X2 relative to the fourth insulating resin section 61. That is, the fourth external wiring terminals 63 protrude from the surface of the fourth insulating resin section 61 on the second wiring layer LN2 side. The circumferential surfaces of these 11 fourth external wiring terminals 63 are not covered by other members. These fourth external wiring terminals 63 are connected to the second external wiring terminals 33. The circumferential surfaces of the fourth external wiring terminals 63 and the second external wiring terminals 33 are not covered by other members. Therefore, a gap is created between the second insulating resin section 31 and the fourth insulating resin section 61.

[0130] In the example shown in Figure 14, a gap is created between the second insulating resin part 31 and the fourth insulating resin part 61. With this configuration, even if bending stress is generated in the entire semiconductor package 10, the stress can be distributed by this gap. In other words, with this configuration, it is possible to suppress the occurrence of cracks or other damage in the semiconductor package 10 due to bending stress generated in the semiconductor package 10.

[0131] Furthermore, in the example shown in Figure 14, the maximum dimension of each second columnar wiring 32B in the direction parallel to the first main surface 10A decreases as it approaches the fourth wiring layer LN4. Similarly, the maximum dimension of each fourth columnar wiring 62B in the direction parallel to the first main surface 10A decreases as it approaches the second wiring layer LN2. In other words, the shapes of the second columnar wiring 32B and the fourth columnar wiring 62B are reversed in the direction along the first axis X. If the second wiring layer LN2 and the fourth wiring layer LN4 are manufactured using the same process, the second columnar wiring 32B and the fourth columnar wiring 62B will have similar tapered shapes. On the other hand, if the second wiring layer LN2 and the fourth wiring layer LN4 are formed and then stacked on top of each other, the shapes of each columnar wiring can be reversed between the second wiring layer LN2 and the fourth wiring layer LN4. According to the above configuration, it is also possible to form each wiring layer in parallel. In other words, by forming each wiring layer in parallel, it is possible to shorten the manufacturing time.

[0132] In the second embodiment, the second component layer PT2 does not have to cover the entirety of the adjacent layer. In the example shown in Figure 14, the semiconductor package 10 includes a fifth layer L5 stacked on the first positive direction X1 side of the fourth layer L4. The fifth layer L5 has a first portion P1 and a second portion P2.

[0133] The first part P1 comprises a second component layer PT2, four fifth wiring layers LN5, and a dummy section DM. In the first part P1, the fifth wiring layers LN5, which are a separate layer from the second component layer PT2, are embedded inside the second component layer PT2.

[0134] The second component layer PT2 has a second sealing portion 41 and a plurality of second electronic components 42. The outer shape of the second sealing portion 41 is substantially rectangular parallelepiped. The four fifth wiring layers LN5 described above are located inside the second sealing portion 41. That is, the fifth wiring layers LN5 are adjacent to the second sealing portion 41 or the second electronic components 42, which are part of the second component layer PT2, in a direction perpendicular to the first main surface 10A. The material of the second sealing portion 41 is a synthetic resin containing an inorganic filler. In the example shown in Figure 14, the inorganic filler is silica. That is, the second sealing portion 41 contains an inorganic material.

[0135] In the example shown in Figure 14, the second component layer PT2 has four second electronic components 42. All of the second electronic components 42 are active components 42A. Each active component 42A is located inside the second sealing portion 41.

[0136] Two of the four second electronic components 42 are arranged in a direction parallel to the first main surface 10A. A fifth wiring layer LN5 is laminated on the first negative direction X2 side of each of these two second electronic components 42. Furthermore, on the first positive direction X1 side of one active component 42A, there is a laminate consisting of a total of six elements, with a fifth wiring layer LN5, another second electronic component 42, a fifth wiring layer LN5, and another second electronic component 42 laminated in this order. In this laminate, adjacent fifth wiring layers LN5 and second electronic components 42 are electrically connected to each other. However, each fifth wiring layer LN5 is not electrically connected to each other within the first portion P1.

[0137] Two of the three second electronic components 42 included in this laminate are equipped with four through-wirings 44. Specifically, two of the three laminated second electronic components 42, starting from the first negative direction X2 side, are equipped with four through-wirings 44. The four through-wirings 44 are arranged in a direction parallel to the first main surface 10A. Each through-wiring 44 penetrates the second electronic component 42 in a direction perpendicular to the first main surface 10A. Furthermore, each through-wiring 44 also penetrates the fifth wiring layer LN5, which is laminated on the first positive direction X1 side of the second electronic component 42, in a direction perpendicular to the first main surface 10A. The through-wirings 44 of each second electronic component 42 are connected to each other. In other words, in the laminate, each through-wiring 44 electrically connects the fifth wiring layer LN5, located furthest to the first negative direction X2 side, to the second electronic component 42 located furthest to the first positive direction X1 side.

[0138] In the example shown in Figure 14, a dummy portion DM is located on the first positive direction X1 side of the remaining unstacked second electronic component 42 among the four second electronic components 42. The dummy portion DM directly covers the entire surface of the second electronic component 42 on the first positive direction X1 side. The dummy portion DM is made of a thermally conductive synthetic resin. The dummy portion DM can efficiently absorb heat from the second electronic component 42 and dissipate it to the outside.

[0139] Each fifth wiring layer LN5 has a fifth wiring section 72 and a fifth insulating resin section 71. Note that in Figure 14, the fifth wiring section 72 and the fifth insulating resin section 71 inside the fifth wiring layer LN5 are not shown. The fifth wiring section 72 and the fifth insulating resin section 71 have the same configuration as the first wiring layer LN1. That is, the outer shape of each fifth insulating resin section 71 is approximately a rectangular parallelepiped. However, the dimension of each fifth insulating resin section 71 in the direction parallel to the first main surface 10A is smaller than the dimension of the first section P1 in the direction parallel to the first main surface 10A. Also, the dimension of each fifth insulating resin section 71 in the direction perpendicular to the first main surface 10A is smaller than the dimension of the first section P1 in the direction perpendicular to the first main surface 10A. The material of each fifth insulating resin section 71 is a synthetic resin containing an inorganic filler.

[0140] Each fifth wiring section 72 extends within each fifth insulating resin section 71 in an arbitrary pattern. The material of each fifth wiring section 72 is the same as the material of the first wiring section 12. That is, the volume fraction of Cu in the fifth wiring section 72 is 50 vol% or more.

[0141] The second portion P2 is located apart from the first portion P1 in a direction parallel to the first main surface 10A. The second portion P2 consists only of the third component layer PT3. The third component layer PT3 has a third sealing portion 81 and a plurality of third electronic components 82.

[0142] The third sealing portion 81 has a roughly rectangular parallelepiped shape. The material of the third sealing portion 81 is a synthetic resin containing an inorganic filler. However, the third sealing portion 81 contains a different inorganic filler than the second sealing portion 41. The third sealing portion 81 contains a magnetic metal filler containing the element Fe. In other words, the material of the second sealing portion 41 is different from the material of the third sealing portion 81. Note that "different materials" includes not only cases where the composition of the second sealing portion 41 and the third sealing portion 81 is different, but also cases where the particle size of the inorganic filler contained in them is different.

[0143] In the example shown in Figure 14, the third component layer PT3 has two third electronic components 82. Each third electronic component 82 is located inside the third sealing portion 81. All third electronic components 82 are passive components. The two third electronic components 82 are aligned in a direction parallel to the first main surface 10A.

[0144] As described above, the second component layer PT2 and the third component layer PT3 are stacked on the first component layer PT1 via the fourth wiring layer LN4 in a direction perpendicular to the first main surface 10A. Furthermore, the second component layer PT2 and the third component layer PT3 are aligned on the fourth wiring layer LN4 in a direction parallel to the first main surface 10A. In other words, the second component layer PT2 and the third component layer PT3 are located at the same location in a direction perpendicular to the first main surface 10A.

[0145] In the example shown in Figure 14, the second component layer PT2 and the third component layer PT3 are located in the same layer in a direction perpendicular to the first main surface 10A. That is, the second component layer PT2 and the third component layer PT3 can be formed at similar timings. In other words, this configuration allows for high-density mounting at low cost without complicating the manufacturing process.

[0146] Furthermore, in the example shown in Figure 14, the material of the second sealing portion 41 and the material of the third sealing portion 81 are different. The material of the second sealing portion 41 can be selected to match the active component. The material of the third sealing portion 81 can be selected to match the passive component. In other words, with the above configuration, a suitable material can be selected for each electronic component. In particular, as mentioned above, by using a magnetic metal filler containing Fe element in the third sealing portion 81, the inductance of the passive component can be improved, noise emission can be suppressed, and heat dissipation can be enhanced.

[0147] In the example shown in Figure 14, the shape of the second columnar wiring 32B and the shape of the fourth columnar wiring 62B may be the same. That is, both the second columnar wiring 32B and the fourth columnar wiring 62B may have a diameter that decreases as they move toward the first negative direction X2, or their diameters may decrease as they move toward the first positive direction X1.

[0148] In the example shown in Figure 14, the material of the second sealing portion 41 and the material of the third sealing portion 81 may be the same. In the example shown in Figure 14, the first portion P1 does not necessarily have a fifth wiring layer LN5.

[0149] In the example shown in Figure 14, the first part P1 does not necessarily have a dummy part DM. Furthermore, other component layers may have a dummy part DM. The same applies to the component layers of the first and second embodiments.

[0150] In the example shown in Figure 14, there does not need to be a gap between the second insulating resin part 31 and the fourth insulating resin part 61. In the example shown in Figure 15, a portion of the second external wiring terminal 33 is exposed from the surface of the second insulating resin part 31 on the LN4 side of the fourth wiring layer. The circumferential surface of the second external wiring terminal 33 is covered by the second insulating resin part 31. Also, a portion of the fourth external wiring terminal 63 is exposed from the surface of the fourth insulating resin part 61 on the LN2 side of the second wiring layer. The circumferential surface of the fourth external wiring terminal 63 is covered by the fourth insulating resin part 61. The fourth external wiring terminal 63 is connected to the second external wiring terminal 33. The circumferential surfaces of the fourth external wiring terminal 63 and the second external wiring terminal 33 are covered by the second insulating resin part 31 and the fourth insulating resin part 61, respectively. That is, the circumferential surfaces of the fourth external wiring terminal 63 and the second external wiring terminal 33 are covered with synthetic resin. In the example shown in Figure 15, the second insulating resin part 31 and the fourth insulating resin part 61 are in contact with each other.

[0151] In the example configuration shown in Figure 15, the connection between the second wiring layer LN2 and the fourth wiring layer LN4 is made not only by the external terminals but also by synthetic resin. As a result, the adhesion between the second wiring layer LN2 and the fourth wiring layer LN4 is improved.

[0152] In the example shown in Figure 15, the second external wiring terminal 33 and the synthetic resin covering the circumferential surface of the second external wiring terminal 33 are not limited to the second insulating resin portion 31 and the fourth insulating resin portion 61. For example, the second external wiring terminal 33 and the second external wiring terminal 33 may be covered with a synthetic resin such as underfill.

[0153] In the example shown in Figure 13, the third active component 42A3 may be located on the first negative direction X2 side relative to the first active component 42A1 and the second active component 42A2. For example, in the example shown in Figure 15, the third active component 42A3 is laminated on the fourth wiring layer LN4 via the fifth wiring layer LN5. The first active component 42A1 is laminated on the first positive direction X1 side relative to the third active component 42A3 via the fifth wiring layer LN5. The second active component 42A2 is also laminated on the first positive direction X1 side relative to the third active component 42A3 via the fifth wiring layer LN5. The first active component 42A1 and the second active component 42A2 are aligned in a direction parallel to the first main surface 10A. In other words, as shown in the example in Figure 15, multiple active components 42A may be stacked in a direction parallel to the first main surface 10A relative to one active component 42A.

[0154] In a second embodiment, the passive component 22B may include a through-wiring 27. In the example shown in Figure 15, at least one of the first electronic components 22 is a passive component 22B. The passive component 22B includes a through-wiring 27. The through-wiring 27 penetrates the passive component 22B in a direction perpendicular to the first main surface 10A. The through-wiring 27 is substantially cylindrical. The maximum dimension of the through-wiring 27 in the direction parallel to the first main surface 10A is smaller than the maximum dimension of the first via wiring 24 in the direction parallel to the first main surface 10A. Also, the maximum dimension of the through-wiring 27 in the passive component 22B in the direction parallel to the first main surface 10A is larger than the maximum dimension of the through-wiring 23 in the active component 22A in the direction parallel to the first main surface 10A.

[0155] In the example shown in Figure 15, the maximum dimension of the through-wiring 27 in the passive component 22B in the direction parallel to the first main surface 10A may be the same as or larger than the maximum dimension of the first via wiring 24 in the direction parallel to the first main surface 10A. Also, the maximum dimension of the through-wiring 27 in the passive component 22B in the direction parallel to the first main surface 10A may be the same as or smaller than the maximum dimension of the through-wiring 23 in the active component 22A in the direction parallel to the first main surface 10A.

[0156] In the first embodiment, the connection terminal 13 of the first electronic component 12 may have a multi-layer structure. For example, the connection terminal 13 may include layers mainly composed of Ni, Sn, Au, etc. However, in order to achieve the effects described in (1-4) above, it is preferable that the volume fraction of Cu on the outer surface of each connection terminal 13 is 50 vol% or more. Alternatively, the volume fraction of Cu on the outer surface of the connection terminal 13 may be less than 50 vol%.

[0157] In the first embodiment, the volume fraction of Cu in the first wiring section 22 may be less than 50 vol%. Alternatively, Ag, Al, and Au may be used instead of Cu in the first wiring section 22. The same applies to the wiring sections of each wiring layer. The same also applies to the wiring sections of each wiring layer in the second embodiment.

[0158] In the first embodiment, the shape of the first columnar wiring 22B is not limited to a frustoconical shape. For example, it may be cylindrical or prismatic. The same applies to other columnar wiring.

[0159] In the first embodiment, the first component layer only needs to have at least one active component. The semiconductor package 10 only needs to have at least one passive component and one active component. The same applies to the second embodiment.

[0160] In the first embodiment, the first component layer only needs to have at least one first via wiring 14. Furthermore, if the first component layer has the first via wiring 14, the other component layers do not need to have via wiring. The same applies to the component layers in the second embodiment.

[0161] In the first embodiment, the maximum dimension of the passive component 12B in the direction perpendicular to the first main surface 10A may be the same as or smaller than the maximum dimension of the active component 12A in the direction perpendicular to the first main surface 10A.

[0162] In the first embodiment, the volume fraction of inorganic material in the passive component 12B is not limited to the example of the first embodiment. That is, the volume fraction of inorganic material in the passive component 12B may be less than 50 vol%. The same applies to other passive components. The same also applies to the passive component 42B in the second embodiment.

[0163] In the first embodiment, the amount of protrusion of the connection terminal 13 may be less than the amount of protrusion of the internal terminal 13A. Also, the internal terminal 13A may protrude in the first positive direction X1 from the surface of the component body 12M on the first positive direction X1 side, or it may be recessed on the first negative direction X2 side.

[0164] In the second embodiment, the end of the through-wiring 23 on the first positive direction X1 side may be connected to the first via wiring 24. That is, the through-wiring 23 may be directly connected to the first via wiring 24 without going through the first wiring section 12. Also, if the first positive direction X1 side of the first electronic component 22 faces the first component external terminal 25, the end of the through-wiring 23 on the first positive direction X1 side may be connected to the first component external terminal 25. Furthermore, in the second embodiment, the first electronic component 22 does not have to have the through-wiring 23. Also, the second electronic component 42 may have the through-wiring.

[0165] In the second embodiment, the dimensional relationship between the through-wiring 23 and the first via wiring 24 is not limited to the second embodiment. The maximum dimension of the through-wiring 23 in the direction parallel to the first main surface 10A may be the same as or greater than the maximum dimension of the first via wiring 24 in the direction parallel to the first main surface 10A.

[0166] In the second embodiment, the position of the first wiring layer LN1 is not limited to the example of the second embodiment, as long as the first wiring layer LN1 is adjacent to the first component layer PT1 in a direction perpendicular to the first main surface 10A. For example, the first wiring layer LN1 may be laminated on the first negative direction X2 side with respect to the first electronic component 22.

[0167] In the second embodiment, the volume ratio of inorganic material in the entire semiconductor package 10 may be less than 90 vol%. In the second embodiment, the dimensional relationship between the active component 42A and the passive component 42B in the second electronic component 42 is not limited to the example of the second embodiment. For example, the maximum dimension of the passive component 42B in the direction perpendicular to the first main surface 10A may be the same as or smaller than the sum of the maximum dimension of the first active component 42A1 in the direction perpendicular to the first main surface 10A and the maximum dimension of the second active component 42A2 in the direction perpendicular to the first main surface 10A.

[0168] In the second embodiment, other wiring layers may be located between the first layer L1 and the second layer L2. That is, other members may be interposed between the first component external terminal 25 and the second component external terminal 43.

[0169] <Note> The technical concepts that can be derived from the above embodiments and modifications are described below. [1] A semiconductor package having passive and active components, comprising: a first component layer having a first main surface and a second main surface opposite to the first main surface; and a first wiring layer adjacent to the first component layer in a direction perpendicular to the first main surface, wherein the first component layer comprises a first sealing portion containing an inorganic material, at least one of the active components located inside the first sealing portion, and a plurality of first via wirings extending inside the first sealing portion in a direction intersecting the first main surface, with their ends exposed from the first sealing portion on the first main surface; and the first wiring layer comprises a first insulating resin portion and a first wiring portion extending inside the first insulating resin portion, wherein the connection terminals of the active components are exposed from the first sealing portion on the second main surface side of the first sealing portion.

[0170] [2] The semiconductor package according to [1], wherein the first wiring layer is laminated on the first main surface or the second main surface of the first component layer. [3] The semiconductor package according to [2], wherein the first wiring layer is laminated on the first main surface of the first component layer, the first end of the first via wiring is connected to the active component, and the second end of the first via wiring is connected to the first wiring portion in the first wiring layer.

[0171] [4] The semiconductor package according to [2] or [3], wherein the first wiring layer has a first external wiring terminal on a surface facing away from the first component layer in a direction perpendicular to the first main surface, and the first external wiring terminal has a land portion for connecting a mother board mounted on the first wiring layer.

[0172] [5] A semiconductor package according to [2] or [3], comprising a second wiring layer laminated on the first wiring layer in a direction perpendicular to the first main surface, wherein the second wiring layer comprises a second insulating resin portion and a second wiring portion extending inside the second insulating resin portion, the first wiring layer has a first external wiring terminal protruding from the surface of the first insulating resin portion on the side of the second wiring layer, the second wiring layer has a second external wiring terminal protruding from the surface of the second insulating resin portion on the side of the first wiring layer and connected to the first external wiring terminal, and a gap is created between the first insulating resin portion and the second insulating resin portion.

[0173] [6] A semiconductor package according to [2] or [3], comprising a second wiring layer laminated with respect to the first wiring layer in a direction perpendicular to the first main surface, wherein the second wiring layer comprises a second insulating resin portion and a second wiring portion extending inside the second insulating resin portion, the first wiring layer has a first external wiring terminal exposed from the surface of the first insulating resin portion on the side of the second wiring layer, the second wiring layer has a second external wiring terminal exposed from the surface of the second insulating resin portion on the side of the first wiring layer and connected to the first external wiring terminal, and the circumferential surfaces of the first external wiring terminal and the second external wiring terminal are covered with a synthetic resin.

[0174] [7] The semiconductor package according to [5] or [6], wherein the first wiring section has a first columnar wiring extending in a direction intersecting the first main surface and a first wiring connected to the first columnar wiring and extending in a direction parallel to the first main surface, the maximum dimension of the first columnar wiring in the direction parallel to the first main surface decreasing as it approaches the second wiring layer, and the second wiring section has a second columnar wiring extending in a direction intersecting the first main surface and a second wiring connected to the second columnar wiring and extending in a direction parallel to the first main surface, the maximum dimension of the second columnar wiring in the direction parallel to the first main surface decreasing as it approaches the first wiring layer.

[0175] [8] The semiconductor package according to any one of [1] to [7], wherein the first insulating resin part is an organic resin. [9] The semiconductor package according to any one of [1] to [8], wherein the volume fraction of Cu on the outer surface of the connection terminal of the active component located inside the first sealing portion is 50 vol% or more, and the volume fraction of Cu in the first wiring portion is 50 vol% or more.

[0176]

[10] One or more of the active components located inside the first sealing portion are provided with through wiring that penetrates the active component in a direction perpendicular to the first main surface, and the through wiring is connected to the first wiring portion or the first via wiring, according to any one of [1] to [9].

[0177]

[11] The semiconductor package according to

[10] , wherein the maximum dimension of the through-wiring in the direction parallel to the first main surface is smaller than the maximum dimension of the first via wiring in the direction parallel to the first main surface.

[12] The semiconductor package according to any one of [1] to

[11] , wherein the passive component includes an inorganic material, and the volume fraction of the inorganic material in the passive component is 50 vol% or more.

[0178]

[13] The semiconductor package according to

[12] , wherein the volume fraction of the inorganic material in the passive component is 80 vol% or more, and the volume fraction of the inorganic material in the entire semiconductor package is 90 vol% or more.

[0179]

[14] The maximum dimension of the passive component in the direction perpendicular to the first main surface is greater than the maximum dimension of the active component in the direction perpendicular to the first main surface. [1] to

[13] The semiconductor package according to any one of these.

[0180]

[15] A semiconductor package according to any one of [1] to

[14] , comprising a second component layer laminated on the first component layer in a direction perpendicular to the first main surface, wherein the second component layer has a second sealing portion containing an inorganic material, at least one active component located inside the second sealing portion, and a second component external terminal exposed from the side of the second sealing portion facing the first component layer, and the first component layer has a first component external terminal exposed from the side of the first sealing portion facing the second component layer, and the first component external terminal is connected to the second component external terminal without any other member in between.

[0181]

[16] A semiconductor package according to any one of [1] to

[15] , comprising a first active component, a second active component, and a third active component stacked on a first component layer in a direction perpendicular to the first main surface, wherein the first active component and the second active component are arranged in a direction parallel to the first main surface without other electronic components in between, and the third active component is stacked on the first active component and the second active component in a direction perpendicular to the first main surface without other electronic components in between, and when viewed from a direction perpendicular to the first main surface, the third active component overlaps the first active component and the second active component.

[0182]

[17] A semiconductor package according to any one of [1] to

[16] , comprising a first active component, a second active component, and at least one passive component, which are stacked on the first component layer in a direction perpendicular to the first main surface, wherein the first active component and the second active component are stacked on the first component layer in a direction perpendicular to the first main surface without any other electronic components in between, and the maximum dimension of the passive component in the direction perpendicular to the first main surface is greater than the sum of the maximum dimension of the first active component in the direction perpendicular to the first main surface and the maximum dimension of the second active component in the direction perpendicular to the first main surface.

[0183]

[18] A semiconductor package according to any one of [1] to

[17] , comprising a second component layer and a third component layer stacked on the first component layer in a direction perpendicular to the first main surface, wherein the second component layer has a second sealing portion containing an inorganic material and at least one active component located inside the second sealing portion, and the third component layer has a third sealing portion containing an inorganic material and at least one passive component located inside the third sealing portion, and the second component layer and the third component layer are located at the same location in a direction perpendicular to the first main surface.

[0184]

[19] The semiconductor package according to

[18] , wherein the material of the second sealing portion is different from the material of the third sealing portion.

[20] The semiconductor package according to any one of [1] to

[19] , wherein the active component located inside the first sealing portion comprises a component body, a connection terminal protruding from the component body, and an internal terminal exposed from the component body on the opposite side of the connection terminal in a direction perpendicular to the first main surface, wherein the amount of protrusion of the connection terminal is greater than the amount of protrusion of the internal terminal. [Explanation of symbols]

[0185] L1…1st layer L2…Second layer 10… Semiconductor packages 10A...First main surface 10B...Second main surface 11...First sealing section 12A... Active component 12B... Passive components 13…Connection terminals 14…First via wiring 21...First insulating resin part 22...1st wiring section

Claims

1. A semiconductor package having passive and active components, The device comprises: a first component layer having a first main surface and a second main surface opposite to the first main surface; a first wiring layer laminated on the first main surface or the second main surface of the first component layer; and a second wiring layer laminated on the first wiring layer in a direction perpendicular to the first main surface. The first component layer is, A first sealing part containing an inorganic material, At least one of the active components located inside the first sealing portion, A plurality of first via wirings extending within the first sealing portion in a direction intersecting the first main surface, with their ends exposed from the first sealing portion on the first main surface, It has, The first wiring layer is, First insulating resin part, The first wiring portion extends inside the first insulating resin portion, The first insulating resin portion has a first external wiring terminal that protrudes from the surface on the second wiring layer side, The aforementioned second wiring layer is The second insulating resin part, The second wiring portion extends inside the second insulating resin portion, The second insulating resin portion has a second external wiring terminal that protrudes from the surface on the first wiring layer side and connects to the first external wiring terminal, The connection terminals of the active component are exposed from the first sealing portion on the second main surface side of the first sealing portion. A gap is formed between the first insulating resin part and the second insulating resin part. Semiconductor package.

2. A semiconductor package having passive and active components, The device comprises: a first component layer having a first main surface and a second main surface opposite to the first main surface; a first wiring layer laminated on the first main surface or the second main surface of the first component layer; and a second wiring layer laminated on the first wiring layer in a direction perpendicular to the first main surface. The first component layer is, A first sealing part containing an inorganic material, At least one of the active components located inside the first sealing portion, A plurality of first via wirings extending within the first sealing portion in a direction intersecting the first main surface, with their ends exposed from the first sealing portion on the first main surface, It has, The first wiring layer is, First insulating resin part, The first wiring portion extends inside the first insulating resin portion, The first insulating resin portion has a first wiring external terminal exposed from the surface on the second wiring layer side, The aforementioned second wiring layer is The second insulating resin part, The second wiring portion extends inside the second insulating resin portion, The second insulating resin portion has a second external wiring terminal that is exposed from the surface on the first wiring layer side and connects to the first external wiring terminal, The connection terminals of the active component are exposed from the first sealing portion on the second main surface side of the first sealing portion. The circumferential surfaces of the first external wiring terminal and the second external wiring terminal are covered with synthetic resin. Semiconductor package.

3. The first wiring layer is laminated on the first main surface of the first component layer. The first end of the first via wiring is connected to the active component, and the second end of the first via wiring is connected to the first wiring section in the first wiring layer. The semiconductor package according to claim 1 or claim 2.

4. The first wiring layer has a first external wiring terminal on the surface facing away from the first component layer in a direction perpendicular to the first main surface. The first external wiring terminal is provided with a land portion for connecting the motherboard mounted on the first wiring layer. The semiconductor package according to claim 1 or claim 2.

5. The first wiring section includes a first columnar wiring extending in a direction intersecting the first main surface, and a first wiring connected to the first columnar wiring and extending in a direction parallel to the first main surface. The first columnar wiring has a maximum dimension in the direction parallel to the first main surface that decreases as it approaches the second wiring layer. The second wiring section includes a second columnar wiring extending in a direction intersecting the first main surface, and a second wiring connected to the second columnar wiring and extending in a direction parallel to the first main surface. The second columnar wiring has a maximum dimension in the direction parallel to the first main surface that decreases as it approaches the first wiring layer. The semiconductor package according to claim 1 or claim 2.

6. The first insulating resin part is an organic resin. The semiconductor package according to claim 1 or claim 2.

7. On the outer surface of the connection terminal of the active component located inside the first sealing portion, the volume fraction of Cu is 50 vol% or more. In the first wiring section, the volume fraction of Cu is 50 vol% or more. The semiconductor package according to claim 1 or claim 2.

8. One or more of the active components located inside the first sealing portion are provided with through wiring that penetrates the active component in a direction perpendicular to the first main surface. The through-wiring is connected to the first wiring section or the first via wiring. The semiconductor package according to claim 1 or claim 2.

9. The maximum dimension of the through-wiring in the direction parallel to the first main surface is smaller than the maximum dimension of the first via wiring in the direction parallel to the first main surface. The semiconductor package according to claim 8.

10. The aforementioned passive component includes an inorganic material, The volume fraction of the inorganic material in the passive component is 50 vol% or more. The semiconductor package according to claim 1 or claim 2.

11. The volume fraction of the inorganic material in the passive component is 80 vol% or more. Furthermore, the volume fraction of inorganic materials in the entire semiconductor package is 90 vol% or more. The semiconductor package according to claim 10.

12. The maximum dimension of the passive component in the direction perpendicular to the first main surface is greater than the maximum dimension of the active component in the direction perpendicular to the first main surface. The semiconductor package according to claim 1 or claim 2.

13. A semiconductor package having passive and active components, The device comprises a first component layer having a first main surface and a second main surface opposite to the first main surface, a second component layer laminated to the first component layer in a direction perpendicular to the first main surface, and a first wiring layer adjacent to the first component layer in a direction perpendicular to the first main surface. The first component layer is, A first sealing part containing an inorganic material, At least one of the active components located inside the first sealing portion, A plurality of first via wirings extending within the first sealing portion in a direction intersecting the first main surface, with their ends exposed from the first sealing portion on the first main surface, The first component external terminal exposed from the side of the second component layer in the first sealing portion, It has, The aforementioned second component layer is A second sealing part containing an inorganic material, At least one of the active components located inside the second sealing portion, The second component external terminal exposed from the surface on the first component layer side of the second sealing portion, It has, The first wiring layer is, First insulating resin part, It has a first wiring portion extending inside the first insulating resin portion, The connection terminals of the active component are exposed from the first sealing portion on the second main surface side of the first sealing portion. The external terminal of the first component is connected to the external terminal of the second component without any other components in between. Semiconductor package.

14. A semiconductor package having passive and active components, The device comprises: a first component layer having a first main surface and a second main surface opposite to the first main surface; a first wiring layer adjacent to the first component layer in a direction perpendicular to the first main surface; and a first active component, a second active component, and a third active component laminated relative to the first component layer in a direction perpendicular to the first main surface. The first component layer is, A first sealing part containing an inorganic material, At least one of the active components located inside the first sealing portion, A plurality of first via wirings extending within the first sealing portion in a direction intersecting the first main surface, with their ends exposed from the first sealing portion on the first main surface, It has, The first wiring layer is, First insulating resin part, It has a first wiring portion extending inside the first insulating resin portion, The connection terminals of the active component are exposed from the first sealing portion on the second main surface side of the first sealing portion. The first active component and the second active component are arranged in a direction parallel to the first main surface without any other electronic components in between. The third active component is stacked on the first active component and the second active component in a direction perpendicular to the first main surface, without any other electronic components in between. When viewed from a direction perpendicular to the first main surface, the third active component overlaps the first active component and the second active component. Semiconductor package.

15. A semiconductor package having passive and active components, The device comprises: a first component layer having a first main surface and a second main surface opposite to the first main surface; a first wiring layer adjacent to the first component layer in a direction perpendicular to the first main surface; and a first active component, a second active component, and at least one of the passive components laminated relative to the first component layer in a direction perpendicular to the first main surface. The first component layer is, A first sealing part containing an inorganic material, At least one of the active components located inside the first sealing portion, A plurality of first via wirings extending within the first sealing portion in a direction intersecting the first main surface, with their ends exposed from the first sealing portion on the first main surface, It has, The first wiring layer is, First insulating resin part, It has a first wiring portion extending inside the first insulating resin portion, The connection terminals of the active component are exposed from the first sealing portion on the second main surface side of the first sealing portion. The first active component and the second active component are stacked on the first component layer in a direction perpendicular to the first main surface, without any other electronic components in between. The maximum dimension of the passive component in the direction perpendicular to the first main surface is greater than the sum of the maximum dimension of the first active component in the direction perpendicular to the first main surface and the maximum dimension of the second active component in the direction perpendicular to the first main surface. Semiconductor package.

16. A semiconductor package having passive and active components, The device comprises: a first component layer having a first main surface and a second main surface opposite to the first main surface; a second component layer and a third component layer stacked on the first component layer in a direction perpendicular to the first main surface; and a first wiring layer adjacent to the first component layer in a direction perpendicular to the first main surface. The first component layer is, A first sealing part containing an inorganic material, At least one of the active components located inside the first sealing portion, A plurality of first via wirings extending within the first sealing portion in a direction intersecting the first main surface, with their ends exposed from the first sealing portion on the first main surface, It has, The aforementioned second component layer is A second sealing part containing an inorganic material, At least one of the active components located inside the second sealing portion, It has, The aforementioned third component layer is A third sealing portion containing an inorganic material, and at least one of the passive components located inside the third sealing portion, It has, The first wiring layer is, First insulating resin part, It has a first wiring portion extending inside the first insulating resin portion, The connection terminals of the active component are exposed from the first sealing portion on the second main surface side of the first sealing portion. The second component layer and the third component layer are located at the same location in a direction perpendicular to the first main surface. Semiconductor package.

17. The material of the second sealing portion is different from the material of the third sealing portion. The semiconductor package according to claim 16.

18. The active component located inside the first sealing portion is The main part and, The connection terminal protruding from the main body of the component, An internal terminal exposed from the component body on the opposite side of the connection terminal in a direction perpendicular to the first main surface, It has, The amount of protrusion of the aforementioned connection terminal is greater than the amount of protrusion of the aforementioned internal terminal. A semiconductor package according to any one of claims 1, 2, 13, 14, 15, and 16.

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