memory devices

Abstract

To provide a memory device capable of executing efficient reading operations.SOLUTION: A memory device of an embodiment includes a plurality of memory cells, a word line, and a controller. Each of the plurality of memory cells stores 5 bit data including first to fifth bit data according to a threshold voltage. The plurality of memory cells stores first to fifth pages including the first to fifth bit data, respectively. The word line is connected to the plurality of memory cells. The controller executes reading operations for reading data from the plurality of memory cells by applying the reading voltage to the word line. The number of times the controller applies different read voltages to the word lines in the respective reading operations of the first to fifth pages is 7, 6, 6, 6, and 6, respectively.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] Embodiments relate to a memory device.

Background Art

[0002] NAND type flash memories capable of storing data non-volatilely are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a memory device capable of performing an efficient read operation.

Means for Solving the Problems

[0005] The memory device of the embodiment includes a plurality of memory cells, a word line, and a controller. Each of the plurality of memory cells stores 5-bit data, including 1st bit data, 2nd bit data, 3rd bit data, 4th bit data, and 5th bit data, depending on the threshold voltage. The plurality of memory cells store pages 1, 2, 3, 4, and 5, each containing 1st bit data, 2nd bit data, 3rd bit data, 4th bit data, and 5th bit data, respectively. The word line is connected to the plurality of memory cells. The controller performs read operations. The threshold voltage of the memory cells is located in one of three distinct states, from state 0 to state 31. Each of states, from state 0 to state 31, is assigned a different 5-bit data. The first read voltage to the 31st read voltage are set in order from the lowest voltage, corresponding to the relationship between adjacent states among states 0 to state 31. In the first page read operation, the controller performs six reads, applying the 7th read voltage, 15th read voltage, 18th read voltage, 22nd read voltage, 25th read voltage, and 29th read voltage to the word line, respectively. In the second page read operation, the controller performs six reads, applying the 4th read voltage, 8th read voltage, 13th read voltage, 21st read voltage, 27th read voltage, and 31st read voltage to the word line, respectively. In the third page read operation, the controller performs six reads, applying the 3rd read voltage, 9th read voltage, 12th read voltage, 16th read voltage, 20th read voltage, and 26th read voltage to the word line, respectively. In the fourth page read operation, the controller performs seven reads, applying the 2nd read voltage, 6th read voltage, 10th read voltage, 14th read voltage, 19th read voltage, 23rd read voltage, and 28th read voltage to the word line, respectively. In the read operation on page 5, the controller performs six reads, applying the first read voltage, fifth read voltage, eleventh read voltage, seventeenth read voltage, twenty-fourth read voltage, and thirtyth read voltage to the word line, respectively. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of an information processing system according to the first embodiment. [Figure 2] A block diagram showing an example of the hardware configuration of the memory controller according to the first embodiment. [Figure 3] A block diagram showing an example of the hardware configuration of a memory device according to the first embodiment. [Figure 4] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the first embodiment. [Figure 5] A circuit diagram showing an example of the circuit configuration of a low decoder module included in a memory device according to the first embodiment. [Figure 6] A circuit diagram showing an example of the circuit configuration of a sense amplifier module included in a memory device according to the first embodiment. [Figure 7] A schematic diagram showing an example of the threshold voltage distribution of a memory cell transistor in a memory device according to the first embodiment. [Figure 8] A table showing the data allocation and read voltage settings used in the memory device according to the first embodiment. [Figure 9] A timing chart showing an example of first page readout in the memory system according to the first embodiment. [Figure 10] A timing chart showing an example of second page readout in the memory system according to the first embodiment. [Figure 11] A timing chart showing an example of reading the third page in the memory system according to the first embodiment. [Figure 12] A timing chart showing an example of reading the fourth page in the memory system according to the first embodiment. [Figure 13] A timing chart showing an example of reading the fifth page in the memory system according to the first embodiment. [Figure 14]Table showing the data assignment and read voltage setting of the first modification example. [Figure 15] Waveform diagram showing an example of the voltage applied to the selected word line in the read operation of the first modification example. [Figure 16] Table showing the data assignment and read voltage setting of the second modification example. [Figure 17] Waveform diagram showing an example of the voltage applied to the selected word line in the read operation of the second modification example. [Figure 18] Table showing the data assignment and read voltage setting of the third modification example. [Figure 19] Waveform diagram showing an example of the voltage applied to the selected word line in the read operation of the third modification example. [[ID=1,7]] [Figure 20] Table showing the data assignment and read voltage setting of the fourth modification example. [Figure 21] Waveform diagram showing an example of the voltage applied to the selected word line in the read operation of the fourth modification example. [Figure 22] Table showing the data assignment and read voltage setting of the fifth modification example. [Figure 23] Waveform diagram showing an example of the voltage applied to the selected word line in the read operation of the fifth modification example. [Figure 24] Table showing the data assignment and read voltage setting of the sixth modification example. [Figure 25] Table showing the data assignment and read voltage setting of the seventh modification example. [Figure 26] Table showing the data assignment and read voltage setting of the eighth modification example. [Figure 27] Table showing the data assignment and read voltage setting of the ninth modification example. <oo00092>Table showing the data assignment and read voltage setting of the tenth modification example. [Figure 29] Table showing the data assignment and read voltage setting of the eleventh modification example. [Figure 30]Table showing the data assignment and read voltage setting of the 12th modification example. [Figure 31] Table showing the data assignment and read voltage setting of the 13th modification example. [Figure 32] Table showing the data assignment and read voltage setting of the 14th modification example. [Figure 33] Table showing the data assignment and read voltage setting of the 15th modification example. [Figure 34] Table showing the data assignment and read voltage setting of the 16th modification example. [Figure 35] Table showing the data assignment and read voltage setting of the 17th modification example. [Figure 36] Table showing the data assignment and read voltage setting of the 18th modification example. [Figure 37] Table showing the data assignment and read voltage setting of the 19th modification example. [Figure 38] Table showing the data assignment and read voltage setting of the 20th modification example. [Figure 39] Table showing the data assignment and read voltage setting of the 21st modification example. [Figure 40] Table showing the data assignment and read voltage setting of the 22nd modification example. [Figure 41] Table showing the data assignment and read voltage setting of the 23rd modification example. <on [Figure 42] Table showing the data assignment and read voltage setting of the 24th modification example. [Figure 43] Table showing the data assignment and read voltage setting of the 25th modification example. [Figure 44] Table showing the data assignment and read voltage setting of the 26th modification example. [Figure 45] Table showing the data assignment and read voltage setting of the 27th modification example. [Figure 46] Table showing the data assignment and read voltage setting of the 28th modification example. [Figure 47] A table showing the data allocation and readout voltage settings for the 29th variation. [Figure 48] A table showing the data allocation and readout voltage settings for the 30th variation. [Figure 49] A table showing the data allocation and readout voltage settings for the 31st variation. [Figure 50] A table showing the data allocation and readout voltage settings for the 32nd variation. [Figure 51] A table showing the data allocation and readout voltage settings for the 33rd variation. [Figure 52] A table showing the data allocation and readout voltage settings for the 34th variation. [Figure 53] A table showing the data allocation and readout voltage settings for the 35th variation. [Figure 54] A table showing the data allocation and readout voltage settings for the 36th variation. [Figure 55] A table showing the data allocation and readout voltage settings for the 37th modified example. [Figure 56] A table showing the data allocation and readout voltage settings for the 38th variation. [Figure 57] A table showing the data allocation and readout voltage settings for the 39th modified example. [Figure 58] A table showing the data allocation and readout voltage settings for the 40th variation. [Figure 59] A table showing the data allocation and readout voltage settings for the 41st variation. [Figure 60] A table showing the data allocation and readout voltage settings for the 42nd variation. [Figure 61] A table showing the data allocation and readout voltage settings for the 43rd variation. [Figure 62] A table showing the data allocation and readout voltage settings for the 44th variation. [Figure 63]A table showing the data allocation and readout voltage settings for the 45th variation. [Figure 64] A table showing the data allocation and readout voltage settings for the 46th variation. [Figure 65] A table showing the data allocation and readout voltage settings for the 47th variation. [Figure 66] A table showing the data allocation and readout voltage settings for the 48th variation. [Figure 67] A table showing the data allocation and readout voltage settings for the 49th variation. [Figure 68] A table showing the data allocation and readout voltage settings for the 50th variation. [Figure 69] A table showing the data allocation and readout voltage settings for variation 51. [Figure 70] A table showing the data allocation and readout voltage settings for variation 52. [Figure 71] A table showing the data allocation and readout voltage settings for the 53rd variation. [Figure 72] A timing chart showing an example of first page readout in the memory system according to the second embodiment. [Figure 73] A timing chart showing an example of sequential reads in a memory system according to the third embodiment. [Figure 74] A plan view showing an example of the circuit layout of a memory device related to a comparative example. [Figure 75] A plan view showing an example of the circuit arrangement of a memory device according to the fourth embodiment. [Figure 76] A plan view showing an example of the circuit arrangement of a memory device according to a modified example of the fourth embodiment. [Figure 77] A schematic diagram showing a first configuration example of a sense amplifier module in a memory device according to the fourth embodiment. [Figure 78] A schematic diagram showing a second configuration example of a sense amplifier module in a memory device according to the fourth embodiment. [Figure 79]A plan view showing an example of the circuit arrangement of a memory device according to the fifth embodiment. [Figure 80] A schematic diagram showing a first configuration example of a sense amplifier set and a latch set in a memory device according to the fifth embodiment. [Figure 81] A schematic diagram showing a second configuration example of a sense amplifier set and a latch set in a memory device according to the fifth embodiment. [Figure 82] A schematic diagram showing a third configuration example of a sense amplifier set and a latch set in a memory device according to the fifth embodiment. [Figure 83] A schematic diagram showing a fourth configuration example of a sense amplifier set and a latch set in a memory device according to the fifth embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. Each embodiment illustrates an apparatus or method for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions and proportions in each drawing are not necessarily the same as those in reality. In the following description, components having substantially the same function and configuration are denoted by the same reference numeral. The numbers following the letters that make up the reference numerals are used to distinguish elements that are referenced by reference numerals containing the same letters and have similar configurations.

[0008] [1] First Embodiment The first embodiment will be described below.

[0009] [1-1] Composition [1-1-1] Configuration of Information Processing System 1 Figure 1 is a block diagram showing an example of the configuration of an information processing system 1 according to the first embodiment. As shown in Figure 1, the information processing system 1 includes, for example, a host device HD and a memory system MS. The host device HD is an electronic device such as a personal computer, a portable information terminal, or a server. The memory system MS is a storage medium such as a memory card or an SSD (solid state drive). The memory system MS includes, for example, a memory controller 10 and a memory device 20.

[0010] The memory controller 10 is, for example, a semiconductor integrated circuit configured as a System On a Chip (SoC). The memory controller 10 is connected to the host device HD via the host bus HB. The memory controller 10 is connected to the memory device 20 via the memory bus MB. The memory controller 10 controls the memory device 20 based on instructions received from the host device HD. For example, the memory controller 10 controls the memory device 20 to perform read operations, write operations, erase operations, etc.

[0011] Memory device 20 is a semiconductor memory device that stores data non-volatilely. Memory device 20 is, for example, a NAND flash memory. In NAND flash memory, the unit of data reading and writing is called a "page". Memory device 20 includes a plurality of memory cell transistors MT, a plurality of bit lines BL, and a plurality of word lines WL. Each memory cell transistor MT is associated with one bit line BL and one word line WL. Each bit line BL is assigned a column address. Each word line WL is assigned a page address.

[0012] [1-1-2] Hardware configuration of the memory controller 10 Figure 2 is a block diagram showing an example of the hardware configuration of the memory controller 10 according to the first embodiment. As shown in Figure 2, the memory controller 10 includes, for example, a host interface (host I / F) 11, a memory interface (memory I / F) 12, a CPU (Central Processing Unit) 13, an ECC (Error Correction Code) circuit 14, a ROM (Read Only Memory) 15, a RAM (Random Access Memory) 16, and a buffer memory 17.

[0013] The host I / F11 is a hardware interface that conforms to the interface standard between the host device HD and the memory controller 10. The host I / F11 is connected to the host device HD via the host bus HB. The host I / F11 is, for example, SATA (Serial Advanced Technology Attachment), PCIe TM It supports interface standards such as PCI Express.

[0014] The memory interface 12 is a hardware interface that conforms to the interface standard between the memory controller 10 and the memory device 20. The memory interface 12 is connected to the memory device 20 via the memory bus MB. The memory interface 12 supports, for example, the NAND interface standard.

[0015] The CPU 13 is a processor that controls the overall operation of the memory controller 10. The CPU 13 instructs the memory device 20 via the memory interface 12 to write data in accordance with a write request received via the host interface 11. The CPU 13 also instructs the memory device 20 via the memory interface 12 to read data in accordance with a read request received via the host interface 11.

[0016] The ECC circuit 14 is a circuit that performs ECC processing. ECC processing includes data encoding and decoding. The ECC circuit 14 encodes the data to be written to the memory device 20 and decodes the data read from the memory device 20.

[0017] ROM15 is a non-volatile memory. ROM15 stores programs such as firmware. ROM15 is, for example, an EEPROM. TM This is an electrically erasable, programmable, read-only memory. The operation of the memory controller 10 is realized by the execution of firmware stored in the ROM 15, etc., by the CPU 13.

[0018] RAM16 is volatile memory. RAM16 is used as the CPU13's workspace. RAM16 includes DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), among others.

[0019] Buffer memory 17 is, for example, volatile memory. Buffer memory 17 temporarily stores data received via host I / F 11, data received via memory I / F 12, etc. Buffer memory 17 can be DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), etc.

[0020] [1-1-3] Hardware configuration of memory device 20 Figure 3 is a block diagram showing an example of the hardware configuration of a memory device 20 according to the first embodiment. As shown in Figure 3, the memory device 20 includes, for example, an input / output circuit 201, a logic controller 202, a register circuit 203, a sequencer 204, a ready-busy controller 205, a driver circuit 206, a memory cell array 207, a row decoder module 208, and a sense amplifier module 209. Signals transmitted or received via the memory bus MB include, for example, input / output signals I / O0 to I / O7, control signals CEn, CLE, ALE, WEn, REn, and WPn, and a ready-busy signal RBn.

[0021] The input / output circuit 201 is an interface circuit that controls the transmission and reception of input / output signals I / O0 to I / O7. The input / output signals I / O include data DAT, status information STS, address information ADD, command CMD, etc. The input / output circuit 201 can transfer (input or output) data DAT to and from the sense amplifier module 209. The input / output circuit 201 can transfer (output) status information STS transferred from register circuit 203 to the memory controller 10. The input / output circuit 201 can transfer address information ADD and command CMD, respectively, transferred from the memory controller 10 to register circuit 203.

[0022] The logic controller 202 controls the input / output circuit 201 and the sequencer 204 based on the control signals CEn, CLE, ALE, WEn, REn, and WPn input from the memory controller 10. Based on the control signal CEn, the logic controller 202 enables the memory device 20. Based on the control signals CLE and ALE, the logic controller 202 notifies the input / output circuit 201 that the input / output signals I / O received by the memory device 20 are command CMD and address information ADD, respectively. Based on the control signal WEn, the logic controller 202 commands the input / output circuit 201 to input the input / output signal I / O, and based on the control signal REn, commands the input / output circuit 201 to output the input / output signal I / O. Based on the control signal WPn, the logic controller 202 puts the memory device 20 into a protected state when the power is turned on or off.

[0023] The register circuit 203 is a circuit that temporarily stores status information STS, address information ADD, and command CMD. The status information STS stored in the register circuit 203 is updated based on the control of the sequencer 204 and transferred to the input / output circuit 201. The address information ADD includes block address, page address, column address, etc. The command CMD includes instructions related to various operations of the memory device MD.

[0024] The sequencer 204 is a controller that controls the overall operation of the memory device 20. Based on the command CMD and address information ADD stored in the register circuit 203, the sequencer 204 performs read operations, write operations, erase operations, etc.

[0025] The ready-busy controller 205 is a controller that generates a ready-busy signal RBn based on the control of the sequencer 204. The ready-busy signal RBn is a signal that notifies the memory controller 10 whether the memory device 20 is in a ready state or a busy state. "Ready state" is a state in which the memory device 20 is ready to accept commands from the memory controller 10, and is notified by a ready-busy signal RBn at the "H" level. "Busy state" is a state in which the memory device 20 is not ready to accept commands from the memory controller 10, and is notified by a ready-busy signal RBn at the "L" level.

[0026] The driver circuit 206 is a circuit that generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 206 supplies the generated voltages to the raw decoder module 208 and the sense amplifier module 209, etc.

[0027] The memory cell array 207 is a collection of multiple memory cell transistors MT. The memory cell array 207 contains multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). Each block BLK is assigned a block address. Each block BLK contains multiple pages. Each block BLK is used, for example, as a data erasure unit. The memory cell array 207 is provided with multiple bit lines BL0 to BLm (where m is an integer greater than or equal to 1) and multiple word lines WL.

[0028] The row decoder module 208 is a circuit used for selecting the block BLK to operate on and for transferring voltage to wiring such as word lines WL. The row decoder module 208 includes multiple row decoders RD0 to RDn. Row decoders RD0 to RDn are each associated with blocks BLK0 to BLKn.

[0029] The sense amplifier module 209 is a circuit used for transferring voltage to each bit line BL and for reading data. The sense amplifier module 209 includes multiple sense amplifier units SAU0 to SAUm. Each of the sense amplifier units SAU0 to SAUm is associated with multiple bit lines BL0 to BLm.

[0030] [1-1-4] Circuit configuration of memory device 20 (Circuit configuration of memory cell array 207) Figure 4 is a circuit diagram showing an example of the circuit configuration of a memory cell array 207 provided in the memory device 20 according to the first embodiment. Figure 4 shows an extracted circuit configuration of one block BLK. As shown in Figure 4, the block BLK includes, for example, string units SU0 to SU4, word lines WL0 to WL7, selection gate lines SGD0 to SGD4, selection gate line SGS, and source line SL.

[0031] Each string unit SU includes multiple NAND strings NS. Each of the multiple NAND strings NS in each string unit SU is connected to bit lines BL0 to BLm. Each NAND string NS includes memory cell transistors MT0 to MT7, as well as selection transistors ST1 and ST2. Each memory cell transistor MT has a control gate and a charge storage layer and stores data nonvolatilically. Selection transistors ST1 and ST2 are used for selecting the string unit SU, respectively.

[0032] The drain of selection transistor ST1 is connected to the associated bit line BL. The source of selection transistor ST1 is connected to the drain of memory cell transistor MT7. Memory cell transistors MT0 to MT7 are connected in series. The source of memory cell transistor MT0 is connected to the drain of selection transistor ST2. The source of selection transistor ST2 is connected to the source line SL. The source line SL is shared by, for example, multiple blocks BLK. Word lines WL0 to WL7 are connected to memory cell transistors MT0 to MT7 of each NAND string NS, respectively. Selection gate lines SGD0 to SGD4 are connected to the respective gates of multiple selection transistors ST1 contained in string units SU0 to SU4, respectively. Selection gate line SGS is connected to the gate of selection transistor ST2 of each NAND string NS.

[0033] In this specification, a set of multiple memory cell transistors MT included in the same string unit SU and connected to the same word line WL is referred to as a “cell unit CU”. In the memory device 20, each memory cell transistor MT stores 5 bits of data. That is, each cell unit CU can store 5 pages of data. Note that the circuit configuration of the memory cell array 207 may be other circuit configurations. The number of string units SU included in each block BLK, and the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS, can be freely designed.

[0034] (Circuit configuration of the Low Decoder Module 208) Figure 5 is a circuit diagram showing an example of the circuit configuration of a row decoder module 208 included in the memory device 20 according to the first embodiment. Figure 5 shows the connection relationships between the row decoder module 208 and the driver circuit 206 and the memory cell array 207, and a detailed circuit configuration of row decoder RD0 among row decoders RD0 to RDn. As shown in Figure 5, each row decoder RD is connected to the driver circuit 206 via signal lines CG0 to CG11, SGDD0 to SGDD4, SGSD, USGD, and USGS. Each row decoder RD is connected to its associated block BLK via word lines WL0 to WL7 and selection gate lines SGS and SGD0 to SGD4.

[0035] The following describes the connection relationships between each element of the raw decoder RD and the driver circuit 206 and block BLK0, using the raw decoder RD0 as a representative. The raw decoder RD0 includes transistors TR0 to TR19, transfer gate lines TG and bTG, and block decoder BD. Each of transistors TR0 to TR19 is a high-voltage N-type MOS transistor.

[0036] The drain and source of transistor TR0 are connected to signal line SGSD and select gate line SGS, respectively. The drains of transistors TR1 to TR8 are connected to signal lines CG0 to CG7, respectively. The sources of transistors TR1 to TR8 are connected to word lines WL0 to WL7, respectively. The drains of transistors TR9 to TR13 are connected to signal lines SGDD0 to SGDD4, respectively. The sources of transistors TR9 to TR13 are connected to select gate lines SGD0 to SGD4, respectively. The drain and source of transistor TR14 are connected to signal line USGS and select gate line SGS, respectively. The drains of transistors TR15 to TR19 are connected to signal line USGD. The sources of transistors TR15 to TR19 are connected to select gate lines SGD0 to SGD4, respectively. The gates of transistors TR0 to TR13 are connected to transfer gate line TG. The gates of transistors TR14 to TR19 are connected to transfer gate line bTG.

[0037] The block decoder BD is a decoder that decodes block addresses. Based on the decoding result of the block address, the block decoder BD applies predetermined voltages to the transfer gate lines TG and bTG, respectively. Specifically, the block decoder BD corresponding to the selected block BLK applies "H" level and "L" level voltages to the transfer gate lines TG and bTG, respectively. The block decoder BD corresponding to the unselected block BLK applies "L" level and "H" level voltages to the transfer gate lines TG and bTG, respectively. As a result, the voltages of signal lines CG0 to CG7 are transferred to the word lines WL0 to WL7 of the selected block BLK, respectively; the voltages of signal lines SGDD0 to SGDD4 and SGSD are transferred to the selected gate lines SGD0 to SGD4 and SGS of the selected block BLK, respectively; and the voltages of signal lines USGD and USGS are transferred to the selected gate lines SGD and SGS of the unselected block BLK, respectively.

[0038] The raw decoder module 208 may have other circuit configurations. For example, the number of transistors TR included in the raw decoder module 208 can be changed according to the number of wires provided in each block BLK. The signal line CG may be called a "global word line" because it is shared among multiple block BLKs. The word line WL may be called a "local word line" because it is provided for each block. The signal lines SGDD and SGSD may each be called "global transfer gate lines" because they are shared among multiple block BLKs. The selection gate lines SGD and SGS may each be called "local transfer gate lines" because they are provided for each block.

[0039] (Circuit configuration of sense amplifier module 209) Figure 6 is a circuit diagram showing an example of the circuit configuration of a sense amplifier module 209 included in the memory device 20 according to the first embodiment. Figure 6 shows an extracted circuit configuration of one sense amplifier unit SAU. As shown in Figure 6, the sense amplifier unit SAU includes a sense amplifier section SA, a bit line connection section BLHU, latch circuits SDL, ADL, BDL, CDL, DDL, EDL and XDL, and a bus LBUS. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, DDL, EDL and XDL are configured to transmit and receive data via the bus LBUS.

[0040] The sense amplifier section SA is a circuit used for determining data based on the voltage of the bit line BL and for applying voltage to the bit line BL. When the control signal STB is asserted during a read operation, the sense amplifier section SA determines whether the data read from the selected memory cell transistor MT is "0" or "1" based on the voltage of the associated bit line BL. The latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and XDL are circuits capable of temporarily holding data. The latch circuit XDL is used for input and output of data DAT between the sense amplifier unit SAU and the input / output circuit 201. The latch circuit XDL can also be used as a cache memory. The memory device MD can become ready as long as at least the latch circuit XDL is free.

[0041] The sense amplifier section SA includes transistors T0 to T7, capacitor CP, and nodes ND1, ND2, SEN, and SRC. The bit line connection section BLHU includes transistor T8. The latch circuit SDL includes inverters IV0 and IV1, transistors T10 and T11, and nodes SINV and SLAT. Transistor T0 is a P-type MOS transistor. Transistors T1 to T8, T10, and T11 are each N-type MOS transistors. Transistor T8 is an N-type MOS transistor with a higher voltage rating than the N-type transistors in the sense amplifier section SA.

[0042] The gate of transistor T0 is connected to node SINV. The source of transistor T0 is connected to the power line. The drain of transistor T0 is connected to node ND1. Node ND1 is connected to the drains of transistors T1 and T2, respectively. The sources of transistors T1 and T2 are connected to nodes ND2 and SEN, respectively. Nodes ND2 and SEN are connected to the source and drain of transistor T3, respectively. Node ND2 is connected to the drains of transistors T4 and T5, respectively. The source of transistor T5 is connected to node SRC. The gate of transistor T5 is connected to node SINV. Node SEN is connected to the gate of transistor T6 and one electrode of capacitor CP. The source of transistor T6 is grounded. The drain and source of transistor T7 are connected to bus LBUS and the drain of transistor T6, respectively. The drain of transistor T8 is connected to the source of transistor T4. The source of transistor T8 is connected to the associated bit line BL.

[0043] For example, the power supply voltage VDD is applied to the source of transistor T0. For example, the ground voltage VSS is applied to node SRC. The control signals BLX, HLL, XXL, BLC, and STB are input to the gates of transistors T1, T2, T3, T4, and T7, respectively. The control signal BLS is input to the gate of transistor T8. The clock signal CLK is input to the other electrode of capacitor CP.

[0044] The input node of inverter IV0 is connected to node SLAT. The output node of inverter IV0 is connected to node SINV. The input node of inverter IV1 is connected to node SINV. The output node of inverter IV1 is connected to node SLAT. One end of transistor T10 is connected to node SINV. The other end of transistor T10 is connected to bus LBUS. The control signal STI is input to the gate of transistor T10. One end of transistor T11 is connected to node SLAT. The other end of transistor T11 is connected to bus LBUS. The control signal STL is input to the gate of transistor T11. The latch circuit SDL holds data in node SLAT and holds the inverted data of the data held in node SLAT in node SINV.

[0045] The circuit configurations of latch circuits ADL, BDL, CDL, DDL, EDL, and XDL are similar to those of latch circuit SDL. For example, latch circuit ADL holds data at node ALAT and its inverted data at node AINV. The control signal ATI is input to the gate of transistor T10 of latch circuit ADL, and the control signal ATL is input to the gate of transistor T11 of latch circuit ADL. Latch circuit BDL holds data at node BLAT and its inverted data at node BINV. The control signal BTI is input to the gate of transistor T10 of latch circuit BDL, and the control signal BTL is input to the gate of transistor T11 of latch circuit BDL. The same applies to latch circuits CDL, DDL, and EDL, so their explanation is omitted.

[0046] The control signals BLX, HLL, XXL, BLC, STB, BLS, STI, and STL, as well as the clock signal CLK, are each generated, for example, by the sequencer 204. The sense amplifier module 209 may have other circuit configurations. For example, the number of latch circuits in each sense amplifier unit SAU may be eight or more. The sense amplifier unit SAU may have an arithmetic circuit capable of performing simple logic operations. In this specification, asserting a control signal corresponds to temporarily changing a voltage at the "L" level to a voltage at the "H" level. If transistor T6 is a P-type transistor, asserting the control signal STB corresponds to temporarily changing a voltage at the "H" level to a voltage at the "L" level. The sense amplifier module 209 can determine (determine) the data stored in the memory cell transistor MT by appropriately performing arithmetic processing using latch circuits during the read operation of each page.

[0047] [1-1-5] Threshold voltage distribution of memory cell transistor MT Figure 7 is a schematic diagram showing an example of the threshold voltage distribution of memory cell transistors MT in a memory device 20 according to the first embodiment. The vertical axis, "NMTs," indicates the number of memory cell transistors MT. The horizontal axis, "Vth," indicates the threshold voltage of the memory cell transistors MT. As shown in Figure 7, the threshold voltage distribution of memory cell transistors MT in the memory device 20 can form states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31 in order from the lowest threshold voltage.

[0048] Furthermore, in the memory device 20, read voltages R1 to R31 and read path voltage VREAD are set for states S0 to S31. Specifically, read voltage R1 is set between states S0 and S1, read voltage R2 is set between states S1 and S2, read voltage R3 is set between states S2 and S3, read voltage R4 is set between states S3 and S4, ..., read voltage R30 is set between states S29 and S30, and read voltage R30 is set between states S30 and S31. The read path voltage VREAD is set to a voltage higher than state S31, which has the highest threshold voltage among states S0 to S31. When the read path voltage VREAD is applied to the gate of the memory cell transistor MT, it turns ON regardless of the data to be stored.

[0049] Note that the set of read voltages R1 to R31 shown in Figure 7 may include negative voltages. The set of read voltages R1 to R31 may also be a combination of negative voltages, 0V, and positive voltages. That is, in the set of read voltages R1 to R31, some of the read voltages may be negative voltages, while the other read voltages may be 0V or positive read voltages. For example, each of the read voltages R1 to R4 may be a negative voltage, R5 may be 0V, and each of the read voltages R6 to R31 may be a positive voltage. The set of read voltages R1 to R31 may not include 0V, but may include both negative and positive voltages.

[0050] Each of the states S0 to S31 is assigned one of the datasets D0 to D31. Datasets D0 to D31 correspond to 32 sets of distinct 5-bit data. Each of datasets D0 to D31 contains the first to fifth bits of data. The specific data contents of each of datasets D0 to D31 are listed below.

[0051] (Example) Dataset: “1st bit data / 2nd bit data / 3rd bit data / 4th bit data / 5th bit data” D0:“00000” D1:“00001” D2: “00010” D3: “00011” D4: “00100” D5:“00101” D6: “00110” D7: “00111” D8:“01000” D9: “01001” D10: “01010” D11: “01011” D12: “01100” D13: “01101” D14: “01110” D15: “01111” D16: “10000” D17: “10001” D18: “10010” D19: “10011” D20: “10100” D21: “10101” D22: “10110” D23: “10111” D24: “11000” D25: “11001” D26: “11010” D27: “11011” D28: “11100” D29: “11101” D30: “11110” D31: “11111”

[0052] [1-1-6] Data allocation Figure 8 is a table showing the data allocation and read voltage settings used in the memory device 20 according to the first embodiment. The memory device 20 according to the first embodiment uses a data allocation where one cell unit CU stores 5 pages of data, i.e., a 5-bit / cell coding. The data allocation and read voltage settings of the first embodiment will be described below with reference to Figure 8.

[0053] In the drawings referenced herein, the “State ID” corresponds to the number appended to the reference code “S” indicating the state. In the drawings referenced herein, the “Dataset ID” corresponds to the number appended to the reference code “D” indicating the dataset. “Page 1 (Page 1 Data PG1)” corresponds to the group of first-bit data stored in the cell unit CU. “Page 2 (Page 2 Data PG2)” corresponds to the group of second-bit data stored in the cell unit CU. “Page 3 (Page 3 Data PG3)” corresponds to the group of third-bit data stored in the cell unit CU. “Page 4 (Page 4 Data PG4)” corresponds to the group of fourth-bit data stored in the cell unit CU. “Page 5 (Page 5 Data PG5)” corresponds to the group of fifth-bit data stored in the cell unit CU. Hereinafter, the read operations targeting pages 1 to 5 will be referred to as page 1 to page 5 read operations, respectively.

[0054] In the data allocation of the first embodiment, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D8, D9, D1, D3, D19, D23, D21, D20, D4, D12, D14, D10, D2, D0, D16, D17, D25, D29, D13, D5, D7, D6, D22, D18, D26, D27, D11, and D15 are assigned to 1, respectively.

[0055] In the data allocation of the first embodiment, the read voltages used for reading the first page are R4, R8, R12, R18, R22, R26, and R30. In the data allocation of the first embodiment, the read voltages used for reading the second page are R6, R13, R16, R20, R23, and R28. In the data allocation of the first embodiment, the read voltages used for reading the third page are R3, R9, R15, R21, R27, and R31. In the data allocation of the first embodiment, the read voltages used for reading the fourth page are R2, R7, R10, R14, R17, and R24. In the data allocation of the first embodiment, the read voltages used for reading the fifth page are R1, R5, R11, R19, R25, and R29.

[0056] In the first page readout, the data is finalized after 7 readouts. In the second, third, fourth, and fifth page readouts, the data is finalized after 6 readouts each. Such data allocation is called, for example, "7-6-6-6-6 coding". In the data allocation of the first embodiment, the difference between the maximum and minimum number of readouts set to finalize the data between pages is "1". Also, in the data allocation of the first embodiment, the interval between readout voltages for each page is at least "3" and at most "8".

[0057] In this specification, the "number of reads" in the read operation of each page corresponds to the number of times the control signal STB is asserted. In other words, the "number of reads" corresponds to the number of times the threshold voltage determination based on a certain read voltage is performed. The act of determining the data according to a read voltage while a certain read voltage is applied may simply be called "reading". The "read voltage interval" corresponds to the number of read voltages that are not used in the read operation of a page among the multiple read voltages used for that page, between adjacent read voltages. In other words, the "read voltage interval" corresponds to the number of states placed between adjacent read voltages in the read operation of each page. For example, the interval between read voltages R4 and R8 in the first page read is "4 (4 states)" because four states S4 to S7 are placed between read voltages R4 and R8. The interval between read voltages R12 and R18 in the first page read is "6 (6 states)" because six states S12 to S17 are placed between read voltages R12 and R18.

[0058] [1-2] Operation The operation of the memory system MS according to the first embodiment is described below. Hereinafter, the selected word line WL will be referred to as “selected word line WLsel”. The sequencer 204 applying a voltage to the selected word line WLsel corresponds to the driver circuit 206 applying a voltage via the row decoder module 208 based on the control of the sequencer 204. The address information ADD and command CMD received by the memory device 20 are transferred to the register circuit 203. In the diagram, “tR” indicates the period (time) during which the memory device 20 is busy based on the instructions of the memory controller 10.

[0059] The details of each of the first to fifth page readouts in the first embodiment will be described in order below. In this specification, the case in which the voltage of the source line SL is constant is illustrated for each of the first to fifth page readouts. The drawings referenced below illustrate the case in which the voltage of the selection word line WLsel at the start and end of the readout operation is the ground voltage VSS. However, the voltage of the selection word line WLsel at the start and end of the readout operation may be a negative voltage.

[0060] [1-2-1] Read page 1 Figure 9 is a timing chart showing an example of a first page readout in the memory system MS according to the first embodiment. Figure 9 shows the transitions of the input / output signal I / O, the ready busy signal RBn, the selected word line WLsel, and the control signal STB during the first page readout in the first embodiment. The first page readout of the first embodiment will be described below with reference to Figure 9.

[0061] When the memory controller 10 performs a first-page read, it sends the following commands to the memory device 20 in this order: command "01h", command "00h", address "ADD", and command "30h". Command "01h" is a command that specifies the operation of selecting the first page. Command "00h" is a command that specifies the read operation. Address "ADD" contains the address of the word line WL to be read. Command "30h" is a command that instructs the start of the read operation.

[0062] When the memory device 20 receives the command "30h", the sequencer 204 transitions the memory device 20 from the ready state to the busy state based on the command and address stored in the register circuit 203. The sequencer 204 then applies the read voltages R4, R8, R12, R18, R22, R26, and R30 to the selection word line WLsel in that order. The sequencer 204 also asserts the control signal STB while each of the read voltages R4, R8, R12, R18, R22, R26, and R30 is applied. Each sense amplifier unit SAU confirms (determines) the first bit data read from the memory cell transistor MT connected to the selection word line WLsel based on the control of the sequencer 204, and stores the determination result in the latch circuit XDL.

[0063] When the sequencer 204 receives the result of the first bit data determination and stores it in the latch circuit XDL, it transitions the memory device 20 from a busy state to a ready state. Based on the fact that the memory device 20 has transitioned from a busy state to a ready state, the memory controller 10 instructs the memory device 20 to output the data DAT (first page data PG1) stored in each latch circuit XDL of the sense amplifier module 209. For example, the memory controller 10 can sequentially output the data DAT to the memory device 20 by toggling the control signal REn. When the memory controller 10 receives the first page data PG1, it transfers the first page data PG1 to the host device HD, for example, and terminates the first page read operation.

[0064] [1-2-2] Read page 2 Figure 10 is a timing chart showing an example of a second page readout in the memory system MS according to the first embodiment. Figure 10 shows the transitions of the input / output signal I / O, the ready busy signal RBn, the selected word line WLsel, and the control signal STB during the second page readout in the first embodiment. The second page readout of the first embodiment will be described below with reference to Figure 10.

[0065] When the memory controller 10 performs a second-page read operation, it sends the following commands to the memory device 20 in this order: command "02h", command "00h", address "ADD", and command "30h". Command "02h" is a command that specifies the operation of selecting the second page.

[0066] When memory device 20 receives the command "30h", sequencer 204 transitions memory device 20 from the ready state to the busy state based on the command and address stored in register circuit 203. Then, sequencer 204 applies read voltages R6, R13, R16, R20, R23, and R28 to the selection word line WLsel in that order. Also, while each of the read voltages R6, R13, R16, R20, R23, and R28 is applied, sequencer 204 asserts the control signal STB for each. Each sense amplifier unit SAU confirms (determines) the second bit data read from memory cell transistor MT connected to the selection word line WLsel based on the control of sequencer 204, and stores the determination result in latch circuit XDL.

[0067] When the sequencer 204 receives the result of the second bit data determination and stores it in the latch circuit XDL, it transitions the memory device 20 from a busy state to a ready state. Based on the fact that the memory device 20 has transitioned from a busy state to a ready state, the memory controller 10 commands the memory device 20 to output the data DAT (second page data PG2) stored in each latch circuit XDL of the sense amplifier module 209. Upon receiving the second page data PG2, the memory controller 10 transfers the second page data PG2 to, for example, the host device HD, and terminates the second page read operation.

[0068] [1-2-3] Read page 3 Figure 11 is a timing chart showing an example of a third-page readout in the memory system MS according to the first embodiment. Figure 11 shows the transitions of the input / output signal I / O, the ready-busy signal RBn, the selected word line WLsel, and the control signal STB during the third-page readout in the first embodiment. The third-page readout of the first embodiment will be described below with reference to Figure 11.

[0069] When the memory controller 10 performs a third-page read, it sends the following commands to the memory device 20 in this order: command "03h", command "00h", address "ADD", and command "30h". Command "03h" is a command that specifies the operation of selecting the third page.

[0070] When the memory device 20 receives the command "30h", the sequencer 204 transitions the memory device 20 from the ready state to the busy state based on the command and address stored in the register circuit 203. The sequencer 204 then applies the read voltages R3, R9, R15, R21, R27, and R31 to the selection word line WLsel in that order. The sequencer 204 also asserts the control signal STB while each of the read voltages R3, R9, R15, R21, R27, and R31 is applied. Each sense amplifier unit SAU confirms (determines) the third bit data read from the memory cell transistor MT connected to the selection word line WLsel based on the control of the sequencer 204, and stores the determination result in the latch circuit XDL.

[0071] When the sequencer 204 receives the result of the determination of the third bit data and stores it in the latch circuit XDL, it transitions the memory device 20 from a busy state to a ready state. Based on the fact that the memory device 20 has transitioned from a busy state to a ready state, the memory controller 10 commands the memory device 20 to output the data DAT (third page data PG3) stored in each latch circuit XDL of the sense amplifier module 209. Upon receiving the third page data PG3, the memory controller 10 transfers the third page data PG3 to, for example, the host device HD, and terminates the third page read operation.

[0072] [1-2-4] Read page 4 Figure 12 is a timing chart showing an example of a fourth page readout in the memory device according to the first embodiment. Figure 12 shows the transitions of the input / output signal I / O, the ready busy signal RBn, the selected word line WLsel, and the control signal STB during the fourth page readout of the first embodiment. The fourth page readout of the first embodiment will be described below with reference to Figure 12.

[0073] When the memory controller 10 performs a read operation on the fourth page, it sends the following commands to the memory device 20 in this order: command "04h", command "00h", address "ADD", and command "30h". Command "04h" is a command that specifies the operation of selecting the fourth page.

[0074] When the memory device 20 receives the command "30h", the sequencer 204 transitions the memory device 20 from the ready state to the busy state based on the command and address stored in the register circuit 203. The sequencer 204 then applies the read voltages R2, R7, R10, R14, R17, and R24 to the selection word line WLsel in that order. The sequencer 204 also asserts the control signal STB while each of the read voltages R2, R7, R10, R14, R17, and R24 is applied. Each sense amplifier unit SAU determines (determines) the 4th bit data read from the memory cell transistor MT connected to the selection word line WLsel based on the control of the sequencer 204, and stores the determination result in the latch circuit XDL.

[0075] When the sequencer 204 receives the result of the determination of the fourth bit data and stores it in the latch circuit XDL, it transitions the memory device 20 from a busy state to a ready state. Based on the fact that the memory device 20 has transitioned from a busy state to a ready state, the memory controller 10 commands the memory device 20 to output the data DAT (fourth page data PG4) stored in each latch circuit XDL of the sense amplifier module 209. Upon receiving the fourth page data PG4, the memory controller 10 transfers the fourth page data PG4 to, for example, the host device HD, and terminates the reading of the fourth page.

[0076] [1-2-5] Read page 5 Figure 13 is a timing chart showing an example of a fifth-page readout in a memory device according to the first embodiment. Figure 13 shows the transitions of the input / output signal I / O, the ready-busy signal RBn, the selected word line WLsel, and the control signal STB during the fifth-page readout of the first embodiment. The fifth-page readout of the first embodiment will be described below with reference to Figure 13.

[0077] When the memory controller 10 performs a read operation on the fifth page, it sends the following commands to the memory device 20 in this order: command "02h", command "00h", address "ADD", and command "30h". Command "05h" is a command that specifies the operation of selecting the fifth page.

[0078] When the memory device 20 receives the command "30h", the sequencer 204 transitions the memory device 20 from the ready state to the busy state based on the command and address stored in the register circuit 203. The sequencer 204 then applies the read voltages R1, R5, R11, R19, R25, and R29 to the selection word line WLsel in that order. The sequencer 204 also asserts the control signal STB while each of the read voltages R1, R5, R11, R19, R25, and R29 is applied. Each sense amplifier unit SAU confirms (determines) the 5th bit data read from the memory cell transistor MT connected to the selection word line WLsel based on the control of the sequencer 204, and stores the determination result in the latch circuit XDL.

[0079] When the sequencer 204 receives the result of the determination of the 5th bit data and stores it in the latch circuit XDL, it transitions the memory device 20 from a busy state to a ready state. Based on the fact that the memory device 20 has transitioned from a busy state to a ready state, the memory controller 10 commands the memory device 20 to output the data DAT (5th page data PG5) stored in each latch circuit XDL of the sense amplifier module 209. Upon receiving the 5th page data PG5, the memory controller 10 transfers the 5th page data PG5 to, for example, the host device HD, and terminates the reading of the 5th page.

[0080] [1-3] Effects of the first embodiment The memory device 20 according to the first embodiment described above enables efficient read operations. The effects of the first embodiment are described in detail below.

[0081] In memory-specific data allocation, 5-bit data allocated to a state is set to differ by only one bit from 5-bit data allocated to an adjacent state. There are over 10 million possible memory-specific coding combinations using 5 bits per cell, without considering page allocation. Even with page allocation considered, there are still around 100,000 possible coding combinations using 5 bits per cell.

[0082] Efficient read voltage allocation is preferable when the number of reads per page is average and the interval between read voltages per page is average. An average number of reads per page can average out the probability of failure per page. An average interval between read voltages per page can reduce read noise and average out the read voltage setup time. Furthermore, averaging out the setup time can shorten the read operation time per page, thus improving the read operation latency of the memory device 20.

[0083] When applied to 5 bits / cell, the ideal scenario is that the number of reads is (PG1,PG2,PG3,PG4,PG5)=(7,6,6,6,6), and the minimum interval between the read voltages for each page is "4", with the maximum being as small as possible. The fact that the optimal minimum interval between read voltages is "4" is based on the fact that there are 31 types of read voltages in 5-bit / cell coding, and dividing "31" by the maximum number of reads "7" results in a value close to "4". However, there is no data assignment where the number of reads is (PG1,PG2,PG3,PG4,PG5)=(7,6,6,6,6) and the minimum interval between the read voltages for each page is "4".

[0084] Furthermore, data judgment using the lowest read voltage R1 tends to have a higher probability of failure due to the widening of the upper tail of the lowest state S0. Data judgment using the highest read voltage R31 tends to have a higher probability of failure due to the widening of the lower tail of the highest state S31. Pages with 7 read counts tend to have a higher probability of failure than pages with 6 read counts. For this reason, in memory, it is preferable that the interval between read voltages is set on average for pages with 7 read counts, and that the lowest or highest read voltage among the 31 types of read voltages is not used.

[0085] In contrast, the data allocation in the memory device 20 according to the first embodiment is set to conditions close to ideal. Specifically, in the data allocation of the first embodiment, the number of read operations is (PG1, PG2, PG3, PG4, PG5) = (7, 6, 6, 6, 6), and the interval between read voltages in each page is at least "3" and at most "8". In the first page, which has 7 read operations, the lowest read voltage is R4 and the highest read voltage is R30. That is, in the first page read operation of the first embodiment, the lowest read voltage R4 is set to be 3 states away from R1, and the highest read voltage R30 is set to be 1 state away from R31.

[0086] As a result, the memory device 20 according to the first embodiment has an average number of read operations per page and can average the probability of failure per page. By averaging the probability of failure, the memory device 20 can suppress the occurrence of read operation retries and improve latency. By limiting the interval between read voltages to a minimum of "3" and a maximum of "8", the memory device 20 achieves an approximately average setup time for the read voltage per page. Therefore, the memory device 20 can shorten the read operation time. Consequently, the memory device 20 according to the first embodiment can perform efficient read operations.

[0087] [1-4] Modified form of the first embodiment Other data allocation methods exist that enable efficient reading operations similar to those in the first embodiment. Below, the first to seventeenth modified examples of data allocation in the first embodiment are described.

[0088] (First variation) Figure 14 is a table showing the data allocation and read voltage settings for the first modified example. The data allocation and read voltage settings for the first modified example will be described below with reference to Figure 14.

[0089] In the data assignment of the first modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 Datasets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D23, D7, D5, D1, D9, D25, D27, D26, D10, D14, D6, D4, D20, D21, and D29 are assigned to each, respectively.

[0090] In the data allocation of the first modified example, the read voltages used for reading the first page are R7, R15, R18, R22, R25, and R29. In the data allocation of the first modified example, the read voltages used for reading the second page are R4, R8, R13, R21, R27, and R31. In the data allocation of the first modified example, the read voltages used for reading the third page are R3, R9, R12, R16, R20, and R26. In the data allocation of the first modified example, the read voltages used for reading the fourth page are R2, R6, R10, R14, R19, R23, and R28. In the data allocation of the first modified example, the read voltages used for reading the fifth page are R1, R5, R11, R17, R24, and R30.

[0091] Figure 15 is a waveform diagram showing an example of the voltage (read waveform) applied to the selection word line WLsel during the read operation of the first modified example. In each of the first to fifth page readouts of the first modified example, the sequencer 204 can read the desired page data from the cell unit CU by applying a readout voltage to the selection word line WLsel, as shown in Figure 15. The operation is the same between the first embodiment and the first modified example, except that the type of readout voltage applied to the selection word line WLsel differs for each page readout.

[0092] (Second variation) Figure 16 is a table showing the data allocation and read voltage settings for the second modified example. The data allocation and read voltage settings for the second modified example will be explained below with reference to Figure 16.

[0093] In the data assignment of the second modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 Datasets D31, D30, D28, D24, D8, D9, D1, D5, D7, D23, D19, D18, D26, D10, D14, D12, D4, D0, D16, D17, D25, D27, D11, D3, D2, D6, D22, D20, D21, D29, D13, and D15 are assigned to each, respectively.

[0094] In the data allocation of the second modified example, the read voltages used for reading the first page are R4, R9, R13, R18, R22, R26, and R30. In the data allocation of the second modified example, the read voltages used for reading the second page are R6, R12, R16, R20, R23, and R29. In the data allocation of the second modified example, the read voltages used for reading the third page are R3, R7, R10, R14, R17, and R25. In the data allocation of the second modified example, the read voltages used for reading the fourth page are R2, R8, R15, R21, R27, and R31. In the data allocation of the second modified example, the read voltages used for reading the fifth page are R1, R5, R11, R19, R24, and R28.

[0095] Figure 17 is a waveform diagram showing an example of the voltage (read waveform) applied to the selection word line WLsel during the read operation of the second modified example. In each of the first to fifth page readouts of the second modified example, the sequencer 204 can read the desired page data from the cell unit CU by applying a readout voltage to the selection word line WLsel, as shown in Figure 17. The operation is the same in the first embodiment and the second modified example, except that the type of readout voltage applied to the selection word line WLsel differs in each page readout.

[0096] (Third variation) Figure 18 is a table showing the data allocation and read voltage settings for the third modified example. The data allocation and read voltage settings for the third modified example will be described below with reference to Figure 18.

[0097] In the data assignment of the third modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 Datasets D31, D30, D28, D24, D16, D17, D19, D23, D7, D15, D13, D12, D4, D0, D2, D18, D26, D27, D11, D3, D1, D5, D21, D20, D22, D6, D14, D10, D8, D9, D25, and D29 are assigned to each, respectively.

[0098] In the data allocation of the third modified example, the read voltages used for reading the first page are R8, R15, R18, R22, R25, and R30. In the data allocation of the third modified example, the read voltages used for reading the second page are R4, R9, R12, R16, R19, and R26. In the data allocation of the third modified example, the read voltages used for reading the third page are R3, R7, R13, R21, R27, and R31. In the data allocation of the third modified example, the read voltages used for reading the fourth page are R2, R6, R10, R14, R20, R24, and R28. In the data allocation of the third modified example, the read voltages used for reading the fifth page are R1, R5, R11, R17, R23, and R29.

[0099] Figure 19 is a waveform diagram showing an example of the voltage (read waveform) applied to the selection word line WLsel during the read operation of the third modified example. In each of the first to fifth page readouts of the third modified example, the sequencer 204 can read the desired page data from the cell unit CU by applying a readout voltage to the selection word line WLsel, as shown in Figure 19. The operation is the same in the first embodiment and the third modified example, except that the type of readout voltage applied to the selection word line WLsel differs in each page readout.

[0100] (Fourth variation) Figure 20 is a table showing the data allocation and readout voltage settings for the fourth modified example. The data allocation and readout voltage settings for the fourth modified example will be described below with reference to Figure 20.

[0101] In the data assignment of the fourth modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 Datasets D31, D30, D28, D24, D25, D17, D19, D23, D7, D15, D14, D12, D4, D0, D16, D18, D26, D27, D11, D3, D1, D5, D21, D20, D22, D6, D2, D10, D8, D9, D13, and D29 are assigned to each, respectively.

[0102] In the data allocation of the fourth modified example, the read voltages used for reading the first page are R8, R14, R18, R22, R25, and R31. In the data allocation of the fourth modified example, the read voltages used for reading the second page are R5, R9, R12, R16, R19, and R27. In the data allocation of the fourth modified example, the read voltages used for reading the third page are R3, R7, R13, R21, R26, and R30. In the data allocation of the fourth modified example, the read voltages used for reading the fourth page are R2, R6, R11, R15, R20, R24, and R28. In the data allocation of the fourth modified example, the read voltages used for reading the fifth page are R1, R4, R10, R17, R23, and R29.

[0103] Figure 21 is a waveform diagram showing an example of the voltage (read waveform) applied to the selection word line WLsel during the read operation of the fourth modified example. In each of the first to fifth page readouts of the fourth modified example, the sequencer 204 can read the desired page data from the cell unit CU by applying a readout voltage to the selection word line WLsel, as shown in Figure 21. The operation is the same between the first embodiment and the fourth modified example, except that the type of readout voltage applied to the selection word line WLsel differs for each page readout.

[0104] (Fifth variation) Figure 22 is a table showing the data allocation and read voltage settings for the fifth modified example. The data allocation and read voltage settings for the fifth modified example will be described below with reference to Figure 22.

[0105] In the data assignment of the fifth variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 Datasets D31, D30, D28, D24, D8, D0, D2, D3, D19, D23, D22, D20, D4, D12, D13, D9, D1, D17, D16, D18, D26, D10, D14, D6, D7, D5, D21, D29, D25, D27, D11, and D15 are assigned to each, respectively.

[0106] In the data allocation of the fifth modified example, the read voltages used for reading the first page are R4, R8, R12, R17, R21, R26, and R30. In the data allocation of the fifth modified example, the read voltages used for reading the second page are R5, R13, R16, R20, R23, and R27. In the data allocation of the fifth modified example, the read voltages used for reading the third page are R3, R9, R15, R22, R28, and R31. In the data allocation of the fifth modified example, the read voltages used for reading the fourth page are R2, R6, R11, R19, R25, and R29. In the data allocation of the fifth modified example, the read voltages used for reading the fifth page are R1, R7, R10, R14, R18, and R24.

[0107] Figure 23 is a waveform diagram showing an example of the voltage (read waveform) applied to the selection word line WLsel during the read operation of the fifth modified example. In each of the first to fifth page readouts of the fifth modified example, the sequencer 204 can read the desired page data from the cell unit CU by applying a readout voltage to the selection word line WLsel, as shown in Figure 23. The operation is the same between the first embodiment and the fifth modified example, except that the type of readout voltage applied to the selection word line WLsel differs in each page readout.

[0108] (Sixth variation) Figure 24 is a table showing the data allocation and readout voltage settings for the sixth modified example. The data allocation and readout voltage settings for the sixth modified example will be described below with reference to Figure 24.

[0109] In the data assignment of the sixth variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 Datasets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D20, D4, D5, D1, D9, D25, D27, D26, D10, D14, D6, D7, D23, D21, and D29 are assigned to each, respectively.

[0110] In the data allocation of the sixth modified example, the read voltages used for reading the first page are R7, R15, R18, R22, R25, and R29. In the data allocation of the sixth modified example, the read voltages used for reading the second page are R4, R8, R13, R21, R27, and R31. In the data allocation of the sixth modified example, the read voltages used for reading the third page are R3, R9, R12, R16, R20, and R26. In the data allocation of the sixth modified example, the read voltages used for reading the fourth page are R2, R6, R10, R14, R17, R23, and R30. In the data allocation of the sixth modified example, the read voltages used for reading the fifth page are R1, R5, R11, R19, R24, and R28.

[0111] (Seventh variation) Figure 25 is a table showing the data allocation and read voltage settings for the seventh modified example. The data allocation and read voltage settings for the seventh modified example will be described below with reference to Figure 25.

[0112] In the data assignment of the seventh variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 Datasets D31, D30, D28, D24, D16, D17, D1, D5, D13, D15, D11, D10, D26, D18, D22, D20, D4, D0, D2, D3, D19, D27, D25, D9, D8, D12, D14, D6, D7, D23, D21, and D29 are assigned to each, respectively.

[0113] In the data allocation of the seventh modified example, the read voltages used for reading the first page are R6, R12, R16, R20, R23, and R29. In the data allocation of the seventh modified example, the read voltages used for reading the second page are R4, R8, R13, R21, R27, and R31. In the data allocation of the seventh modified example, the read voltages used for reading the third page are R3, R7, R10, R14, R17, and R25. In the data allocation of the seventh modified example, the read voltages used for reading the fourth page are R2, R9, R15, R18, R22, R26, and R30. In the data allocation of the seventh modified example, the read voltages used for reading the fifth page are R1, R5, R11, R19, R24, and R28.

[0114] (Variation 8) Figure 26 is a table showing the data allocation and read voltage settings for the eighth modified example. The data allocation and read voltage settings for the eighth modified example will be described below with reference to Figure 26.

[0115] In the data assignment of the eighth variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 Datasets D31, D30, D28, D24, D16, D17, D1, D5, D13, D15, D11, D3, D19, D18, D22, D20, D4, D12, D14, D10, D26, D27, D25, D9, D8, D0, D2, D6, D7, D23, D21, and D29 are assigned to each, respectively.

[0116] In the data allocation of the 8th modified example, the read voltages used for reading the first page are R6, R12, R16, R20, R23, and R29. In the data allocation of the 8th modified example, the read voltages used for reading the second page are R4, R8, R11, R17, R25, and R31. In the data allocation of the 8th modified example, the read voltages used for reading the third page are R3, R7, R10, R14, R19, and R27. In the data allocation of the 8th modified example, the read voltages used for reading the fourth page are R2, R9, R15, R18, R22, R26, and R30. In the data allocation of the 8th modified example, the read voltages used for reading the fifth page are R1, R5, R13, R21, R24, and R28.

[0117] (9th variation) Figure 27 is a table showing the data allocation and readout voltage settings for the ninth modified example. The data allocation and readout voltage settings for the ninth modified example will be described below with reference to Figure 27.

[0118] In the data assignment of the ninth variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 Datasets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D5, D1, D0, D2, D18, D22, D20, D4, D12, D8, D9, D25, D27, D26, D10, D14, D6, D7, D23, D21, and D29 are assigned to each, respectively.

[0119] In the data allocation of the ninth modified example, the read voltages used for reading the first page are R7, R15, R18, R22, R25, and R29. In the data allocation of the ninth modified example, the read voltages used for reading the second page are R4, R8, R11, R19, R27, and R31. In the data allocation of the ninth modified example, the read voltages used for reading the third page are R3, R9, R12, R16, R20, and R26. In the data allocation of the ninth modified example, the read voltages used for reading the fourth page are R2, R6, R10, R14, R17, R23, and R30. In the data allocation of the ninth modified example, the read voltages used for reading the fifth page are R1, R5, R13, R21, R24, and R28.

[0120] (10th variation) Figure 28 is a table showing the data allocation and read voltage settings for the 10th modified example. The data allocation and read voltage settings for the 10th modified example will be described below with reference to Figure 28.

[0121] In the data assignment of the 10th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D1, D5, D13, D15, D11, D3, D19, D18, D22, D20, D4, D0, D2, D10, D26, D27, D25, D9, D8, D12, D14, D6, D7, D23, D21, and D29 are assigned to 1, respectively.

[0122] In the data allocation of the 10th modified example, the read voltages used for reading the first page are R6, R12, R16, R20, R23, and R29. In the data allocation of the 10th modified example, the read voltages used for reading the second page are R4, R8, R11, R19, R27, and R31. In the data allocation of the 10th modified example, the read voltages used for reading the third page are R3, R7, R10, R14, R17, and R25. In the data allocation of the 10th modified example, the read voltages used for reading the fourth page are R2, R9, R15, R18, R22, R26, and R30. In the data allocation of the 10th modified example, the read voltages used for reading the fifth page are R1, R5, R13, R21, R24, and R28.

[0123] (11th variation) Figure 29 is a table showing the data allocation and read voltage settings for the 11th modified example. The data allocation and read voltage settings for the 11th modified example will be described below with reference to Figure 29.

[0124] In the data assignment of the 11th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D0, D2, D3, D11, D15, D13, D5, D1, D17, D19, D18, D22, D20, D4, D12, D8, D9, D25, D27, D26, D10, D14, D6, D7, D23, D21, and D29 are assigned to 1, respectively.

[0125] In the data allocation of the 11th modified example, the read voltages used for reading the first page are R5, R13, R18, R22, R25, and R29. In the data allocation of the 11th modified example, the read voltages used for reading the second page are R4, R8, R11, R19, R27, and R31. In the data allocation of the 11th modified example, the read voltages used for reading the third page are R3, R9, R12, R16, R20, and R26. In the data allocation of the 11th modified example, the read voltages used for reading the fourth page are R2, R6, R10, R14, R17, R23, and R30. In the data allocation of the 11th modified example, the read voltages used for reading the fifth page are R1, R7, R15, R21, R24, and R28.

[0126] (12th variation) Figure 30 is a table showing the data allocation and read voltage settings for the 12th modified example. The data allocation and read voltage settings for the 12th modified example will be described below with reference to Figure 30.

[0127] In the data assignment of the 12th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D23, D7, D5, D1, D9, D25, D29, D21, D20, D4, D6, D14, D10, D26, and D27 are assigned to 1, respectively.

[0128] In the data allocation of the 12th modified example, the read voltages used for the first page readout are R7, R15, R18, R22, R26, and R30. In the data allocation of the 12th modified example, the read voltages used for the second page readout are R4, R8, R13, R21, R24, and R28. In the data allocation of the 12th modified example, the read voltages used for the third page readout are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of the 12th modified example, the read voltages used for the fourth page readout are R2, R6, R10, R14, R19, and R27. In the data allocation of the 12th modified example, the read voltages used for the fifth page readout are R1, R5, R11, R17, R25, and R31.

[0129] (13th variation) Figure 31 is a table showing the data allocation and read voltage settings for the 13th modified example. The data allocation and read voltage settings for the 13th modified example will be described below with reference to Figure 31.

[0130] In the data assignment of the 13th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D0, D2, D3, D11, D15, D13, D5, D1, D17, D19, D18, D22, D20, D4, D12, D8, D9, D25, D29, D21, D23, D7, D6, D14, D10, D26, and D27 are assigned to 1, respectively.

[0131] In the data allocation of the 13th modified example, the read voltages used for reading the first page are R5, R13, R18, R22, R26, and R30. In the data allocation of the 13th modified example, the read voltages used for reading the second page are R4, R8, R11, R19, R24, and R28. In the data allocation of the 13th modified example, the read voltages used for reading the third page are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of the 13th modified example, the read voltages used for reading the fourth page are R2, R6, R10, R14, R17, and R25. In the data allocation of the 13th modified example, the read voltages used for reading the fifth page are R1, R7, R15, R21, R27, and R31.

[0132] (14th variation) Figure 32 is a table showing the data allocation and readout voltage settings for the 14th modified example. The data allocation and readout voltage settings for the 14th modified example will be described below with reference to Figure 32.

[0133] In the data assignment of the 14th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D20, D4, D5, D1, D9, D25, D29, D21, D23, D7, D6, D14, D10, D26, and D27 are assigned to 1, respectively.

[0134] In the data allocation of the 14th modified example, the read voltages used for reading the first page are R7, R15, R18, R22, R26, and R30. In the data allocation of the 14th modified example, the read voltages used for reading the second page are R4, R8, R13, R21, R24, and R28. In the data allocation of the 14th modified example, the read voltages used for reading the third page are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of the 14th modified example, the read voltages used for reading the fourth page are R2, R6, R10, R14, R17, and R25. In the data allocation of the 14th modified example, the read voltages used for reading the fifth page are R1, R5, R11, R19, R27, and R31.

[0135] (15th variation) Figure 33 is a table showing the data allocation and read voltage settings for the 15th modified example. The data allocation and read voltage settings for the 15th modified example will be described below with reference to Figure 33.

[0136] In the data assignment of the 15th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D5, D1, D0, D2, D18, D22, D20, D4, D12, D8, D9, D25, D29, D21, D23, D7, D6, D14, D10, D26, and D27 are assigned to 1, respectively.

[0137] In the data allocation of the 15th modified example, the read voltages used for reading the first page are R7, R15, R18, R22, R26, and R30. In the data allocation of the 15th modified example, the read voltages used for reading the second page are R4, R8, R11, R19, R24, and R28. In the data allocation of the 15th modified example, the read voltages used for reading the third page are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of the 15th modified example, the read voltages used for reading the fourth page are R2, R6, R10, R14, R17, and R25. In the data allocation of the 15th modified example, the read voltages used for reading the fifth page are R1, R5, R13, R21, R27, and R31.

[0138] (16th variation) Figure 34 is a table showing the data allocation and readout voltage settings for the 16th modified example. The data allocation and readout voltage settings for the 16th modified example will be described below with reference to Figure 34.

[0139] In the data assignment of the 16th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D8, D10, D14, D6, D22, D20, D21, D29, D13, D12, D4, D0, D16, D17, D19, D23, D7, D5, D1, D9, D25, D27, D26, D18, D2, D3, D11, and D15 are assigned to 1, respectively.

[0140] In the data allocation of the 16th modified example, the read voltages used for reading the first page are R4, R8, R12, R16, R20, R24, and R28. In the data allocation of the 16th modified example, the read voltages used for reading the second page are R7, R11, R14, R23, R27, and R30. In the data allocation of the 16th modified example, the read voltages used for reading the third page are R3, R6, R15, R19, R22, and R31. In the data allocation of the 16th modified example, the read voltages used for reading the fourth page are R2, R5, R9, R18, R21, and R25. In the data allocation of the 16th modified example, the read voltages used for reading the fifth page are R1, R10, R13, R17, R26, and R29.

[0141] (17th variation) Figure 35 is a table showing the data allocation and readout voltage settings for the 17th modified example. The data allocation and readout voltage settings for the 17th modified example will be described below with reference to Figure 35.

[0142] In the data assignment of the 17th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D8, D9, D1, D5, D21, D29, D25, D27, D11, D3, D2, D0, D16, D17, D19, D23, D7, D6, D14, D10, D26, D18, D22, D20, D4, D12, D13, and D15 are assigned to 1, respectively.

[0143] In the data allocation of the 17th modified example, the read voltages used for reading the first page are R4, R8, R12, R16, R20, R24, and R28. In the data allocation of the 17th modified example, the read voltages used for reading the second page are R6, R9, R13, R22, R25, and R29. In the data allocation of the 17th modified example, the read voltages used for reading the third page are R3, R7, R10, R19, R23, and R26. In the data allocation of the 17th modified example, the read voltages used for reading the fourth page are R2, R11, R15, R18, R27, and R31. In the data allocation of the 17th modified example, the read voltages used for reading the fifth page are R1, R5, R15, R17, R21, and R30.

[0144] (18th variation) Figure 36 is a table showing the data allocation and read voltage settings for the 18th modified example. The data allocation and read voltage settings for the 18th modified example will be described below with reference to Figure 36.

[0145] In the data assignment of the 18th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D8, D10, D14, D6, D22, D18, D26, D27, D11, D3, D2, D0, D16, D17, D19, D23, D7, D5, D1, D9, D25, D29, D21, D20, D4, D12, D13, and D15 are assigned to 1, respectively.

[0146] In the data allocation of the 18th modified example, the read voltages used for reading the first page are R8, R12, R16, R20, R24, and R28. In the data allocation of the 18th modified example, the read voltages used for reading the second page are R4, R7, R10, R13, R23, R26, and R29. In the data allocation of the 18th modified example, the read voltages used for reading the third page are R3, R6, R9, R19, R22, and R25. In the data allocation of the 18th modified example, the read voltages used for reading the fourth page are R2, R5, R15, R18, R21, and R31. In the data allocation of the 18th modified example, the read voltages used for reading the fifth page are R1, R11, R14, R17, R27, and R30.

[0147] (19th variation) Figure 37 is a table showing the data allocation and read voltage settings for the 19th modified example. The data allocation and read voltage settings for the 19th modified example will be described below with reference to Figure 37.

[0148] In the data assignment of the 19th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D27, D11, D3, D2, D0, D16, D20, D22, D6, D14, D10, D26, D18, D19, D23, D7, D5, D4, D12, D8, D9, D1, D17, D21, D29, D13, and D15 are assigned to 1, respectively.

[0149] In the data allocation of the 19th modified example, the read voltages used for reading the first page are R6, R10, R13, R16, R20, R27, and R30. In the data allocation of the 19th modified example, the read voltages used for reading the second page are R7, R14, R17, R23, R26, and R29. In the data allocation of the 19th modified example, the read voltages used for reading the third page are R3, R11, R15, R19, R24, and R28. In the data allocation of the 19th modified example, the read voltages used for reading the fourth page are R2, R5, R9, R12, R21, and R31. In the data allocation of the 19th modified example, the read voltages used for reading the fifth page are R1, R4, R8, R18, R22, and R25.

[0150] (20th variation) Figure 38 is a table showing the data allocation and read voltage settings for the 20th modified example. The data allocation and read voltage settings for the 20th modified example will be described below with reference to Figure 38.

[0151] In the data assignment of the 20th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D17, D21, D20, D22, D6, D2, D3, D1, D5, D4, D12, D14, D10, D26, D18, D16, D0, D8, D9, D11, D27, D19, D23, D7, D15, D13, and D29 are assigned to 1, respectively.

[0152] In the 20th modified example's data allocation, the read voltages used for the first page readout are R9, R18, R21, R25, R28, and R31. In the 20th modified example's data allocation, the read voltages used for the second page readout are R5, R15, R19, R22, R26, and R29. In the 20th modified example's data allocation, the read voltages used for the third page readout are R3, R6, R10, R13, R17, and R27. In the 20th modified example's data allocation, the read voltages used for the fourth page readout are R2, R8, R12, R16, R20, R24, and R30. In the 20th modified example's data allocation, the read voltages used for the fifth page readout are R1, R4, R7, R11, R14, and R23.

[0153] (21st variation) Figure 39 is a table showing the data allocation and read voltage settings for the 21st modified example. The data allocation and read voltage settings for the 21st modified example will be described below with reference to Figure 39.

[0154] In the data assignment of the 21st variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D8, D10, D14, D6, D22, D18, D26, D27, D25, D9, D1, D5, D7, D23, D19, D17, D16, D0, D2, D3, D11, D15, D13, D12, D4, D20, D21, and D29 are assigned to 1, respectively.

[0155] In the data allocation of the 21st modified example, the read voltages used for reading the first page are R4, R8, R13, R17, R21, and R29. In the data allocation of the 21st modified example, the read voltages used for reading the second page are R7, R10, R14, R24, R28, and R31. In the data allocation of the 21st modified example, the read voltages used for reading the third page are R3, R6, R9, R15, R18, and R25. In the data allocation of the 21st modified example, the read voltages used for reading the fourth page are R2, R5, R12, R16, R19, R22, and R26. In the data allocation of the 21st modified example, the read voltages used for reading the fifth page are R1, R11, R20, R23, R27, and R30.

[0156] (22nd variation) Figure 40 is a table showing the data allocation and readout voltage settings for the 22nd modified example. The data allocation and readout voltage settings for the 22nd modified example will be described below with reference to Figure 40.

[0157] In the data assignment of the 22nd variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D27, D11, D3, D2, D0, D16, D20, D21, D29, D13, D9, D1, D17, D19, D23, D7, D5, D4, D12, D8, D10, D26, D18, D22, D6, D14, and D15 are assigned to 1, respectively.

[0158] In the data allocation of the 22nd modified example, the read voltages used for reading the first page are R6, R10, R14, R17, R20, R26, and R29. In the data allocation of the 22nd modified example, the read voltages used for reading the second page are R7, R13, R16, R23, R27, and R30. In the data allocation of the 22nd modified example, the read voltages used for reading the third page are R3, R11, R15, R19, R24, and R28. In the data allocation of the 22nd modified example, the read voltages used for reading the fourth page are R2, R5, R9, R18, R21, and R25. In the data allocation of the 22nd modified example, the read voltages used for reading the fifth page are R1, R4, R8, R12, R22, and R31.

[0159] (23rd variation) Figure 41 is a table showing the data allocation and readout voltage settings for the 23rd modified example. The data allocation and readout voltage settings for the 23rd modified example will be described below with reference to Figure 41.

[0160] In the data assignment of the 23rd modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D17, D19, D18, D26, D10, D14, D12, D4, D5, D1, D3, D2, D6, D22, D20, D16, D0, D8, D9, D13, D29, D21, D23, D7, D15, D11, and D27 are assigned to 1, respectively.

[0161] In the data allocation of the 23rd modified example, the read voltages used for reading the first page are R9, R18, R21, R25, R28, and R31. In the data allocation of the 23rd modified example, the read voltages used for reading the second page are R5, R8, R12, R22, R26, and R29. In the data allocation of the 23rd modified example, the read voltages used for reading the third page are R3, R10, R14, R17, R20, R24, and R30. In the data allocation of the 23rd modified example, the read voltages used for reading the fourth page are R2, R6, R11, R15, R19, and R27. In the data allocation of the 23rd modified example, the read voltages used for reading the fifth page are R1, R4, R7, R13, R16, and R23.

[0162] (24th variation) Figure 42 is a table showing the data allocation and readout voltage settings for the 24th modified example. The data allocation and readout voltage settings for the 24th modified example will be described below with reference to Figure 42.

[0163] In the data assignment of the 24th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D17, D21, D20, D22, D6, D2, D3, D1, D9, D8, D10, D26, D18, D16, D0, D4, D12, D14, D15, D11, D27, D19, D23, D7, D5, D13, and D29 are assigned to 1, respectively.

[0164] In the data allocation of the 24th modified example, the read voltages used for reading the first page are R9, R16, R19, R25, R28, and R31. In the data allocation of the 24th modified example, the read voltages used for reading the second page are R5, R13, R17, R21, R26, and R30. In the data allocation of the 24th modified example, the read voltages used for reading the third page are R3, R6, R10, R20, R24, and R27. In the data allocation of the 24th modified example, the read voltages used for reading the fourth page are R2, R8, R12, R15, R18, R22, and R29. In the data allocation of the 24th modified example, the read voltages used for reading the fifth page are R1, R4, R7, R11, R14, and R23.

[0165] (25th variation) Figure 43 is a table showing the data allocation and readout voltage settings for the 25th modified example. The data allocation and readout voltage settings for the 25th modified example will be described below with reference to Figure 43.

[0166] In the data assignment of the 25th variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D18, D22, D6, D14, D12, D13, D29, D25, D17, D1, D5, D7, D15, D11, D9, D8, D0, D4, D20, D21, D23, D19, D3, D2, D10, D26, and D27 are assigned to 1, respectively.

[0167] In the data allocation of the 25th modified example, the read voltages used for reading the first page are R7, R11, R14, R23, R27, and R30. In the data allocation of the 25th modified example, the read voltages used for reading the second page are R4, R8, R13, R17, R21, and R29. In the data allocation of the 25th modified example, the read voltages used for reading the third page are R3, R6, R12, R15, R18, R22, and R26. In the data allocation of the 25th modified example, the read voltages used for reading the fourth page are R2, R5, R9, R16, R19, and R25. In the data allocation of the 25th modified example, the read voltages used for reading the fifth page are R1, R10, R20, R24, R28, and R31.

[0168] (26th variation) Figure 44 is a table showing the data allocation and readout voltage settings for the 26th modified example. The data allocation and readout voltage settings for the 26th modified example will be described below with reference to Figure 44.

[0169] In the data assignment of the 26th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D0, D2, D3, D11, D15, D13, D29, D21, D20, D22, D18, D26, D10, D14, D6, D7, D23, D19, D17, D1, D5, D4, D12, D8, D9, D25, and D27 are assigned to 1, respectively.

[0170] In the data allocation of the 26th modified example, the read voltages used for reading the first page are R5, R11, R17, R24, and R30. In the data allocation of the 26th modified example, the read voltages used for reading the second page are R4, R8, R12, R16, R19, and R27. In the data allocation of the 26th modified example, the read voltages used for reading the third page are R3, R9, R15, R18, R22, R25, and R28. In the data allocation of the 26th modified example, the read voltages used for reading the fourth page are R2, R6, R10, R14, R23, and R31. In the data allocation of the 26th modified example, the read voltages used for reading the fifth page are R1, R7, R13, R20, R26, and R29.

[0171] (27th variation) Figure 45 is a table showing the data allocation and readout voltage settings for the 27th modified example. The data allocation and readout voltage settings for the 27th modified example will be described below with reference to Figure 45.

[0172] In the data assignment of the 27th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D8, D0, D4, D20, D22, D23, D7, D5, D1, D9, D25, D27, D19, D3, D2, D6, D14, D12, D13, D29, D21, D17, D16, D18, D26, D10, D11, and D15 are assigned to 1, respectively.

[0173] In the data allocation of the 27th modified example, the read voltages used for reading the first page are R4, R7, R10, R14, R17, R23, and R29. In the data allocation of the 27th modified example, the read voltages used for reading the second page are R5, R13, R16, R20, R24, and R28. In the data allocation of the 27th modified example, the read voltages used for reading the third page are R3, R6, R12, R19, R25, and R31. In the data allocation of the 27th modified example, the read voltages used for reading the fourth page are R2, R8, R11, R15, R21, and R27. In the data allocation of the 27th modified example, the read voltages used for reading the fifth page are R1, R9, R18, R22, R26, and R30.

[0174] (28th variation) Figure 46 is a table showing the data allocation and readout voltage settings for the 28th modified example. The data allocation and readout voltage settings for the 28th modified example will be described below with reference to Figure 46.

[0175] In the data assignment of the 28th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D1, D5, D7, D23, D19, D27, D25, D9, D8, D10, D26, D18, D22, D6, D14, D12, D13, D29, D21, D20, D4, D0, D2, D3, D11, and D15 are assigned to 1, respectively.

[0176] In the data allocation of the 28th modified example, the read voltages used for reading the first page are R6, R9, R13, R1, R19, R23, and R26. In the data allocation of the 28th modified example, the read voltages used for reading the second page are R4, R11, R17, R20, R24, and R30. In the data allocation of the 28th modified example, the read voltages used for reading the third page are R3, R7, R10, R18, R27, and R31. In the data allocation of the 28th modified example, the read voltages used for reading the fourth page are R2, R8, R12, R15, R21, and R28. In the data allocation of the 28th modified example, the read voltages used for reading the fifth page are R1, R5, R14, R22, R25, and R29.

[0177] (29th variation) Figure 47 is a table showing the data allocation and readout voltage settings for the 29th modified example. The data allocation and readout voltage settings for the 29th modified example will be described below with reference to Figure 47.

[0178] In the data assignment of the 29th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D0, D4, D12, D14, D15, D11, D3, D2, D6, D22, D20, D21, D29, D13, D9, D8, D10, D26, D18, D19, D23, D7, D5, D1, D17, D25, and D27 are assigned to 1, respectively.

[0179] In the data allocation of the 29th modified example, the read voltages used for reading the first page are R5, R14, R18, R22, R26, and R29. In the data allocation of the 29th modified example, the read voltages used for reading the second page are R4, R7, R11, R17, R23, and R30. In the data allocation of the 29th modified example, the read voltages used for reading the third page are R3, R6, R10, R13, R19, R25, and R28. In the data allocation of the 29th modified example, the read voltages used for reading the fourth page are R2, R8, R15, R21, R27, and R31. In the data allocation of the 29th modified example, the read voltages used for reading the fifth page are R1, R9, R12, R16, R20, and R24.

[0180] (30th variation) Figure 48 is a table showing the data allocation and readout voltage settings for the 30th modified example. The data allocation and readout voltage settings for the 30th modified example will be described below with reference to Figure 48.

[0181] In the data assignment of the 30th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D8, D9, D13, D29, D21, D23, D19, D18, D26, D10, D14, D12, D4, D5, D1, D17, D25, D27, D11, D3, D2, D0, D16, D20, D22, D6, D7, and D15 are assigned to 1, respectively.

[0182] In the data allocation of the 30th modified example, the read voltages used for reading the first page are R4, R7, R13, R19, R22, R26, and R29. In the data allocation of the 30th modified example, the read voltages used for reading the second page are R8, R12, R16, R20, R23, and R31. In the data allocation of the 30th modified example, the read voltages used for reading the third page are R3, R6, R10, R14, R18, and R27. In the data allocation of the 30th modified example, the read voltages used for reading the fourth page are R2, R9, R15, R21, R25, and R28. In the data allocation of the 30th modified example, the read voltages used for reading the fifth page are R1, R5, R11, R17, R24, and R30.

[0183] (31st variation) Figure 49 is a table showing the data allocation and read voltage settings for the 31st modified example. The data allocation and read voltage settings for the 31st modified example will be described below with reference to Figure 49.

[0184] In the data assignment of the 31st modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D17, D19, D23, D7, D5, D1, D9, D8, D12, D4, D6, D22, D18, D26, D10, D14, D15, D13, D29, D21, D20, D16, D0, D2, D3, D11, and D27 are assigned to 1, respectively.

[0185] In the data allocation of the 31st modified example, the read voltages used for reading the first page are R8, R16, R19, R23, R27, and R31. In the data allocation of the 31st modified example, the read voltages used for reading the second page are R5, R11, R14, R18, R24, and R30. In the data allocation of the 31st modified example, the read voltages used for reading the third page are R3, R7, R10, R13, R17, R20, and R26. In the data allocation of the 31st modified example, the read voltages used for reading the fourth page are R2, R6, R9, R15, R22, and R28. In the data allocation of the 31st modified example, the read voltages used for reading the fifth page are R1, R4, R12, R21, R25, and R29.

[0186] (32nd variation) Figure 50 is a table showing the data allocation and readout voltage settings for the 32nd modified example. The data allocation and readout voltage settings for the 32nd modified example will be described below with reference to Figure 50.

[0187] In the data assignment of the 32nd variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D1, D5, D7, D6, D14, D10, D26, D27, D25, D9, D8, D0, D2, D18, D22, D20, D4, D12, D13, D29, D21, D23, D19, D3, D11, and D15 are assigned to 1, respectively.

[0188] In the data allocation of the 32nd modified example, the read voltages used for reading the first page are R6, R12, R15, R19, R22, R25, and R29. In the data allocation of the 32nd modified example, the read voltages used for reading the second page are R4, R10, R17, R23, R26, and R30. In the data allocation of the 32nd modified example, the read voltages used for reading the third page are R3, R7, R11, R20, R28, and R31. In the data allocation of the 32nd modified example, the read voltages used for reading the fourth page are R2, R8, R14, R18, R21, and R27. In the data allocation of the 32nd modified example, the read voltages used for reading the fifth page are R1, R5, R9, R13, R16, and R24.

[0189] (33rd variation) Figure 51 is a table showing the data allocation and read voltage settings for the 33rd modified example. The data allocation and read voltage settings for the 33rd modified example will be described below with reference to Figure 51.

[0190] In the data assignment of the 33rd variant, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D17, D1, D5, D4, D20, D16, D18, D26, D10, D11, D9, D13, D29, D21, D23, D22, D6, D2, D0, D8, D12, D14, D15, D7, D3, D19, and D27 are assigned to 1, respectively.

[0191] In the data allocation of the 33rd modified example, the read voltages used for reading the first page are R6, R9, R13, R17, R21, and R30. In the data allocation of the 33rd modified example, the read voltages used for reading the second page are R5, R12, R18, R24, R28, and R31. In the data allocation of the 33rd modified example, the read voltages used for reading the third page are R3, R7, R10, R16, R22, R25, and R29. In the data allocation of the 33rd modified example, the read voltages used for reading the fourth page are R2, R11, R15, R19, R23, and R26. In the data allocation of the 33rd modified example, the read voltages used for reading the fifth page are R1, R4, R8, R14, R20, and R27.

[0192] (34th variation) Figure 52 is a table showing the data allocation and readout voltage settings for the 34th modified example. The data allocation and readout voltage settings for the 34th modified example will be described below with reference to Figure 52.

[0193] In the data assignment of the 34th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D27, D19, D3, D1, D9, D8, D12, D14, D6, D2, D0, D16, D17, D21, D23, D7, D15, D11, D10, D26, D18, D22, D20, D4, D5, D13, and D29 are assigned to 1, respectively.

[0194] In the data allocation of the 34th modified example, the read voltages used for reading the first page are R7, R16, R20, R24, R28, and R31. In the data allocation of the 34th modified example, the read voltages used for reading the second page are R6, R9, R13, R21, R25, and R30. In the data allocation of the 34th modified example, the read voltages used for reading the third page are R3, R11, R14, R18, R22, and R26. In the data allocation of the 34th modified example, the read voltages used for reading the fourth page are R2, R5, R8, R12, R15, R19, and R27. In the data allocation of the 34th modified example, the read voltages used for reading the fifth page are R1, R4, R10, R17, R23, and R29.

[0195] (35th variation) Figure 53 is a table showing the data allocation and read voltage settings for the 35th modified example. The data allocation and read voltage settings for the 35th modified example will be described below with reference to Figure 53.

[0196] In the data assignment of the 35th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D9, D1, D3, D2, D6, D14, D12, D13, D29, D21, D17, D16, D0, D8, D10, D26, D18, D22, D20, D4, D5, D7, D23, D19, D27, D11, and D15 are assigned to 1, respectively.

[0197] In the data allocation of the 35th modified example, the read voltages used for reading the first page are R5, R13, R17, R20, R24, R27, and R30. In the data allocation of the 35th modified example, the read voltages used for reading the second page are R6, R10, R14, R18, R21, and R29. In the data allocation of the 35th modified example, the read voltages used for reading the third page are R3, R9, R15, R22, R28, and R31. In the data allocation of the 35th modified example, the read voltages used for reading the fourth page are R2, R7, R11, R19, R23, and R26. In the data allocation of the 35th modified example, the read voltages used for reading the fifth page are R1, R4, R8, R12, R16, and R25.

[0198] (36th variation) Figure 54 is a table showing the data allocation and readout voltage settings for the 36th modified example. The data allocation and readout voltage settings for the 36th modified example will be described below with reference to Figure 54.

[0199] In the data assignment of the 36th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D27, D11, D3, D2, D6, D22, D20, D21, D29, D13, D9, D8, D0, D16, D18, D26, D10, D14, D12, D4, D5, D1, D17, D19, D23, D7, and D15 are assigned to 1, respectively.

[0200] In the data allocation of the 36th modified example, the read voltages used for reading the first page are R6, R10, R14, R18, R21, R27, and R30. In the data allocation of the 36th modified example, the read voltages used for reading the second page are R7, R13, R17, R20, R24, and R31. In the data allocation of the 36th modified example, the read voltages used for reading the third page are R3, R9, R15, R22, R26, and R29. In the data allocation of the 36th modified example, the read voltages used for reading the fourth page are R2, R5, R11, R19, R23, and R28. In the data allocation of the 36th modified example, the read voltages used for reading the fifth page are R1, R4, R8, R12, R16, and R25.

[0201] (37th variation) Figure 55 is a table showing the data allocation and read voltage settings for the 37th modified example. The data allocation and read voltage settings for the 37th modified example will be described below with reference to Figure 55.

[0202] In the data assignment of the 37th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D18, D22, D6, D7, D15, D11, D9, D8, D0, D2, D3, D19, D23, D21, D20, D4, D12, D14, D10, D26, D27, D25, D17, D1, D5, D13, and D29 are assigned to 1, respectively.

[0203] In the data allocation of the 37th modified example, the read voltages used for reading the first page are R7, R16, R20, R24, R28, and R31. In the data allocation of the 37th modified example, the read voltages used for reading the second page are R4, R9, R13, R21, R27, and R30. In the data allocation of the 37th modified example, the read voltages used for reading the third page are R3, R6, R10, R17, R23, and R29. In the data allocation of the 37th modified example, the read voltages used for reading the fourth page are R2, R5, R11, R14, R18, R22, and R26. In the data allocation of the 37th modified example, the read voltages used for reading the fifth page are R1, R8, R12, R15, R19, and R25.

[0204] (38th variation) Figure 56 is a table showing the data allocation and readout voltage settings for the 38th modified example. The data allocation and readout voltage settings for the 38th modified example will be described below with reference to Figure 56.

[0205] In the data assignment of the 38th modification example, data sets D31, D30, D28, D24, D25, D17, D1, D3, D2, D6, D22, D20, D16, D0, D8, D9, D13, D29, D21, D23, D19, D18, D26, D10, D14, D12, D4, D5, D7, D15, D1, and D27 are assigned to states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31, respectively.

[0206] In the data assignment of the 38th modification example, the read voltages used for the first page reading are R6, R10, R13, R17, R23, and R31. In the data assignment of the 38th modification example, the read voltages used for the second page reading are R5, R14, R18, R22, R26, and R29. In the data assignment of the 38th modification example, the read voltages used for the third page reading are R3, R9, R12, R16, R20, R24, and R30. In the data assignment of the 38th modification example, the read voltages used for the fourth page reading are R2, R7, R11, R19, R25, and R28. In the data assignment of the 38th modification example, the read voltages used for the fifth page reading are R1, R4, R8, R15, R21, and R27. <{0000895}>

[0207] (39th modification example) FIG. 57 is a table showing the data assignment and read voltage setting of the 39th modification example. Hereinafter, the data assignment and read voltage setting of the 39th modification example will be described with reference to FIG. 57.

[0208] In the data assignment of the 39th modification example, data sets D31, D30, D28, D24, D16, D0, D4, D12, D14, D15, D11, D27, D25, D17, D21, D20, D22, D6, D2, D3, D1, D9, D8, D10, D26, D18, D19, D23, D7, D5, D13, and D29 are respectively assigned to states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31.

[0209] In the data assignment of the 39th modification example, the read voltages used for the first page read are R5, R11, R17, R24, R28, and R31. In the data assignment of the 39th modification example, the read voltages used for the second page read are R4, R7, R13, R21, R25, and R30. In the data assignment of the 39th modification example, the read voltages used for the third page read are R3, R6, R10, R14, R18, and R27. In the data assignment of the 39th modification example, the read voltages used for the fourth page read are R2, R8, R12, R16, R20, R23, and R29. In the data assignment of the 39th modification example, the read voltages used for the fifth page read are R1, R9, R15, R19, R22, and R26.

[0210] (40th modification example) Figure 58 is a table showing the data assignment and read voltage setting of the 40th modification example. Hereinafter, the data assignment and read voltage setting of the 40th modification example will be described with reference to Figure 58.

[0211] In the data assignment of the 40th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D21, D23, D7, D6, D14, D12, D8, D0, D2, D3, D19, D27, D25, D9, D1, D5, D4, D20, D22, D18, D26, D10, D11, D15, D13, and D29 are assigned to 1, respectively.

[0212] In the data allocation of the 40th modified example, the read voltages used for reading the first page are R8, R16, R19, R23, R27, and R31. In the data allocation of the 40th modified example, the read voltages used for reading the second page are R4, R10, R13, R17, R20, and R26. In the data allocation of the 40th modified example, the read voltages used for reading the third page are R3, R6, R12, R21, R25, and R29. In the data allocation of the 40th modified example, the read voltages used for reading the fourth page are R2, R7, R11, R14, R18, R24, and R30. In the data allocation of the 40th modified example, the read voltages used for reading the fifth page are R1, R5, R9, R15, R22, and R28.

[0213] (41st variation) Figure 59 is a table showing the data allocation and readout voltage settings for the 41st modified example. The data allocation and readout voltage settings for the 41st modified example will be described below with reference to Figure 59.

[0214] In the data assignment of the 41st modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D1, D5, D7, D6, D14, D10, D26, D27, D25, D9, D8, D0, D2, D18, D22, D20, D4, D12, D13, D15, D11, D3, D19, D23, D21, and D29 are assigned to 1, respectively.

[0215] In the data allocation of the 41st modified example, the read voltages used for reading the first page are R6, R12, R15, R19, R22, and R28. In the data allocation of the 41st modified example, the read voltages used for reading the second page are R4, R10, R17, R23, R27, and R31. In the data allocation of the 41st modified example, the read voltages used for reading the third page are R3, R7, R11, R20, R26, and R29. In the data allocation of the 41st modified example, the read voltages used for reading the fourth page are R2, R8, R14, R18, R21, R25, and R30. In the data allocation of the 41st modified example, the read voltages used for reading the fifth page are R1, R5, R9, R13, R16, and R24.

[0216] (42nd variation) Figure 60 is a table showing the data allocation and readout voltage settings for the 42nd modified example. The data allocation and readout voltage settings for the 42nd modified example will be described below with reference to Figure 60.

[0217] In the data assignment of the 42nd modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D27, D19, D3, D7, D15, D14, D12, D8, D0, D2, D6, D22, D23, D21, D17, D1, D9, D11, D10, D26, D18, D16, D20, D4, D5, D13, and D29 are assigned to 1, respectively.

[0218] In the data allocation of the 42nd modified example, the read voltages used for reading the first page are R7, R16, R20, R24, R28, and R31. In the data allocation of the 42nd modified example, the read voltages used for reading the second page are R6, R9, R13, R21, R25, and R30. In the data allocation of the 42nd modified example, the read voltages used for reading the third page are R3, R8, R12, R15, R19, and R27. In the data allocation of the 42nd modified example, the read voltages used for reading the fourth page are R2, R5, R11, R14, R18, R22, and R26. In the data allocation of the 42nd modified example, the read voltages used for reading the fifth page are R1, R4, R10, R17, R23, and R29.

[0219] (43rd variation) Figure 61 is a table showing the data allocation and readout voltage settings for the 43rd modified example. The data allocation and readout voltage settings for the 43rd modified example will be described below with reference to Figure 61.

[0220] In the data assignment of the 43rd modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D25, D17, D1, D3, D2, D6, D22, D20, D21, D29, D13, D9, D8, D0, D16, D18, D26, D10, D14, D12, D4, D5, D7, D23, D19, D27, D11, and D15 are assigned to 1, respectively.

[0221] In the data allocation of the 43rd modified example, the read voltages used for reading the first page are R6, R10, R14, R18, R21, R27, and R30. In the data allocation of the 43rd modified example, the read voltages used for reading the second page are R5, R13, R17, R20, R24, and R29. In the data allocation of the 43rd modified example, the read voltages used for reading the third page are R3, R9, R15, R22, R28, and R31. In the data allocation of the 43rd modified example, the read voltages used for reading the fourth page are R2, R7, R11, R19, R23, and R26. In the data allocation of the 43rd modified example, the read voltages used for reading the fifth page are R1, R4, R8, R12, R16, and R25.

[0222] (44th variation) Figure 62 is a table showing the data allocation and readout voltage settings for the 44th modified example. The data allocation and readout voltage settings for the 44th modified example will be described below with reference to Figure 62.

[0223] In the data assignment of the 44th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D21, D5, D7, D15, D11, D10, D8, D0, D4, D20, D22, D23, D19, D3, D1, D9, D25, D27, D26, D18, D2, D6, D14, D12, D13, and D29 are assigned to 1, respectively.

[0224] In the data allocation of the 44th modified example, the read voltages used for reading the first page are R7, R15, R19, R22, R26, and R31. In the data allocation of the 44th modified example, the read voltages used for reading the second page are R4, R9, R13, R21, R25, and R28. In the data allocation of the 44th modified example, the read voltages used for reading the third page are R3, R6, R10, R14, R18, and R27. In the data allocation of the 44th modified example, the read voltages used for reading the fourth page are R2, R8, R12, R16, R20, R23, and R29. In the data allocation of the 44th modified example, the read voltages used for reading the fifth page are R1, R5, R11, R17, R24, and R30.

[0225] (45th variation) Figure 63 is a table showing the data allocation and readout voltage settings for the 45th modified example. The data allocation and readout voltage settings for the 45th modified example will be described below with reference to Figure 63.

[0226] In the data assignment of the 45th modification example, data sets D31, D30, D28, D24, D16, D0, D1, D9, D11, D15, D14, D6, D2, D3, D19, D17, D21, D20, D4, D12, D8, D10, D26, D18, D22, D23, D7, D5, D13, D29, D25, and D27 are respectively assigned to states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, and S31.

[0227] In the data assignment of the 45th modification example, the read voltages used for the first page read are R5, R14, R18, R22, R26, and R29. In the data assignment of the 45th modification example, the read voltages used for the second page read are R4, R7, R11, R19, R23, and R28. In the data assignment of the 45th modification example, the read voltages used for the third page read are R3, R9, R12, R16, R20, R24, and R30. In the data assignment of the 45th modification example, the read voltages used for the fourth page read are R2, R8, R15, R21, R27, and R31. In the data assignment of the 45th modification example, the read voltages used for the fifth page read are R1, R6, R10, R13, R17, and R25.

[0228] (46th modification example) FIG. 64 is a table showing the data assignment and read voltage setting of the 46th modification example. Hereinafter, the data assignment and read voltage setting of the 46th modification example will be described with reference to FIG. 64.

[0229] In the data assignment of the 46th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D21, D23, D7, D15, D11, D10, D26, D18, D22, D20, D4, D5, D1, D3, D19, D27, D25, D9, D8, D0, D2, D6, D14, D12, D13, and D29 are assigned to 1, respectively.

[0230] In the data allocation of the 46th modified example, the read voltages used for reading the first page are R8, R12, R16, R20, R23, and R31. In the data allocation of the 46th modified example, the read voltages used for reading the second page are R4, R9, R13, R21, R25, and R28. In the data allocation of the 46th modified example, the read voltages used for reading the third page are R3, R6, R10, R14, R18, and R27. In the data allocation of the 46th modified example, the read voltages used for reading the fourth page are R2, R7, R15, R19, R22, R26, and R29. In the data allocation of the 46th modified example, the read voltages used for reading the fifth page are R1, R5, R11, R17, R24, and R30.

[0231] (47th variation) Figure 65 is a table showing the data allocation and readout voltage settings for the 47th modified example. The data allocation and readout voltage settings for the 47th modified example will be described below with reference to Figure 65.

[0232] In the data assignment of the 47th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D0, D4, D12, D14, D15, D11, D3, D2, D6, D22, D20, D21, D17, D1, D9, D8, D10, D26, D18, D19, D23, D7, D5, D13, D29, D25, and D27 are assigned to 1, respectively.

[0233] In the data allocation of the 47th modified example, the read voltages used for reading the first page are R5, R14, R18, R22, R26, and R29. In the data allocation of the 47th modified example, the read voltages used for reading the second page are R4, R7, R11, R19, R23, and R28. In the data allocation of the 47th modified example, the read voltages used for reading the third page are R3, R6, R10, R13, R17, R25, and R30. In the data allocation of the 47th modified example, the read voltages used for reading the fourth page are R2, R8, R15, R21, R27, and R31. In the data allocation of the 47th modified example, the read voltages used for reading the fifth page are R1, R9, R12, R16, R20, and R24.

[0234] (48th variation) Figure 66 is a table showing the data allocation and readout voltage settings for the 48th modified example. The data allocation and readout voltage settings for the 48th modified example will be described below with reference to Figure 66.

[0235] In the data assignment of the 48th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D1, D5, D7, D6, D22, D18, D26, D10, D14, D12, D4, D20, D21, D23, D19, D27, D25, D9, D8, D0, D2, D3, D11, D15, D13, and D29 are assigned to 1, respectively.

[0236] In the data allocation of the 48th modified example, the read voltages used for reading the first page are R6, R10, R13, R17, R23, and R31. In the data allocation of the 48th modified example, the read voltages used for reading the second page are R4, R12, R16, R21, R25, and R28. In the data allocation of the 48th modified example, the read voltages used for reading the third page are R3, R7, R11, R14, R20, and R29. In the data allocation of the 48th modified example, the read voltages used for reading the fourth page are R2, R8, R15, R19, R22, R26, and R30. In the data allocation of the 48th modified example, the read voltages used for reading the fifth page are R1, R5, R9, R18, R24, and R27.

[0237] (49th variation) Figure 67 is a table showing the data allocation and readout voltage settings for the 49th modified example. The data allocation and readout voltage settings for the 49th modified example will be described below with reference to Figure 67.

[0238] In the data assignment of the 49th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D0, D2, D10, D26, D27, D25, D17, D21, D23, D7, D6, D14, D12, D8, D9, D1, D5, D4, D20, D22, D18, D19, D3, D11, D15, D13, and D29 are assigned to 1, respectively.

[0239] In the data allocation of the 49th modified example, the read voltages used for reading the first page are R5, R8, R14, R23, R27, and R31. In the data allocation of the 49th modified example, the read voltages used for reading the second page are R4, R7, R11, R16, R20, and R28. In the data allocation of the 49th modified example, the read voltages used for reading the third page are R3, R12, R18, R21, R25, and R29. In the data allocation of the 49th modified example, the read voltages used for reading the fourth page are R2, R6, R10, R13, R17, R24, and R30. In the data allocation of the 49th modified example, the read voltages used for reading the fifth page are R1, R9, R15, R19, R22, and R26.

[0240] (50th variation) Figure 68 is a table showing the data allocation and readout voltage settings for the 50th modified example. The data allocation and readout voltage settings for the 50th modified example will be described below with reference to Figure 68.

[0241] In the data assignment of the 50th modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D8, D9, D1, D5, D7, D6, D14, D10, D26, D18, D22, D20, D4, D12, D13, D29, D21, D23, D19, D3, D2, D0, D16, D17, D25, D27, D11, and D15 are assigned to 1, respectively.

[0242] In the data allocation of the 50th modified example, the read voltages used for reading the first page are R4, R12, R16, R19, R23, R26, and R30. In the data allocation of the 50th modified example, the read voltages used for reading the second page are R6, R10, R13, R17, R20, and R28. In the data allocation of the 50th modified example, the read voltages used for reading the third page are R3, R7, R11, R14, R22, and R31. In the data allocation of the 50th modified example, the read voltages used for reading the fourth page are R2, R8, R15, R21, R25, and R29. In the data allocation of the 50th modified example, the read voltages used for reading the fifth page are R1, R5, R9, R18, R24, and R27.

[0243] (51st variation) Figure 69 is a table showing the data allocation and read voltage settings for the 51st modified example. The data allocation and read voltage settings for the 51st modified example will be described below with reference to Figure 69.

[0244] In the data assignment of the 51st modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D8, D0, D2, D6, D14, D12, D13, D9, D25, D27, D19, D3, D1, D5, D4, D20, D22, D23, D7, D15, D11, D10, D26, D18, D16, D17, D21, and D29 are assigned to 1, respectively.

[0245] In the data allocation of the 51st modified example, the read voltages used for reading the first page are R4, R12, R15, R19, R22, and R26. In the data allocation of the 51st modified example, the read voltages used for reading the second page are R5, R8, R14, R23, R27, and R31. In the data allocation of the 51st modified example, the read voltages used for reading the third page are R3, R7, R11, R17, R24, and R30. In the data allocation of the 51st modified example, the read voltages used for reading the fourth page are R2, R6, R9, R13, R16, R20, and R28. In the data allocation of the 51st modified example, the read voltages used for reading the fifth page are R1, R10, R18, R21, R25, and R29.

[0246] (52nd variation) Figure 70 is a table showing the data allocation and read voltage settings for the 52nd modified example. The data allocation and read voltage settings for the 52nd modified example will be described below with reference to Figure 70.

[0247] In the data assignment of the 52nd modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D16, D17, D19, D23, D7, D6, D14, D10, D26, D27, D25, D9, D8, D0, D2, D18, D22, D20, D4, D12, D13, D15, D11, D3, D1, D5, D21, and D29 are assigned to 1, respectively.

[0248] In the data allocation of the 52nd modified example, the read voltages used for reading the first page are R8, R12, R15, R19, R22, and R30. In the data allocation of the 52nd modified example, the read voltages used for reading the second page are R4, R10, R17, R23, R27, and R31. In the data allocation of the 52nd modified example, the read voltages used for reading the third page are R3, R7, R11, R20, R26, and R29. In the data allocation of the 52nd modified example, the read voltages used for reading the fourth page are R2, R6, R14, R18, R21, R25, and R28. In the data allocation of the 52nd modified example, the read voltages used for reading the fifth page are R1, R5, R9, R13, R16, and R24.

[0249] (53rd variation) Figure 71 is a table showing the data allocation and read voltage settings for the 53rd modified example. The data allocation and read voltage settings for the 53rd modified example will be described below with reference to Figure 71.

[0250] In the data assignment of the 53rd modified example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S3 Datasets D31, D30, D28, D24, D8, D9, D13, D29, D21, D20, D22, D6, D2, D0, D16, D17, D25, D27, D11, D3, D1, D5, D4, D12, D14, D10, D26, D18, D19, D23, D7, and D15 are assigned to 1, respectively.

[0251] In the data allocation of the 53rd modified example, the read voltages used for reading the first page are R4, R7, R11, R14, R18, R26, and R30. In the data allocation of the 53rd modified example, the read voltages used for reading the second page are R8, R16, R19, R23, R27, and R31. In the data allocation of the 53rd modified example, the read voltages used for reading the third page are R3, R6, R12, R21, R25, and R29. In the data allocation of the 53rd modified example, the read voltages used for reading the fourth page are R2, R10, R13, R17, R20, and R24. In the data allocation of the 53rd modified example, the read voltages used for reading the fifth page are R1, R5, R9, R15, R22, and R28.

[0252] [1-5] Characteristics of each data assignment The data assignment for each of the first to 53 modifications is "7-6-6-6-6 coding". That is, in the data assignments for each of the first to 53 modifications, the difference between the maximum and minimum number of reads set to confirm the data between pages is "1", as in the first embodiment. In the data assignments for each of the first to 15 modifications, the interval of the read voltage on each page is at a minimum of "3" and at a maximum of "8", as in the first embodiment. In the data assignments for the 16th and 17th modifications, the interval of the read voltage on each page is at a minimum of "3" and at a maximum of "9". Also, in the data assignments for the 16th and 17th modifications, the interval of the read voltage on pages with 7 reads consists only of "4". In the data assignments for the 18th to 25th modifications, the interval of the read voltage on each page is at a minimum of "3" and at a maximum of "10". In the data assignments for each of the 26th to 53rd variations, the interval between the read voltages on each page is at least "3" and at most "9".

[0253] The following conditions (1) to (5) are conditions that, in addition to the conditions described in the effects of the embodiment, should preferably be avoided as much as possible when considering data allocation. (1) The lowest read voltage used in the read operation of a page with 7 read operations is one state away from the lowest read voltage R1 among the read voltages R1 to R31. (2) The highest read voltage used in the read operation of a page with 7 read operations is one state away from the highest read voltage R31 among the read voltages R1 to R31. (3) The minimum interval between the multiple read voltages used in a page read operation with 7 read operations is "3 (i.e., 3 states)". (4) The minimum interval between multiple read voltages used in a page read operation using the lowest read voltage R1 or the highest read voltage R31 is "3 (i.e., 3 states)", or the maximum is "9 (i.e., 9 states)". (5) There are pages in which both the lowest read voltage R1 and the highest read voltage R31 among the read voltages R1 to R31 are used for the read operation. In other words, pages 1 to 5 include pages in which both read voltages R1 and R31 are used for the read operation. (6) The minimum interval of the read voltage used in the read operation of each page is "3 (i.e., 3 states)" and the maximum is "9 (i.e., 9 states)" or more.

[0254] The priority of avoiding each condition is (1), (2) < (3), (4) < (5) < (6). The fewer conditions (1) to (6) that are satisfied, the closer each data assignment gets to the ideal data assignment. Also, between satisfying one low-priority condition and satisfying one high-priority condition, satisfying one low-priority condition is closer to the ideal data assignment. When conditions (1) to (6) are considered, the embodiments and the first to seventeenth modifications are classified, for example, into groups 1 to 7.

[0255] The first group includes embodiments and the first to fourth variations. The data assignments in the first group satisfy either condition (1) or (2) from conditions (1) to (6). That is, the data assignments in the first group do not satisfy the other of conditions (1) or (2), and conditions (3), (4), (5), and (6).

[0256] The second group includes the fifth variation. The data assignment for the second group satisfies conditions (2) and (4). That is, the data assignment for the second group does not satisfy conditions (1), (3), (5) and (6).

[0257] The third group includes the sixth and seventh variations. The data assignment for the third group satisfies conditions (1), (2), and (3). That is, the data assignment for the third group does not satisfy conditions (4), (5), and (6).

[0258] The fourth group includes the eighth variant. The data assignment for the fourth group satisfies conditions (2), (3), and (4). That is, the data assignment for the fourth group does not satisfy conditions (1), (5), and (6).

[0259] Group 5 includes variations of 9 through 11. The data assignment for Group 5 satisfies conditions (1), (2), (3), and (4). That is, the data assignment for Group 5 does not satisfy conditions (5) and (6).

[0260] Group 6 includes variations of the 12th to 15th sets. The data assignment for Group 6 satisfies conditions (3) and (5). That is, the data assignment for Group 6 does not satisfy conditions (1), (2), (4) and (6).

[0261] Group 7 includes variations of the 16th and 17th. The data assignment for Group 7 satisfies conditions (4) and (6). That is, the data assignment for Group 7 does not satisfy conditions (1), (2), (3) and (5).

[0262] When scoring using conditions (1) to (6), the read efficiency is ranked from best to worst as follows: Group 1, Group 2, Group 3, Group 4, Group 5, Group 6, and Group 7. Note that the data assignments for each of the 26th to 53rd variations have read efficiency similar to that of Group 7, for example. The read efficiency in the data assignments for each of the 18th to 25th variation examples is slightly worse than that of Group 7, because the maximum interval between read voltages on each page is "10". Also, each of the 18th, 19th, 20th, 21st, 23rd, and 24th variations does not have a page that uses both the lowest read voltage R1 and the highest read voltage R31. Therefore, the read efficiency of each of the 18th, 19th, 20th, 21st, 23rd, and 24th variations is higher than the data allocation of each of the 22nd and 25th variations, which have pages that use both the lowest read voltage R1 and the highest read voltage R31. The memory device 20 can perform efficient read operations regardless of which group of data allocation is used.

[0263] Conditions (1) to (6) can be rephrased as conditions (1a) to (6a) below. Conditions (1a) to (6a) are preferable to apply as much as possible, in addition to the conditions described in the effects of the embodiment. (1a) The lowest read voltage used in a page read operation with 7 read counts is 2 states or more away from the lowest read voltage R1 among the read voltages R1 to R31. (2a) The highest read voltage used in a page read operation with 7 read counts is 2 states or more away from the highest read voltage R31 among the read voltages R1 to R31. (3a) The minimum interval between the multiple read voltages used in a page read operation with 7 reads is "4 (i.e., 4 states)". (4a) The minimum interval between multiple read voltages used in a page read operation using the lowest read voltage R1 or the highest read voltage R31 is "4 (i.e., 4 states)", or the maximum is "8 (i.e., 8 states)". (5a) The lowest read voltage R1 and the highest read voltage R31 among the read voltages R1 to R31 are used for reading different pages. In other words, pages 1 to 5 do not contain any pages where both read voltages R1 and R31 are used for reading operations. (6a) The minimum interval of the read voltage used in the read operation of each page is "4 (i.e., 4 states)" and the maximum is "8 (i.e., 8 states)".

[0264] The priority order for each condition is (1a), (2a) > (3a), (4a) > (5a) > (6a). The more conditions (1a) to (6a) that are met, the closer the data assignment will be to the ideal data assignment. Also, between meeting one low-priority condition and meeting one high-priority condition, meeting one high-priority condition will bring the data assignment closer to the ideal.

[0265] [2] Second embodiment The configuration of the information processing system 1 according to the second embodiment is the same as that of the information processing system 1 according to the first embodiment. In the second embodiment, the memory device 20 performs a page-by-page read operation by applying a read voltage from the higher of the two. The differences between the second embodiment and the first embodiment are described below.

[0266] [2-1] Operation Figure 72 is a timing chart showing an example of a first page readout in the memory system MS according to the second embodiment. Figure 72 shows the transitions of the input / output signal I / O, the ready busy signal RBn, the selected word line WLsel, and the control signal STB during the first page readout in the second embodiment. The first page readout of the second embodiment will be described below with reference to Figure 72.

[0267] When the memory controller 10 performs a first-page read, it sends, for example, the command "01h", the command "00h", the address "ADD", and the command "30h" to the memory device 20 in this order. When the memory device 20 receives the command "30h", the sequencer 204 transitions the memory device 20 from the ready state to the busy state based on the command and address stored in the register circuit 203.

[0268] The sequencer 204 then applies the read voltages R30, R26, R22, R18, R12, R8, and R4 to the selected word line WLsel in that order. The sequencer 204 also asserts the control signal STB while each of the read voltages R30, R26, R22, R18, R12, R8, and R4 is applied. Each sense amplifier unit SAU confirms (determines) the first bit data read from the memory cell transistor MT connected to the selected word line WLsel based on the control of the sequencer 204, and stores the determination result in the latch circuit XDL.

[0269] Other operations of the first page read in the second embodiment are the same as in the first embodiment. A read operation in which the higher read voltage is applied first is called, for example, a "reverse read". The memory device 20 according to the second embodiment can perform each of the second to fifth page reads by reverse read, similar to the first page read.

[0270] In Figure 72, the read voltage is applied to the selected word line WLsel immediately following the application of the ground voltage VSS to the selected word line WLsel, but this is not limited to this. For example, a predetermined voltage higher than the read voltage may be applied to the selected word line WLsel before the read voltage is applied to the selected word line WLsel. The predetermined voltage value may be equivalent to the voltage applied to the unselected word line WL during readout, or it may be a voltage higher than the highest read voltage R31.

[0271] [2-2] Effects of the second embodiment As described above, the memory device MD according to the second embodiment performs a read operation in which the read voltages are applied in the reverse order of the first embodiment. Thus, the data allocation of the first embodiment can be used regardless of the order in which the read voltages are applied. The reverse read described in the second embodiment may be applied to any of the data allocations of the first to seventeenth modified examples.

[0272] [3] Third embodiment The configuration of the information processing system 1 according to the third embodiment is the same as that of the information processing system 1 according to the first embodiment. In the third embodiment, the memory device 20 performs a sequential read operation (hereinafter referred to as sequential read) of 5 pages of data stored in the cell unit CU. The differences between the third embodiment and the first embodiment are described below.

[0273] [3-1] Operation Figure 73 is a timing chart showing an example of a sequential read in the memory system MS according to the third embodiment. Figure 73 shows the transitions of the input / output signal I / O, the ready-busy signal RBn, the selected word line WLsel, and the control signal STB during a sequential read in the third embodiment. The sequential read of the third embodiment will be described below with reference to Figure 73.

[0274] When the memory controller 10 performs a sequential read, it sends the following commands to the memory device 20 in this order: for example, command "xxh", command "00h", address "ADD", and command "30h". Command "xxh" is a command that specifies a sequential read.

[0275] When the memory device 20 receives the command "30h", the sequencer 204 transitions the memory device 20 from the ready state to the busy state based on the command and address stored in the register circuit 203. The sequencer 204 then applies read voltages R1 to R31 to the selection word line WLsel in that order. The sequencer 204 also asserts the control signal STB while each of the read voltages R1 to R31 is applied. Each sense amplifier unit SAU determines (judges) the first to fifth bits of data read from the memory cell transistor MT connected to the selection word line WLsel based on the control of the sequencer 204, and stores the judgment result in the latch circuits ADL, BDL, CDL, DDL, and EDL, respectively.

[0276] For example, when the readout using the readout voltage R24 is completed and the fourth bit data is determined, the sequencer 204 transitions the memory device 20 from a busy state to a ready state. Then, based on the fact that the memory device 20 has transitioned from a busy state to a ready state, the memory controller 10 commands the memory device 20 to output the data DAT (fourth page data PG4) stored in each latch circuit DDL of the sense amplifier module 209, and the fourth page data PG4 is output to the memory controller 10.

[0277] Furthermore, while the fourth page data PG4 is being output to the memory controller 10, the reading using the read voltages R25~R31 is completed, and the first, second, third, and fifth page data are determined. Once the memory controller 10 has finished receiving the fourth page data PG4, it instructs the memory device 20 to output the data in the order in which the data was determined (for example, PG2, PG5, PG1, and PG3). When the memory controller 10 has received data for five pages, it terminates the sequential read.

[0278] In this example, the case where data is output in the order in which it is confirmed is illustrated, but the system is not limited to this. When there are multiple pages with confirmed data, the order in which the pages are output from the memory device 20 to the memory controller 10 can be freely designed. In the third embodiment, the case where the lower read voltage is applied first in a sequential read is illustrated, but the system is not limited to this. The sequential read may be performed by a reverse read as in the second embodiment.

[0279] [3-2] Effects of the third embodiment As described above, the memory device 20 according to the third embodiment can read five pages of data stored in the cell unit CU all at once. The data allocation of the first embodiment can also be applied when sequential reading is performed. Note that sequential reading may be applied to any of the data allocations of the first to seventeenth modifications. Furthermore, the memory system MS according to the third embodiment can improve latency in sequential reading by outputting data from the memory device 20 to the memory controller 10 sequentially from the pages for which data has been confirmed.

[0280] [3-3] Modified form of the third embodiment Furthermore, the memory device 20 can speed up the data output timing in sequential reads by optimizing page allocation or utilizing reverse reads. For example, in the data allocation of the embodiment shown in Figure 8, the first and second pages are swapped, and a sequential read using reverse reads (i.e., a read operation in which the read voltages are applied sequentially starting from the higher read voltage) can be performed. In this case, the memory device 20 can output the data of the first page after reading using read voltage R6, and can output the data of the second page after reading using read voltage R3. This can improve the latency of the memory system MS.

[0281] [4] Fourth Embodiment The fourth embodiment relates to the circuit arrangement of the memory device 20 described in the first to third embodiments. Below, the memory device 20a according to the fourth embodiment will be described, with reference to comparative examples. In the following description, the X, Y, and Z directions are directions that intersect each other. For example, the Z direction is perpendicular to the XY plane formed by the X and Y directions. The XY plane corresponds, for example, to a plane parallel to the surface of the semiconductor substrate for forming the memory device 20a.

[0282] [4-1] Structure of the comparative example Figure 74 is a plan view showing an example of the circuit arrangement of a memory device 20b according to a comparative example. The memory device 20b has a structure in which the memory cell array 207 and the sense amplifier module 209 are adjacent in the Z direction. Figure 74(A) shows the circuit arrangement in the layer containing the memory cell array 207 of the memory device 20b. Figure 74(B) shows the circuit arrangement in the layer containing the sense amplifier module 209 of the memory device 20b.

[0283] The memory device 20b includes, for example, four planes LUN1 to LUN4, a wiring section 210, and peripheral circuits 211. Planes LUN1 and LUN2 are adjacent in the Y direction. Planes LUN3 and LUN4 are adjacent in the Y direction. Planes LUN1 and LUN3 are adjacent in the X direction. Planes LUN2 and LUN4 are adjacent in the X direction. Each plane LUN shares a wiring section 210 and peripheral circuits 211. The wiring section 210 is provided in the layer containing the memory cell array 207. The wiring section 210 is arranged overlapping with the peripheral circuits 211 in the Z direction. The wiring section 210 is used to connect the peripheral circuits 211 to a plurality of pads provided on the memory device 20b (i.e., pads used for connecting input / output circuits 201, etc., to the memory controller 10). The peripheral circuits 211 are provided in the layer containing the sense amplifier module 209. The peripheral circuitry 211 may include input / output circuits 201, logic controllers 202, register circuits 203, sequencers 204, etc. Each of the wiring section 210 and the peripheral circuitry 211 is adjacent to a set of planes LUN1 to LUN4 in the Y direction.

[0284] Each plane LUN includes a memory cell array 207, a draw area HR, a row decoder module 208, and a sense amplifier module 209. Specifically, plane LUN1 includes a memory cell array 207A, draw areas HR_A1 and HR_A2, row decoder modules 208_A1 and 208_A2, and a sense amplifier module 209A. Plane LUN2 includes a memory cell array 207B, draw areas HR_B1 and HR_B2, row decoder modules 208_B1 and 208_B2, and a sense amplifier module 209B. Plane LUN3 includes a memory cell array 207C, draw areas HR_C1 and HR_C2, row decoder modules 208_C1 and 208_C2, and a sense amplifier module 209C. The plane LUN4 includes a memory cell array 207D, extraction areas HR_D1 and HR_D2, row decoder modules 208_D1 and 208_D2, and a sense amplifier module 209D.

[0285] Here, we will focus on plane LUN1 and describe the specific circuit arrangement in plane LUN1. As shown in Figure 74(A), the memory cell array 207A is sandwiched in the X direction between extraction regions HR_A1 and HR_A2. As shown in Figure 74(B), the sense amplifier module 209A is sandwiched in the X direction between the row decoder modules 208_A1 and 208_A2. As shown in Figures 74(A) and (B), the memory cell array 207A is provided overlapping with the sense amplifier module 209A in the Z direction. The extraction regions HR_A1 and HR_A2 are provided overlapping with the row decoder modules 208_A1 and 208_A2 in the Z direction, respectively. The memory cell array 207A is connected to row decoder module 208_A1 via multiple wires provided in extraction region HR_A1, and to row decoder module 208_A2 via multiple wires provided in extraction region HR_A2. The pair of raw decoder modules 208_A1 and 208_A2 constitute the raw decoder module 208, as described in Figure 5.

[0286] The Y-direction widths of the extraction regions HR_A1 and HR_A2 are approximately equal to the Y-direction width of the memory cell array 207A. The Y-direction widths of the row decoder modules 208_A1 and 208_A2 are approximately equal to the Y-direction widths of the extraction regions HR_A1 and HR_A2. When 5-bit / cell coding, as described in the first embodiment, is applied to the memory cell array 207A, for example, the Y-direction width of the sense amplifier module 209A becomes wider than the Y-direction width of the memory cell array 207A. This is because the sense amplifier module 209 requires many latch circuits when handling ultra-high-level data such as 5-bit / cell. Thus, when the Y-direction widths differ between the memory cell array 207A and the sense amplifier module 209A, surplus regions SP can be formed in the layer where the memory cell array 207A is located and in the layer where the sense amplifier module 209A is located. The configurations of planes LUN2 to LUN4 are the same as those of plane LUN1.

[0287] In the comparative example memory device 20b described above, the area of ​​the sense amplifier module 209 becomes larger than the area of ​​the memory cell array 207, which can increase the chip area of ​​the memory device 20b to match the area of ​​the sense amplifier module 209. In particular, in memory cell arrays 207 with 5 bits / cell or 4 bits / cell as described in the first embodiment, the number of latch circuits in the sense amplifier module 209 increases, which can increase the circuit area of ​​the sense amplifier module 209.

[0288] [4-2] Configuration of the fourth embodiment In contrast, the memory device 20a according to the fourth embodiment has a circuit configuration that utilizes at least two types of memory cell arrays 207 with different numbers of bits stored by the memory cell transistors MT. For example, the memory device 20a according to the fourth embodiment utilizes a memory cell array 207 with k values ​​(e.g., 4 values ​​(2 bits / cell), where "k" is an integer greater than or equal to 1) and an l value (e.g., 32 values ​​(5 bits / cell), where "l" is an integer greater than "k"). Hereinafter, a "memory cell array 207 composed of memory cell transistors MT capable of storing k values" will be referred to as a "multi-level or less memory cell array 207," and a "memory cell array 207 composed of memory cell transistors MT capable of storing l values" will be referred to as a "super-multi-level memory cell array 207."

[0289] [4-2-1]Circuit layout Figure 75 is a plan view showing an example of the circuit arrangement of the memory device 20a according to the fourth embodiment. Figure 75(A) shows the circuit arrangement in the layer containing the memory cell array 207 of the memory device 20a. Figure 75(B) shows the circuit arrangement in the layer containing the sense amplifier module 209 of the memory device 20a. The circuit arrangement of the memory device 20a according to the fourth embodiment has a configuration in which the surplus region SP is omitted compared to the circuit arrangement of the memory device 20b according to the comparative example.

[0290] Specifically, in memory device 20a, each of the memory cell arrays 207A and 207C is a very high-level memory cell array 207. In memory device 20a, each of the memory cell arrays 207B and 207D is a low-level memory cell array 207. In other words, adjacent memory cell arrays 207A and 207B in the Y direction are a combination of a very high-level memory cell array 207 and a low-level memory cell array 207. Similarly, adjacent memory cell arrays 207C and 207D in the Y direction are a combination of a very high-level memory cell array 207 and a low-level memory cell array 207. The following explanation will focus on the circuit arrangement of the pair of planes LUN1 and LUN2.

[0291] The Y-direction width of the sense amplifier module 209A, which is arranged overlapping the ultra-high-level memory cell array 207A in the Z-direction, is wider than that of the memory cell array 207A. On the other hand, the Y-direction width of the sense amplifier module 209B, which is arranged overlapping the multi-level or lower-level memory cell array 207B in the Z-direction, is narrower than that of the memory cell array 207B. This is because the number of latch circuits required for the operation of the multi-level or lower-level memory cell array 207 is less than the number of latch circuits required for the operation of the ultra-high-level memory cell array 207. In the memory device 20a, the Y-direction width of the ultra-high-level memory cell array 207A is designed to be narrower than the Y-direction width of the multi-level or lower-level memory cell array 207B.

[0292] As a result, the combined width in the Y direction of the memory cell arrays 207A and 207B and the combined width in the Y direction of the sense amplifier modules 209A and 209B can be designed to be approximately the same. That is, the set of memory cell arrays 207A and 207B and the set of sense amplifier modules 209A and 209B can be provided in approximately the same area and arranged overlapping in the Z direction. Similarly, the set of extraction regions HR_A1 and HR_B1 and the set of raw decoder modules 208_A1 and 208_B1 are provided in approximately the same area and arranged overlapping in the Z direction. The set of extraction regions HR_A2 and HR_B2 and the set of raw decoder modules 208_A2 and 208_B2 are provided in approximately the same area and arranged overlapping in the Z direction. Thus, in the fourth embodiment, the surplus region SP can be omitted. The circuit arrangement of the set of planes LUN3 and LUN4 is the same as the circuit arrangement of the set of planes LUN1 and LUN2.

[0293] Furthermore, some peripheral circuits may be placed in the area of ​​the sense amplifier module 209. That is, some peripheral circuits may be placed in the area of ​​the sense amplifier module 209 in Figures 74 and 75. Therefore, the relationship between the areas of the associated memory cell array 207 and the sense amplifier module 209 is not limited to the example shown in Figure 75.

[0294] Figure 76 is a plan view showing another example of the circuit arrangement of the memory device 20a according to the fourth embodiment. Figure 76(A) shows the circuit arrangement in the layer containing the memory cell array 207 of the memory device 20a. Figure 76(B) shows the circuit arrangement in the layer containing the sense amplifier module 209 of the memory device 20a. The circuit arrangement of the memory device 20a shown in Figure 76 differs from the circuit arrangement of the memory device 20a shown in Figure 75 in that the area (size) of the sense amplifier module 209 is different.

[0295] Specifically, in the example shown in Figure 76, the area of ​​the sense amplifier module 209 associated with the multi-level memory cell array 207 is larger than the area of ​​the multi-level memory cell array 207. Also, the area of ​​the sense amplifier module 209 associated with the ultra-multi-level memory cell array 207 is smaller than the area of ​​the ultra-multi-level memory cell array 207. Even in such cases, the combined width in the Y direction of the memory cell arrays 207A and 207B and the combined width in the Y direction of the sense amplifier modules 209A and 209B can be designed to be approximately the same. That is, in the example shown in Figure 76, the set of memory cell arrays 207A and 207B and the set of sense amplifier modules 209A and 209B can be provided with approximately the same area and arranged overlapping in the Z direction.

[0296] [4-2-2] Example configuration of sense amplifier module 209 The following describes an example configuration of a combination of the circuit configuration of one sense amplifier unit SAU included in a sense amplifier module 209 connected to a very high-level memory cell array 207 and the circuit configuration of one sense amplifier unit SAU included in a sense amplifier module 209 connected to a high-level or lower-level memory cell array 207, according to the fourth embodiment.

[0297] (Example of configuration 1) Figure 77 is a schematic diagram showing a first configuration example of the sense amplifier module 209 in the memory device 20a according to the fourth embodiment. As shown in Figure 77, in the first configuration example in the fourth embodiment, the sense amplifier unit SAU of the sense amplifier module 209A includes a sense amplifier section SA, latch circuits SDL, ADL, BDL, CDL and XDL configured to transmit and receive data via the bus LBUS1. In the first configuration example in the fourth embodiment, the sense amplifier unit SAU of the sense amplifier module 209B includes a sense amplifier section SA, latch circuits SDL and XDL configured to transmit and receive data via the bus LBUS2. In this example, the number of latch circuits connected to buses LBUS1 and LBUS2, respectively, can be appropriately changed according to the number of bits stored by the memory cell transistor MT of the associated memory cell array 207.

[0298] (Second example configuration) Figure 78 is a schematic diagram showing a second configuration example of the sense amplifier module 209 in the memory device 20a according to the fourth embodiment. As shown in Figure 78, the second configuration example in the fourth embodiment has a configuration in which the latch circuit SDL of the sense amplifier unit SAU of the sense amplifier module 209B is omitted compared to the first configuration example in the fourth embodiment. Depending on the number of bits stored by the memory cell transistor MT in the multi-level or lower memory cell array 207B (for example, if it is 1 bit), latch circuits other than the latch circuit XDL may be omitted in the sense amplifier unit SAU of the sense amplifier module 209B, as in the second configuration example in the fourth embodiment.

[0299] [4-3] Effects of the fourth embodiment As described above, the memory device 20a according to the fourth embodiment combines a plane LUN equipped with a very high-level memory cell array 207 and a plane LUN equipped with a low-level memory cell array 207. This allows the memory device 20a according to the fourth embodiment to suppress the formation of excess region SP based on the difference in area between the memory cell array 207 and the sense amplifier module 209 in a single plane LUN. As a result, the memory device 20a according to the fourth embodiment can have a smaller chip area than the comparative example. In other words, the memory device 20a according to the fourth embodiment can reduce the manufacturing cost of the memory device 20a.

[0300] Furthermore, in the memory device 20a according to the fourth embodiment, when memory cell arrays 207A and 207C are used as a very high-level memory cell array 207, and memory cell arrays 207B and 207D are used as a low-level memory cell array 207, the four planes LUN1 to LUN4 can be operated in parallel (i.e., 4-plane operation). Also, in the memory device 20a according to the fourth embodiment, when all of memory cell arrays 207A, 207B, 207C, and 207D are used as low-level memory cell arrays 207, the four planes LUN1 to LUN4 can be operated in parallel. On the other hand, in the memory device 20a according to the fourth embodiment, when memory cell arrays 207A and 207C are used as a very high-level memory cell array 207, memory cell arrays 207B and 207D cannot be used as a very high-level memory cell array 207.

[0301] [5] Fifth embodiment The memory device 20c according to the fifth embodiment has a configuration in which a latch circuit is shared by a plurality of memory cell arrays 207, with respect to the circuit arrangement of the memory system MS described in the first to third embodiments. The memory device 20c according to the fifth embodiment will be described below.

[0302] [5-1] Configuration of the fifth embodiment The memory device 20c according to the fifth embodiment utilizes a multi-value memory cell array 207 by sharing a latch circuit among multiple plane LUNs, and has a configuration that suppresses the area of ​​the latch circuit.

[0303] [5-1-1] Circuit layout Figure 79 is a plan view showing an example of the circuit arrangement of a memory device 20c according to the fifth embodiment. The memory device 20c has a structure in which a memory cell array 207 and a sense amplifier module 209 are adjacent to each other in the Z direction. Figure 79(A) shows the circuit arrangement in the layer containing the memory cell array 207 of the memory device 20c. Figure 79(B) shows the circuit arrangement in the layer containing the sense amplifier module 209 of the memory device 20c.

[0304] The memory device 20c includes, for example, four plane LUNs 1 to 4, a wiring section 210, and peripheral circuits 211. The arrangement of plane LUNs 1 to 4 in the fifth embodiment is the same as the arrangement of plane LUNs 1 to 4 in the comparative example described in the fourth embodiment. Each plane LUN includes a memory cell array 207, a draw area HR, a row decoder module 208, and a sense amplifier set SAS. The sense amplifier set SAS includes at least a sense amplifier section SA. For example, two adjacent plane LUNs in the Y direction share a latch set LS. The latch set LS includes, for example, at least one latch circuit shared by a plurality of sense amplifier sets SAS for each row address. The sense amplifier set SAS and latch set LS can be used in the same way as the sense amplifier module 209 described in the first embodiment.

[0305] Specifically, plane LUN1 includes memory cell array 207A, draw-out areas HR_A1 and HR_A2, row decoder modules 208_A1 and 208_A2, and sense amplifier set SAS1. Plane LUN2 includes memory cell array 207B, draw-out areas HR_B1 and HR_B2, row decoder modules 208_B1 and 208_B2, and sense amplifier set SAS2. Plane LUN3 includes memory cell array 207C, draw-out areas HR_C1 and HR_C2, row decoder modules 208_C1 and 208_C2, and sense amplifier set SAS3. Plane LUN4 includes memory cell array 207D, draw-out areas HR_D1 and HR_D2, row decoder modules 208_D1 and 208_D2, and sense amplifier set SAS4. Sense amplifier sets SAS1 and SAS2 share latch set LS1. Sense amplifier sets SAS3 and SAS4 share latch set LS1.

[0306] Here, we will describe the specific circuit arrangement in plane LUN1. As shown in Figure 79(A), the memory cell array 207A is sandwiched in the X direction between extraction regions HR_A1 and HR_A2. As shown in Figure 79(B), the sense amplifier module 209A is sandwiched in the X direction between the row decoder modules 208_A1 and 208_A2. As shown in Figures 79(A) and (B), the memory cell array 207A is provided overlapping the sense amplifier set SAS1 in the Z direction. The extraction regions HR_A1 and HR_A2 are provided overlapping the row decoder modules 208_A1 and 208_A2 in the Z direction, respectively. The Y-direction width of each extraction region HR_A1 and HR_A2 is approximately equal to the Y-direction width of the memory cell array 207A. The Y-direction width of each row decoder module 208_A1 and 208_A2 is approximately equal to the Y-direction width of each extraction region HR_A1 and HR_A2. The Y-direction widths of the raw decoder modules 208_A1 and 208_A2 are wider than the Y-direction width of the sense amplifier set SAS1.

[0307] Plane LUN2 has a circuit layout similar to that of plane LUN1, except that the sense amplifier set SAS2 is located in a separate area from plane LUN1. Sense amplifier sets SAS1 and SAS2 sandwich the latch set LS1 in the Y direction. As a result, the combined Y-width of memory cell arrays 207A and 207B and the combined Y-width of sense amplifier sets SAS1 and SAS2 and latch set LS1 can be designed to be approximately the same. That is, the set of memory cell arrays 207A and 207B and the set of sense amplifier sets SAS1 and SAS2 and latch set LS1 can be provided in approximately the same area and overlap in the Z direction. The circuit layout of the set of planes LUN3 and LUN4 is the same as that of the set of planes LUN1 and LUN2. Note that some peripheral circuits may be located in the area of ​​sense amplifier set SAS in Figure 79.

[0308] [5-1-2] Example configuration of sense amplifier set SAS and latch set LS The following describes the first to fourth configuration examples of the circuit configurations of the sense amplifier set SAS and latch set LS1 in the fifth embodiment. In the following description, the circuit configurations included in the sense amplifier sets SAS1 and SAS2 and latch set LS1 corresponding to the pair of planes LUN1 and LU2 will be used as examples.

[0309] (Example of configuration 1) Figure 80 is a schematic diagram showing a first configuration example of the sense amplifier set SAS and latch set LS in the memory device 20c according to the fifth embodiment. As shown in Figure 80, in the first configuration example in the fifth embodiment, sense amplifier set SAS1 includes a sense amplifier section SA and a latch circuit XDL configured to transmit and receive data via bus LBUS1, and sense amplifier set SAS2 includes a sense amplifier section SA and a latch circuit XDL configured to transmit and receive data via bus LBUS2. In the first configuration example in the fifth embodiment, latch set LS1 includes latch circuits SDL, ADL, BDL, and CDL configured to transmit and receive data via bus SBUS, and switches SW1 and SW2. Switches SW1 and SW2 are, for example, MOS transistors. Switch SW1 is connected between LBUS1 and SBUS. Switch SW2 is connected between LBUS2 and SBUS. Control signals CS1 and CS2 are input to the respective gates of switches SW1 and SW2. Switch SW1 operates based on control signal CS1. Switch SW2 operates based on control signal CS2. The control signals CS1 and CS2 are generated, for example, by the sequencer 204.

[0310] In the first configuration example of the fifth embodiment, the memory device 20c uses a sense amplifier set SAS1 and a latch set LS1 when handling ultra-multi-level values. Specifically, when ultra-multi-level values ​​are assigned to memory cell array 207A and multi-level values ​​are assigned to memory cell array 207B, the sequencer 204 electrically connects LBUS1 and SBUS by controlling switch SW1 to the ON state and performs ultra-multi-level operation (for example, the operation described in the first to third embodiments) on the memory cell array 207A. On the other hand, when the memory device 20c handles multi-level values, it uses only, for example, the sense amplifier set SAS2. Specifically, the sequencer 204 electrically disconnects LBUS2 and SBUS by controlling switch SW2 to the OFF state and performs multi-level operation.

[0311] (Second example configuration) Figure 81 is a schematic diagram showing a second configuration example of the sense amplifier set SAS and latch set LS in the memory device 20c according to the fifth embodiment. As shown in Figure 81, the second configuration example in the fifth embodiment has a configuration in which the latch circuit SDL of latch set LS1 is omitted compared to the first configuration example in the fifth embodiment, and one latch circuit SDL is connected to each of the buses LBUS1 and LBUS2. In the second configuration example in the fifth embodiment, for example, when coding is used in which read and write operations can be performed with one latch circuit such as 1 bit / cell, read and write operations can be performed with only the sense amplifier set SAS. Specifically, in the second configuration example of the fifth embodiment, the memory device 20c can perform read and write operations of planes LUN1 and LUN2 in parallel, for example, using a set of sense amplifier set SAS1 and latch set LS1 used for ultra-multi-level systems and a sense amplifier set SAS2 used for multi-level systems.

[0312] (Third example configuration) Figure 82 is a schematic diagram showing a third configuration example of the sense amplifier set SAS and latch set LS in the memory device 20c according to the fifth embodiment. As shown in Figure 82, the third configuration example in the fifth embodiment has a configuration in which the latch circuits XDL of latch sets LS1 and LS2 are omitted, and one latch circuit XDL is connected to the bus SBUS, compared to the first configuration example in the fifth embodiment. In this way, the sense amplifier set SAS may include only the sense amplifier section SA, and the latch circuits used for read and write operations may be grouped in latch set LS1. In this case, the memory device 20c can selectively perform operations targeting plane LUN1 and operations targeting plane LUN2 in the combined planes LUN1 and LUN2.

[0313] (Fourth example configuration) Figure 83 is a schematic diagram showing a fourth configuration example of the sense amplifier set SAS and latch set LS in the memory device 20c according to the fifth embodiment. As shown in Figure 83, the fourth configuration example in the fifth embodiment has a configuration in which the latch circuit SDL of latch set LS1 is omitted compared to the third configuration example in the fifth embodiment, and one latch circuit SDL is connected to each of the buses LBUS1 and LBUS2. In the fourth configuration example in the fifth embodiment, by including the latch circuit SDL in the sense amplifier set SAS, it is possible to perform, for example, 1-bit / cell operation and ultra-multi-level or multi-level operation in parallel.

[0314] [5-2] Effects of the fifth embodiment In the fifth embodiment, the memory device 20c shares a latch set LS among multiple memory cell arrays 207 (sense amplifier set SAS). Two plane LUNs sharing the latch set LS operate independently when handling ultra-high-level data. For example, in two plane LUNs sharing the latch set LS, while a write operation is being performed on one plane LUN, the other plane LUN becomes unavailable and enters a standby state. Furthermore, two plane LUNs sharing the latch set LS can operate in parallel when handling multi-level data (or 1 bit / cell).

[0315] The memory device 20c may use one of two plane LUNs sharing a latch set LS in a very multi-level manner and the other in a multi-level manner. By providing a memory cell array 207 used in a multi-level manner, the area required for arranging the latch circuit can be reduced. Furthermore, in the fifth embodiment, if a memory cell array 207 in which the memory cell transistor MT stores only 1 bit of data (a 1-bit / cell memory cell array 207) is provided, and for example, a sense amplifier set SAS and a latch set LS are provided as in the first configuration example, the 1-bit / cell memory cell array 207 can perform read and write operations using the sense amplifier set SAS without using the latch set LS.

[0316] As described above, the memory device 20c according to the fifth embodiment can reduce the area of ​​the circuit that functions as the sense amplifier module 209 by sharing the latch set LS. As a result, the memory device 20a according to the fifth embodiment can have a smaller chip area, and the manufacturing cost of the memory device 20c can be reduced.

[0317] Furthermore, in the memory device 20c according to the fifth embodiment, all of the memory cell arrays 207A, 207B, 207C, and 207D can be used as a multi-level memory cell array 207. When each of the two plane LUNs sharing a latch set LS has a multi-level memory cell array 207, the memory device 20c performs write operations on one plane LUN at a time. Also, in the memory device 20c according to the fifth embodiment, when memory cell arrays 207A and 207C are used as a multi-level memory cell array 207 and memory cell arrays 207B and 207D are used as multi-level or lower memory cell arrays 207, the four plane LUNs 1 to 4 can be operated in parallel. Also, in the memory device 20a according to the fifth embodiment, when all of the memory cell arrays 207A, 207B, 207C, and 207D are used as multi-level or lower memory cell arrays 207, the four plane LUNs 1 to 4 can be operated in parallel.

[0318] [6] Others In the data allocation described in the above embodiment, the data allocation for each page may be swapped between pages. The commands used in the above embodiment are merely examples. For example, each of the commands "01h" to "05h" and "xxh" can be replaced with any command. Commands that specify the pages to be read, such as "01h" to "05h", may be omitted by including the page information in the address "ADD". The address "ADD" may be transmitted in multiple cycles. In the read operation of the first embodiment, the sequencer 204 may transition the memory device 20 from a busy state to a ready state based on the confirmation of the data. In this case, the memory controller 10 instructs the memory device 20 to transfer the data determination result to the latch circuit XDL, and then instructs the memory device 20 to output the confirmed page data.

[0319] In the fourth and fifth embodiments, multiple plane LUNs are operated in parallel, but this is not limited to cases where the start times of each operation are the same. The start times of each operation may be different, as long as the operations of multiple plane LUNs overlap for a certain period of time. For example, when four plane LUNs LUN1 to LUN4 are operated in parallel, the operations may be executed in the following order: start of LUN1 operation, start of LUN2 operation, start of LUN3 operation, start of LUN4 operation, end of LUN1 operation, end of LUN2 operation, end of LUN3 operation, end of LUN4 operation. In this example, the start of LUN4 operation and the end of LUN1 operation may be executed in the reverse order.

[0320] The fourth and fifth embodiments illustrate, but are not limited to, a case where the memory device 20 has four plane LUNs. Each of the fourth and fifth embodiments may be applied when the memory device 20 has at least a number of plane LUNs. In the fourth and fifth embodiments, when a multi-level or less memory cell array 207 and a very multi-level memory cell array 207 are combined, the multi-level or less memory cell array 207 is used, for example, as a buffer area for speeding up operation. That is, the fourth and fifth embodiments can speed up the operation of the memory device 20 by using a combination of a multi-level or less memory cell array 207 and a very multi-level memory cell array 207.

[0321] During the read operation, the voltage applied to the selected word line WLsel is, for example, similar to the voltage of the signal line CG that the driver circuit 206 supplies to the raw decoder module 208. The height of the voltage applied to various wires and the duration for which the voltage is applied can be roughly determined by examining the voltage of the corresponding signal line CG. When estimating the voltages of the selected gate line and word line, etc., from the voltages of each signal line connected to the driver circuit 206, the voltage drop due to the transistor TR included in the raw decoder RD may be taken into consideration. In this case, the voltages of the selected gate line and word line will be lower than the voltage applied to the corresponding signal line by the amount of the voltage drop across the transistor TR.

[0322] In this specification, “connected” means electrically connected, and does not exclude, for example, the presence of another element in between. “On state” means that a voltage equal to or greater than the threshold voltage of the corresponding transistor (a “H” level voltage) is applied to the gate of the corresponding transistor. “Off state” means that a voltage equal to or less than the threshold voltage of the corresponding transistor (a “L” level voltage) is applied to the gate of the corresponding transistor. A small current, such as leakage current, may flow through a transistor in the off state. “Readout voltage” may also be called “readout level”. “Lowest readout voltage” means the lowest readout voltage in a specified group. “Highest readout voltage” means the highest readout voltage in a specified group.

[0323] Furthermore, some or all of the above embodiments may also be described as follows, but are not limited to these descriptions.

[0324] [Note 1] A group of first memory cell arrays having a first memory cell array having a threshold value of k (where k is an integer greater than or equal to 1), and having a first memory cell array of a units (where a is an integer greater than or equal to 1), A second memory cell array group having a memory cell that stores data according to a threshold value of l (where l is an integer greater than k), and having b second memory cell arrays (where b is an integer greater than or equal to 1), Sequencer and, Equipped with, The above sequencer simultaneously writes data with a value of k or less to c (where c is less than or equal to a) of the first memory cell array and data with a value of l or less to d (where d is less than or equal to b) of the second memory cell array. Semiconductor memory device.

[0325] [Note 2] A first sense amplifier unit connected to a memory cell of the first memory cell array described above, A second sense amplifier unit connected to the memory cells of the second memory cell array described above, Furthermore, The number of latch circuits included in the second sense amplifier unit is greater than the number of latch circuits included in the first sense amplifier unit. Semiconductor memory device as described in Appendix 2.

[0326] [Note 3] A first memory cell array group having a first memory cell array of a elements (where a is an integer greater than or equal to 1), which has memory cells that can be selected to store data according to a threshold value of k (where k is an integer greater than k) or l (where l is an integer greater than k), A group of two memory cell arrays having a memory cell that can be selected to store data according to a threshold value of k (where k is an integer greater than or equal to 1) or l (where l is an integer greater than k), and having a second memory cell array of b elements (where b is an integer greater than or equal to 1), Sequencer and, Equipped with, The above sequencer simultaneously writes data with a value of k or less to c (where c is less than or equal to a) of the first memory cell array and data with a value of l or less to d (where d is less than or equal to b) of the second memory cell array. Semiconductor memory device.

[0327] [Note 4] A first sense amplifier set connected to the memory cells of the first memory cell array described above, A second sense amplifier set connected to the memory cells of the second memory cell array described above, A latch circuit connected to the first sense amplifier set and the second sense amplifier set described above, Sequencer and, Furthermore, The above sequencer drives both the first sense amplifier set and the latch circuit when writing data less than or equal to l value to the memory cells of the first memory cell array group, and drives both the second sense amplifier set and the latch circuit when writing data less than or equal to l value to the memory cells of the second memory cell array group. Semiconductor memory device as described in Appendix 3.

[0328] [Note 5] The writing of data to the first memory cell array and the writing of data to the second memory cell array are performed at different start times. A semiconductor memory device as described in Appendix 1 or 3.

[0329] [Note 6] The writing of data to the first memory cell array and the writing of data to the second memory cell array are performed with approximately the same start time. A semiconductor memory device as described in Appendix 1 or 3.

[0330] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0331] 1…Information processing system, 10…Memory controller, 11…Host interface, 12…Memory interface, 13…CPU, 14…ECC circuit, 15…ROM, 16…RAM, 17…Buffer memory, 20…Memory device, 101…Input / output circuit, 201…Input / output circuit, 202…Logic controller, 203…Register circuit, 204…Sequencer, 205…Ready-busy controller, 206…Driver circuit, 207…Memory cell array, 208…Raw decoder module, 209…Sense amplifier module, BLK…Block, SU…String unit, NS…NAND string, RD…Raw decoder, SAU…Sense amplifier unit, BL…Bit line, WL…Word line, SGD, SGS…Selection gate line, SL…Source line, MT…Memory cell transistor, ST1, ST2…Selection transistor, S0~S31…State, D0~D31…Data set, R1~R31…Read voltage, VREAD…Read path voltage

Claims

1. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the seventh reading voltage, the fifteenth reading voltage, the eighteenth reading voltage, the twenty-second reading voltage, the twenty-fifth reading voltage, and the twenty-nine reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the fourth reading voltage, the eighth reading voltage, the thirteenth reading voltage, the twenty-first reading voltage, the twenty-seventh reading voltage, and the thirty-first reading voltage to the word line, respectively. In the reading operation on page 3, six readings are performed by applying the third reading voltage, the ninth reading voltage, the twelfth reading voltage, the sixteenth reading voltage, the twentieth reading voltage, and the twenty-sixth reading voltage to the word line, respectively. In the read operation on page 4, seven read operations are performed by applying the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the nineteenth read voltage, the twenty-third read voltage, and the twenty-eighth read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the eleventh reading voltage, the seventeenth reading voltage, the twenty-fourth reading voltage, and the thirtyth reading voltage to the word line, respectively. Memory device.

2. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, seven readings are performed by applying the fourth reading voltage, the ninth reading voltage, the thirteenth reading voltage, the eighteenth reading voltage, the twenty-second reading voltage, the twenty-sixth reading voltage, and the thirty-third reading voltage to the word line, respectively. In the reading operation of the second page, six readings are performed by applying the sixth reading voltage, the twelfth reading voltage, the sixteenth reading voltage, the twenty reading voltage, the twenty-third reading voltage, and the twenty-nine reading voltage to the word line, respectively. In the read operation on page 3, six read operations are performed by applying the third read voltage, the seventh read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, and the twenty-fifth read voltage to the word line, respectively. In the read operation on page 4, six read operations are performed by applying the second read voltage, the eighth read voltage, the fifteenth read voltage, the 21st read voltage, the 27th read voltage, and the 31st read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the eleventh reading voltage, the nineteenth reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. Memory device.

3. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the eighth reading voltage, the fifteenth reading voltage, the eighteenth reading voltage, the twenty-second reading voltage, the twenty-fifth reading voltage, and the thirty-third reading voltage to the word line, respectively. In the reading operation of the second page, six readings are performed by applying the fourth reading voltage, the ninth reading voltage, the twelfth reading voltage, the sixteenth reading voltage, the nineteenth reading voltage, and the twenty-sixth reading voltage to the word line, respectively. In the read operation on page 3, six read operations are performed by applying the third read voltage, the seventh read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-seventh read voltage, and the thirty-first read voltage to the word line, respectively. In the read operation on page 4, seven read operations are performed, each applying the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the twentieth read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage to the word line. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the eleventh reading voltage, the seventeenth reading voltage, the twenty-third reading voltage, and the twenty-nine reading voltage to the word line, respectively. Memory device.

4. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the eighth reading voltage, the fourteenth reading voltage, the eighteenth reading voltage, the eighteenth reading voltage, the twenty-second reading voltage, the twenty-fifth reading voltage, and the thirty-first reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the 5th reading voltage, the 9th reading voltage, the 12th reading voltage, the 16th reading voltage, the 19th reading voltage, and the 27th reading voltage to the word line, respectively. In the read operation on page 3, six read operations are performed by applying the third read voltage, the seventh read voltage, the thirteenth read voltage, the twenty-first read voltage, the twenty-sixth read voltage, and the thirty-first read voltage to the word line, respectively. In the read operation on page 4, seven read operations are performed by applying the second read voltage, the sixth read voltage, the eleventh read voltage, the fifteenth read voltage, the twentieth read voltage, the twenty-fourth read voltage, and the twenty-eighth read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fourth reading voltage, the tenth reading voltage, the seventeenth reading voltage, the twenty-third reading voltage, and the twenty-nine reading voltage to the word line, respectively. Memory device.

5. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, seven readings are performed by applying the fourth reading voltage, the eighth reading voltage, the twelfth reading voltage, the seventeenth reading voltage, the 21st reading voltage, the 26th reading voltage, and the 30th reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the 5th reading voltage, the 13th reading voltage, the 16th reading voltage, the 20th reading voltage, the 23rd reading voltage, and the 27th reading voltage to the word line, respectively. In the read operation on page 3, six read operations are performed by applying the third read voltage, the ninth read voltage, the fifteenth read voltage, the twenty-second read voltage, the twenty-eighth read voltage, and the thirty-first read voltage to the word line, respectively. In the read operation on page 4, six read operations are performed by applying the second read voltage, the sixth read voltage, the eleventh read voltage, the nineteenth read voltage, the twenty-fifth read voltage, and the twenty-nineth read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the seventh reading voltage, the tenth reading voltage, the fourteenth reading voltage, the eighteenth reading voltage, and the twenty-fourth reading voltage to the word line, respectively. Memory device.

6. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the seventh reading voltage, the fifteenth reading voltage, the eighteenth reading voltage, the twenty-second reading voltage, the twenty-fifth reading voltage, and the twenty-nine reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the fourth reading voltage, the eighth reading voltage, the thirteenth reading voltage, the twenty-first reading voltage, the twenty-seventh reading voltage, and the thirty-first reading voltage to the word line, respectively. In the reading operation on page 3, six readings are performed by applying the third reading voltage, the ninth reading voltage, the twelfth reading voltage, the sixteenth reading voltage, the twentieth reading voltage, and the twenty-sixth reading voltage to the word line, respectively. In the read operation on page 4, seven read operations are performed by applying the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, the twenty-third read voltage, and the thirtyth read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the eleventh reading voltage, the nineteenth reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. Memory device.

7. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the sixth reading voltage, the twelfth reading voltage, the sixteenth reading voltage, the twentieth reading voltage, the twenty-third reading voltage, and the twenty-nine reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the fourth reading voltage, the eighth reading voltage, the thirteenth reading voltage, the twenty-first reading voltage, the twenty-seventh reading voltage, and the thirty-first reading voltage to the word line, respectively. In the read operation on page 3, six read operations are performed by applying the third read voltage, the seventh read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, and the twenty-fifth read voltage to the word line, respectively. In the read operation on page 4, seven read operations are performed by applying the second read voltage, the ninth read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-sixth read voltage, and the thirty-third read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the eleventh reading voltage, the nineteenth reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. Memory device.

8. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the sixth reading voltage, the twelfth reading voltage, the sixteenth reading voltage, the twentieth reading voltage, the twenty-third reading voltage, and the twenty-nine reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the fourth reading voltage, the eighth reading voltage, the eleventh reading voltage, the seventeenth reading voltage, the twenty-fifth reading voltage, and the thirty-first reading voltage to the word line, respectively. In the read operation on page 3, six read operations are performed by applying the third read voltage, the seventh read voltage, the tenth read voltage, the fourteenth read voltage, the nineteenth read voltage, and the twenty-seventh read voltage to the word line, respectively. In the read operation on page 4, seven read operations are performed by applying the second read voltage, the ninth read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-sixth read voltage, and the thirty-third read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the thirteenth reading voltage, the twenty-first reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. Memory device.

9. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the seventh reading voltage, the fifteenth reading voltage, the eighteenth reading voltage, the twenty-second reading voltage, the twenty-fifth reading voltage, and the twenty-nine reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the fourth reading voltage, the eighth reading voltage, the eleventh reading voltage, the nineteenth reading voltage, the twenty-seventh reading voltage, and the thirty-first reading voltage to the word line, respectively. In the reading operation on page 3, six readings are performed by applying the third reading voltage, the ninth reading voltage, the twelfth reading voltage, the sixteenth reading voltage, the twentieth reading voltage, and the twenty-sixth reading voltage to the word line, respectively. In the read operation on page 4, seven read operations are performed by applying the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, the twenty-third read voltage, and the thirtyth read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the thirteenth reading voltage, the twenty-first reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. Memory device.

10. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the sixth reading voltage, the twelfth reading voltage, the sixteenth reading voltage, the twentieth reading voltage, the twenty-third reading voltage, and the twenty-nine reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the fourth reading voltage, the eighth reading voltage, the eleventh reading voltage, the nineteenth reading voltage, the twenty-seventh reading voltage, and the thirty-first reading voltage to the word line, respectively. In the read operation on page 3, six read operations are performed by applying the third read voltage, the seventh read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, and the twenty-fifth read voltage to the word line, respectively. In the read operation on page 4, seven read operations are performed by applying the second read voltage, the ninth read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-second read voltage, the twenty-sixth read voltage, and the thirty-third read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the thirteenth reading voltage, the twenty-first reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. Memory device.

11. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the fifth reading voltage, the thirteenth reading voltage, the eighteenth reading voltage, the twenty-second reading voltage, the twenty-fifth reading voltage, and the twenty-nineth reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the fourth reading voltage, the eighth reading voltage, the eleventh reading voltage, the nineteenth reading voltage, the twenty-seventh reading voltage, and the thirty-first reading voltage to the word line, respectively. In the reading operation on page 3, six readings are performed by applying the third reading voltage, the ninth reading voltage, the twelfth reading voltage, the sixteenth reading voltage, the twentieth reading voltage, and the twenty-sixth reading voltage to the word line, respectively. In the read operation on page 4, seven read operations are performed by applying the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the seventeenth read voltage, the twenty-third read voltage, and the thirtyth read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the seventh reading voltage, the fifteenth reading voltage, the twenty-first reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. Memory device.

12. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the seventh reading voltage, the fifteenth reading voltage, the eighteenth reading voltage, the twenty-second reading voltage, the twenty-sixth reading voltage, and the thirty-third reading voltage to the word line, respectively. In the reading operation on the second page, six readings are performed by applying the fourth reading voltage, the eighth reading voltage, the thirteenth reading voltage, the twenty-first reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. In the read operation on page 3, seven read operations are performed, each applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-nine read voltage to the word line. In the read operation on page 4, six read operations are performed by applying the second read voltage, the sixth read voltage, the tenth read voltage, the fourteenth read voltage, the nineteenth read voltage, and the twenty-seventh read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the eleventh reading voltage, the seventeenth reading voltage, the twenty-fifth reading voltage, and the thirty-first reading voltage to the word line, respectively. Memory device.

13. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the fifth reading voltage, the thirteenth reading voltage, the eighteenth reading voltage, the twenty-second reading voltage, the twenty-sixth reading voltage, and the thirty-third reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the fourth reading voltage, the eighth reading voltage, the eleventh reading voltage, the nineteenth reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. In the read operation on page 3, seven read operations are performed, each applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-nine read voltage to the word line. In the reading operation on page 4, six readings are performed by applying the second reading voltage, the sixth reading voltage, the tenth reading voltage, the fourteenth reading voltage, the seventeenth reading voltage, and the twenty-fifth reading voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the seventh reading voltage, the fifteenth reading voltage, the 21st reading voltage, the 27th reading voltage, and the 31st reading voltage to the word line, respectively. Memory device.

14. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the seventh reading voltage, the fifteenth reading voltage, the eighteenth reading voltage, the twenty-second reading voltage, the twenty-sixth reading voltage, and the thirty-third reading voltage to the word line, respectively. In the reading operation on the second page, six readings are performed by applying the fourth reading voltage, the eighth reading voltage, the thirteenth reading voltage, the twenty-first reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. In the read operation on page 3, seven read operations are performed, each applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-nine read voltage to the word line. In the reading operation on page 4, six readings are performed by applying the second reading voltage, the sixth reading voltage, the tenth reading voltage, the fourteenth reading voltage, the seventeenth reading voltage, and the twenty-fifth reading voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the eleventh reading voltage, the nineteenth reading voltage, the twenty-seventh reading voltage, and the thirty-first reading voltage to the word line, respectively. Memory device.

15. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, six readings are performed by applying the seventh reading voltage, the fifteenth reading voltage, the eighteenth reading voltage, the twenty-second reading voltage, the twenty-sixth reading voltage, and the thirty-third reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the fourth reading voltage, the eighth reading voltage, the eleventh reading voltage, the nineteenth reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. In the read operation on page 3, seven read operations are performed, each applying the third read voltage, the ninth read voltage, the twelfth read voltage, the sixteenth read voltage, the twentieth read voltage, the twenty-third read voltage, and the twenty-nine read voltage to the word line. In the reading operation on page 4, six readings are performed by applying the second reading voltage, the sixth reading voltage, the tenth reading voltage, the fourteenth reading voltage, the seventeenth reading voltage, and the twenty-fifth reading voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the thirteenth reading voltage, the twenty-first reading voltage, the twenty-seventh reading voltage, and the thirty-first reading voltage to the word line, respectively. Memory device.

16. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, seven readings are performed by applying the fourth reading voltage, the eighth reading voltage, the twelfth reading voltage, the sixteenth reading voltage, the twentieth reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. In the reading operation on page 2, six readings are performed by applying the 7th reading voltage, the 11th reading voltage, the 14th reading voltage, the 23rd reading voltage, the 27th reading voltage, and the 30th reading voltage to the word line, respectively. In the reading operation on page 3, six readings are performed by applying the third reading voltage, the sixth reading voltage, the fifteenth reading voltage, the nineteenth reading voltage, the twenty-second reading voltage, and the thirty-first reading voltage to the word line, respectively. In the read operation on page 4, six read operations are performed by applying the second read voltage, the fifth read voltage, the ninth read voltage, the eighteenth read voltage, the twenty-first read voltage, and the twenty-fifth read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the tenth reading voltage, the thirteenth reading voltage, the seventeenth reading voltage, the twenty-sixth reading voltage, and the twenty-nineth reading voltage to the word line, respectively. Memory device.

17. A plurality of memory cells, each storing 5-bit data including 1st bit data to 5th bit data according to a threshold voltage, and storing 1st page to 5th page corresponding to the 1st bit data to 5th bit data, Word lines connected to the plurality of memory cells, A controller that performs a read operation, The threshold voltage of the memory cell is located in one of the 0th to 31st states, each of which is assigned different 5-bit data, and the 1st to 31st read voltages are set in order from the lowest voltage to the highest voltage, corresponding to adjacent states among the 0th to 31st states. The aforementioned controller, In the reading operation of the first page, seven readings are performed by applying the fourth reading voltage, the eighth reading voltage, the twelfth reading voltage, the sixteenth reading voltage, the twentieth reading voltage, the twenty-fourth reading voltage, and the twenty-eighth reading voltage to the word line, respectively. In the reading operation on the second page, six readings are performed by applying the sixth reading voltage, the ninth output voltage, the thirteenth reading voltage, the twenty-second reading voltage, the twenty-fifth reading voltage, and the twenty-nine reading voltage to the word line, respectively. In the read operation on page 3, six read operations are performed by applying the third read voltage, the seventh read voltage, the tenth read voltage, the nineteenth read voltage, the twenty-third read voltage, and the twenty-sixth read voltage to the word line, respectively. In the read operation on page 4, six read operations are performed by applying the second read voltage, the eleventh read voltage, the fifteenth read voltage, the eighteenth read voltage, the twenty-seventh read voltage, and the thirty-first read voltage to the word line, respectively. In the reading operation on page 5, six readings are performed by applying the first reading voltage, the fifth reading voltage, the fourteenth reading voltage, the seventeenth reading voltage, the twenty-first reading voltage, and the thirty-first reading voltage to the word line, respectively. Memory device.

18. The first read voltage and the second read voltage are both negative voltages. A memory device according to any one of claims 1 to 17.

19. The first read voltage, the second read voltage, the third read voltage, and the fourth read voltage are all negative voltages. A memory device according to any one of claims 1 to 17.

20. The controller applies the read voltages in order from the highest to the lowest during each of the following operations: the read operation of the first page, the read operation of the second page, the read operation of the third page, the read operation of the fourth page, and the read operation of the fifth page. A memory device according to any one of claims 1 to 17.

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