Magnetic memory and memory systems

Abstract

To provide a magnetic memory with a small number of error bits.SOLUTION: A flow of data reading by a magnetic memory includes: setting a temporary value at a first bit of temporarily read data in a data latch 31; shifting a magnetic wall and moving a next reading target memory cell to a reading position when the acquisition of temporarily read data for all reading target memory cells has not been completed yet; determining the presence or absence of a magnetic wall between the memory cells; setting, at the first bit of the temporarily read data, the same value as a second bit; shifting the bit of the temporarily read data towards an upper bit side by one bit when the magnetic wall has been detected; setting, at the first bit, a value opposite to the value of the second bit; and using magnetization information to update a value of a magnetization information latch with a value based on a type of a change in the detected magnetic wall. When the acquisition of the temporarily read data has been completed for all the reading target memory cells, magnetization resolution is performed.SELECTED DRAWING: Figure 15

Description

Technical Field

[0001] Embodiments generally relate to magnetic memories and memory systems.

Background Art

[0002] Memory systems including a memory and a memory controller are known. Examples of memories include magnetic memories using magnetic materials. Memory systems are required to accurately store and output data.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object is to provide a magnetic memory and a memory system with a small number of error bits.

Means for Solving the Problems

[0005] A magnetic memory according to one embodiment includes a magnetic material, a first circuit, a first memory circuit, a second memory circuit, and a second circuit. The magnetic material extends in a first direction and includes a plurality of parts aligned in the first direction. The first circuit outputs first information indicating the presence or absence of a magnetic domain wall between each pair of adjacent parts, and second information based on the combination of the two magnetization states. The first memory circuit stores a plurality of first bits corresponding to each of the plurality of parts. The most significant bit of the plurality of first bits has a value independent of one of the corresponding magnetization states of the plurality of parts. Each of the plurality of first bits has a value based on the first information. The second memory circuit stores the second information in the second bit. The second circuit outputs the multiple first bits from the first memory circuit if the value of the least significant bit of the multiple first bits matches the value of the second information stored in the second memory circuit. If the value of the least significant bit differs from the value of the second information stored in the second memory circuit, the second circuit outputs a plurality of third bits from the first memory circuit, each of which has a value opposite to the value of the multiple first bits. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows an example of a functional block of an information processing system including a memory system according to the first embodiment. [Figure 2] Figure 2 shows an example of a functional block of the memory system according to the first embodiment. [Figure 3] Figure 3 shows an example of a functional block of the magnetic memory in the memory system of the first embodiment. [Figure 4] Figure 4 shows an example of the components of the memory cell array of the memory system according to the first embodiment. [Figure 5] Figure 5 shows an example of a partial structure of the memory cell array of the memory system of the first embodiment. [Figure 6] Figure 6 shows an example of the structure of the magnetic material and laminate of the memory system according to the first embodiment. [Figure 7] Figure 7 shows an example of the components of the read circuit of the memory system in the first embodiment. [Figure 8] Figure 8 shows the data writing flow using the magnetic memory of the memory system in the first embodiment. [Figure 9] Figure 9 shows the states of several elements during operation of the memory system of the first embodiment. [Figure 10] Figure 10 shows the states of several elements during operation of the memory system of the first embodiment. [Figure 11] Figure 11 shows the states of several elements during operation of the memory system of the first embodiment. [Figure 12] Figure 12 shows the states of several elements during operation of the memory system of the first embodiment. [Figure 13] Figure 13 shows the states of several elements during operation of the memory system of the first embodiment. [Figure 14] Figure 14 shows the states of several elements during operation of the memory system of the first embodiment. [Figure 15] Figure 15 shows the data retrieval flow using the magnetic memory of the memory system in the first embodiment. [Figure 16] Figure 16 shows the data retrieval flow by the memory system of the first embodiment. [Figure 17] Figure 17 shows an unintended reversal of the magnetization state for unit magnetization. [Figure 18] Figure 18 shows an example of a functional block of the memory controller in the second embodiment of the memory system. [Figure 19] Figure 19 shows the data retrieval flow using the magnetic memory of the memory system in the second embodiment. [Figure 20] Figure 20 shows the data retrieval flow by the memory system of the second embodiment. [Figure 21] Figure 21 shows an example of a functional block of the magnetic memory in the memory system of the third embodiment. [Figure 22] Figure 22 shows the state of several elements during operation of the memory system of the third embodiment. [Figure 23]FIG. 23 shows the data reading flow by the magnetic memory of the memory system of the third embodiment. [Figure 24] FIG. 24 shows the data reading flow by the magnetic memory of the memory system of the third embodiment. [Figure 25] FIG. 25 shows the data reading flow by the memory system of the third embodiment. [Figure 26] FIG. 26 shows the data reading flow by the memory system of the third embodiment. [Figure 27] FIG. 27 shows an example of data generated during the operation in the memory system of the third embodiment. [Figure 28] FIG. 28 shows the data reading flow by the magnetic memory of the memory system of the fourth embodiment. [Figure 29] FIG. 29 shows the data reading flow by the memory system of the fourth embodiment.

Embodiments for Carrying Out the Invention

[0007] Embodiments will be described below with reference to the drawings. For a plurality of components having substantially the same functions and configurations in one embodiment or different embodiments, additional numbers or characters may be added to the end of the reference numerals in order to distinguish them from each other. In embodiments following a described embodiment, the differences from the described embodiment are mainly described. All descriptions of an embodiment also apply as descriptions of another embodiment unless explicitly or implicitly excluded.

[0008] Each functional block can be realized as either hardware, computer software, or a combination of both. Therefore, it is generally described from the perspective of those functions so that it is clear that each functional block is any of these.

[0009] Any step in the method flow of the embodiment is not limited to the illustrative order and, unless otherwise indicated, may occur in a different order and / or in parallel with other steps.

[0010] In this specification and in the claims, "connected" to another second element means that the first element is connected to the second element directly, or via an element that is always or selectively conductive.

[0011] 1. First Embodiment 1.1.Configuration (Structure) 1.1.1. Information Processing Systems Figure 1 shows an example of a functional block of an information processing system including a memory system according to the first embodiment. The information processing system 100 includes a memory system 1 and a host device 5.

[0012] The host device 5 requests the memory system 1 to read data and write data.

[0013] Memory system 1 is a system for storing data. Memory system 1 receives a data write request from host device 5 and stores the requested data. Memory system 1 receives a data read request from host device 5 and transmits the requested data to host device 5.

[0014] 1.1.2. Memory System Figure 2 shows an example of the functional block of the memory system 1 of the first embodiment. As shown in Figure 2, the memory system 1 includes a magnetic memory 2 and a memory controller 3.

[0015] Magnetic memory 2 is a device that stores data non-volatilely using magnetization. Magnetic memory 2 includes a magnetic material having multiple magnetic domains, and stores data using the orientation of the magnetization of the magnetic domains.

[0016] The memory controller 3 is a device that controls the magnetic memory 2. The memory controller 3 controls the magnetic memory 2 to read data and write data based on requests from the host device 5.

[0017] The memory controller 3 includes functional blocks such as a host interface 11, ROM (read-only memory) 12, RAM (random access memory) 13, CPU (central processing unit) 14, memory interface 15, and error correction circuit 16.

[0018] The memory controller 3 functions as a sub-unit, such as an error correction control unit, a write control unit, a read control unit, a signal transmission control unit, and a signal reception control unit, based on the operation it is performing. The error correction control unit controls the entire process performed for error correction, including data splitting, data merging, temporary data storage, data supply, control of the encoding control unit, and control of the decoding control unit. The write control unit controls the process for writing data to the magnetic memory 2, including preparing the data to be written to the magnetic memory 2 and generating the write command CMD and address information ADD. The read control unit controls the process for reading data from the magnetic memory 2, and generates the read command CMD and address information ADD that identifies the data based on the data read from the magnetic memory 2. The signal transmission control unit controls the transmission of signals including data DAT, command CMD, address information ADD, and control signal CNT to the magnetic memory 2 and controls the memory interface 15. The signal reception control unit controls the reception of signals including data DAT and control signal CNT from the magnetic memory 2 and controls the memory interface 15.

[0019] The host interface 11 is an interface for the memory controller 3 to communicate with the host device 5. The host interface 11 can consist of hardware or a combination of hardware and software. The host interface 11 is connected to the host device 5 by wiring that enables communication in a manner (or standard) to which the host interface 11 and the host device 5 conform.

[0020] ROM12 is a non-volatile memory. ROM12 stores a program, including firmware. The program is configured to be executed by the CPU14, causing the memory controller3 to perform the operations described herein. ROM12 may be implemented as a single semiconductor chip, as a plurality of independent semiconductor chips, or as a circuit formed on a semiconductor substrate.

[0021] RAM13 is a volatile memory. RAM13 temporarily stores data and stores programs stored in ROM12 while the memory system 1 is powered. Examples of RAM13 include DRAM (Dynamic Random Access Memory) and SRAM (Static RAM). RAM13 also functions as working memory and a data buffer while the memory controller 3 is operating. RAM13 may be implemented as a single semiconductor chip, as multiple independent semiconductor chips, or as a circuit formed on a semiconductor substrate.

[0022] The CPU 14 is a circuit that controls the overall operation of the memory controller 3. The CPU 14 executes programs stored in the ROM 12 and loaded onto the RAM 13, allowing the memory controller 3 to perform various operations and function as various sub-components. The CPU 14 may be implemented as a single semiconductor chip, as multiple independent semiconductor chips, or as a circuit formed on a semiconductor substrate.

[0023] The memory interface 15 is an interface for the memory controller 3 to communicate with the magnetic memory 2. The memory interface 15 can consist of hardware or a combination of hardware and software. The memory interface 15 is connected to the magnetic memory 2 by wiring that enables communication between the magnetic memory 2 and the memory controller 3 in a manner compliant with the memory interface 15. The memory interface 15 transmits the command CMD and address information ADD to the magnetic memory 2. The memory interface 15 transmits the control signal CNT and data DAT to the magnetic memory 2 and receives the control signal CNT and data DAT from the magnetic memory 2.

[0024] The command CMD indicates the operation that magnetic memory 2 should perform. The address information ADD identifies the area in magnetic memory 2 to be read from or written to. The control signal CNT is a signal for controlling the timing of operations between magnetic memory 2 and memory controller 3, and the timing of operations within magnetic memory 2.

[0025] The error correction circuit 16 uses an Error Correction Code (ECC) to detect and correct errors in the data read from the magnetic memory 2. The error correction circuit 16 generates an error correction code from the data written to the magnetic memory 2 (actual write data). The actual write data and the error correction code generated from this actual write data are written to the magnetic memory 2. The error correction circuit 16 uses the error correction code to detect errors in the data read from the magnetic memory 2 and corrects the errors if they are detected. The error correction circuit 16 may be implemented as an independent, dedicated semiconductor chip, as a circuit formed on a semiconductor substrate, or by the CPU 14 executing firmware.

[0026] 1.1.3. Magnetic Memory Figure 3 shows the functional blocks of the magnetic memory in the memory system of the first embodiment. As shown in Figure 3, the magnetic memory 2 includes functional blocks such as a memory cell array 21, input / output circuits 22, control circuits 23, row selection circuits 24, column selection circuits 25, write circuits 26, read circuits 27, shift circuits 29, data latch 31, magnetization information latch 32, and magnetization resolution circuits 33.

[0027] The memory cell array 21 includes multiple strings STR. Each string STR includes multiple memory cells MC. Each memory cell MC can store 1 bit of data non-volatilely and contains a magnetic material. The memory cell array 21 also contains wiring such as multiple source lines SL, multiple bit lines BL, and multiple field lines EL. The wiring is not shown in Figure 3.

[0028] The input / output circuit 22 is a circuit that inputs signals to the magnetic memory 2 and outputs signals from the magnetic memory 2. The input / output circuit 22 is connected to the memory controller 3 by wiring. The input / output circuit 22 receives the control signal CNT, command CMD, address information ADD, and data DAT from the memory controller 3. The input / output circuit 22 transmits the control signal CNT and data DAT to the memory controller 3. In the case of data writing to the magnetic memory 2, data DAT includes the written data. In the case of data reading from the magnetic memory 2, data DAT includes the read data.

[0029] The row selection circuit 24 is a circuit that selects a row of memory cell MC. The row selection circuit 24 receives address information ADD from the input / output circuit 22. The row selection circuit 24 obtains a row address from the address information ADD. The row selection circuit 24 selects the row identified by the row address in the memory cell array 21. The row selection circuit 24 includes circuits such as a multiplexer, a switch circuit, and a driver circuit.

[0030] The column selection circuit 25 is a circuit that selects a row of memory cells MC. The column selection circuit 25 receives address information ADD from the input / output circuit 22. The column selection circuit 25 obtains the column address from the address information ADD. The row selection circuit 24 selects the column (e.g., bit line BL) in the memory cell array 21 that is identified by the column address. The column selection circuit 25 includes circuits such as a multiplexer, a switch circuit, and a driver circuit.

[0031] The write circuit 26 is a circuit that controls the writing of data to memory cells MC. During data writing, the write circuit 26 supplies a write current or write voltage to the memory cell array 21. This writes the data to the selected memory cell MC. For example, the write circuit 26 is connected to the memory cell array 21 via a row selection circuit 24. The write circuit 26 includes a voltage source and / or a current source.

[0032] The read circuit 27 is a circuit that controls the reading of data from the memory cell MC. The read circuit 27 supplies a read current or voltage to the memory cell array 21, senses the signal output from the memory cell MC, and outputs data relating to the state of the memory cell MC from which data is to be read. The data relating to the state of the memory cell MC from which data is to be read includes domain wall presence information and magnetization information. The domain wall presence information indicates by at least one bit whether it is determined that the magnetizations of two adjacent memory cell MCs are different. The magnetization information indicates by at least one bit the combination of magnetizations of two adjacent memory cell MCs. The magnetization information expresses how the state of the memory cell MC from which a certain state is to be determined has changed from the state of the memory cell MC adjacent to the memory cell MC from which this state is to be determined.

[0033] The shift control circuit 29 is a circuit that controls the movement of memory cells MC. The shift control circuit 29 shifts magnetic domain walls to store data in a memory cell MC at a specified address and to read data from a memory cell MC at a specified address. The shift control circuit 29 supplies current or voltage to the memory cell array 21, thereby moving the magnetic domain walls. For example, the shift control circuit 29 is connected to the memory cell array 21 via a column selection circuit 25.

[0034] The data latch 31 is a circuit that stores data. When data is written, the data latch 31 receives the data to be written from the input / output circuit and transmits the received data to the write circuit 26. During data reading, the data latch 31 stores the read data and temporary read data. The temporary read data is used to generate the read data. The data latch 31 further has the function of a shift register and the function of storing data in which the value of one or more specified bits of the stored data has been inverted. The data latch 31 transmits the read data to the input / output circuit 22.

[0035] The magnetization information latch 32 is a circuit that stores magnetization information. The magnetization information latch 32 can store one or more bits. The magnetization information latch 32 receives magnetization information from the magnetization resolution circuit 33.

[0036] The magnetization resolution circuit 33 is a circuit that generates read data from domain wall existence information and magnetization information. The magnetization resolution circuit 33 stores the latest received magnetization information in the magnetization information latch 32. Based on the received domain wall existence information, the magnetization resolution circuit 33 generates information indicating the data that is determined to be stored in the memory cell MC to be read, and generates provisional read data. The magnetization resolution circuit 33 refers to the magnetization information in the magnetization information latch 32 and uses the magnetization information to generate read data that is determined to be stored in the memory cell MC to be read from the provisional read data.

[0037] The control circuit 23 is a circuit that controls the entire magnetic memory 2. The control circuit 23 receives control signals CNT and commands CMD from the input / output circuit 22. The control circuit 23 generates control signals based on the control signals CNT and commands CMD. The control circuit 23 uses the generated control signals to control the write circuit 26, the read circuit 27, the shift control circuit 29, and the magnetization resolution circuit 33.

[0038] 1.1.4. Memory cell array Figure 4 shows an example of the components of the memory cell array of the memory system of the first embodiment. As shown in Figure 4, each string STR contains N memory cells MC_0 to MC_N-1, where N is a positive integer. In each string STR, the memory cell MC of this string STR consists of a single magnetic material portion that extends in a certain direction as a whole.

[0039] Figure 5 shows an example of a partial structure of the memory cell array of the memory system of the first embodiment. As shown in Figure 5, the memory cell array 21 includes a plurality of magnetic materials UT and a plurality of stacked materials LS. The memory cell array 21 also contains a plurality of conductors 41, a plurality of conductors 42, and a plurality of conductors 43.

[0040] The magnetic materials UT are arranged in mutually orthogonal X and Y directions. Each magnetic material UT has a linear shape and extends in the Z direction. The Z direction is orthogonal to the X and Y directions. Hereinafter, a position in the Z direction from a certain point may be referred to as "above," and a position in the opposite direction to the Z direction (-Z direction) from a certain point may be referred to as "below." In one example, each magnetic material UT includes a thin magnetic surface film and an internal non-magnetic material. Each magnetic material UT functions as a string STR. The magnetic material UT contains multiple unit parts ML. Each unit part ML is arranged one at a time in the direction in which the magnetic material UT extends and is in contact with the adjacent unit part ML.

[0041] Each laminate LS includes multiple magnetic materials and multiple insulators. Each of the multiple magnetic materials and multiple insulators has a layered shape and is aligned in the Z direction. Each laminate LS includes a structure that functions as a switching element and a structure that functions as an MTJ (Magnetic Tunneling Junction) element. The structure that functions as an MTJ element is located on the upper surface of the structure that functions as a switching element. Each laminate LS is in contact with the lower surface of one magnetic material UT on its upper surface. The structure that functions as an MTJ element includes an MTJ and includes two ferromagnetic materials and an insulator between the two ferromagnetic materials. The structure that functions as a switching element controls the electrical conduction and non-conductivity at both ends of the switching element.

[0042] The conductor 41 is located in the -Z direction relative to the set of laminates LS. The conductor 41 extends in the X direction and is aligned in the Y direction. Each conductor 41 functions as one source line SL. Each conductor 41 is connected to the underside of multiple laminates LS aligned in the X direction.

[0043] The conductor 42 is located in the Z direction relative to the set of magnetic materials UT. The conductor 42 is aligned along the XY plane, which consists of the X and Y directions, and also in directions that intersect the X and Y directions, for example, in directions that intersect the direction in which the conductor 42 extends. Each conductor 42 functions as one bit line BL. Each conductor 42 is connected to the upper surface of each of the multiple magnetic materials UT, which are different from the multiple magnetic materials UT connected to one conductor 41.

[0044] The conductor 43 extends in the X direction. Each conductor 43 extends along a unit portion ML located at the upper end of each of the multiple magnetic materials UT aligned in the X direction. Each conductor 43 is spaced apart from the unit portions ML located at the upper end of each of the multiple magnetic materials UT aligned in the X direction. Each conductor 43 functions as a single field line EL. When current flows through the conductor 43 during data writing, a magnetic field is generated around the conductor 43. This magnetic field causes the unit portions ML, which are spaced apart from the conductor 43, to be magnetized in a direction based on the direction of the magnetic field.

[0045] Figure 6 shows an example of the structure of the magnetic material and laminate of the memory system of the first embodiment. The magnetic material UT includes a plurality of unit parts ML as described above with reference to Figure 5, and for example includes N unit parts ML_0 to ML_N-1. The boundary of each pair of adjacent unit parts ML has a smaller XY area than the XY area at other locations. The XY area is the area of ​​the plane along the XY plane. Due to the small XY area at each boundary of the unit parts ML, magnetic domain walls are more likely to remain at the boundaries of the unit parts ML than at other locations. Based on the tendency of magnetic domain walls to remain at the boundaries of the unit parts ML, magnetic domains are formed in each unit part ML. Each magnetic domain has magnetization. The magnetization can have one of two different directions. The direction of magnetization is variable by control by the magnetic memory 2. For ease of understanding, Figure 6 shows a configuration in which each unit part ML has one magnetic domain. However, if two or more adjacent unit portions ML have magnetization in the same direction, the region consisting of these unit portions ML has a single magnetic domain and does not contain a domain wall. Magnetic memory 2 stores one bit of data based on the direction of magnetization in each unit portion ML. That is, each unit portion ML functions as one memory cell MC.

[0046] The conductor 43 is aligned with the uppermost unit portion ML_0. Data is written to the memory cell MC located at the unit portion ML_0. The unit portion ML_0 is sometimes referred to as the write position.

[0047] The laminate LS includes an MTJ element MTJ and a variable resistance material SEL. The variable resistance material SEL functions as a switching element. The variable resistance material SEL is a material that exhibits dynamically variable resistance and has, for example, a layered shape. The variable resistance material SEL is a two-terminal switching element, where the first terminal of the two terminals is one of the upper and lower surfaces of the variable resistance material SEL, and the second terminal of the two terminals is the other of the upper and lower surfaces of the variable resistance material SEL. When the voltage applied between the two terminals is below a certain threshold voltage, the variable resistance material is in a "high resistance" state, for example, electrically non-conductive. When the voltage applied between the two terminals of the variable resistance material SEL in the low resistance state decreases and falls below the threshold voltage, the variable resistance material returns to a high resistance state.

[0048] In one example, the variable resistor material SEL comprises an insulator and a dopant introduced into the insulator by ion implantation. The insulator includes, for example, an oxide and a material substantially composed of SiO2. The dopant includes, in one example, arsenic (As) and germanium (Ge). The phrase "substantially composed of" and similar phrases means that the "substantially composed" components may contain unintended impurities.

[0049] An MTJ element includes a ferromagnetic layer RL, an insulating layer TB, and a ferromagnetic layer FL. In one example, as shown in Figure 6, the insulating layer TB is located on the upper surface of the ferromagnetic layer RL, and the ferromagnetic layer FL is located on the upper surface of the insulating layer TB.

[0050] The ferromagnetic layer RL is a layer of ferromagnetic material. The ferromagnetic layer RL has an easy magnetization axis aligned in a certain direction. The direction of magnetization of the ferromagnetic layer RL is intended to remain unchanged even when reading and writing data in the memory cell MC and when voltage or current is applied for domain wall shifting. The ferromagnetic layer RL functions as a so-called reference layer. The ferromagnetic layer RL may comprise multiple layers.

[0051] The insulating layer TB is an insulating layer. The insulating layer TB contains, for example, magnesium oxide (MgO) or is substantially composed of MgO and functions as a so-called tunnel barrier.

[0052] The ferromagnetic layer FL is a layer of ferromagnetic material. The ferromagnetic layer FL may contain, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or may be substantially composed of CoFeB or FeB. The ferromagnetic layer FL has an easy magnetization axis aligned with the easy magnetization axis of the ferromagnetic layer RL. The magnetization direction of the ferromagnetic layer FL is variable and is linked to the magnetization direction of the lowest unit portion ML_N-1, for example, having a magnetization direction parallel to the magnetization direction of the lowest unit portion ML_N-1. The ferromagnetic layer FL functions as a so-called memory layer.

[0053] When the magnetization direction of the memory layer FL is parallel to the magnetization direction of the reference layer RL, the MTJ element has a certain low resistance. When the magnetization direction of the memory layer FL is antiparallel to the magnetization direction of the reference layer RL, the MTJ element has a higher resistance than when the magnetization directions of the memory layer FL and the reference layer RL are parallel. Based on the resistance of the MTJ element, it is possible to determine the magnetization direction of the memory layer FL, and by extension, the magnetization direction of the unit portion ML_N-1. Based on the magnetization direction of the unit portion ML_N-1, it is possible to determine the data stored in the memory cell MC located in the unit portion ML_N-1. The lowest unit portion ML_N-1 is sometimes referred to as the read position.

[0054] Hereinafter, a state in which a unit portion has magnetization in one of two opposite directions and the other will be referred to as the north pole state and the south pole state, respectively.

[0055] To read data from a memory cell MC, the magnetic domain walls of the magnetic material UT are shifted toward the stack LS until the memory cell MC to be read is located in unit portion ML_N-1. That is, data writing is performed in unit portion ML_0, and data reading is performed in unit portion ML_N-1. This data writing and reading method is a FIFO (First In First Out) method.

[0056] The laminate LS may include further layers such as a conductor.

[0057] 1.1.5. Readout Circuit Figure 7 shows an example of the components of the read circuit of the memory system according to the first embodiment. As shown in Figure 7, the read circuit 27 includes information holding circuits 271 and 272, and a sense amplifier 273.

[0058] The information retention circuits 271 and 272 each retain a physical value that reflects the magnetization direction of the memory cell MC, i.e., whether it is in a north pole state or a south pole state. That is, based on the magnetization direction of the memory cell MC, the MTJ element is in a high-resistance state or a low-resistance state, and therefore, a physical value based on the resistance state of the MTJ element can be obtained. The physical value reflects the magnetization state of the memory cell MC at the read position, i.e., whether it is in a north pole state or a south pole state. An example of a physical value is a voltage based on the resistance of the memory cell MC, in which case the information retention circuits 271 and 272 are capacitors.

[0059] One of the information holding circuits 271 and 272 holds a value based on the state of the memory cell MC at the read position. The memory cell MC at the read position may be referred to as the read position cell MC. The other of the information holding circuits 271 and 272 holds a value based on the state of the memory cell MC adjacent to the read position cell MC in the -Z direction, for example, a value based on the state of the memory cell MC that was at the read position before the domain wall shift. The memory cell MC adjacent to the read position cell MC in the -Z direction may be referred to as the previous read position cell MC.

[0060] The sense amplifier 273 outputs magnetic domain wall presence information and magnetization information based on the values ​​of the information holding circuits 271 and 272, respectively, namely the value for the read position cell MC and the value for the previously read position cell MC.

[0061] If the value for the currently read cell MC is substantially the same as the value for the previously read cell MC, for example, if the difference between the two values ​​falls within a certain range, this means that the currently read cell MC and the previously read cell MC have the same magnetization state. In this case, there is no magnetic domain wall between the currently read cell MC and the previously read cell MC, and therefore the sense amplifier 273 outputs magnetic domain wall presence information, such as "0" data, indicating the absence of a magnetic domain wall.

[0062] On the other hand, if the value for the currently read cell MC differs from the value for the previously read cell MC, for example, if the difference between the two values ​​exceeds a certain range, this means that the currently read cell MC and the previously read cell MC have different magnetization states. In this case, a magnetic domain wall exists between the currently read cell MC and the previously read cell MC, and therefore, the sense amplifier 273 outputs magnetic domain wall presence information, for example, "1" data, indicating the presence of a magnetic domain wall.

[0063] The magnetization information contains a value, for example, "0", indicating that the previously read cell MC is in a north pole state and the read cell MC is in a south pole state. Conversely, the magnetization information contains a value, for example, "1", indicating that the previously read cell MC is in a south pole state and the read cell MC is in a north pole state. The values ​​contained in the magnetization information may be the reverse of this example.

[0064] 1.2.Operation The following description is based on an example in which magnetic memory 2 treats memory cells MC in the south pole state as storing "0" data and memory cells MC in the north pole state as storing "1" data. Magnetic memory 2 may store "1" data using memory cells MC in the south pole state and "0" data using memory cells MC in the north pole state.

[0065] 1.2.1. Data Writing Figure 8 shows the data writing flow by the magnetic memory of the memory system of the first embodiment. The flow in Figure 8 begins when the magnetic memory 2 receives a write command instructing data writing and the data to be written. The write command includes or is accompanied by address information ADD that identifies the memory cell MC to which the data to be written is to be written.

[0066] The magnetic memory 2 sets the data to be written into the data latch 31 (ST1). The data to be written contains one or more bits. In the case of writing data of multiple bits, the data is written one bit at a time.

[0067] The magnetic memory 2, for example, the writing circuit 26, selects the bits (write bits) to be written to the memory cell MC in the data to be written (ST2). The write bits are selected one by one from the most significant bit to the least significant bit of the bit sequence of the data to be written.

[0068] The magnetic memory 2, for example, the control circuit 23, controls the shift control circuit 29 to shift the memory cell MC to the write position (ST3). If the memory cell MC at the write position is unwritten, step ST3 is skipped.

[0069] If the bit to be written has "0" data (ST4_Yes), the magnetic memory 2, for example, the writing circuit 26, sets the memory cell MC to the S pole state (ST5). If the bit to be written has "1" data (ST4_No), the magnetic memory 2, for example, the writing circuit 26, sets the memory cell MC to the N pole state (ST6).

[0070] Steps ST5 and ST6 continue to step ST7. The magnetic memory 2, for example, the writing circuit 26, determines whether all bits of the data to be written have been written (ST7). If all bits have been written (ST7_Yes), the flow in Figure 8 ends. If all bits have not been written (ST7_No), the flow proceeds to step ST2.

[0071] 1.2.2. Data Retrieval Data retrieval uses magnetization resolution. The principle of magnetization resolution is described with reference to Figures 9 to 14. Figures 9 to 14 sequentially show the states of several elements during operation of the memory system of the first embodiment. Each of Figures 9 to 14 shows different times in the left-right direction of the figure. Each of Figures 9 to 14 shows a unit portion ML of the read position and several unit portions ML adjacent to this unit portion in the top row of the figure. Each of Figures 9 to 14 shows domain wall presence information, provisional read data, and magnetization information latch values ​​in the second, third, and bottom rows from the top, respectively. The provisional read data is a sequence of bits the same number as the number of memory cells MC to be read. Each bit of the provisional read data indicates the magnetization state of a certain memory cell MC. The bits of the provisional read data, from the most significant bit to the least significant bit, indicate the memory cells MC located from the beginning to the end in the direction of the domain wall shift during the read. The bits of the provisional data are referred to as the 1st bit, 2nd bit, 3rd bit, 4th bit, and 5th bit, starting from the least significant bit (or last bit) and moving towards the most significant bit (or first bit). Below, the state in which each bit has invalid data is indicated by the symbol "-".

[0072] As shown in Figure 9, as an example, the data to be read consists of five memory cells MC, and the unit parts ML_N-1, ML_N-2, ML_N-3, ML_N-4, and ML_N-5 are in state 0. In state 0, the unit parts ML_N-1, ML_N-2, ML_N-3, ML_N-4, and ML_N-5 are occupied by memory cells MC1, MC2, MC3, MC4, and MC5, respectively. Memory cells MC1, MC2, MC4, and MC5 are in the north pole state, and memory cell MC3 is in the south pole state.

[0073] The magnetization state of memory cell MC1 is unknown, and therefore, as shown in Figure 10, the magnetization resolution circuit 33 stores a temporary value in the first bit of the temporary read data. Thus, the temporary read data has "----0" in the fifth bit to the first bit, respectively. The temporary value data may be "0" data (i.e., data indicating the south pole state) or "1" data (i.e., data indicating the north pole state). First, an example in which "0" data is entered, that is, an example in which a magnetization state opposite to the actual magnetization state of memory cell MC1 is assumed, is described. That is, it is assumed that memory cell MC1 is in the south pole state, and the subsequent processing takes place under this assumption.

[0074] Since no change in magnetization has been detected, the magnetization resolution circuit 33 does not update the value of the magnetization information latch 32, regardless of the value of the magnetization information.

[0075] As shown in Figure 11, the magnetic domain walls are shifted, and state 1 is obtained. In state 1, memory cells MC2 to MC5 are located in unit parts ML_N-1, ML_N-2, ML_N-3, and ML_N-4, respectively.

[0076] Since memory cell MC2 has the same magnetization state as memory cell MC1, the domain wall presence information has "0" data. The magnetization resolution circuit 33 shifts the bits of the provisional read data by one bit to the higher bit side and stores a value based on the domain wall presence information in the first bit. If the domain wall presence information indicates the absence of a domain wall, the magnetization resolution circuit 33 sets the first bit of the provisional read data to the same value as the second bit (i.e., the first bit before the domain wall shift). In other words, memory cell MC2 is treated as having the same S-pole state as the S-pole state assumed to be present in memory cell MC1. The provisional read data has "---00" in the fifth bit to the first bit, respectively.

[0077] Since no change in magnetization has occurred, the magnetization resolution circuit 33 does not update the value of the magnetization information latch 32, regardless of the value of the magnetization information.

[0078] As shown in Figure 12, the magnetic domain walls are shifted, and state 2 is obtained. In state 2, memory cells MC3 to MC5 are located in unit parts ML_1, ML_2, and ML_3, respectively.

[0079] Since memory cell MC3 has a different magnetization state than memory cell MC2, the domain wall presence information has the data value "1". The magnetization resolution circuit 33 shifts the bits of the provisional read data by one bit to the higher bit side and stores a value based on the domain wall presence information in the first bit. If the domain wall presence information indicates the presence of a domain wall, the magnetization resolution circuit 33 stores the opposite value of the second bit in the first bit of the provisional read data based on this. That is, memory cell MC3 is treated as having an N-pole state opposite to the S-pole state assumed to be present in memory cell MC2. Therefore, the provisional read data has "--001" in the fifth to first bits, respectively.

[0080] Because a change in magnetization has occurred, the magnetization resolution circuit 33 updates the value of the magnetization information latch 32 with a value indicating the change in the poles of memory cell MC3, based on the magnetization state assumed to be present in memory cell MC2, which was determined before the domain wall shift. In the current example, since memory cell MC3 has changed from the N pole state to the S pole state of memory cell MC2, the data "0" is set in the magnetization information latch 32.

[0081] As shown in Figure 13, the same process described above with reference to Figures 11 and 12 is performed consecutively. In state 3, memory cells MC4 and MC5 are located in unit parts ML_0 and ML_1, respectively. Memory cell MC4 has a different magnetization state from memory cell MC3. Therefore, the domain wall presence information has "1" data. The magnetization resolution circuit 33 shifts the bits of the provisional read data by one bit to the higher-order bit side, and sets a different value from the second-order bit, i.e., "0" data, in the first-order bit. Therefore, the provisional read data has "-0010" in the fifth-order bit to the first-order bit, respectively. Since memory cell MC4 has changed from the S state to the N-pole state of memory cell MC3, "1" data is set in the magnetization information latch 32.

[0082] In state 4, memory cell MC5 is located in unit part ML_1. Memory cell MC5 has the same magnetization state as memory cell MC4. Therefore, the domain wall presence information has "0" data. The magnetization resolution circuit 33 shifts the bits of the temporarily read data by one bit to the higher bit side, and sets the first bit to the same value as the second bit, i.e., "0" data. Therefore, the temporarily read data has "00100" in the fifth to first bits, respectively. Since no change in magnetization has occurred, the magnetization information latch 32 maintains "1" data.

[0083] When a magnetic domain wall shift occurs from state 4, the shift is completed. Then, the magnetization resolution circuit 33 performs magnetization resolution. Magnetization resolution refers to generating read data from the temporary read data based on the value of the first bit of the temporary read data.

[0084] The magnetization resolution circuit 33 generates read data based on the value of the magnetization information latch 32 and the value of the first bit of the temporary read data. If the value of the magnetization information latch 32 and the value of the first bit of the temporary read data match, the magnetization resolution circuit 33 uses the temporary read data as is.

[0085] On the other hand, if the value of the magnetization information latch 32 does not match the value of the first bit of the provisional read data, this means that the assumed magnetization state of the first memory cell MC to be read (i.e., memory cell MC1) does not match the actual magnetization state. Based on this, the set of values ​​that are the opposite of the values ​​of all the bits of the provisional read data is used as the read data. In the current example, the value of the magnetization information latch 32 does not match the value of the first bit of the provisional read data. Therefore, the magnetization resolution circuit 33 uses the bit sequence "11011" as the read data.

[0086] Unlike Figures 9 to 13, Figure 14 shows a case where the assumed magnetization state of the first memory cell MC to be read (i.e., memory cell MC1) matches the actual magnetization state. The magnetization states of memory cells MC1 to MC5 are the same as those in Figures 9 to 13.

[0087] In state 0, the tentatively read data has "----1" in the 5th bit through the 1st bit.

[0088] In state 1, the tentatively read data has "---11" in the 5th bit to the 1st bit, respectively.

[0089] In state 2, the provisional readout data has "--110" in the 5th bit to the 1st bit, and the magnetization information latch 32 has "0" data.

[0090] In state 3, the provisional readout data has "-1101" in the 5th bit to the 1st bit, and the magnetization information latch 32 has the data "1".

[0091] In states 4 and 5, the tentatively read data has "11011" in the 5th bit to the 1st bit, respectively.

[0092] The value of the magnetization information latch 32 matches the value of the first bit of the temporary readout data. Therefore, the magnetization resolution circuit 33 uses the temporary readout data as is for readout.

[0093] Figure 15 shows the data read flow from the magnetic memory of the memory system of the first embodiment. The flow in Figure 15 begins when the magnetic memory 2 receives a read command instructing it to read data. The read command is accompanied by or includes address information ADD that identifies the memory cell MC to be read.

[0094] The magnetic memory 2 first acquires preliminary read data and magnetization information through steps ST11, ST12, ST13, ST14, ST15, ST16, ST17, ST18, and ST19.

[0095] The magnetic memory 2, for example, the magnetization resolution circuit 33, sets a temporary value in the first bit of the temporarily read data in the data latch 31 according to the control of the control circuit 23 (ST11).

[0096] If the magnetic memory 2, for example, the control circuit 23, has not yet completed acquiring preliminary read data for all memory cells MC to be read (ST12_No), it shifts the magnetic wall (ST13) to move the next memory cell MC to be read to the read position.

[0097] The magnetic memory 2, for example, the magnetization resolution circuit 33, determines whether there is a magnetic domain wall between the memory cell MC at the read position and the memory cell MC that was at the read position before the previous magnetic domain wall shift. If no magnetic domain wall is detected (ST14_No), the magnetization resolution circuit 33 shifts the bits of the temporarily read data by one bit towards the higher bit side (ST15). Next, the magnetization resolution circuit 33 sets the first bit of the temporarily read data to the same value as the second bit (ST16). Step ST16 continues to step ST12.

[0098] If a magnetic domain wall is detected (ST14_Yes), the magnetization resolution circuit 33 shifts the bits of the temporarily read data one bit to the higher bit side (ST17). Then, the magnetization resolution circuit 33 sets the first bit of the temporarily read data to the inverse of the value of the second bit (ST18).

[0099] The magnetization resolution circuit 33 uses the magnetization information to update the value of the magnetization information latch 32 with a value based on the type of change in the magnetic domain wall detected in step ST14 (ST19). Step ST19 continues to step ST12.

[0100] If the acquisition of preliminary read data for all memory cells MC to be read is complete (ST12_Yes), the process proceeds to step ST21. Magnetic memory 2 undergoes magnetization resolution by ST21, ST22, and ST23.

[0101] If the value of the first bit of the temporary readout data matches the value of the magnetization information latch 32 (ST21_Yes), the magnetization resolution circuit 33 uses the temporary readout data as is as readout data (ST22). The flow in Figure 15 ends with the acquisition of the readout data.

[0102] If the value of the first bit of the temporary readout data does not match the value of the magnetization information latch 32 (ST21_No), the magnetization resolution circuit 33 generates a set of bits in which all bits of the temporary readout data have inverse values ​​as the readout data (ST23).

[0103] Figure 16 shows the data retrieval flow by the memory system of the first embodiment. The flow in Figure 16 begins when the host device 5 decides to read data from the memory system 1.

[0104] The host device 5 sends a read request command (ST31) instructing the reading of data. The read request command is accompanied by or includes an address that specifies the area from which the data to be read is to be read.

[0105] When memory system 1 receives a read request command, it sends a read command to magnetic memory 2 based on the received read request command (ST32). Sending a read command includes generating the read command. Generating a read command includes obtaining information (e.g., a physical address) that identifies the memory cell MC storing the data to be read from the area (e.g., a logical address) to which the data to be read is to be read. The read command includes or is accompanied by address information ADD that identifies the memory cell MC to which the data to be read is to be read.

[0106] When magnetic memory 2 receives a read command, it performs data read using magnetization resolution (ST33). Data read using magnetization resolution involves performing steps ST11, ST12, ST13, ST14, ST15, ST16, ST17, ST18, ST19, ST21, ST22, and ST23 of the flow shown in Figure 15. Upon completion of step ST33, the read data is obtained.

[0107] The magnetic memory 2, for example, the control circuit 23, transmits the read data to the memory controller 3 (ST34).

[0108] When the memory controller 3 receives the read data, it uses the error correction circuit 16 to perform error correction on the read data (ST35). If the error correction is successful (ST36_Yes), the memory controller 3 sends the error-corrected data to the host device 5 as the data to be read (ST37). Successful error correction includes cases where the data to be corrected does not contain any errors. When the host device 5 receives the data to be read (ST38), the flow in Figure 16 ends.

[0109] If error correction fails (ST36_No), the memory controller 3 sends a signal to the host device 5 indicating the read error status (ST39). When the host device 5 receives the status (ST40), the flow in Figure 16 ends.

[0110] 1.3. Advantages (Effects) According to the first embodiment, a magnetic memory and memory system with fewer error bits in the data read out are provided, as described below.

[0111] It is conceivable to store 1 bit of data in the unit portion. This type is hereafter referred to as the magnetization-data-compatible type. The difference between the resistance of an MTJ element when the magnetizations of the two ferromagnetic layers are parallel and the resistance of an MTJ element when the magnetizations of the two ferromagnetic layers are antiparallel is small. Therefore, it is difficult to store data in the magnetization-data-compatible type and read the data using the difference in resistance. For this reason, memories that use domain wall shifting generally store 1 bit of data between unit portions. For example, if there is no domain wall between two adjacent unit portions, the data between these unit portions is treated as "0", and if there is a domain wall between the two unit portions, the data between these unit portions is treated as "1". This type is hereafter referred to as the domain wall-data-compatible type.

[0112] As shown in Figure 17, the magnetization state of a unit portion can change unintentionally after data writing. Furthermore, data writing may fail, resulting in data different from the intended data being written. For example, suppose the data "1010" was written, or intended to be written, by setting unit portions ML_1, ML_2, ML_3, ML_4, and ML_5 to S-pole, N-pole, N-pole, S-pole, and S-pole states, respectively, but during reading, unit portion ML_N-2 is in an S-pole state. In this case, the data that should have been written, or was written, is "1010," but "0110" is read. This means that the reversal of the magnetization state of one unit portion resulted in a 2-bit error. Additionally, domain wall shifts may fail during data reading. In this case, the magnetization of many unit portions is incorrectly determined, resulting in a large number of bit errors.

[0113] According to the first embodiment, the magnetic memory 2 generates provisional read data using the similarities and differences between the magnetization state of the memory cell MC to be read and the magnetization state of a memory cell MC adjacent to the memory cell MC whose magnetization state was determined earlier. The magnetic memory 2 then continuously updates magnetization information indicating the type of magnetization change of two adjacent memory cells MCs, and generates read data using the magnetization information and provisional read data. Although the magnetization state of the first memory cell MC to be read is unknown, by using a provisional value and using the magnetization change and type of change of adjacent memory cells, it is possible to generate correct read data even if the provisional value is incorrect. Through this method, data can be read even if the magnetization-data correspondence type is used.

[0114] Depending on the magnetization and data handling type, the number of error bits caused by the reversal of the magnetization state of one unit portion is limited to 1 bit. Therefore, a magnetic memory 2 with a small number of error bits is realized.

[0115] Furthermore, the memory system and magnetic memory of the first embodiment, being of the magnetization-data-compatible type, can read data with low latency and have a large storage capacity. As is clear from Figure 17, while the domain wall-data-compatible type stores 4 bits of data using 5 unit parts ML, the magnetization-data-compatible type as in the first embodiment can store 5 bits of data. Therefore, reading a certain number of bits of data is completed faster in the case of the magnetization-data-compatible type than in the case of the domain wall-data-compatible type. The magnetization-data-compatible type can achieve more bits with a certain number of unit parts than in the case of the domain wall-data-compatible type using the same number of unit parts ML.

[0116] Furthermore, the memory system and magnetic memory of the first embodiment are of the magnetization-data-compatible type, which allows data to be appended to unwritten unit portions of a magnetic material that has already had data written to it. The domain wall-data-compatible type stores data that differs depending on the presence or absence of domain walls, so in order to determine the magnetization state of a certain unit portion for data writing, it is necessary to know the state of the adjacent unit portion. For this reason, data cannot be appended to unwritten unit portions of a magnetic material that has already had data written to it. On the other hand, according to the first embodiment, because it is of the magnetization-data-compatible type, it is not necessary to know the magnetization state of the adjacent unit portion ML, and therefore, data can be appended to the unwritten unit portion ML of a magnetic material that has already had data written to it.

[0117] 1.4. Variations The description so far is based on an example where data writing and data reading are of the FIFO type, but the first embodiment can also employ a LIFO (Last In First Out) type. In the FIFO type, the direction of the domain wall shift during data reading is the same as the direction of the domain wall shift during data writing, whereas in the LIFO type, it is opposite to the direction of the domain wall shift during data writing. In the LIFO type, a structure inverted with respect to the Z direction of the laminate LS is located between the unit portion ML_0 and the conductor 42.

[0118] If all the bits of the data targeted by the write request from the host device 5 have the same value, the set of unit parts ML on which the data is written does not contain a magnetic domain wall. In such a case, an error bit can be created by deliberately inverting, for example, the value of one bit in the bit sequence written to the memory cell. The creation of the error bit may be performed by the memory controller 3 or by the magnetic memory 2.

[0119] 2. Second Embodiment The second embodiment differs from the first embodiment in terms of the components that perform magnetization resolution.

[0120] Figure 18 shows an example of a functional block of the memory controller of a second embodiment of the memory system. As shown in Figure 18, the memory controller 3b further includes a magnetization resolution unit 18 in addition to the functional blocks included in the memory controller 3 of the first embodiment. The magnetization resolution unit 18 is a functional block that uses magnetization information to generate read data from temporary read data. The magnetization resolution unit 18 may be implemented as one or more dedicated semiconductor chips or circuits, or as a circuit formed on a semiconductor substrate. Alternatively, the magnetization resolution unit 18 may be implemented as a sub-part implemented by a program stored in the ROM 12 and loaded onto the RAM 13, which is executed by the CPU 14.

[0121] The magnetization resolution unit 18 performs a part of the function of the magnetization resolution circuit 33 of the memory system in the first embodiment. Specifically, in response to the memory controller 3b sending a data read command, the magnetization resolution unit 18 receives temporary read data and magnetization information from the magnetic memory 2b. Based on the received temporary read data and magnetization information, the magnetization resolution unit 18 generates read data.

[0122] The magnetic memory 2b includes the same functional blocks as the magnetic memory 2 of the first embodiment. The magnetization resolution circuit 33b of the magnetic memory 2b generates provisional read data based on domain wall presence information and updates the value in the magnetization information latch 32, just as in the first embodiment. On the other hand, the magnetization resolution circuit 33b does not perform magnetization resolution.

[0123] Figure 19 shows the data read flow using the magnetic memory of the memory system in the second embodiment. The flow in Figure 19 starts when the magnetic memory 2b receives a read command. The flow in Figure 19 differs from the flow in Figure 15 of the first embodiment in that the flow ends when the acquisition of preliminary read data for all memory cells MC to be read is complete (ST12_Yes).

[0124] Figure 20 shows the data retrieval flow by the memory system in the second embodiment. The flow in Figure 20 begins when the host device 5 decides to read data from the memory system 1b.

[0125] As shown in Figure 20, step ST32 continues to step ST41. In step ST41, the magnetic memory 2b acquires the temporary read data and magnetization information. The acquisition of the temporary read data and magnetization information involves performing steps ST11, ST12, ST13, ST14, ST15, ST16, ST17, ST18, and ST19 of the flow shown in Figure 19.

[0126] The magnetic memory 2b transmits the temporary read data and the magnetization information in the magnetization information latch 32b to the memory controller 3b (ST42).

[0127] Upon receiving the provisional read data and magnetization information, the memory controller 3b performs magnetization resolution using the magnetization resolution unit 18 (ST43). Magnetization resolution includes the execution of steps ST21, ST22, and ST23 of the flow shown in Figure 15 of the first embodiment. Read data is obtained through magnetization resolution. Step ST43 continues to step ST35. The subsequent operations, including step ST35, are the same as the operations in the first embodiment (Figure 16).

[0128] According to the second embodiment, the magnetic memory 2b generates temporary read data and magnetization information, as in the first embodiment, and the memory controller 3b performs magnetization resolution to generate read data. Therefore, the same advantages as the first embodiment can be obtained.

[0129] 3. Third Embodiment The third embodiment differs from the first embodiment in terms of the method for storing magnetization information.

[0130] The memory controller 3c of the third embodiment has the same functional blocks as the memory controller 3 of the first embodiment. On the other hand, the error correction circuit 16c of the memory controller 3c is configured to perform the operations described later.

[0131] Figure 21 shows an example of the functional blocks of the magnetic memory in the memory system of the third embodiment. As shown in Figure 21, the magnetic memory 2c includes a domain wall presence information latch 37 in addition to the functional blocks included in the magnetic memory 2 of the first embodiment. The domain wall presence information latch 37 has the function of a shift register. The magnetization information latch 32c also has the function of a shift register.

[0132] Figure 22, similar to Figures 9 to 14 of the first embodiment, shows the state of several elements during operation of the memory system of the third embodiment. In Figure 22, the second, third, fourth, and bottom rows from the top show domain wall presence information, provisional readout data, domain wall presence information latch value, and magnetization information latch value, respectively.

[0133] The domain wall presence information latch 37 operates in the same way as a shift register to store domain wall presence information. That is, each time the domain wall presence information latch 37 receives new domain wall presence information, it shifts the bits of the domain wall presence information already stored by one bit toward the higher bits, and sets the last received domain wall presence information in the first bit.

[0134] Unlike the first embodiment, the magnetization information latch 32c operates in the same way as a shift register to store magnetization information. That is, each time the magnetization information latch 32c receives new magnetization information, it shifts the bits of the already stored magnetization information one bit to the higher bit side and sets the last received magnetization information in the first bit.

[0135] Magnetization resolution is performed by comparing the value of the first bit of the provisionally read data with the value of the bit of the magnetization information latch 32c that is equivalent in value to the least significant bit of all the bits of the domain wall existence information latch 37 that have "1" data. In other words, if the value of the first bit of the provisionally read data matches the value of the bit of the magnetization information latch 32c that is equivalent in value to the least significant bit of all the bits of the domain wall existence information latch 37 that have "1" data, the magnetization resolution circuit 33c uses the provisionally read data as is. Hereinafter, the least significant bit of all the bits of the domain wall existence information latch 37 that have "1" data may be referred to as the least significant bit of "1" data.

[0136] On the other hand, if the value of the first bit of the provisional readout data does not match the value of the bit in the magnetization information latch 32c that is equivalent to the least significant bit of the "1" data in the domain wall existence information latch 37, the magnetization resolution circuit 33c uses a set of values ​​that are the opposite of the values ​​of all the bits of the provisional readout data as the readout data.

[0137] 3.2. Operation Figures 23 and 24 show the data retrieval flow by magnetic memory of the memory system of the third embodiment. As shown in Figures 23 and 24, after step ST16, the magnetization resolution circuit 33c shifts the bits of the domain wall presence information latch 37 by one bit toward the higher bit (ST51). The magnetization resolution circuit 33c sets the first bit of the domain wall presence information latch 37 to "0" (ST52). The magnetization resolution circuit 33c shifts the bits of the magnetization information latch 32c by one bit toward the higher bit (ST53). The magnetization resolution circuit 33c sets the first bit of the magnetization information latch 32c to "0" (ST54). Step ST54 continues to step ST12.

[0138] After step ST18, the magnetization resolution circuit 33c shifts the bits of the domain wall presence information latch 37 by one bit towards the higher bit side (ST55). The magnetization resolution circuit 33c sets the first bit of the domain wall presence information latch to "1" (ST56). The magnetization resolution circuit 33c shifts the bits of the magnetization information latch 32c by one bit towards the higher bit side (ST57). The magnetization resolution circuit 33c sets the value of the magnetization information to the first bit of the magnetization information latch 32c (ST58). Step ST58 continues to step ST12.

[0139] If the acquisition of preliminary read data for all memory cells MC to be read is complete (ST12_Yes), the process proceeds to step ST59. Magnetic memory 2 undergoes magnetization resolution by ST59, ST22, and ST23.

[0140] If the value of the first bit of the provisionally read data matches the value of the bit in the magnetization information latch 32c that is equivalent to the least significant bit of the "1" data in the domain wall existence information latch 37 (ST59_Yes), the process proceeds to step ST22. If the value of the first bit of the provisionally read data does not match the value of the bit in the magnetization information latch 32c that is equivalent to the least significant bit of the "1" data in the domain wall existence information latch 37 (ST59_No), the process proceeds to step ST23.

[0141] The pairs of steps ST15 and ST16, ST51 and ST52, and ST53 and ST54 can be performed in any order. The pairs of steps ST17 and ST18, ST55 and ST56, and ST57 and ST58 can be performed in any order.

[0142] Figures 25 and 26 show the data retrieval flow by the memory system of the third embodiment. The flow in Figures 25 and 26 begins when the host device 5 decides to read data from the memory system 1c.

[0143] As shown in Figures 25 and 26, step ST32 continues to step ST61. In step ST61, the magnetic memory 2c performs data reading using magnetization resolution. Data reading using magnetization resolution involves performing steps ST11, ST12, ST13, ST14, ST15, ST16, ST17, ST18, ST22, ST23, ST51, ST52, ST53, ST54, ST55, ST56, ST57, ST58, and ST59 of the flow shown in Figures 23 and 24. Upon completion of step ST61, the read data is obtained. Step ST61 continues to step ST34.

[0144] If error correction fails (ST36_No), the memory controller 3c sends a command to the magnetic memory 2c instructing it to output the bit sequence of domain wall presence information in the domain wall presence information latch 37 and the bit sequence of magnetization information in the magnetization information latch 32c (ST62).

[0145] When the magnetic memory 2c receives a command, it transmits information about the presence of a magnetic domain wall and magnetization information to the memory controller 3c (ST63).

[0146] The memory controller 3c, for example, the error correction circuit 16c, generates one or more candidate read data (ST64) in which errors based on false detection of magnetic domain walls are presumed to have been corrected by inverting the values ​​of several bits in the read data that were determined using magnetic domain wall presence information and magnetization information. Details of the generation of candidate read data in which errors based on false detection of magnetic domain walls are presumed to have been corrected will be described later with reference to Figure 27.

[0147] The memory controller 3c uses the error correction circuit 16c to perform error correction on candidate read data that is presumed to have had errors due to false domain wall detection corrected (ST65). Correction of errors due to false domain wall detection may result in successful error correction in step ST65 for read data that would otherwise fail in step ST36. If error correction is successful (ST66_Yes), the process proceeds to step ST37. If error correction fails (ST66_No), the process proceeds to step ST39.

[0148] Figure 27 shows an example of data generated during operation in the memory system of the third embodiment. Specifically, Figure 27 shows an example of data generated during error correction caused by false magnetic domain wall detection by the memory system of the third embodiment.

[0149] Let's consider an example where the data written to the memory cell MC to be read, and consequently the data to be read, have "11000010" in order from the first bit read (most significant bit). Let's assume that a domain wall is mistakenly detected between the memory cell MC storing the 4th bit and the memory cell MC storing the 5th bit, even though no domain wall exists between them. As a result, the provisional read data obtained has "11001101" in order from the most significant bit. The domain wall presence information has "0101011" in the 7th bit to the 1st bit, respectively. The magnetization information latch has "0001010" in the 7th bit to the 1st bit, respectively.

[0150] Magnetization resolution generates the read data "00110010". The read data differs from the expected (or correct) read data, and all bits higher than the misdetected domain wall differ from the bit values ​​of the correct read data. Based on this phenomenon, the error correction circuit 16c performs the following processing to generate several candidate read data that are estimated to be obtained if there were no domain wall misdetection.

[0151] When a domain wall exists, the magnetization states of the memory cells MC on both sides of the domain wall are different. Therefore, the magnetization information latch should have opposite values ​​for the memory cells MC on both sides of the domain wall. Based on this, for example, the error correction circuit 16c refers to the same bit in the magnetization information latch 32c that has the "1" data in the domain wall presence information latch 37. The values ​​of the 6th bit and the 4th bit are inverted. However, the values ​​of the 4th bit and the 2nd bit are the same. Since magnetization alternates between two states, it should not occur that the magnetization changes in the same direction in both the adjacent first and second domain walls. Based on this, for example, the error correction circuit 16c infers that the domain wall was incorrectly detected at the boundary on the higher bit side of each of the two bits that indicate the presence of a domain wall in the domain wall presence information latch 37 and hold the same value in the magnetization information latch 32c, and at any of the boundaries between these boundaries. In the example in Figure 27, it is estimated that a magnetic domain wall was falsely detected at one of the following boundaries in the provisional read data: the boundary between the 5th and 4th bits, the boundary between the 4th and 3rd bits, or the boundary between the 3rd and 2nd bits. Based on this estimation, for each of the boundaries, multiple read data sets are generated as candidates, in which the values ​​of all bits from the most significant bit to the boundary are inverted.

[0152] According to the third embodiment, the magnetic memory 2c generates temporary read data and magnetization information, as in the first embodiment, and performs magnetization resolution to generate read data. Therefore, the same advantages as in the first embodiment can be obtained.

[0153] Furthermore, according to the third embodiment, the magnetic memory 2c stores domain wall presence information and magnetization information throughout the entire memory cell MC to be read. The memory controller 3c, if it fails to correct errors in the initially received read data in response to a read command, receives the bit sequence of domain wall presence information and the bit sequence of magnetization information from the magnetic memory 2c and attempts to correct the errors in the initially received read data based on these. Thus, the memory system 1c can achieve fewer read errors by having another error correction mechanism in addition to the error correction using error correction codes.

[0154] 4. Fourth Embodiment The fourth embodiment differs from the third embodiment in terms of the components that perform magnetization resolution.

[0155] The memory controller 3d of the memory system 1d in the fourth embodiment has the same configuration as the memory controller 3b in the second embodiment. However, the memory controller 3d is configured to perform the operations described later.

[0156] The magnetic memory 2d of the memory system 1d in the fourth embodiment includes the same functional blocks as the magnetic memory 2c in the third embodiment. The magnetization resolution circuit 33d of the magnetic memory 2d generates provisional read data based on domain wall presence information, just as in the first embodiment, and stores domain wall presence information in the domain wall presence information latch 37d and magnetization information in the magnetization information latch 32d, just as in the third embodiment. On the other hand, the magnetization resolution circuit 33d does not perform magnetization resolution.

[0157] Figure 28 shows the data readout flow using the magnetic memory of the memory system in the fourth embodiment. The flow in Figure 28 starts when the magnetic memory 2d receives a read command. The flow in Figure 28 differs from the flow in Figure 23 of the third embodiment in that the flow ends when the acquisition of preliminary read data for all memory cells MC to be read is complete (ST12_Yes).

[0158] Figure 29 shows the data retrieval flow by the memory system in the fourth embodiment. The flow in Figure 29 begins when the host device 5 decides to read data from the memory system 1d.

[0159] As shown in Figure 29, step ST32 continues to step ST71. In step ST71, the magnetic memory 2d obtains the temporary read data, the bit sequence of domain wall presence information, and the bit sequence of magnetization information. Obtaining the temporary read data, the bit sequence of domain wall presence information, and the bit sequence of magnetization information involves performing steps ST11, ST12, ST13, ST14, ST15, ST16, ST17, ST18, ST51, ST52, ST53, ST54, ST55, ST56, ST57, and ST58 of the flow shown in Figure 28.

[0160] The magnetic memory 2d transmits to the memory controller 3d the temporary read data, the bit sequence of domain wall presence information in the domain wall presence information latch 37, and the bit sequence of domain wall presence information in the magnetization information latch 32d (ST72).

[0161] Upon receiving the provisional read data, the bit sequence of domain wall presence information, and the bit sequence of magnetization information, the memory controller 3d performs magnetization resolution using the magnetization resolution unit 18d (ST73). Magnetization resolution includes the execution of steps ST59, ST22, and ST23 of the flow shown in Figures 23 and 24 of the third embodiment. Magnetization resolution yields the read data. Step ST73 continues to step ST35. The subsequent operations, including step ST35, are the same as those in the third embodiment (Figure 26).

[0162] According to the fourth embodiment, the magnetic memory 2d generates temporary read data and magnetization information, as in the third embodiment, and the memory controller 3d performs magnetization resolution to generate read data. Therefore, the same advantages as the third embodiment can be obtained.

[0163] Furthermore, according to the fourth embodiment, as in the third embodiment, domain wall presence information and magnetization information are accumulated throughout the entire memory cell MC to be read. If error correction of the first read data received in response to the read command fails, an attempt is made to correct the error in the first read data based on the bit sequence of domain wall presence information and the bit sequence of magnetization information. Thus, the same advantages as in the third embodiment can be obtained.

[0164] In step ST72, only the provisional read data and magnetization information are transmitted, and immediately before step ST64, the memory controller 3d may obtain the bit sequence of domain wall existence information in the domain wall existence information latch 37 from the magnetic memory 2d by sending a command.

[0165] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0166] 100... Information processing systems, 1…Memory system, 5…Host device, 2…Magnetic memory, 3…Memory controller, 11…Host interface, 12...ROM, 13…RAM, 14…CPU, 15…Memory interface, 16…Error correction circuit, 21…Memory cell array, STR...string, MC…Memory cell SL... Source line, BL... bit line, EL...field line, 22…Input / Output Circuits, 23...control circuit, 24... Row selection circuit, 25... Column selection circuit, 26... Programming circuit, 27...Read circuit, 29... Shift control circuit, 31...Data latch, 32…Magnetic information latch, 33...Magnetization solution circuit, UT...magnetic material, LS...Laminated structure, 41... Conductors, 42... Conductor, 43... Conductor, ML... Unit part, 271...information retention circuit, 272...information retention circuit, 273...Sense amp, 18...Magnetization solution section, 37... Magnetic field wall presence information latch

Claims

1. A magnetic material that extends in a first direction and includes a plurality of parts aligned in the first direction, A first circuit that outputs first information indicating the presence or absence of a magnetic domain wall between each pair of adjacent parts, and second information based on the combination of the magnetization states of each pair, A first memory circuit that stores a plurality of first bits corresponding to each of the plurality of parts, wherein the most significant bit of the plurality of first bits has a value independent of one of the corresponding magnetization states among the plurality of parts, and each of the plurality of first bits has a value based on the first information, A second memory circuit that stores the second information in the second bit, The second circuit outputs the plurality of first bits from the first memory circuit if the value of the least significant bit of the plurality of first bits matches the value of the second information stored in the second memory circuit, and outputs a plurality of third bits from the first memory circuit, each of which has a value opposite to the value of the plurality of first bits. A magnetic memory equipped with this feature.

2. Each of the plurality of first bits has the same value as the adjacent bit on the most significant side of the plurality of first bits when it is determined that the magnetization state is the same between a corresponding part of the plurality of parts and an adjacent part aligned with the corresponding part on the first direction side, and has a different value from the adjacent bit when it is determined that the magnetization state is different between the corresponding part and the adjacent part. The magnetic memory according to claim 1.

3. The first memory circuit, each time it receives the first information, moves the value of each of the plurality of first bits to the adjacent bit and stores the value based on the received first information in the least significant bit of the plurality of first bits. The magnetic memory according to claim 2.

4. The second information has a first value when the first portion of the plurality of parts has a first magnetization state and the first portion has a second magnetization state before the magnetic domain wall in the plurality of parts moves in the first direction, and has a second value when the first portion has a second magnetization state and the first portion has a first magnetization state before the movement of the magnetic domain wall. The magnetic memory according to claim 1.

5. The first magnetization state is a magnetization state that faces the second direction, The aforementioned second magnetization state is a magnetization state that faces the third direction, The aforementioned third direction is different from the aforementioned second direction. The magnetic memory according to claim 4.

6. Each time a magnetic domain wall in the plurality of parts moves in the first direction, the first circuit successively outputs first information and second information based on the magnetization state of the first part of the plurality of parts and the magnetization state of the first part before the movement of the magnetic domain wall. The magnetic memory according to claim 1.

7. The second memory circuit updates the value of the second bit with the received second information each time it receives the second information. The magnetic memory according to claim 1.

8. The magnetic memory further comprises a third memory circuit that stores a plurality of fourth bits, The third memory circuit, each time it receives the first information, moves the value of each of the plurality of fourth bits to the adjacent bit, and stores the value based on the received first information in the least significant bit of the plurality of fourth bits. The first information has a third value when it is determined that a magnetic domain wall exists. The second memory circuit stores a plurality of fifth bits, The second memory circuit, each time it receives the second information, moves the value of each of the plurality of fifth bits to the adjacent bit, and stores the value based on the received second information in the least significant bit of the plurality of fifth bits. The second bit is the same bit as the least significant bit among the plurality of fourth bits that have the third value. The magnetic memory according to claim 1.

9. A magnetic material that extends in a first direction and includes a plurality of parts aligned in the first direction, A first circuit that outputs first information indicating the presence or absence of a magnetic domain wall between each pair of adjacent parts, and second information based on the combination of the magnetization states of each pair, A first memory circuit that stores a plurality of first bits corresponding to each of the plurality of parts, wherein the most significant bit of the plurality of first bits has a value independent of one of the corresponding magnetization states among the plurality of parts, and each of the plurality of first bits has a value based on the first information, A second memory circuit that stores the second information in the second bit, The second circuit outputs the plurality of first bits from the first memory circuit if the value of the least significant bit of the plurality of first bits matches the value of the second information stored in the second memory circuit, and outputs a plurality of third bits from the first memory circuit, each of which has a value opposite to the value of the plurality of first bits. A memory system equipped with the following features.

10. Each of the plurality of first bits has the same value as the adjacent bit on the most significant side of the plurality of first bits when it is determined that the magnetization state is the same between a corresponding part of the plurality of parts and an adjacent part aligned with the corresponding part on the first direction side, and has a different value from the adjacent bit when it is determined that the magnetization state is different between the corresponding part and the adjacent part. The memory system according to claim 9.

11. The first memory circuit, each time it receives the first information, moves the value of each of the plurality of first bits to the adjacent bit and stores the value based on the received first information in the least significant bit of the plurality of first bits. The memory system according to claim 10.

12. The second information has a first value when the first portion of the plurality of parts has a first magnetization state and the first portion has a second magnetization state before the magnetic domain wall in the plurality of parts moves in the first direction, and has a second value when the first portion has a second magnetization state and the first portion has a first magnetization state before the movement of the magnetic domain wall. The memory system according to claim 9.

13. The first magnetization state is a magnetization state that faces the second direction, The aforementioned second magnetization state is a magnetization state that faces the third direction, The aforementioned third direction is different from the aforementioned second direction. The memory system according to claim 12.

14. Each time a magnetic domain wall in the plurality of parts moves in the first direction, the first circuit successively outputs first information and second information based on the magnetization state of the first part of the plurality of parts and the magnetization state of the first part before the movement of the magnetic domain wall. The memory system according to claim 9.

15. The second memory circuit updates the value of the second bit with the received second information each time it receives the second information. The memory system according to claim 9.

16. The memory system further comprises a third memory circuit that stores a plurality of fourth bits, The third memory circuit, each time it receives the first information, moves the value of each of the plurality of fourth bits to the adjacent bit, and stores the value based on the received first information in the least significant bit of the plurality of fourth bits. The first information has a third value when it is determined that a magnetic domain wall exists. The second memory circuit stores a plurality of fifth bits, The second memory circuit, each time it receives the second information, moves the value of each of the plurality of fifth bits to the adjacent bit, and stores the value based on the received second information in the least significant bit of the plurality of fifth bits. The second bit is the same bit as the least significant bit among the plurality of fourth bits that have the third value. The memory system according to claim 9.

17. The memory system comprises a magnetic memory and a memory controller. The magnetic memory comprises the magnetic material, the first circuit, the first memory circuit, and the second memory circuit. The memory controller includes the second circuit, The memory controller receives read data containing the plurality of first bits or the plurality of third bits, and if it fails to correct errors in the read data, it causes the magnetic memory to output the plurality of fourth bits and the plurality of fifth bits. The memory system according to claim 16.

18. The memory system comprises a magnetic memory and a memory controller. The magnetic memory comprises the magnetic material, the first circuit, the first memory circuit, and the second memory circuit. The memory controller sends a first command to the magnetic memory, When the magnetic memory receives the first command, it outputs the plurality of first bits, the plurality of fourth bits, and the plurality of fifth bits. The memory system according to claim 16.

19. The memory system comprises a magnetic memory and a memory controller. The magnetic memory comprises the magnetic material, the first circuit, the first memory circuit, the second memory circuit, and the second circuit. The memory system according to claim 9.

20. The memory system comprises a magnetic memory and a memory controller. The magnetic memory comprises the magnetic material, the first circuit, the first memory circuit, and the second memory circuit. The memory controller includes the second circuit, The memory system according to claim 9.

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