Memory device and its operating method

Abstract

To provide an electronic device.SOLUTION: A memory device according to the present technology includes: a memory block including a plurality of memory cells respectively connected to a plurality of word lines; a voltage generation unit for generating program-related voltages including a program voltage, a first pass voltage, a second pass voltage, a third pass voltage, a hold voltage, and a verify voltage to be applied to the plurality of word lines; an address decoder for transmitting the program-related voltages to the plurality of word lines; an operation control unit for controlling the voltage generation unit and the address decoder so as to apply the program voltage to the word line selected from the plurality of word lines, apply the second pass voltage to the word line adjacent to the selected word line, apply ground voltage to the selected word line in a first period, after applying the first pass voltage to the remaining word lines excluding the selected word line and the adjacent word line among the plurality word lines, and apply the first pass voltage to the adjacent word line.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to a memory device and an operating method thereof.

Background Art

[0002] A semiconductor memory device is a storage device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Memory devices are broadly classified into volatile memory devices and nonvolatile memory devices.

[0003] A volatile memory device is a memory device in which stored data is lost when the power supply is cut off. Examples of volatile memory devices include SRAM (Static RAM), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM). A nonvolatile memory device is a memory device that retains stored data even when the power supply is cut off. Examples of nonvolatile memory devices include ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), flash memory, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (registered trademark) (Ferroelectric RAM). Flash memory is broadly classified into NOR type and NAND type.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a memory device and a method of operating the same that can reduce program time. [Means for solving the problem]

[0005] A memory device according to an embodiment of the present invention includes a memory block containing a plurality of memory cells connected to a plurality of word lines, a voltage generation unit that generates program-related voltages including a program voltage, a first pass voltage, a second pass voltage, a third pass voltage, a hold voltage, and a verification voltage to be applied to the plurality of word lines, an address decoder that transmits the program-related voltages to the plurality of word lines, and an operation control unit that controls the voltage generation unit and the address decoder to apply the program voltage to a selected word line from the plurality of word lines, apply the second pass voltage to the selected word line and adjacent word lines, apply the first pass voltage to the remaining word lines from the plurality of word lines excluding the selected word line and the adjacent word lines, apply a ground voltage to the selected word line for a first interval, and apply the first pass voltage to the adjacent word lines.

[0006] A method for operating a memory device including a plurality of memory cells connected to a plurality of word lines according to one embodiment of the present invention includes the steps of: applying a program voltage to a selected word line from among the plurality of word lines; applying a first pass voltage to the remaining word lines from among the plurality of word lines excluding the selected word line and the word lines adjacent to the selected word line; and applying a ground voltage to the selected word line; and applying the first pass voltage to the adjacent word lines.

[0007] A memory device according to an embodiment of the present invention includes: a plurality of memory cells each connected to a plurality of word lines; a peripheral circuit that performs a program operation including a program voltage application operation which applies a program voltage to a selected word line connected to a selected memory cell from the plurality of memory cells, and a verification operation which applies a verification voltage to the selected word line to verify whether the threshold voltage of the selected memory cell has reached a threshold voltage corresponding to a target program state; and an operation control unit that controls the peripheral circuit to apply a voltage lower than the verification voltage to the selected word line for a time determined according to the magnitude of the verification voltage during the verification operation, and then apply the verification voltage to the selected word line.

[0008] An operation method for a memory device that performs a program operation to store data in a plurality of memory cells connected to a plurality of word lines, according to one embodiment of the present invention, includes a program voltage application step of applying a program voltage to a selected word line connected to a selected memory cell from among the plurality of memory cells; a discharge step of applying a hold voltage to the plurality of word lines; a step of applying a ground voltage to the selected word line for an application time determined according to the magnitude of the verification voltage applied to the selected word line; and a verification step of applying the verification voltage to the selected word line. [Effects of the Invention]

[0009] This technology provides a memory device and a method of operating the same that can reduce program time. [Brief explanation of the drawing]

[0010] [Figure 1] This is a diagram illustrating a memory system including a memory device according to one embodiment of the present invention. [Figure 2] This diagram illustrates the structure of the memory device shown in Figure 1. [Figure 3]This diagram illustrates the structure of one of the memory blocks BLK1 to BKLz shown in Figure 2. [Figure 4] This diagram illustrates the distribution of threshold voltages in memory cells due to the programmed operation of a memory device. [Figure 5] This is a diagram illustrating the program operation of a memory device. [Figure 6] This diagram illustrates the program voltage application stage in the program operation of a memory device. [Figure 7] This diagram illustrates the change in the magnitude of the word line voltage due to the program operation of the memory device. [Figure 8] This figure illustrates the change in the magnitude of the word line voltage during program operation of a memory device according to one embodiment of the present invention. [Figure 9] This figure illustrates another example of the change in the magnitude of the word line voltage during program operation of a memory device according to one embodiment of the present invention. [Figure 10] This figure illustrates yet another example of the change in the magnitude of the word line voltage during program operation of a memory device according to one embodiment of the present invention. [Figure 11] This is a flowchart illustrating the program operation of a memory device according to one embodiment of the present invention. [Figure 12] This diagram illustrates the memory controller shown in Figure 1. [Figure 13] Block diagram showing a memory card system to which a memory system according to one embodiment of the present invention is applied. [Figure 14] This is a block diagram showing an SSD (Solid State Drive) system to which a memory system according to one embodiment of the present invention is applied. [Figure 15] This is a block diagram showing a user system to which a memory system according to one embodiment of the present invention is applied. [Modes for carrying out the invention]

[0011] The specific structural or functional descriptions of embodiments of the concept of the present invention disclosed herein or in the application are illustrative only for the purpose of illustrating embodiments of the concept of the present invention, and embodiments of the concept of the present invention may be carried out in various forms and should not be construed as being limited to embodiments described herein or in the application.

[0012] Figure 1 is a diagram illustrating a memory system including a memory device according to one embodiment of the present invention.

[0013] Referring to Figure 1, the memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may also be a device that stores data in response to the control of a host 300 such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0014] Memory system 50 may be manufactured from any one of various types of storage devices according to a host interface which is a communication method with host 300. For example, memory system 50 may consist of any one of various types of storage devices such as SSD, MMC, eMMC, RS-MMC, multimedia card in the form of micro-MMC, secure digital card in the form of SD, mini-SD, micro-SD, USB (universal serial bus) storage device, UFS (universal flash storage) device, storage device in the form of PCMCIA (personal computer memory card international association) card, storage device in the form of PCI (peripheral component interconnection) card, storage device in the form of PCI-E (PCI express) card, CF (compact flash) card, smart media card, memory stick, etc.

[0015] Memory system 50 may be manufactured in any one of various types of package forms. For example, memory system 50 may be manufactured in any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package).

[0016] Memory device 100 can store data. Memory device 100 operates in response to the control of memory controller 200. Memory device 100 may include a memory cell array (not shown) including a plurality of memory cells for storing data.

[0017] Memory cells may be composed of single level cells (SLCs) that store 1-bit data each, multi level cells (MLCs) that store 2-bit data, triple level cells (TLCs) that store 3-bit data, or quad level cells (QLCs) that store 4-bit data.

[0018] The memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. One memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading out the data stored in the memory device 100. A memory block may be a unit for erasing data.

[0019] In the embodiment, the memory device 100 may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM®), spin transfer torque random access memory (STT-RAM), etc. For the sake of explanation, this specification will describe the case where the memory device 100 is a NAND flash memory.

[0020] The memory device 100 is configured to receive commands and addresses from the memory controller 200 and access the memory cell array selected by the address. The memory device 100 can perform operations instructed by the command on the memory cell array selected by the address. For example, the memory device 100 can perform write operations (program operations), read operations, and erase operations. During a write operation, the memory device 100 programs data into the memory cell array selected by the address. During a read operation, the memory device 100 reads data from the memory cell array selected by the address. During an erase operation, the memory device 100 erases the data stored in the memory cell array selected by the address.

[0021] In this embodiment, the memory device 100 may also include an operation control unit 150.

[0022] The operation control unit 150 can control program operations on the memory cell. A program operation may be an operation to save data to the memory cell. Specifically, a program operation may be an operation to raise the threshold voltage of the memory cell according to the data to be saved in the memory cell. When a program operation is performed, the memory cell may have a threshold voltage corresponding to one of several program states. The number of program states may be determined according to the number of data bits that one memory cell saves. For example, if one memory cell is programmed as a TLC (Triple Level Cell; TLC) that saves 3 bits of data, the number of program states may mean the erase state and the first to seventh program states. The threshold voltage that the memory cell has after a program operation is performed may be determined according to the data saved in the memory cell. Each memory cell may have one of several program states as its target program state according to the data it saves.

[0023] In the embodiment, the program operation may include a program voltage application operation and a verification operation. The program voltage application operation may be an operation to increase the threshold voltage of the memory cell using the program voltage. The verification operation may be an operation to verify whether the threshold voltage of the memory cell has reached the threshold voltage corresponding to the target program state using the verification voltage.

[0024] In this embodiment, the operation control unit 150 can control the voltage applied to each word line to which a memory cell is connected during program operation.

[0025] The memory controller 200 can control the overall operation of the memory system 50.

[0026] When power is applied to the memory system 50, the memory controller 200 can execute firmware (FW). If the memory device 100 is a flash memory device, the firmware (FW) may include a Host Interface Layer (HIL) that controls communication with the host 300, a Flash Translation Layer (FTL) that controls communication between the host 300 and the memory device 100, and a Flash Interface Layer (FLA) that controls communication with the memory device 100.

[0027] In this embodiment, the memory controller 200 receives data and a logical block address (LBA) from the host 300 and can convert the logical block address into a physical block address (PBA) that indicates the address of the memory cell where the data contained in the memory device 100 is stored. In this specification, the terms "logical block address (LBA)" and "logical address" or "logical address" may be used interchangeably. Similarly, the terms "physical block address (PBA)" and "physical address" or "physical address" may be used interchangeably.

[0028] The memory controller 200 can control the memory device 100 to perform write, read, or erase operations in response to a request from the host 300. During a write operation, the memory controller 200 can provide the memory device 100 with a write command, a physical block address, and data. During a read operation, the memory controller 200 can provide the memory device 100 with a read command and a physical block address. During an erase operation, the memory controller 200 can provide the memory device 100 with an erase command and a physical block address.

[0029] In this embodiment, the memory controller 200 can autonomously generate commands, addresses, and data and transmit them to the memory device 100 regardless of requests from the host 300. For example, the memory controller 200 can provide the memory device 100 with commands, addresses, and data for executing read and write operations associated with wear leveling, read reclaim, and garbage collection.

[0030] In this embodiment, the memory controller 200 can control at least two or more memory devices 100. In this case, the memory controller 200 can control the memory devices 100 in an interleaved manner in order to improve operational performance. The interleaved manner may be a method of controlling at least two or more memory devices 100 so that their operations are superimposed.

[0031] The host 300 can communicate with the memory system 50 using at least one of various communication methods, such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), and LRDIMM (Load Reduced DIMM).

[0032] Figure 2 is a diagram illustrating the structure of the memory device shown in Figure 1.

[0033] Referring to Figure 2, the memory device 100 may include a memory cell array 110, peripheral circuits 120, and control logic 130.

[0034] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 121 via row line RL. The plurality of memory blocks BLK1 to BLKz are connected to the page buffer group 123 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In this embodiment, the plurality of memory cells are non-volatile memory cells. The plurality of memory cells are defined as a single page when connected to the same word line. That is, the memory cell array 110 consists of a plurality of pages. According to this embodiment of the present invention, each of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 may include a plurality of dummy cells. At least one dummy cell may be connected in series between the drain selection transistor and the memory cell, and between the source selection transistor and the memory cell.

[0035] The memory cells of the memory device 100 may each consist of a single-level cell that stores 1 bit of data, a multi-level cell that stores 2 bits of data, a triple-level cell that stores 3 bits of data, or a quad-level cell that stores 4 bits of data.

[0036] The peripheral circuit 120 drives the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform program, read, and erase operations in accordance with the control logic 130. In another example, the peripheral circuit 120 may apply various operating voltages to the row line RL and bit lines BL1 to BLm, or discharge the applied voltages, in accordance with the control logic 130.

[0037] The peripheral circuit 120 may include an address decoder 121, a voltage generation unit 122, a page buffer group 123, a data input / output circuit 124, and a sensing circuit 125.

[0038] The address decoder 121 is connected to the memory cell array 110 via a row line RL. The row line RL may include a drain selection line, a word line, a source selection line, and a common source line. According to embodiments of the present invention, the word line may include a normal word line and a dummy word line. According to embodiments of the present invention, the row line RL may further include a pipe selection line.

[0039] The address decoder 121 is configured to operate in response to control from the control logic 130. The address decoder 121 receives the address ADDR from the control logic 130.

[0040] The address decoder 121 is configured to decode the block address from the received address ADDR. The address decoder 121 selects at least one memory block from memory blocks BLK1 to BLKz according to the decoded block address. The address decoder 121 is configured to decode the row address RADD from the received address ADDR. The address decoder 121 can select at least one word line of the selected memory block by applying a voltage provided by the voltage generator 122 to at least one word line WL according to the decoded row address RADD.

[0041] During program operation, the address decoder 121 applies a program voltage to the selected word line and a path voltage lower than the program voltage to the unselected word line. During program verification operation, the address decoder 121 applies a verification voltage to the selected word line and a verification path voltage higher than the verification voltage to the unselected word line.

[0042] During a read operation, the address decoder 121 applies a read voltage to the selected word line and a read path voltage at a higher level than the read voltage to the unselected word lines.

[0043] The erase operation of the memory device 100 is performed on a memory block basis. The address ADDR input to the memory device 100 during the erase operation includes the block address. The address decoder 121 decodes the block address and can select one memory block according to the decoded block address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0044] According to embodiments of the present invention, the address decoder 121 may be configured to decode the column address from the transmitted address ADDR. The decoded column address may be transmitted to the page buffer group 123. For example, the address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0045] The voltage generation unit 122 is configured to generate multiple operating voltages Vop using the external power supply voltage supplied to the memory device 100. The voltage generation unit 122 operates in response to the control logic 130.

[0046] In one embodiment, the voltage generation unit 122 can regulate an external power supply voltage to generate an internal power supply voltage. The internal power supply voltage generated by the voltage generation unit 122 is used as the operating voltage of the memory device 100.

[0047] As an example, the voltage generation unit 122 can generate various operating voltages Vop used for programming, reading, and erasing operations in response to the operation signal OPSIG. The voltage generation unit 122 can generate multiple operating voltages Vop using an external power supply voltage or an internal power supply voltage. The voltage generation unit 122 may be configured to generate various voltages required by the memory device 100. For example, the voltage generation unit 122 can generate multiple erase voltages, multiple program voltages, multiple path voltages, multiple selective read voltages, and multiple non-selective read voltages.

[0048] The voltage generation unit 122 includes multiple pumping capacitors that receive an internal power supply voltage to generate multiple operating voltages Vop having various voltage levels, and selectively activates the multiple pumping capacitors in response to the control logic 130 to generate multiple operating voltages Vop.

[0049] The multiple operating voltages Vop generated can be supplied to the memory cell array 110 by the address decoder 121.

[0050] The page buffer group 123 includes the first to m-th page buffers PB1 to PBm. The first to m-th page buffers PB1 to PBm are each connected to the memory cell array 110 via the first to m-th bit lines BL1 to BLm. The first to m-th page buffers PB1 to PBm operate in response to the control logic 130.

[0051] The first to m-page buffers PB1 to PBm communicate data DATA with the data input / output circuit 124. During programming, the first to m-page buffers PB1 to PBm receive data DATA stored via the data input / output circuit 124 and data line DL.

[0052] During program operation, when a program pulse is applied to a selected word line, the first to m-page buffers PB1 to PBm transmit the stored data DATA received via the data input / output circuit 124 to the selected memory cell via bit lines BL1 to BLm. The memory cell of the selected page is programmed according to the transmitted data DATA. Memory cells connected to a bit line to which a program-allowable voltage (e.g., ground voltage) is applied have an elevated threshold voltage. The threshold voltage of memory cells connected to a bit line to which a program-prohibited voltage (e.g., power supply voltage) is applied is maintained. During program verification operation, the first to m-page buffers PB1 to PBm read the data DATA stored in the memory cell from the selected memory cell via bit lines BL1 to BLm.

[0053] During a read operation, the page buffer group 123 can read the data DATA from the memory cell of the selected page via the bit line BL and store the read data DATA in the first to m-th page buffers PB1 to PBm.

[0054] During the erase operation, the page buffer group 123 can float bit line BL. In one embodiment, the page buffer group 123 may include a column selection circuit.

[0055] In this embodiment, while data stored in some of the multiple page buffers included in the page buffer group 123 is programmed into the memory cell array 110, the other page buffers can receive and store new data input from the memory controller 200.

[0056] The data input / output circuit 124 is connected to the first to m-page buffers PB1 to PBm via data line DL. The data input / output circuit 124 operates in response to the control logic 130.

[0057] The data input / output circuit 124 may include multiple input / output buffers (not shown) that receive input data DATA. During program operation, the data input / output circuit 124 receives stored data DATA from an external controller (not shown). During read operations, the data input / output circuit 124 outputs data DATA transmitted from the first to the mth page buffers PB1 to PBm included in the page buffer group 123 to the external controller.

[0058] During readout or verification operations, the sensing circuit 125 generates a reference current in response to the allowable bit VRYBIT signal generated by the control logic 130, compares the sensing voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current, and outputs a pass signal or fail signal to the control logic 130.

[0059] The control logic 130 may be connected to the address decoder 121, the voltage generation unit 122, the page buffer group 123, the data input / output circuit 124, and the sensing circuit 125. The control logic 130 may be configured to control various operations of the memory device 100. The control logic 130 can operate in response to a command CMD transmitted from an external device.

[0060] The control logic 130 can control the peripheral circuit 120 by generating various signals in response to the command CMD and address ADDR. For example, the control logic 130 can generate the operation signal OPSIG, the row address RADD, the read and write circuit control signals PBSIGNALS, and the allow bit VRYBIT in response to the command CMD and address ADDR. The control logic 130 can output the operation signal OPSIG to the voltage generation unit 122, the row address RADD to the address decoder 121, the read and write circuit control signals to the page buffer group 123, and the allow bit VRYBIT to the sensing circuit 125. In addition, the control logic 130 can determine whether the verification operation has passed or failed in response to the pass or fail signal PASS / FAIL output by the sensing circuit 125.

[0061] In this embodiment, the control logic 130 may include an operation control unit 150. The operation control unit 150 can control the peripheral circuit 120 to perform programmed operations. The programmed operations may include programmed voltage application operations and verification operations.

[0062] In this embodiment, the operation control unit 150 can control the peripheral circuit 120 to apply program-related voltages to multiple word lines during program operation. The program-related voltages may be voltages applied to multiple word lines during program operation. The program-related voltages may include a program voltage, multiple path voltages, a hold voltage, a verification path voltage, and a ground voltage. In this embodiment, the operation control unit 150 can control the peripheral circuit 120 to change the magnitude of the voltages on multiple word lines during program operation.

[0063] Specifically, the operation control unit 150 can control the voltage generation unit 122 to generate program-related voltages. The voltage generation unit 122 can then provide the generated program-related voltages to the address decoder 121. The address decoder 121 can transmit the program-related voltages to multiple word lines. During program operation, the magnitude of the voltages on the multiple word lines may be changed by the program-related voltages. Specifically, the magnitude of the voltages on the multiple word lines may be changed by the program-related voltages applied to the program voltage application operation and the verification operation, respectively.

[0064] Figure 3 is a diagram illustrating the structure of one of the memory blocks BLK1 to BKLz shown in Figure 2.

[0065] Memory block BLKi refers to one of the memory blocks BLK1 to BLKz in Figure 2.

[0066] Referring to Figure 3, multiple word lines arranged parallel to each other may be connected between the first and second selection lines. Here, the first selection line may be the source selection line SSL, and the second selection line may be the drain selection line DSL. More specifically, the memory block BLKi may include multiple strings (ST) connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn may each be connected to a string ST, and the source line SL may be connected to a string ST in common. Since the strings ST may be configured similarly to each other, we will specifically explain using the string ST connected to the first bit line BL1 as an example.

[0067] A string ST may include a source selection transistor SST connected in series with each other between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A single string ST may contain at least one source selection transistor SST and at least one drain selection transistor DST, and may also contain more memory cells MC1 to MC16 than shown in the figure.

[0068] The source of the source-selection transistor SST may be connected to the source line SL, and the drain of the drain-selection transistor DST may be connected to the first bit line BL1. Memory cells MC1 to MC16 may be connected in series between the source-selection transistor SST and the drain-selection transistor DST. The gates of source-selection transistors SST included in different strings ST may be connected to the source-selection line SSL, the gates of drain-selection transistor DST may be connected to the drain-selection line DSL, and the gates of memory cells MC1 to MC16 may be connected to multiple word lines WL1 to WL16. A group of memory cells included in different strings ST that are connected to the same word line can be called a physical page (PG). Therefore, a memory block BLKi can contain as many physical pages PG as there are word lines WL1 to WL16.

[0069] A single memory cell can store one bit of data. This is typically called a single-level cell. In this case, one physical page (PG) can store one logical page (LPG) of data. One logical page (LPG) of data can contain as many data bits as there are cells in that physical page (PG).

[0070] A single memory cell can store two or more bits of data. In this case, one physical page (PG) can store two or more logical page (LPG) data.

[0071] Figure 4 is a diagram illustrating the distribution of threshold voltages of memory cells due to the programmed operation of a memory device.

[0072] In Figure 4, the horizontal axis of the graph represents the threshold voltage Vth of the memory cell, and the vertical axis of the graph represents the number of memory cells #of cells.

[0073] Referring to Figure 4, the threshold voltage distribution of the memory cell can change from the initial state to the final programmed state according to the program operation.

[0074] Figure 4 illustrates the case where one memory cell is programmed into a TLC that stores 3 bits of data.

[0075] The initial state is one in which no program operations are performed, and the distribution of the memory cell threshold voltage can be in the erased state E.

[0076] The final program state can be the distribution of threshold voltages of the memory cell that underwent the program operation. The threshold voltage of the memory cell that underwent the program operation can have a threshold voltage corresponding to any one of several program states. For example, if one memory cell is programmed into a TLC that stores 3 bits of data, the multiple program states can mean the erase state E and the first to seventh program states PV1 to PV7. In this embodiment, the threshold voltage of the memory cell that underwent the program operation can have a threshold voltage corresponding to any one of the erase state E and the first to seventh program states PV1 to PV7. The threshold voltage of the memory cell in its initial state can rise through the program operation to a threshold voltage corresponding to the erase state E and any one of the first to seventh program states PV1 to PV7.

[0077] Each memory cell can have one of the following states as its target program state: an erase state E, or one of the first to seventh program states PV1 to PV7. The target program state may be determined according to the data stored in the memory cell. Each memory cell can have a threshold voltage corresponding to the target program state among the final program states through its programming operation.

[0078] Figure 5 is a diagram illustrating the program operation of the memory device.

[0079] In Figure 5, the horizontal axis of the graph represents time, and the vertical axis represents the magnitude of the program voltage Vpgm.

[0080] Figure 5 illustrates the concept of a TLC (Total Light Cell) where one memory cell stores 3 bits of data.

[0081] Referring to Figure 5, the program operation of the memory device 100 may include multiple program loops PL1 to PLn. The memory device 100 can perform program operations by running multiple program loops PL1 to PLn so that the selected memory cell connected to the selected word line has a threshold voltage corresponding to any one of multiple program states. For example, when one memory cell is programmed into a TLC, the memory device 100 can perform program operations by running multiple program loops PL1 to PLn so that it has a threshold voltage corresponding to any one of the erase state E or the first to seventh program states PV1 to PV7.

[0082] Each of the multiple program loops PL1 to PLn may include a program voltage application step (PGM Step) and a verification step (Verify Step).

[0083] The program voltage application stage may be a stage in which a program voltage is applied to the selected word line to which the selected memory cell is connected. For example, the memory device 100 can apply a first program voltage Vpgm1 to the selected word line to which the memory cell selected in the first program loop PL1 is connected. After the first program voltage Vpgm1 is applied to the selected word line, the threshold voltage of each selected memory cell may have a threshold voltage corresponding to a target program state among a plurality of program states.

[0084] The verification step may involve applying a verification voltage to the selected word line to which the selected memory cell is connected. The verification step may involve determining whether the threshold voltage of each selected memory cell has a threshold voltage corresponding to a target program state among multiple program states. The verification step may involve applying a verification voltage corresponding to each target program state of the selected memory cell. For example, if the selected memory cell is determined to be off-cell by the verification voltage corresponding to each target program state of the selected memory cell, the verification step may be passed. As another example, if the selected memory cell is determined to be on-cell by the verification voltage corresponding to each target program state of the selected memory cell, the verification step may be failed.

[0085] In this embodiment, the memory device 100 can apply the first program voltage Vpgm1 to the selected word line to which the selected memory cell is connected in the first program loop PL1, and then apply the first to seventh verification voltages V_vfy1 to V_vfy7. At this time, a memory cell whose target program state is the first program state may perform the verification step using the first verification voltage V_vfy1. A memory cell whose target program state is the second program state may perform the verification step using the second verification voltage V_vfy2. A memory cell whose target program state is the third program state may perform the verification step using the third verification voltage V_vfy3. A memory cell whose target program state is the fourth program state may perform the program verification step using the fourth verification voltage V_vfy4. A memory cell whose target program state is the fifth program state may perform the program verification step using the fifth verification voltage V_vfy5. A memory cell whose target program state is the sixth program state may perform the program verification step using the sixth verification voltage V_vfy6. A memory cell whose target program state is the seventh program state may perform the program verification stage using the seventh verification voltage V_vfy7. The magnitudes of the verification voltages V_vfy1 to V_vfy7 can increase from the first verification voltage V_vfy1 to the seventh verification voltage V_vfy7. Specifically, the magnitudes of the verification voltages V_vfy1 to V_vfy7 may be such that the first verification voltage V_vfy1 is the smallest and the seventh verification voltage V_vfy7 is the largest. The number of verification voltages is not limited to this embodiment.

[0086] The threshold voltages of memory cells that have passed the verification stage using each of the verification voltages V_vfy1 to V_vfy7 can be determined to have threshold voltages corresponding to the target program state. Memory cells that have passed the verification stage can be programmed (program inhibited) in the second program loop PL2. A program inhibit voltage can be applied to the bit line connected to the programmed memory cell.

[0087] The threshold voltage of a memory cell whose verification stage has failed can be determined by each of the verification voltages V_vfy1 to V_vfy7 to be one that does not have a threshold voltage corresponding to the target program state. A memory cell whose verification stage has failed can then perform the second program loop PL2.

[0088] In the second program loop PL2, the memory device 100 can apply a second program voltage Vpgm2 to the selected word line to which the selected memory cell is connected, which is higher than the first program voltage Vpgm1 by a unit voltage ΔVpgm. Subsequently, the memory device 100 can perform the verification step of the second program loop PL2 in the same way as the verification step of the first program loop PL1.

[0089] Subsequently, the memory device 100 can perform the next program loop in the same way as the second program loop PL2 for a predetermined number of times.

[0090] In the embodiment, if the program operation is not completed within a predetermined number of program loops, the program operation may fail. If the program operation is completed within a predetermined number of program loops, the program operation may pass. Whether the program operation is completed or not can be determined by whether or not all verification stages for the selected memory cells have passed. If all verification stages for the selected memory cells have passed, the next program loop does not need to be performed.

[0091] In this embodiment, the program voltage can be determined by an Incremental Step Pulse Programming (ISPP) method. The level of the program voltage can be gradually increased or decreased by repeating the program loops PL1 to PLn. The number of times the program voltage is applied, the voltage level, and the voltage application time used in each program loop may be determined in various ways depending on the control of the memory controller 200.

[0092] Figure 6 is a diagram illustrating the program voltage application stage in the program operation of a memory device.

[0093] Referring to Figure 6, the program operation of the memory device 100 may include multiple program loops PL1 to PLn. Each of the multiple program loops PL1 to PLn may include a program voltage application stage and a verification stage. The program voltage application stage may include a precharge section, a program pulse (Pgm Pulse) section, and a discharge section.

[0094] The precharge section can be a section in which the bit line voltage is precharged. For example, the memory device 100 can change the bit line voltage to a program-allowable voltage or a program-prohibited voltage during the precharge section.

[0095] The program pulse interval can be an interval in which a program voltage is applied to a selected word line. In this embodiment, the memory device 100 can apply a pass voltage to unselected word lines while applying a program voltage to the selected word line during the program pulse interval.

[0096] A discharge section can be a section in which the voltage magnitude of multiple word lines is reduced. In this embodiment, the memory device 100 can reduce the voltage magnitude of multiple word lines by applying different voltages to each of the multiple word lines in the discharge section. For example, the memory device 100 can apply different voltages to a selected word line, a word line adjacent to the selected word line, and the remaining word lines among the multiple word lines, excluding the selected word line and the word line adjacent to the selected word line, in the discharge section.

[0097] The memory device 100 can perform a verification phase after the discharge phase has ended.

[0098] Figure 7 illustrates the change in the magnitude of the word line voltage due to the program operation of the memory device.

[0099] Referring to Figure 7, the memory device 100 can perform the verification stage after executing the program pulse section and discharge section included in the program voltage application stage.

[0100] Although not shown in Figure 7, the section prior to t1 can be a pre-charge section. The memory device 100 can apply a ground voltage GND to multiple word lines sel WL, ad WL, and r WL during the pre-charge section.

[0101] The t1-t2 interval can be a program pulse interval. The program pulse interval may also be an interval in which data is stored in the selected memory cell. The memory device 100 can apply a program voltage Vpgm to the selected word line sel WL during the program pulse interval. The memory device 100 can apply a first pass voltage Vpass1 to the word line ad WL adjacent to the selected word line during the program pulse interval.

[0102] In a program pulse interval, the magnitude of the voltage between the selected word line and the adjacent word line ad WL may be changed by the program voltage Vpgm applied to the selected word line sel WL. Specifically, the magnitude of the voltage between the selected word line and the adjacent word line ad WL can be increased from the first pass voltage Vpass1 to the second pass voltage Vpass2 due to the coupling phenomenon with the selected word line sel WL.

[0103] The memory device 100 can apply a first pass voltage Vpass1 to the remaining word lines r WL, excluding the selected word line sel WL and the word line ad WL adjacent to the selected word line, during a program pulse interval. The word line ad WL adjacent to the selected word line and the remaining word lines r WL may be unselected word lines.

[0104] The t2-t3 interval can be a discharge interval. The voltage magnitudes of the multiple word lines sel WL, ad WL, and r WL in the discharge interval can be as low as the hold voltage Vhold.

[0105] Specifically, in the interval t2 to t21, the memory device 100 can apply a ground voltage to the selected word line sel WL. In the interval t2 to t21, the magnitude of the voltage of the selected word line and the adjacent word line ad WL may be changed by the coupling phenomenon with the selected word line sel WL. Specifically, the magnitude of the voltage of the selected word line and the adjacent word line ad WL can become lower than the second pass voltage Vpass2 as the voltage of the selected word line sel WL decreases. In the interval t2 to t21, the memory device 100 can maintain the voltage of the remaining word line r WL at the first pass voltage Vpass1.

[0106] In the interval t21-t3, the memory device 100 can perform an equalizing operation on multiple word lines sel WL, ad WL, and r WL. The equalizing operation performed in the interval t21-t3 may be an operation in which the same voltage is applied to multiple word lines sel WL, ad WL, and r WL. After the equalizing operation is completed, the magnitudes of the voltages of the multiple word lines sel WL, ad WL, and r WL can be equal. In the interval t21-t3, after the equalizing operation is completed, the memory device 100 can apply a hold voltage Vhold to multiple word lines sel WL, ad WL, and r WL. The magnitudes of the voltages of the multiple word lines sel WL, ad WL, and r WL that have been changed after the equalizing operation is completed may be greater than the hold voltage Vhold.

[0107] The t3-t4 interval can be a verification phase. Specifically, in the t3-t31 interval, the memory device 100 can apply a ground voltage to the selected word line sel WL. In the t3-t31 interval, the memory device 100 can apply a third pass voltage Vpass3 to the selected word line, the adjacent word line ad WL, and the remaining word line r WL. The third pass voltage Vpass3 may be a verification pass voltage.

[0108] During the interval t31 to t4, the memory device 100 can apply a verification voltage V_vfy to the selected word line sel WL. During the interval t31 to t4, the memory device 100 can hold the voltages of the selected word line, the adjacent word line ad WL, and the remaining word line r WL in the third pass voltage Vpass3.

[0109] Figure 8 is a diagram illustrating the change in the magnitude of the word line voltage during program operation of a memory device according to one embodiment of the present invention.

[0110] Referring to Figure 8, the memory device 100 can perform the verification stage after executing the program pulse section and discharge section included in the program voltage application stage.

[0111] Although not shown in Figure 8, the section prior to t1 can be a pre-charge section. The memory device 100 can apply a ground voltage GND to multiple word lines sel WL, ad WL, and r WL during the pre-charge section.

[0112] The t1-t2 interval can be a program pulse interval. The memory device 100 can apply a program voltage Vpgm to the selected word line sel WL in the program pulse interval. The memory device 100 can apply a first pass voltage Vpass1 to the word line ad WL adjacent to the selected word line in the program pulse interval. For example, if the selected word line sel WL is the seventh word line WL7 shown in Figure 3, the word lines ad WL adjacent to the selected word line can be the sixth and eighth word lines WL6 and WL8. That is, if the selected word line sel WL is the nth word line, the word lines ad WL adjacent to the selected word line can be the n+1th and n-1st word lines. As another example, if the selected word line sel WL is the nth word line, the word lines ad WL adjacent to the selected word line can be the n+1th, n+2nd, n-1st, and n-2nd word lines.

[0113] In one embodiment, the voltage of the selected word line and the adjacent word line ad WL during the program pulse interval can be increased from a first pass voltage Vpass1 to a second pass voltage Vpass2 by the program voltage Vpgm applied to the selected word line sel WL. In another embodiment, the memory device 100 can apply the first pass voltage Vpass1 to the selected word line and the adjacent word line ad WL during the program pulse interval for a set time, and then apply the second pass voltage Vpass2. The second pass voltage Vpass2 can be a higher voltage than the first pass voltage Vpass1.

[0114] The memory device 100 can apply the first pass voltage Vpass1 to the remaining word line r WL during the program pulse interval. The selected word line, the adjacent word line ad WL, and the remaining word line r WL can be unselected word lines.

[0115] The t2-t3 interval can be a discharge interval. Specifically, in the t2-t21 interval, the memory device 100 can apply a ground voltage to the selected word line sel WL. In the t2-t21 interval, the memory device 100 can perform an equalizing operation on the selected word line, the adjacent word line ad WL, and the remaining word line r WL. The equalizing operation performed in the t2-t21 interval may be an operation to apply the same voltage to the selected word line, the adjacent word line ad WL, and the remaining word line r WL. For example, in the t2-t21 interval, the memory device 100 can apply a first pass voltage Vpass1 to the selected word line, the adjacent word line ad WL, and the remaining word line r WL. In the embodiment, the magnitudes of the voltages of multiple word lines sel WL, ad WL, and r WL can be equal during the t2-t21 interval. For example, after the interval t2~t21 ends, the magnitude of the voltages of multiple word lines sel WL, ad WL, and r WL can be the first pass voltage Vpass1.

[0116] In the t21-t22 interval, the memory device 100 can apply a ground voltage to multiple word lines sel WL, ad WL, and r WL. In this embodiment, the memory device 100 can apply a ground voltage to multiple word lines sel WL, ad WL, and r WL until the magnitude of the voltages of the multiple word lines sel WL, ad WL, and r WL becomes equal to or lower than the hold voltage Vhold. After the t21-t22 interval ends, the magnitude of the voltages of the multiple word lines sel WL, ad WL, and r WL can become equal to or lower than the hold voltage Vhold.

[0117] During the interval t22-t3, the memory device 100 can apply a hold voltage Vhold to multiple word lines sel WL, ad WL, and r WL. After the interval t22-t3 ends, the magnitude of the voltages on the multiple word lines sel WL, ad WL, and r WL can be the hold voltage Vhold. The hold voltage Vhold can be lower than the first pass voltage Vpass1. The hold voltage Vhold can be higher than the ground voltage.

[0118] The t3-t4 interval can be a verification phase. In one embodiment, during the t3-t31 interval, the memory device 100 can apply a voltage lower than the verification voltage V_vfy to the selected word line sel WL. In this case, the voltage lower than the verification voltage V_vfy can be a negative voltage. In another embodiment, the memory device 100 can apply a ground voltage to the selected word line sel WL during the t3-t31 interval. In yet another embodiment, the memory device 100 can apply a voltage lower than the ground voltage to the selected word line sel WL for a preset time during the t3-t31 interval, and then apply a ground voltage to the selected word line sel WL.

[0119] In the interval t3 to t31, the memory device 100 can apply a third pass voltage Vpass3 to the selected word line, the adjacent word line ad WL, and the remaining word line r WL. The third pass voltage Vpass3 can be a verification pass voltage.

[0120] During the interval t31 to t4, the memory device 100 can apply a verification voltage V_vfy to the selected word line sel WL. During the interval t31 to t4, the memory device 100 can hold the voltages of the selected word line, the adjacent word line ad WL, and the remaining word line r WL in the third pass voltage Vpass3.

[0121] In the embodiment, the length of the t3-t31 section may vary depending on the magnitude of the verification voltage V_vfy applied to the word line sel WL selected in the t31-t4 section. For example, the length of the t3-t31 section may become shorter as the magnitude of the verification voltage V_vfy applied to the word line sel WL selected in the t31-t4 section increases.

[0122] Specifically, after the t22-t3 interval is completed, the magnitude of the voltage of the selected word line sel WL can be the hold voltage Vhold. In the verification phase performed after the t22-t3 interval, the magnitude of the voltage of the selected word line sel WL must be lower than the hold voltage Vhold to the verification voltage V_vfy.

[0123] The verification voltage V_vfy can be a threshold voltage corresponding to the target program state of the selected memory cell connected to the selected word line sel WL. The magnitude of the verification voltage V_vfy may vary depending on the target program state of the selected memory cell connected to the selected word line sel WL.

[0124] For example, assuming that one memory cell is programmed into a TLC, the verification voltage V_vfy can be any one of the verification voltages V_vfy1 to V_vfy7 shown in Figure 5. The magnitude of the verification voltages V_vfy1 to V_vfy7 can be larger as the target program state increases. Among the selected memory cells, the memory cell whose target program state is the first program state can perform the verification step using the first verification voltage V_vfy1. The magnitude of the first verification voltage V_vfy1 can be the smallest of the verification voltages V_vfy1 to V_vfy7. Therefore, if the target program state of the selected memory cell is the first program state, the voltage of the selected word line sel WL in the verification step must be lower than the hold voltage Vhold to the first verification voltage V_vfy1. The magnitude of the second verification voltage V_vfy2 can be greater than the first verification voltage V_vfy1. Therefore, when the target program state of the selected memory cell is the second program state, the difference in magnitude between the hold voltage Vhold and the second verification voltage V_vfy2 can be smaller than when the target program state of the selected memory cell is the first program state. That is, in the t3~t31 interval, when the verification voltage V_vfy is the second verification voltage V_vfy2, the amount by which the verification voltage V_vfy decreases from the hold voltage Vhold to the verification voltage V_vfy can be smaller than when the verification voltage V_vfy is the first verification voltage V_vfy1. Therefore, the greater the magnitude of the verification voltage V_vfy, the shorter the length of the t3~t31 interval can be. Alternatively, the greater the magnitude of the verification voltage V_vfy, the shorter the time during which a voltage lower than the verification voltage V_vfy is applied to the selected word line sel WL in the t3~t31 interval can be. The greater the magnitude of the verification voltage V_vfy, the shorter the time during which the ground voltage is applied to the selected word line sel WL in the t3~t31 interval can be.

[0125] In other embodiments, the length of the t3-t31 interval may vary depending on the target program state of the selected memory cell connected to the selected word line sel WL. For example, the higher the target program state of the selected memory cell, the shorter the length of the t3-t31 interval can be. As another example, the higher the target program state of the selected memory cell, the shorter the time during which a voltage lower than the verification voltage V_vfy or a ground voltage is applied to the selected word line sel WL in the t3-t31 interval can be.

[0126] In one embodiment of the present invention, the memory device 100 applies a ground voltage to the selected word line sel WL in the interval t2 to t21, while simultaneously applying a first pass voltage Vpass1 to the selected word line and the adjacent word line ad WL and the remaining word line r WL, thereby rapidly reducing the voltage magnitudes of multiple word lines sel WL, ad WL, and r WL to the first pass voltage Vpass1.

[0127] In one embodiment of the present invention, the memory device 100 applies a ground voltage to multiple word lines sel WL, ad WL, and r WL in the t21-t22 interval, and then applies a hold voltage Vhold to multiple word lines sel WL, ad WL, and r WL in the t22-t3 interval, thereby allowing the magnitude of the voltages of multiple word lines sel WL, ad WL, and r WL to rapidly decrease to the hold voltage Vhold.

[0128] In one embodiment of the present invention, the memory device 100 applies a voltage lower than the verification voltage V_vfy or a ground voltage to the selected word line sel WL in the t3 to t31 section, and then applies the verification voltage V_vfy to the selected word line sel WL in the t31 to t4 section, thereby rapidly reducing the magnitude of the voltage of the selected word line sel WL to the verification voltage V_vfy. In other words, in one embodiment of the present invention, the memory device 100 can reduce the program time by rapidly reducing the magnitude of the voltages of multiple word lines sel WL, ad WL, and r WL during program operation.

[0129] Figure 9 illustrates another example of the change in the magnitude of the word line voltage during program operation of a memory device according to one embodiment of the present invention.

[0130] Figure 9 is a diagram that further illustrates the case where the magnitude of the verification voltage V_vfy changes during the verification phase of the program operation of the memory device, as explained with reference to Figure 8. Therefore, in Figure 9, explanations that overlap with those in Figure 8 are omitted.

[0131] Referring to Figure 9, in the t22-t3 interval, the memory device 100 can apply a hold voltage Vhold to the selected word line sel WL. After the t22-t3 interval ends, the magnitude of the voltage across the selected word line sel WL can be the hold voltage Vhold. Subsequently, in the t3-t31 interval, the memory device 100 can apply a ground voltage to the selected word line sel WL.

[0132] In the interval t31 to t4, the memory device 100 can apply a verification voltage V_vfy to the selected word line sel WL. The magnitude of the verification voltage V_vfy shown in Figure 9 may be greater than the verification voltage V_vfy shown in Figure 8. The verification voltage V_vfy shown in Figure 9 may have a higher threshold voltage corresponding to the target program state of the selected memory cell than the verification voltage V_vfy shown in Figure 8. Therefore, the length of the interval t3 to t31 shown in Figure 9 can be shorter than the length of the interval t3 to t31 shown in Figure 8. That is, the larger the magnitude of the verification voltage V_vfy, the shorter the length of the interval t3 to t31 can be. Alternatively, the larger the magnitude of the verification voltage V_vfy, the shorter the time during which the ground voltage is applied to the selected word line sel WL in the interval t3 to t31 can be.

[0133] Figure 10 illustrates yet another example of the change in the magnitude of the word line voltage during program operation of a memory device according to one embodiment of the present invention.

[0134] In Figure 10, explanations for content that overlaps with Figures 8 and 9 are omitted.

[0135] Referring to Figure 10, unlike in Figures 8 and 9, the memory device 100 does not need to apply a ground voltage to the selected word line sel WL during the verification phase. That is, after the t22-t3 phase is completed, the memory device 100 can apply the verification voltage V_vfy to the selected word line sel WL during the t3-t4 phase. In this embodiment, the magnitude of the verification voltage V_vfy shown in Figure 10 may be greater than the verification voltage V_vfy shown in Figures 8 and 9. In other embodiments, the verification voltage V_vfy can be a threshold voltage corresponding to the highest program state among multiple program states. The larger the magnitude of the verification voltage V_vfy, the smaller the difference between the magnitude of the verification voltage V_vfy and the hold voltage Vhold can be. Therefore, if the magnitude of the verification voltage V_vfy is greater than a preset magnitude, the memory device 100 can apply the verification voltage V_vfy to the selected word line sel WL during the verification phase without applying a ground voltage to the selected word line sel WL. In other words, if the magnitude of the verification voltage V_vfy is greater than a preset magnitude, the t3-t31 section shown in Figures 8-9 may be omitted. If the magnitude of the verification voltage V_vfy is greater than a preset magnitude, the length of the t3-t31 section can be 0.

[0136] Figure 11 is a flowchart illustrating the program operation of a memory device according to one embodiment of the present invention.

[0137] Referring to Figure 11, in step S1101, the memory device 100 can apply a program voltage to the selected word line, a second pass voltage to the selected word line and adjacent word lines, and a first pass voltage to the remaining word lines. The remaining word lines can be any word lines other than the selected word line and the word lines adjacent to the selected word line. The magnitude of the second pass voltage may be greater than the first pass voltage.

[0138] In step S1103, the memory device 100 can apply a ground voltage to the selected word line and apply a first pass voltage to the selected word line and adjacent word lines. In this embodiment, after applying the first pass voltage to the selected word line and adjacent word lines, the magnitude of the voltages of the multiple word lines may be changed to the first pass voltage.

[0139] In step S1105, the memory device 100 can apply a ground voltage to multiple word lines. In this embodiment, the magnitude of the voltages on the multiple word lines can be the same as or lower than the magnitude of the hold voltage.

[0140] In step S1107, the memory device 100 can apply a hold voltage to multiple word lines.

[0141] In step S1109, the memory device 100 can apply a ground voltage to the selected word line for a time determined according to the magnitude of the verification voltage, and apply a third-pass voltage to the selected word line, adjacent word lines, and the remaining word lines. For example, the time determined by the magnitude of the verification voltage can be the length of the interval t3 to t31 shown in Figure 9. As the magnitude of the verification voltage increases, the time for which the ground voltage is applied to the selected word line can be shortened. In one embodiment, the memory device 100 can apply a voltage lower than the verification voltage to the selected word line for a time determined according to the magnitude of the verification voltage. In another embodiment, the memory device 100 can apply a voltage lower than the ground voltage to the selected word line for a preset time, and then apply a ground voltage to the selected word line for a time determined according to the magnitude of the verification voltage.

[0142] In step S1111, the memory device 100 can apply a verification voltage to the selected word line.

[0143] Figure 12 is a diagram illustrating the memory controller shown in Figure 1.

[0144] The memory controller 1200 in Figure 12 can be the memory controller 200 in Figure 1.

[0145] Referring to Figure 12, the memory controller 1200 may include a processor 1210, RAM 1220, error correction circuit 1230, host interface 1240, ROM 1250, and flash interface 1260.

[0146] The processor 1210 can control various operations of the memory controller 1200. The RAM 1220 may be used as buffer memory, cache memory, working memory, etc., of the memory controller 1200.

[0147] The error correction circuit 1230 can perform error correction. The error correction circuit 1230 can perform error correction encoding (ECC encoding) based on data written to the memory device 100 via the flash interface 1260. The error correction encoded data can be transmitted to the memory device 100 via the flash interface 1260. The error correction circuit 1230 can perform error correction decoding (ECC decoding) on ​​data received from the memory device 100 via the flash interface 1260. For example, the error correction circuit 1230 may be included in the flash interface 1260 as a component of the flash interface 1260.

[0148] The ROM1250 can store various information required for the operation of the memory controller 1200 in the form of firmware.

[0149] The memory controller 1200 can communicate with external devices (e.g., host 300, application processor, etc.) via the host interface 1240.

[0150] The memory controller 1200 can communicate with the memory device 100 via the flash interface 1260. The memory controller 1200 can transmit commands, addresses, and control signals to the memory device 100 and receive data via the flash interface 1260. For example, the flash interface 1260 may include a NAND interface.

[0151] Figure 13 is a block diagram showing a memory card system to which a memory system according to one embodiment of the present invention is applied.

[0152] Referring to Figure 13, the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0153] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 may be configured to control read, write, erase, and background operations of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and the host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory controller 2100 may be implemented similarly to the memory controller 200 described with reference to Figure 1. The memory device 2200 may be implemented similarly to the memory device 100 described with reference to Figure 1.

[0154] For example, the memory controller 2100 may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0155] The memory controller 2100 can communicate with an external device via the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 is configured to communicate with an external device via at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, and NVMe. For example, the connector 2300 can be defined by at least one of the various communication standards mentioned above.

[0156] For example, the memory device 2200 may be composed of various non-volatile memory elements such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOAH flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Registered Trademark) (Ferroelectric RAM), and STT-MRAM (Spin Transfer Torque-Magnetic RAM).

[0157] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to constitute a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to constitute memory cards such as PC cards (PCMCIA, Personal Computer Memory Card International Association), CompactFlash® cards (CF), SmartMedia cards (SM, SMC), Memory Sticks, Multimedia cards (MMC, RS-MMC, MMCmicro, eMMC), SD cards (SD, miniSD, microSD, SDHC), and general-purpose flash memory devices (UFS).

[0158] Figure 14 is a block diagram showing an SSD (Solid State Drive) system to which a memory system according to one embodiment of the present invention is applied.

[0159] Referring to Figure 14, the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 sends and receives signals to and from the host 3100 via a signal connector 3001 and receives power input via a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memories 3221-322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0160] According to an embodiment of the present invention, the SSD controller 3210 can perform the functions of the memory controller 200 described with reference to Figure 1.

[0161] The SSD controller 3210 can control multiple flash memories 3221-322n in response to signals received from the host 3100. For example, the signals may be based on the interface between the host 3100 and the SSD 3200. For example, the signals may be defined by at least one of the following interfaces: USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc.

[0162] The auxiliary power supply unit 3230 is connected to the host 3100 via the power connector 3002. The auxiliary power supply unit 3230 can receive power input from the host 3100 and be charged. The auxiliary power supply unit 3230 can provide power to the SSD 3200 if the power supply from the host 3100 is not smooth. For example, the auxiliary power supply unit 3230 may be located inside the SSD 3200 or outside the SSD 3200. For example, the auxiliary power supply unit 3230 may be located on the main board and provide auxiliary power to the SSD 3200.

[0163] The buffer memory 3240 operates as a buffer memory for the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from multiple flash memories 3221-322n, or it can temporarily store metadata (e.g., mapping tables) of the flash memories 3221-322n. The buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, or non-volatile memory such as FRAM®, ReRAM, STT-MRAM, PRAM.

[0164] Figure 15 is a block diagram showing a user system to which a memory system according to one embodiment of the present invention is applied.

[0165] Referring to Figure 15, the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0166] The application processor 4100 can drive components, operating systems (OS), or user programs included in the user system 4000. For example, the application processor 4100 may include controllers, interfaces, and graphics engines that control components included in the user system 4000. The application processor 4100 may be provided as a system-on-a-chip (SoC).

[0167] The memory module 4200 can function as the main memory, operating memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, or LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, or FRAM®. For example, the application processor 4100 and the memory module 4200 may be packaged on a POP (Package on Package) basis and provided as a single semiconductor package.

[0168] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communication such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile communication), WCDMA (wideband CDMA), CDMA-2000, TDMA (Time Division Multiple Access), LTE (Long Term Evolution), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 may be included in the application processor 4100.

[0169] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transmit data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 may be embodied in non-volatile semiconductor memory elements such as PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), NAND flash, NOR flash, or 3D structured NAND flash. For example, the storage module 4400 may be provided as a memory card or removable drive such as an external drive in the user system 4000.

[0170] For example, the storage module 4400 may include multiple non-volatile memory devices, and these multiple non-volatile memory devices can operate in the same manner as the memory device 100 described with reference to Figure 1. The storage module 4400 can operate in the same manner as the memory system 50 described with reference to Figure 1.

[0171] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or outputting data to an external device. For example, the user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touchscreen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. The user interface 4500 may also include user output interfaces such as an LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) display device, AMOLED (Active Matrix OLED) display device, LED, speaker, and monitor. [Explanation of symbols]

[0172] 50 memory systems 100 memory devices 150 Operation Control Unit 200 memory controllers 300 hosts

Claims

1. A memory block containing multiple memory cells, each connected to a multiple word line, A voltage generation unit that generates program-related voltages, including program voltage, first pass voltage, second pass voltage, third pass voltage, hold voltage, and verification voltage, to be applied to the above-mentioned multiple word lines, An address decoder that transmits the above program-related voltages to the above multiple word lines, A memory device characterized by including an operation control unit that controls the voltage generation unit and the address decoder to apply the program voltage to a selected word line from among the plurality of word lines, apply the second pass voltage to the selected word line and adjacent word lines, apply the first pass voltage to the remaining word lines from among the plurality of word lines excluding the selected word line and adjacent word lines, apply a ground voltage to the selected word line for a first interval, and apply the first pass voltage to the adjacent word lines.

2. The above operation control unit, The memory device according to claim 1, characterized in that the voltage generation unit and the address decoder are controlled to apply the ground voltage to the plurality of word lines during the second section following the first section described above.

3. The above operation control unit, The memory device according to claim 2, characterized in that the voltage generation unit and the address decoder are controlled to apply the hold voltage to the plurality of word lines during the third section following the second section described above.

4. The above operation control unit, The memory device according to claim 3, characterized in that, during the fourth section following the third section described above, the voltage generation unit and the address decoder are controlled to apply the ground voltage to the selected word line and the third path voltage to the adjacent word line and the remaining word line.

5. The length of the fourth section mentioned above is: The memory device according to claim 4, characterized in that it differs depending on the magnitude of the above verification voltage.

6. The length of the fourth section mentioned above is: The memory device according to claim 4, characterized in that if the magnitude of the above verification voltage is greater than a preset magnitude, it is 0.

7. The above operation control unit, The memory device according to claim 4, characterized in that the voltage generation unit and the address decoder are controlled to apply the verification voltage to the selected word line during the fifth section following the fourth section described above.

8. In a method for operating a memory device that includes multiple memory cells connected to multiple word lines, The process involves applying a program voltage to a selected word line from among the multiple word lines, applying a first pass voltage to the remaining word lines excluding the selected word line and the word lines adjacent to the selected word line, and applying a second pass voltage to the adjacent word lines. A method for operating a memory device, characterized by including the steps of applying a ground voltage to the selected word line and applying the first path voltage to the adjacent word line.

9. The method for operating a memory device according to claim 8, further comprising the step of applying the first path voltage to the adjacent word lines, and then applying the ground voltage to the plurality of word lines.

10. The method for operating a memory device according to claim 9, further comprising the step of applying the ground voltage to the plurality of word lines, and then applying a hold voltage to the plurality of word lines.

11. The method for operating a memory device according to claim 10, further comprising the steps of applying the hold voltage to the plurality of word lines, applying the ground voltage to the selected word line for a first time, and applying a third pass voltage to the adjacent word lines and the remaining word lines.

12. The method for operating a memory device according to claim 11, further comprising the step of applying the ground voltage to the selected word line for the first time, and then applying a verification voltage to the selected word line.

13. In the step of applying the third path voltage to the adjacent word line and the remaining word line, The method for operating a memory device according to claim 12, characterized in that a voltage lower than the ground voltage is applied to the selected word line for a second time, and then the ground voltage is applied to the selected word line for a first time.

14. The first hour mentioned above is The method for operating the memory device according to claim 12, characterized in that the value decreases as the magnitude of the above verification voltage increases.

15. Multiple memory cells connected to multiple word lines, A peripheral circuit that performs a program operation including a program voltage application operation which applies a program voltage to a selected word line connected to a selected memory cell from among the multiple memory cells mentioned above, and a verification operation which applies a verification voltage to the selected word line to verify whether the threshold voltage of the selected memory cell has reached a threshold voltage corresponding to the target program state. A memory device characterized by including an operation control unit that, during the above verification operation, applies a voltage lower than the verification voltage to the selected word line for a time determined according to the magnitude of the verification voltage, and then controls the peripheral circuit to apply the verification voltage to the selected word line.

16. The above operation control unit, The memory device according to claim 15, characterized in that, while the program voltage is applied to the selected word line, a first pass voltage is applied to the remaining word lines among the plurality of word lines, excluding the selected word line and the word lines adjacent to the selected word line, and the peripheral circuit is controlled to apply a second pass voltage higher than the first pass voltage to the adjacent word lines.

17. The above operation control unit, The memory device according to claim 16, characterized in that, in the first section following the completion of the above-mentioned program voltage application operation, the peripheral circuit is controlled to apply a ground voltage to the selected word line and to apply the first path voltage to the adjacent word line and the remaining word line.

18. The above operation control unit, The memory device according to claim 17, characterized in that the peripheral circuit is controlled to apply the ground voltage to the plurality of word lines in the second section following the first section described above.

19. The above operation control unit, The memory device according to claim 18, characterized in that, after applying a hold voltage to the plurality of word lines in the third section following the second section described above, the peripheral circuit is controlled to perform the verification operation described above.

20. Voltages lower than the above verification voltage are: The memory device according to claim 15, characterized in that the voltage is ground voltage or a negative voltage.

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