Common pipeline nonlinear transformation

Abstract

This provides an integrated circuit that performs common pipeline nonlinear transformations. [Solution] The common pipeline nonlinear transformation is a nonlinear transformation pipeline that implements multiple nonlinear functions, and includes extracting fractional and real components from an input floating-point value, applying a linear approximator corresponding to one of the multiple nonlinear functions to the fractional component to obtain an approximate value, and multiplying the approximate value by the real component to generate a transformed floating-point value. It is implemented by a controller of an integrated circuit that transmits input floating-point values ​​from the memory to the nonlinear transformation pipeline, configures a nonlinear transformation pipeline for one of the multiple nonlinear functions, and stores the transformed floating-point value in memory.

Description

Technical Field

[0001] [Background Art] Nonlinear transformation is generally used when performing inference of neural networks. Nonlinear transformation is utilized in attention functions in transformer neural network architectures such as the Generative Pretrained Transformer (GPT) architecture, and activation functions in convolutional neural network (CNN) architectures. Examples of types of nonlinear transformation include exponents, reciprocals, square roots, and other nonlinear calculations, or combinations thereof such as softmax, variance, Root Mean Square (RMS), etc.

Brief Description of the Drawings

[0002] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that various features are not drawn to scale according to standard practice in the industry. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0003] [Figure 1] It is a schematic diagram of a system for common pipeline nonlinear transformation according to at least some embodiments of the present disclosure.

[0004] [Figure 2] It is a schematic diagram of a nonlinear transformation pipeline according to at least some embodiments of the present disclosure.

[0005] [Figure 3] It is a schematic diagram of an exponential function according to at least some embodiments of the present disclosure.

[0006] [Figure 4]This is a schematic diagram of a square root function according to at least some embodiments of the present disclosure.

[0007] [Figure 5] This is a schematic diagram of an inverse function according to at least some embodiments of the present disclosure.

[0008] [Figure 6] This is a computational flow for common pipeline nonlinear transformations according to at least some embodiments of the present disclosure.

[0009] [Figure 7] This is a computational flow for performing a nonlinear transformation according to at least some embodiments of the present disclosure. [Modes for carrying out the invention]

[0010] The following disclosure provides many different embodiments or examples to implement different features of the subject matter provided. Specific examples of components, values, operations, materials, configurations, or the like are described below for the sake of simplicity of this disclosure. Naturally, these are merely examples and not intended to be limiting. Other components, values, operations, materials, configurations, or the like are contemplated. In addition, this disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the sake of brevity and clarity and does not in itself define relationships between the various embodiments and / or configurations discussed.

[0011] In accelerator chips known to the inventors, each type of nonlinear transformation is performed by separate parts of the chip hardware. More specifically, values ​​undergoing nonlinear transformation are sent to a part of the chip dedicated to that type of nonlinear transformation. Furthermore, only one type of nonlinear transformation is performed at a given time. Therefore, the nonlinear transformation chip hardware reduces the average resource utilization by the chip.

[0012] In at least some embodiments of this disclosure, a nonlinear transformation is decomposed into core nonlinear calculations performed on floating-point values. Many nonlinear transformations involve common nonlinear calculations in a unique combination according to a function. In at least some embodiments, the integrated circuit chip includes a common pipeline for multiple types of nonlinear transformations. In at least some embodiments, the common pipeline includes redundant components used for the core nonlinear calculations. In at least some embodiments, the core nonlinear calculations use the redundant components to separate the fractional component from the real component. In at least some embodiments, a common linear approximator is used to perform one of several nonlinear calculations on the fractional component by referencing a unique linear equation or a look-up table (LUT). In at least some embodiments, the core nonlinear calculations are uniquely combined by addition, multiplication, etc., to realize more complex nonlinear transformations.

[0013] In at least some embodiments, greater efficiency and higher average resource utilization are achieved by reusing common components within a common pipeline to perform nonlinear transformations. In at least some embodiments, the common pipeline includes conversions between numeric formats for compatibility with integer and floating-point values. In at least some embodiments, the resulting floating-point values ​​are selectively converted to non-floating-point values ​​or retained as floating-point values. Conversion, or lack thereof, occurs during computation or storage, causing some layers to infer over a wider range and with higher granularity, while others are inferred over a narrower range and with lower granularity.

[0014] Figure 1 is a schematic diagram of a system for common pipeline nonlinear transformation according to at least some embodiments of the present disclosure. The system for common pipeline nonlinear transformation includes an integrated circuit 100, a host computer 102, a nonlinear transformation pipeline 110, a floating-point converter 112, an integer converter 114, a memory 116, and a controller 118.

[0015] In at least some embodiments, the integrated circuit 100 is configured to house a nonlinear transformation pipeline and other components. In at least some embodiments, the integrated circuit 100 is configured for neural network inference. In at least some embodiments, the integrated circuit 100 is configured to interface with a host computer 102. In at least some embodiments, the integrated circuit 100 is in the form of a microchip, an ASIC (Application-Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or any other form of integrated circuit. In at least some embodiments, the integrated circuit 100 is of a type used in a variety of electronic devices, from smartphones to industrial machinery.

[0016] In at least some embodiments, the host computer 102 is configured to provide an interface for configuring and controlling the integrated circuit 100. In at least some embodiments, the host computer 102 is configured to communicate with the integrated circuit 100 to send and receive data and control signals. In at least some embodiments, the host computer 102 is configured to communicate with the integrated circuit 100 through direct connection, network, wide area network, or any other form of electronic communication. In at least some embodiments, the host computer 102 is further configured to handle general computing tasks, run applications, and process data. In at least some embodiments, the host computer 102 is configured to interface with peripherals such as a keyboard, monitor, and external storage devices. In at least some embodiments, the host computer 102 is in the form of a desktop computer, laptop computer, server, etc. In at least some embodiments, the host computer 102 is of a type used in offices, homes, and data centers for a wide range of computing tasks.

[0017] The nonlinear transformation pipeline 110 is a component of the integrated circuit 100. In at least some embodiments, the nonlinear transformation pipeline 110 is configured to perform various nonlinear transformations on floating-point values. In at least some embodiments, the nonlinear transformation pipeline 110 is configured to receive input values ​​from memory 116 and floating-point converter 112. In at least some embodiments, the nonlinear transformation pipeline 110 is configured to send the transformed values ​​to memory 116. In at least some embodiments, the nonlinear transformation pipeline 110 includes dedicated circuitry configured for nonlinear transformations. In at least some embodiments, the nonlinear transformation pipeline 110 is implemented as a set of logic gates and registers. In at least some embodiments, the nonlinear transformation pipeline 110 is as shown in Figure 2, which is described below. In at least some embodiments, the nonlinear transformation pipeline includes an extractor configured to extract fractional and real components from an input floating-point value; an approximator configured to obtain an approximation by applying a linear approximator corresponding to one of a plurality of nonlinear functions to the fractional component; and a multiplier configured to multiply the approximation by the real component to produce a transformed floating-point value. In at least some embodiments, the plurality of nonlinear functions include exponential functions, square root functions, and inversion functions. In at least some embodiments, these nonlinear functions can be combined to form more complex nonlinear transformations. In at least some embodiments, the plurality of nonlinear functions further include sigmoid functions, Gelu functions, ReLU functions, and the like.

[0018] The floating-point converter 112 is a component of the integrated circuit 100. In at least some embodiments, the floating-point converter 112 is configured to convert integer values ​​to floating-point values ​​for processing in the nonlinear conversion pipeline 110. In at least some embodiments, the floating-point converter 112 is configured to receive integer values ​​from memory 116. In at least some embodiments, the floating-point converter 112 is configured to send floating-point values ​​to the nonlinear conversion pipeline 110. In at least some embodiments, the floating-point converter 112 is configured to send floating-point values ​​to memory 116. In at least some embodiments, the floating-point converter 112 is configured to perform conversions from various integer formats to various floating-point formats. In at least some embodiments, the floating-point converter 112 is configured to interact with other components of the integrated circuit 100 that are requesting numerical conversions. In at least some embodiments, the floating-point converter 112 is implemented as a set of logic gates and registers. In at least some embodiments, the floating-point converter 112 is configured to convert an input integer value to an input floating-point value.

[0019] The integer converter 114 is a component of the integrated circuit 100. In at least some embodiments, the integer converter 114 is configured to convert floating-point values ​​to integer values. In at least some embodiments, the integer converter 114 is configured to receive floating-point values ​​from the nonlinear conversion pipeline 110. In at least some embodiments, the integer converter 114 is configured to receive floating-point values ​​from memory 116. In at least some embodiments, the integer converter 114 is configured to send integer values ​​to memory 116. In at least some embodiments, the integer converter 114 is configured to perform conversions from various floating-point formats to various integer formats. In at least some embodiments, the integer converter 114 is configured to interact with other components of the integrated circuit 100 that are requesting numerical conversions. In at least some embodiments, the integer converter 114 is implemented as a set of logic gates and registers. In at least some embodiments, the integer converter 114 is configured to convert converted floating-point values ​​to converted integer values.

[0020] Memory 116 is a component of the integrated circuit 100. In at least some embodiments, memory 116 is configured to store input values, intermediate results, and final converted values. In at least some embodiments, memory 116 is configured to interface with controller 118, nonlinear conversion pipeline 110, floating-point converter 112, and integer converter 114. In at least some embodiments, memory 116 is in communication with the nonlinear conversion pipeline. In at least some embodiments, memory 116 is configured to provide general data storage for various applications. In at least some embodiments, memory 116 is in the form of RAM (Random Access Memory), flash memory, or any other form of on-chip memory.

[0021] The controller 118 is a component of the integrated circuit 100. In at least some embodiments, the controller 118 is configured to manage the flow of data and control signals within the system. In at least some embodiments, the controller 118 is configured to configure the non-linear transformation pipeline 110. In at least some embodiments, the controller 118 is configured to transmit control signals and communicate with the memory 116, the non-linear transformation pipeline 110, the floating-point converter 112, and the integer converter 114 otherwise. In at least some embodiments, the controller 118 is configured to interface with the host computer 102. In at least some embodiments, the controller 118 is in the form of a microcontroller, one or more control units, or any other type of controller used within the integrated circuit. In at least some embodiments, the controller 118 is configured to transmit an input floating-point value from the memory to the non-linear transformation pipeline, configure the non-linear transformation pipeline for one of a plurality of non-linear functions, and store the converted floating-point value in the memory. In at least some embodiments, the controller 118 is configured to transmit an input integer from the memory to the floating-point converter and transmit an input floating-point value from the floating-point converter to the non-linear transformation pipeline. In at least some embodiments, the controller 118 is configured to transmit a converted floating-point value from one of the non-linear transformation pipeline and the memory to the integer converter and store the converted integer value in the memory.

[0022] FIG. 2 is a schematic diagram of a non-linear transformation pipeline 210 according to at least some embodiments of the present disclosure. The non-linear transformation pipeline 210 includes an exponential function 230A, a square root function 230B, a reciprocal function 230C, a linear approximator 225, an exponential LUT 226A, a square root LUT 226B, a reciprocal LUT 226C, and a multiplier 228. The description of the non-linear transformation pipeline 110 in FIG. 1 is applicable to the non-linear transformation pipeline 210.

[0023] The exponential function 230A is a component of the nonlinear transformation pipeline 210. In at least some embodiments, the exponential function 230A is configured to perform operations to calculate the exponential value of an input floating-point value, such as an input floating-point value 220. In at least some embodiments, the exponential function 230A is configured to apply one or more pre-extraction operations to the input floating-point value. In at least some embodiments, the exponential function 230A is configured to extract a fractional component, such as a decimal component 222, and a real component, such as a real component 223, from the input floating-point value. In at least some embodiments, the exponential function 230A is configured to apply one or more post-extraction operations to the extracted fractional and real components. In at least some embodiments, the exponential function 230A is configured to send the fractional component to a linear approximator 225. In at least some embodiments, the exponential function 230A is configured to send the real component, such as a real component 223, to a multiplier 228. In at least some embodiments, the exponential function 230A is as shown in Figure 3, which is described below.

[0024] The square root function 230B is a component of the non-linear transformation pipeline 210. In at least some embodiments, the square root function 230B is configured to perform an operation for calculating the square root of an input floating-point value, such as the input floating-point value 220. In at least some embodiments, the square root function 230B is configured to apply one or more pre-extraction operations to the input floating-point value. In at least some embodiments, the square root function 230B is configured to extract a fractional component, such as the fractional component 222, and a real component, such as the real component 223, from the input floating-point value. In at least some embodiments, the square root function 230B is configured to apply one or more post-extraction operations to the extracted fractional and real components. In at least some embodiments, the square root function 230B is configured to send the fractional component to the linear approximator 225. In at least some embodiments, the square root function 230B is configured to send a real component, such as the real component 223, to the multiplier 228. In at least some embodiments, the square root function 230B is as shown in FIG. 4 described below.

[0025] The reciprocal function 230C is a component of the nonlinear transformation pipeline 210. In at least some embodiments, the reciprocal function 230C is configured to perform an operation to calculate the reciprocal of an input floating-point value, such as an input floating-point value 220. In at least some embodiments, the reciprocal function 230C is configured to apply one or more pre-extraction operations to the input floating-point value. In at least some embodiments, the reciprocal function 230C is configured to extract a fractional component, such as a decimal component 222, and a real component, such as a real component 223, from the input floating-point value. In at least some embodiments, the reciprocal function 230C is configured to apply one or more post-extraction operations to the extracted decimal and real components. In at least some embodiments, the reciprocal function 230C is configured to send the decimal component to a linear approximator 225. In at least some embodiments, the reciprocal function 230C is configured to send the real component, such as a real component 223, to a multiplier 228. In at least some embodiments, the reciprocal function 230C is as shown in Figure 5, which is described below.

[0026] In at least some embodiments, the exponential function 230A, the square root function 230B, and the reciprocal function 230C share one or more components for performing the operations for their respective calculations. In at least some embodiments, the nonlinear transformation pipeline 210 further includes at least one pre-extraction transformer, at least one fractional component transformer, and at least one real component transformer.

[0027] The linear approximator 225 is a component of the nonlinear transformation pipeline 210. In at least some embodiments, the linear approximator 225 is configured to generate a linear approximation of a nonlinear function applied to a fractional component, such as a fractional component 222. In at least some embodiments, the linear approximator 225 utilizes a linear function that is an approximation of the nonlinear function. In at least some embodiments, the linear approximator 225 includes a lookup table (LUT). In at least some embodiments, the linear approximator 225 utilizes LUTs for different functions, such as an exponential LUT 226A, a square root LUT 226B, and an inverse LUT 226C. Each LUT utilized by the linear approximator 225 matches an input value to an output value according to the approximation of the nonlinear function. In at least some embodiments, the linear approximator 225 is configured to receive a fractional component from one of the exponential function 230A, the square root function 230B, and the inverse function 230C. In at least some embodiments, the linear approximator 225 is configured to send the approximation to the multiplier 228. In at least some embodiments, the linear approximator 225 is configured to perform linear interpolation.

[0028] The multiplier 228 is a component of the nonlinear transformation pipeline 210. In at least some embodiments, the multiplier 228 is configured to multiply the approximation from the linear approximator 225 by a real component, such as the real component 223, to produce a transformed floating-point value, such as the floating-point output value 229. In at least some embodiments, the multiplier 228 is configured to receive a real component from one of the exponential function 230A, the square root function 230B, and the reciprocal function 230C. In at least some embodiments, the multiplier 228 is configured to perform floating-point multiplication operations on floating-point values. In at least some embodiments, the multiplier 228 is of a type commonly implemented in integrated circuits, ASICs, or FPGAs.

[0029] Figure 3 is a schematic diagram of an exponential function 330 according to at least some embodiments of the present disclosure. The exponential function 330 includes a multiplier 331, a mantissa and exponent extractor 332, a floating-point input value 320, a fractional component 322, and a real component 323. The description of the exponential function 230A in Figure 2 is applicable to the exponential function 330.

[0030] The multiplier 331 is a component of the exponential function 330. In at least some embodiments, the multiplier 331 is configured to apply a pre-extraction operation as part of calculating the exponential value of an input floating-point value, such as a floating-point input value 320. In at least some embodiments, the multiplier 331 is configured to multiply the floating-point input value by a predetermined value to produce a product. In at least some embodiments, the multiplier 331 is configured to multiply the input floating-point value by an approximate value of the reciprocal of the natural logarithm of 2. In at least some embodiments, the multiplier 331 is configured to send the product to the mantissa and exponential extractor 332. In at least some embodiments, the multiplier 331 is shared between the exponential function 330 and other functions, such as one or more of the square root function 230B and reciprocal function 230C in Figure 2. In at least some embodiments, the multiplier 331 is configured to apply a pre-extraction operation as part of other nonlinear functions. In at least some embodiments, the multiplier 331 is a pre-extraction transformer. In at least some embodiments where one nonlinear function is an exponential function, the pre-extraction transformer includes a pre-extraction multiplier configured to multiply the input floating-point value by an approximate value of the reciprocal of the natural logarithm of 2.

[0031] The mantissa and exponent extractor 332 is a component of the exponential function 330. In at least some embodiments, the mantissa and exponent extractor 332 is configured to extract mantissa data and exponent data from a floating-point input value, such as a floating-point input value 320. In at least some embodiments, the mantissa and exponent extractor 332 is configured to convert the mantissa data to a fractional component, such as a fractional component 322, and the exponent data to a real component, such as a real component 323. In at least some embodiments, the mantissa and exponent extractor 332 is configured to generate a fractional component as a floating-point value. In at least some embodiments, the mantissa and exponent extractor 332 is configured to generate a real component as a floating-point value. In at least some embodiments, the mantissa and exponent extractor 332 is shared between the exponential function 330 and other functions, such as one or more of the square root function 230B and the reciprocal function 230C in Figure 2. In at least some embodiments, the mantissa and exponent extractor 332 is configured to extract mantissa and exponent data as part of other nonlinear functions or other processes in the nonlinear transformation pipeline.

[0032] Figure 4 is a schematic diagram of a square root function 430 according to at least some embodiments of the present disclosure. The square root function 430 includes a mantissa and exponent extractor 432, an adder 434, a register 435, a register 436, a multiplexer 437, a multiplier 438, a floating-point input value 420, a fractional component 422, and a real component 423. The description of the square root function 230B in Figure 2 is applicable to the square root function 430. The description of the mantissa and exponent extractor 332 in Figure 3 is applicable to the mantissa and exponent extractor 432.

[0033] The adder 434 is a component of the square root function 430. In at least some embodiments, the adder 434 is configured to apply a post-extraction operation as part of the square root calculation process. In at least some embodiments, the adder 434 is configured to receive exponent data from the mantissa and exponent extractor 432. In at least some embodiments, the adder 434 is configured to perform a general addition operation. In at least some embodiments, the adder 434 is configured to add the exponent data to a predetermined value to produce a sum. In at least some embodiments, the adder 434 is configured to send the sum to the multiplier 438. In at least some embodiments, the adder 434 is configured to determine whether the sum is even or odd. In at least some embodiments, the adder 434 uses the modulo operator to determine whether the sum is even or odd. In at least some embodiments, the adder 434 is configured to control the input to the multiplexer 437 according to whether the sum is even or odd. In at least some embodiments, the adder 434 is shared between the square root function 430 and other functions, such as one or more of the exponential function 230A and the reciprocal function 230C in Figure 2. In at least some embodiments, the adder 434 is configured to perform addition as part of other nonlinear functions or other processes in a nonlinear transformation pipeline.

[0034] Registers 435 and 436 are components of the square root function 430. In at least some embodiments, registers 435 and 436 are configured to store predetermined values ​​for use in square root calculations. In at least some embodiments, registers 435 and 436 are configured to transmit the stored values ​​to the multiplier 438 via the multiplexer 437. In at least some embodiments, registers 435 and 436 are configured to interact with other registers and memories in the integrated circuit to receive, for example, predetermined values ​​for storage.

[0035] The multiplexer 437 is a component of the square root function 430. In at least some embodiments, the multiplexer 437 is configured to send one of several values ​​to the multiplier 438 as part of the square root calculation process. In at least some embodiments, the multiplexer 437 is configured to receive values ​​from registers 435 and 436. In at least some embodiments, the multiplexer 437 is configured to direct one of the values ​​from registers 435 and 436 to the multiplier 438. In at least some embodiments, the multiplexer 437 is configured to receive a control signal from the adder 434 to select one of the values ​​from registers 435 and 436. In at least some embodiments, the multiplexer 437 is of a type commonly found in digital circuits and processors. In at least some embodiments, the multiplexer 437 is shared between the square root function 430 and other functions, such as one or more of the exponential function 230A and the reciprocal function 230C in Figure 2. In at least some embodiments, the multiplexer 437 is configured to send one of several values ​​as part of another nonlinear function or other process in the nonlinear transformation pipeline.

[0036] The multiplier 438 is a component of the square root function 430. In at least some embodiments, the multiplier 438 is configured to multiply the sum received from the adder 434 by a value received via the multiplexer 437 from one of the registers 435 and 436 to produce a product as part of the square root calculation process. In at least some embodiments, the multiplier 438 is configured to multiply the sum by the square root of 2 in response to the sum being determined to be even. In at least some embodiments, the multiplier 438 is shared between the square root function 430 and other functions such as one or more of the exponential function 230A and the reciprocal function 230C in Figure 2. In at least some embodiments, the multiplier 438 is configured to multiply values ​​as part of other nonlinear functions or other processes in a nonlinear transformation pipeline.

[0037] In at least some embodiments where one nonlinear function is a square root function, the real component converter includes an adder 434 configured to increment the value of the real component by 1; a modulo operator configured to apply a modulo 2 operation to the incremented real component; a multiplexer 437 configured to output the value of the square root of 2 in response to receiving a signal from the modulo operator indicating an even result, and a value of 1 in response to receiving a signal from the modulo operator indicating a non-even result; and a real component multiplier 438 configured to multiply the incremented real component by the value output by the multiplexer 437.

[0038] Figure 5 is a schematic diagram of the reciprocal function 530 according to at least some embodiments of the present disclosure. The reciprocal function 530 includes a mantissa and exponent extractor 532, an exponent inverter 539, a floating-point input value 520, a fractional component 522, and a real component 523. The description of the reciprocal function 230C in Figure 2 is applicable to the reciprocal function 530. The description of the mantissa and exponent extractor 332 in Figure 3 is applicable to the mantissa and exponent extractor 532.

[0039] The exponential inverter 539 is a component of the reciprocal function 530. In at least some embodiments, the exponential inverter 539 is configured to invert exponential data as part of the reciprocal calculation process. In at least some embodiments, the exponential inverter 539 is configured to receive exponential data from the mantissa and exponential extractor 532 and output inverted exponential data. In at least some embodiments, the exponential inverter 539 is shared between the reciprocal function 530 and other functions, such as one or more of the exponential function 230A and the square root function 230B in Figure 2. In at least some embodiments, the exponential inverter 539 is configured to invert exponential data as part of other nonlinear functions or other processes in a nonlinear transformation pipeline. In at least some embodiments, the exponential inverter 539 is a real component transformer. In at least some embodiments, where one of the nonlinear functions is a reciprocal function, the real component transformer includes an inverter for inverting the real component.

[0040] Figure 6 shows a computational flow for a common pipeline nonlinear transformation according to at least some embodiments of the present disclosure. In at least some embodiments, the computational flow provides a method for a common pipeline nonlinear transformation. In at least some embodiments, the method is carried out by a controller of an integrated circuit, such as controller 118 in Figure 1.

[0041] In S640, the controller determines whether the value is a floating-point value. If it is determined that the value is not a floating-point value, the arithmetic flow proceeds to the floating-point conversion in S642. If it is determined that the value is a floating-point value, the arithmetic flow proceeds to the nonlinear transformation in S644.

[0042] In S642, the controller converts the value to a floating-point format. In at least some embodiments, the controller converts an input integer value to a floating-point format. In at least some embodiments, the controller instructs a floating-point converter, such as the floating-point converter 112 in Figure 1, to convert the value to a floating-point format. In at least some embodiments, the value is an integer.

[0043] In S644, the controller performs a nonlinear transformation. In at least some embodiments, the controller performs the nonlinear transformation by extracting the fractional and real components from the floating-point value. In at least some embodiments, the controller applies a linear approximator to the fractional component. In at least some embodiments, the controller multiplies the result by the real component. In at least some embodiments, the controller generates a transformed floating-point value. In at least some embodiments, the controller performs the nonlinear transformation based on a specified nonlinear function. In at least some embodiments, the controller controls the common pipeline to perform the nonlinear transformation. In at least some embodiments, the controller performs the calculation flow shown in Figure 7 below.

[0044] In S646, the controller determines whether an integer value is required. In response to determining that an integer value is required, the arithmetic flow proceeds to integer conversion in S648. In response to determining that an integer value is not required, the arithmetic flow terminates. In at least some embodiments, the controller determines whether the converted floating-point value needs to be converted to an integer format in order to proceed with the inference process. In at least some embodiments, the controller determines whether the inference process requires an integer value or a floating-point value. In at least some embodiments, the controller determines whether the inference process benefits from an integer value or a floating-point value. In at least some embodiments, the controller makes a determination based on instructions from the host computer. In at least some embodiments, the controller applies an output format that satisfies the requirements of a subsequent process or application.

[0045] In S648, the controller converts the converted floating-point value to an integer value. In at least some embodiments, the controller converts the converted floating-point value to an integer format. In at least some embodiments, the controller converts the converted floating-point value to a predetermined integer format.

[0046] Figure 7 shows a computational flow for performing a nonlinear transformation according to at least some embodiments of the present disclosure. In at least some embodiments, the computational flow provides a method for performing a nonlinear function. In at least some embodiments, the method is performed by a nonlinear transformation pipeline of an integrated circuit, such as the nonlinear transformation pipeline 110 in Figure 1.

[0047] In S750, the nonlinear transformation pipeline or its subcomponents perform pre-extraction calculations. In at least some embodiments, the nonlinear transformation pipeline performs pre-extraction calculations according to the type of nonlinear transformation. In at least some embodiments, a controller causes the nonlinear transformation pipeline to perform pre-extraction calculations. In at least some embodiments, a controller configures the nonlinear transformation pipeline for performing pre-extraction calculations. In at least some embodiments where one of the nonlinear functions is an exponential function, the pre-extraction calculations include multiplying the input floating-point value by an approximate value of the reciprocal of the natural logarithm of 2.

[0048] In S752, the nonlinear transformation pipeline or its mantissa and exponent extractor extracts the fractional and real components. In at least some embodiments, the nonlinear transformation pipeline extracts the fractional and real components from the mantissa and exponent data of the input floating-point value. In at least some embodiments, the controller causes the nonlinear transformation pipeline to extract the fractional and real components. In at least some embodiments, the controller configures the nonlinear transformation pipeline for extracting the fractional and real components. In at least some embodiments, the nonlinear transformation pipeline generates the fractional and real components in floating-point format.

[0049] In S754, the nonlinear transformation pipeline or its subcomponents perform fractional component calculations. In at least some embodiments, the nonlinear transformation pipeline performs fractional component calculations by performing post-extraction calculations on the fractional components. In at least some embodiments, a controller causes the nonlinear transformation pipeline to perform fractional component calculations. In at least some embodiments, a controller configures the nonlinear transformation pipeline for performing fractional component calculations. In at least some embodiments, the fractional component calculations include scaling, shifting, or one or more other calculations.

[0050] In S755, the nonlinear transformation pipeline or its subcomponents apply a linear approximator to the fractional component. In at least some embodiments, the nonlinear transformation pipeline approximates the fractional component value by applying a linear approximator to the fractional component, such as by using a lookup table (LUT). In at least some embodiments, the linear approximator converts the input, which is in floating-point format, to integer format for comparison with the address value of the LUT. In at least some embodiments, the address value indirectly corresponds to the values ​​A and B in the following equation:F O =F I *A+B Here, F O is the output fractional component, F I is the input fractional component, and A and B are constants stored in the LUT. In at least some embodiments, the address value directly corresponds to the value of the output fractional component. In at least some embodiments, the linear approximator interpolates a value stored in the LUT that corresponds to the address value closest to the input integer value. In at least some embodiments, the nonlinear transformation pipeline applies a linear approximator to the fractional component by using a linear approximator, such as a linear equation that approximates the fractional component. In at least some embodiments, the controller causes the nonlinear transformation pipeline to apply the linear approximator to the fractional component. In at least some embodiments, the controller configures the nonlinear transformation pipeline for applying the linear approximator to the fractional component.

[0051] In S757, the nonlinear transformation pipeline or its subcomponents perform real component operations. In at least some embodiments, the nonlinear transformation pipeline performs real component operations by performing post-extraction operations on the real components. In at least some embodiments, a controller causes the nonlinear transformation pipeline to perform real component operations. In at least some embodiments, a controller configures the nonlinear transformation pipeline for performing real component operations. In at least some embodiments where one nonlinear function is an inverse function, the real component operation includes inverting the real components. In at least some embodiments where one nonlinear function is a square root function, the real component operation includes incrementing the value of the real components by 1, determining whether the incremented real components are even, and, in response to determining that the incremented real components are even, multiplying the incremented real components by the square root of 2.

[0052] In S759, the nonlinear transformation pipeline or its multiplier multiplies the fractional component by the real component. In at least some embodiments, the nonlinear transformation pipeline multiplies the fractional component by the real component by multiplying the approximated fractional component by the real component. In at least some embodiments, the nonlinear transformation pipeline multiplies the fractional component in floating-point format by the real component in floating-point format. In at least some embodiments, the nonlinear transformation pipeline generates a single floating-point value representing the result of the nonlinear transformation.

[0053] While embodiments of the present invention have been described, the technical scope of any claimed subject matter is not limited to the embodiments described above. Those skilled in the art will understand that various modifications and improvements are possible to the embodiments described above. Those skilled in the art will also understand from the scope of the claims that such modified or improved embodiments fall within the technical scope of the present invention.

[0054] The operations, procedures, steps, and stages of each process performed by the apparatus, system, program, and method shown in the claims, embodiments, or figures may be performed in any order, unless their order is indicated by “prior to” or “before” or similar, and unless the output from a previous process is used in a later process. Even if a process flow is described in the claims, embodiments, or figures using phrases such as “first” or “next,” such description does not necessarily mean that the processes must be performed in the order described.

[0055] A common pipeline nonlinear transformation is implemented by a nonlinear transformation pipeline configured to perform multiple nonlinear functions, which includes extracting fractional and real components from an input floating-point value, applying a linear approximator corresponding to one of the multiple nonlinear functions to the fractional component to obtain an approximation, and multiplying the approximation by the real component to generate a transformed floating-point value; a memory in communication with the nonlinear transformation pipeline; and a controller configured to transmit an input floating-point value from memory to the nonlinear transformation pipeline, configure a nonlinear transformation pipeline for one of the multiple nonlinear functions, and store the transformed floating-point value in memory.

[0056] In at least some embodiments, the common pipeline nonlinear transformation is further implemented by a floating-point converter configured to convert an input integer value to an input floating-point value, where a controller is further configured to send an input integer from memory to the floating-point converter and to send an input floating-point value from the floating-point converter to the nonlinear transformation pipeline. In at least some embodiments, the common pipeline nonlinear transformation is further implemented by an integer converter configured to convert a converted floating-point value to a converted integer value, where a controller is further configured to send a converted floating-point value from one of the nonlinear transformation pipeline and memory to the integer converter and to store the converted integer value in memory. In at least some embodiments, the nonlinear functions include exponential functions, square root functions, and reciprocal functions. In at least some embodiments, the nonlinear transformation pipeline is further configured to perform one or more of the following: pre-extraction operations, fractional component operations, and real component operations. In at least some embodiments, one nonlinear function is an exponential function, and the pre-extraction operation includes multiplying the input floating-point value by an approximate value of the reciprocal of the natural logarithm of 2. In at least some embodiments, one nonlinear function is an inverse function, and the real component operation includes inverting the real component. In at least some embodiments, one nonlinear function is a square root function, and the real component operation includes incrementing the value of the real component by 1, determining whether the incremented real component is even, and, in response to determining that the incremented real component is even, multiplying the incremented real component by the square root of 2. In at least some embodiments, the linear approximator includes a lookup table (LUT).

[0057] The common pipeline nonlinear transformation is implemented by a nonlinear transformation pipeline, which includes an extractor configured to extract fractional and real components from an input floating-point value, an approximator configured to obtain an approximation by applying a linear approximator corresponding to one of several nonlinear functions to the fractional component, and a multiplier configured to generate a transformed floating-point value by multiplying the approximation by the real component; a memory in communication state with the nonlinear transformation pipeline; and a controller configured to send an input floating-point value from memory to the nonlinear transformation pipeline, configure a nonlinear transformation pipeline for one of several nonlinear functions, and store the transformed floating-point value in memory.

[0058] In at least some embodiments, the common pipeline nonlinear transformation is further implemented by a floating-point converter configured to convert an input integer value to an input floating-point value, where a controller is further configured to send an input integer from memory to the floating-point converter and to send an input floating-point value from the floating-point converter to the nonlinear transformation pipeline. In at least some embodiments, the common pipeline nonlinear transformation is further implemented by an integer converter configured to convert a converted floating-point value to a converted integer value, where a controller is further configured to send a converted floating-point value from one of the nonlinear transformation pipeline and memory to the integer converter and to store the converted integer value in memory. In at least some embodiments, the multiple nonlinear functions include exponential functions, square root functions, and inverse functions. In at least some embodiments, the nonlinear transformation pipeline further includes at least one pre-extraction converter, at least one fractional component converter, and at least one real component converter. In at least some embodiments, one nonlinear function is an exponential function, and the pre-extraction converter includes a pre-extraction multiplier configured to multiply the input floating-point value by an approximate value of the reciprocal of the natural logarithm of 2. In at least some embodiments, one nonlinear function is an inverse function, and the real component converter includes an inverter for inverting the real component. In at least some embodiments, one nonlinear function is a square root function, and the real component converter includes an adder configured to increment the value of the real component by 1, a remainder operator configured to apply a remainder 2 operation to the incremented real component, a multiplexer configured to output the value of the square root of 2 in response to receiving a signal from the remainder operator indicating an even result, and a value of 1 in response to receiving a signal from the remainder operator indicating a non-even result, and a real component multiplier configured to multiply the incremented real component by the value output by the multiplexer. In at least some embodiments, the linear approximator includes a lookup table (LUT).

[0059] The foregoing description briefly outlines some embodiments to help those skilled in the art better understand aspects of the disclosure. Those skilled in the art will understand that the disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent configurations do not depart from the spirit and scope of the disclosure, and that various changes, substitutions, and modifications within this specification are possible without departing from the spirit and scope of the disclosure.

Claims

1. A nonlinear transformation pipeline configured to perform multiple nonlinear functions, Extract mantissa data and exponential data from an input floating-point value, and convert the mantissa data and exponential data into a decimal component and a real component. Applying a linear approximator corresponding to one of the aforementioned nonlinear functions to the decimal component to obtain an approximate value, and A nonlinear transformation pipeline that performs the following operations: multiplying the aforementioned approximation by the aforementioned real number component to generate a transformed floating-point value; A memory that communicates with the aforementioned nonlinear transformation pipeline; and The input floating-point value is transmitted from the memory to the nonlinear conversion pipeline. The nonlinear transformation pipeline is configured for one of the multiple nonlinear functions, The converted floating-point value is stored in the memory. A controller configured in such a way Equipped with, The nonlinear transformation pipeline is further configured to perform one or more pre-extraction or post-extraction operations corresponding to the one nonlinear function in the extraction, in an integrated circuit.

2. A floating-point converter configured to convert an input integer value into the aforementioned input floating-point value. Furthermore, The controller is, The input integer value is transmitted from the memory to the floating-point converter. The input floating-point value is transmitted from the floating-point converter to the nonlinear conversion pipeline. It is further structured in the following way: The integrated circuit according to claim 1.

3. An integer converter configured to convert the converted floating-point value back into a converted integer value. Furthermore, The controller is, The converted floating-point value is transmitted from one of the nonlinear conversion pipeline and the memory to the integer converter. The converted integer value is stored in the memory. It is further structured in the following way: The integrated circuit according to claim 1.

4. The integrated circuit according to claim 1, wherein the plurality of nonlinear functions include exponential functions, square root functions, and reciprocal functions.

5. The integrated circuit according to claim 4, wherein the nonlinear transformation pipeline is configured to perform one or more of the following: fractional component calculations and real component calculations.

6. The first nonlinear function is an exponential function, The pre-extraction calculation includes multiplying the input floating-point value by an approximate value of the reciprocal of the natural logarithm of 2. The integrated circuit according to claim 5.

7. The aforementioned nonlinear function is an inverse function, The real number component operation includes inverting the real number component. The integrated circuit according to claim 5.

8. The first nonlinear function is a square root function, The aforementioned real number component operation is, The value of the real component is increased by 1, Determine whether the increased real number component is even, In response to the determination that the increased real number component is even, the increased real number component is multiplied by the square root of 2. including, The integrated circuit according to claim 5.

9. The linear approximator is an integrated circuit according to any one of claims 1 to 8, comprising a lookup table (LUT).

10. An extractor configured to extract mantissa data and exponential data from an input floating-point value, and to convert the mantissa data and exponential data into a decimal component and a real component, An approximator configured to obtain an approximate value by applying a linear approximator corresponding to one of several nonlinear functions to the decimal component, and A multiplier configured to generate a converted floating-point value by multiplying the aforementioned approximation by the aforementioned real number component. A nonlinear transformation pipeline, including; A memory that communicates with the aforementioned nonlinear transformation pipeline; and The input floating-point value is transmitted from the memory to the nonlinear conversion pipeline. The nonlinear transformation pipeline is configured for one of the multiple nonlinear functions, The converted floating-point value is stored in the memory. A controller configured in such a way Equipped with, The nonlinear transformation pipeline is an integrated circuit further comprising at least one pre-extraction transformer or at least one post-extraction transformer corresponding to the one nonlinear function.

11. A floating-point converter configured to convert an input integer value into the aforementioned input floating-point value. Furthermore, The controller is, The input integer value is transmitted from the memory to the floating-point converter. The input floating-point value is transmitted from the floating-point converter to the nonlinear conversion pipeline. It is further structured in the following way: The integrated circuit according to claim 10.

12. An integer converter configured to convert the converted floating-point value back into a converted integer value. Furthermore, The controller is, The converted floating-point value is transmitted from one of the nonlinear conversion pipeline and the memory to the integer converter. The converted integer value is stored in the memory. It is further structured in the following way: The integrated circuit according to claim 10.

13. The integrated circuit according to claim 10, wherein the plurality of nonlinear functions include exponential functions, square root functions, and reciprocal functions.

14. The integrated circuit according to claim 13, wherein the nonlinear conversion pipeline has at least one fractional component converter and at least one real component converter.

15. The first nonlinear function is an exponential function, The pre-extraction converter includes a pre-extraction multiplier configured to multiply the input floating-point value by an approximate value of the reciprocal of the natural logarithm of 2. The integrated circuit according to claim 14.

16. The aforementioned nonlinear function is an inverse function, The real number component converter includes an inverter for inverting the real number component. The integrated circuit according to claim 14.

17. The first nonlinear function is a square root function, The aforementioned real-number component converter is An adder configured to increase the value of the real component by 1, A modulo operator configured to apply the modulo 2 operation to the increased real number component, A multiplexer configured to output the value of the square root of 2 in response to receiving a signal representing an even result from the modulo operator, and the value of 1 in response to receiving a signal that does not represent an even result from the modulo operator, and A real component multiplier configured to multiply the increased real component by the value output by the multiplexer. including, The integrated circuit according to claim 14.

18. The integrated circuit according to any one of claims 10 to 17, wherein the linear approximator includes a lookup table (LUT).

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