Image sensor column readout amplifier

Abstract

Examples include a column readout amplifier and an image sensor including the same. In one example, the column readout amplifier includes a signal amplifier having an amplifier output and first and second amplifier inputs, a filter capacitor having first and second terminals, the second terminal connected to a ground terminal, a buffer amplifier having a buffer amplifier input and a buffer amplifier output, a switching network configured to switchably connect the amplifier output to the buffer amplifier input and the buffer amplifier output to the first terminal of the filter capacitor during a first period and to switchably connect the amplifier output directly to the first terminal of the filter capacitor during a second period, and a low pass filter connected in a feedback path of the signal amplifier between the amplifier output and the first amplifier input, the low pass filter including a series resistor and a capacitor.

Description

[Background technology]

[0001] Image sensors, such as CMOS image sensors, are widely used in a wide variety of applications covering large portions of the electromagnetic spectrum. Many image sensor designs employ a two-dimensional array of sensors that capture working light over a given region. Each sensor can be considered a single pixel in a sensor array having pixels arranged in any number of rows and columns. Each pixel sensor includes some form of photodetector and a readout circuit that converts the charge accumulated by the photodetector ("photocharge") into a voltage during image exposure, which is read out by a readout amplifier shared by all the pixel sensors in a row (hence called a column readout amplifier). The pixel sensors in each row are read out in parallel using the column readout amplifier.

[0002] To maintain low noise, the time between the transfer of photocharge to the readout circuit within the pixel sensor and the readout of that charge must be minimized as much as possible, because noise accumulates in the pixel sensor during this stage. Low-bandwidth amplifiers can be used to limit noise in the column readout amplifier. The lower the bandwidth of the column readout amplifier, the lower the readout noise from the column readout amplifier. However, reducing the bandwidth of the column readout amplifier increases the time required to read out the pixel sensor. This is because an amplifier with reduced bandwidth takes longer to settle. Thus, there is a trade-off between readout time and readout noise. Therefore, reducing noise in the column readout amplifier remains a challenge for image sensors. [Overview of the project]

[0003] The embodiments and models are directed toward a column readout amplifier and a method using the same. In particular, one embodiment is directed toward a column readout amplifier circuit that incorporates a low-pass filter in the amplifier's feedback path to reduce readout noise.

[0004] According to one embodiment, the column readout amplifier comprises a signal amplifier having an amplifier output section, a first amplifier input section, and a second amplifier input section, wherein the second amplifier input section is connected to a reference voltage terminal; a filter capacitor having first and second terminals, wherein the second terminal is connected to a ground terminal; and a buffer amplifier having a buffer amplifier input section and a buffer amplifier output section. The column readout amplifier further comprises a switching network configured to switchably connect the amplifier output section to the buffer amplifier input section and the buffer amplifier output section to the first terminal of the filter capacitor during a first period, and to switchably connect the amplifier output section directly to the first terminal of the filter capacitor during a second period; and a low-pass filter connected between the amplifier output section and the first amplifier input section in the feedback path of the signal amplifier, the low-pass filter including a series resistor and a capacitor.

[0005] According to another embodiment, the image sensor comprises a bit line conductor, a pixel array having at least one row of addressable pixel sensors, each pixel sensor being connected to the bit line conductor in accordance with a word selection signal, and a column amplifier connected to the bit line conductor. The column amplifier comprises a signal amplifier having an amplifier output section, a first amplifier input section, and a second amplifier input section, the second amplifier input section being connected to a reference voltage terminal, a filter capacitor having first and second terminals, the second terminal being connected to a ground terminal, a buffer amplifier having a buffer amplifier input section and a buffer amplifier output section, a switching network configured to switchably connect the amplifier output section to the buffer amplifier input section and the buffer amplifier output section to the first terminal of the filter capacitor during a first period, and to switchably connect the amplifier output section directly to the first terminal of the filter capacitor during a second period, and a low-pass filter connected between the amplifier output section and the first amplifier input section in the feedback path of the signal amplifier, the low-pass filter including a series resistor and a capacitor.

[0006] Examples of column amplifiers and image sensors may include any one or more of the following features.

[0007] In one example, the column readout amplifier further includes a capacitor connected between the amplifier output and the ground terminal.

[0008] In another example, the column readout amplifier further includes a feedback capacitor connected in series with a resistor in the feedback path of the signal amplifier.

[0009] In one example, the signal amplifier includes a capacitive transimpedance amplifier configured with a gain greater than 1.

[0010] In another example, the capacitor is connected between the node between the series resistor and the feedback capacitor and the ground terminal.

[0011] In another example, the capacitance of the capacitor is less than the capacitance of the filter capacitor.

[0012] In another example, the capacitance of the filter capacitor is variable.

[0013] In one example, the buffer amplifier output is disconnected from the filter capacitor during a second period.

[0014] In another example, the buffer amplifier has a gain substantially equal to 1.

[0015] In another example, the column readout amplifier further includes an input capacitor connected to the first input of the signal amplifier.

[0016] Further aspects, embodiments, and the advantageous effects of these exemplary aspects and embodiments will be described in detail below. The embodiments disclosed herein may be combined with other embodiments in any manner consistent with at least one of the principles disclosed herein, and references such as "embodiment", "some embodiments", "alternative embodiments", "various embodiments", "one embodiment", etc. are not necessarily mutually exclusive, indicating that a particular feature, structure, or characteristic described may be included in at least one embodiment. The occurrence of such terms herein does not necessarily refer to all being the same embodiment.

Brief Description of the Drawings

[0017] [Figure 1] FIG. 8 is a block diagram of an example of an image sensor system using a pixel array and a column readout amplifier according to an aspect of the present disclosure. [Figure 2] FIG. 11 is a circuit diagram showing an example of a prior art column readout amplifier connected to one pixel sensor out of a column of pixel sensors. [Figure 3] FIG. 14 is a timing diagram of various signals for controlling specific elements of the readout of the pixel sensor shown in FIG. 2. [Figure 4] FIG. 17 is a circuit diagram showing an example of a column readout amplifier connected to one pixel sensor out of a column of pixel sensors according to an aspect of the present disclosure. [Figure 5] FIG. 20 is a comparison graph showing an example of simulated noise detection for the readout from the circuit of FIG. 2 and the circuit of FIG. 4 according to an aspect of the present disclosure. [Figure 6] FIG. 23 is a block diagram of an example of a computing platform that may include the image sensor of FIG. 1 according to an aspect of the present disclosure.

Modes for Carrying Out the Invention

[0018] The structure of a column readout amplifier is disclosed, which exhibits no or relatively small increase in power consumption and, in particular, reduced noise at high readout frame rates. Embodiments of the column readout amplifier may include a low-pass filter circuit in the amplifier's feedback path to reduce readout noise, as will be described in more detail below. In one example, the column readout amplifier may be used with an image sensor including an array of photosensitive pixel sensors.

[0019] Outline To adequately stabilize the amplifier output during the short readout times available at high frame rates, image sensors operating at high frame rates generally require high-bandwidth column readout amplifiers. However, as mentioned above, the higher the bandwidth of the column readout amplifier, the higher the readout noise from the column readout amplifier. High readout noise can be problematic depending on the imaging application, especially if the image sensor may operate under very low illumination conditions.

[0020] Accordingly, techniques for designing a column readout amplifier that exhibits reduced readout noise at both high and low readout frame rates are disclosed herein. In one example, the column amplifier includes a low-pass filter in the amplifier feedback path. This contributes to reducing readout noise by approximately 10% at high frame rates (e.g., about 120 frames per second (fps)) and by approximately 5% at low frame rates (e.g., about 30 fps) for the same power consumption.

[0021] According to some embodiments, the image sensor includes a pixel array having at least one row of addressable pixel sensors and a column readout amplifier connected to at least one row of addressable pixel sensors. The column readout amplifier may include a signal amplifier having an amplifier output section, a first amplifier input section and a second amplifier input section, the second amplifier input section being connected to a reference voltage terminal, and a filter capacitor having first and second terminals, the second terminal being connected to a ground terminal. The column readout amplifier may further include a buffer amplifier having a buffer amplifier input section and a buffer amplifier output section, and a switching network configured to switchably connect the amplifier output section to the buffer amplifier input section and the buffer amplifier output section to the first terminal of the filter capacitor during a first period, and to switchably connect the amplifier output section directly to the first terminal of the filter capacitor during a second period. The column readout amplifier may further include a low-pass filter connected between the amplifier output section and the first amplifier input section in the feedback path of the signal amplifier, the low-pass filter including a series resistor and a capacitor.

[0022] System Architecture Figure 1 is a block diagram of an example of an image sensor 100 according to some embodiments. The image sensor 100 represents or may be an integral part of a charge-coupled device (CCD) camera or other type of imaging device. In some embodiments, the image sensor 100 may be configured to capture various parts of the electromagnetic spectrum, such as visible light, ultraviolet light, infrared light, or X-rays, to name a few. The image sensor 100 may include a pixel array 110, a column readout amplifier 120, an analog-to-digital converter (ADC) 130, and a processor 140. Each of the components described may be contained together on the same printed circuit board (PCB) or together in a single chip package (e.g., system-in-package or system-on-chip). In some other embodiments, one or more of the elements may be contained in separate chip packages and / or separate PCBs.

[0023] According to some embodiments, the pixel array 110 includes a plurality of pixel sensors 112 arranged in a matrix. Each pixel sensor 112 of the pixel array 110 may have a similar architecture including a photodetector and a readout circuit. The photodetection region of each pixel sensor on which an incident line can act may differ from one embodiment to the next, but in some exemplary cases, it has a physical size of about 1 μm × 1 μm to about 5 μm × 5 μm. Similarly, the shape of the photodetection region (e.g., photodiode) and (if present) the lens configuration may also differ from one example to the next, depending on factors such as the desired filling density of the array. According to some embodiments, each row of pixel sensors may be interconnected via a common row selection line (e.g., word line) to give an independently addressable row of pixel sensors.

[0024] According to some embodiments, outputs from pixel sensors 112 in N different columns are received by a column readout amplifier 120. According to some embodiments, the column readout amplifier 120 represents N separate column readout amplifiers, each configured to receive outputs from the pixel sensors of the corresponding columns of the pixel array 110. In this way, the pixel sensors of a given row of the pixel array 110 can be selected via row selection lines and read out simultaneously via the N column readout amplifiers 120. According to some embodiments, the column readout amplifier 120 may include any number of source follower FETs or any type of amplifier configuration, such as operational amplifiers. In some embodiments, a single column readout amplifier 120 may be used in conjunction with a multiplexer to receive each of the N column outputs from the pixel array 110.

[0025] According to some embodiments, the output from the column readout amplifier 120 is received by the ADC 130. As described above, the ADC 130 may represent N different ADCs, and a given ADC is configured to receive the corresponding output from the column readout amplifier 120. The ADC 130 can be any known type of ADC, without limitation.

[0026] The processor 140 may be configured to receive digitally converted signals from the ADC 130 (i.e., N digitally converted signals across N ADCs) and use those signals to perform any number of operations. For example, the processor 140 may receive signal data from a given row of pixel sensors in a pixel array 110 and use that signal data to generate an image or a portion of an image captured through the pixel array 110. According to some embodiments, the processor 140 may provide a control input 122 to a column readout amplifier to change the operating mode of the amplifier, as further described below. As used herein, the term “processor” may mean any device or part of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. The processor 140 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, custom semiconductors, or any other appropriate processing devices.

[0027] Column Readout Amplifier Design The manner in which the column readout amplifier according to the embodiments disclosed herein provides advantageous effects can be more readily understood by referring to Figure 2. Figure 2 shows a conventional column readout amplifier 200 connected to one pixel sensor 202 of a row of pixel sensors (e.g., one of the pixel sensors 112). The specific pixel sensor 202 connected to the bit line 204 is identified by the signal of the corresponding word line 206. The column readout amplifier 200 includes a capacitive transimpedance amplifier 210, which includes an operational amplifier 212, an input capacitor 214 connected to one input of the operational amplifier 212, and a feedback capacitor 216. Before detecting the voltage of the bit line 204, the input and output of the capacitive transimpedance amplifier 210 are short-circuited by closing a switch 218 to reset the amplifier. The gain of the capacitive transimpedance amplifier 210 is given by the ratio of the capacitances of capacitors 214 and 216, which is typically on the order of 30. The bandwidth of the capacitive transimpedance amplifier 210 is set by capacitor C3.

[0028] Figure 3 is a timing diagram for various signals related to the readout operation of the pixel sensor 202 using the column amplifier 200.

[0029] Referring to FIGS. 2 and 3, the pixel sensor 202 includes a photodiode 208 that accumulates charge during image exposure. At the end of the image exposure, the floating diffusion node 220 is reset to the voltage Vrst by closing the gate 222 using the signal of the reset line (Reset). The voltage of the floating diffusion node 220 after the reset operation is detected via the source follower 224 and the column readout amplifier 200, and is stored in the sample and hold circuit of the capacitor C1 in the column readout amplifier 200. After this voltage detection, the gate 226 is made conductive according to the signal of Tx. Due to the positive potential of the floating diffusion node 220, all the charge of the photodiode 208 is transferred to the floating diffusion node 220. The potential of the floating diffusion node 220 decreases with respect to the reset potential due to the transferred charge. Then, the potential of the floating diffusion node 220 is detected by the column readout amplifier 200 and is stored in the sample and hold circuit of the capacitor C2. Then, the voltage difference between the capacitors C1 and C2 is used to identify the charge generated by the photodiode 208 during exposure.

[0030] The readout operation using the column amplifier 200 can be regarded as being performed in four steps as shown in FIG. 3. During phase 1 (S1 = High, S2 = High, S3 = High, S3￣ = Low), the capacitive transimpedance amplifier 210 is connected to the capacitor C3, and the output (V out1 ) of the capacitive transimpedance amplifier 210 is routed through the buffer amplifier 228 that charges the filter capacitor C4. Due to the gain (G b = 1) of the buffer amplifier 228 equal to 1, the output voltage V out2 follows the voltage V out1 . When the output voltage V out2 stabilizes, its value is given by V out2 = V out1 + V os (1) . Note that V osV is the offset voltage of the buffer amplifier. When the value of C3 is low (small capacitance), the bandwidth of the capacitive transimpedance amplifier 210 may be relatively high, resulting in high readout noise in this phase. Furthermore, V out2 The noise level in V is due to the high current gain associated with the buffer amplifier 228. out1 The noise level can increase significantly in that case.

[0031] To initiate Phase 2, as shown in Figure 3, switch S3 transitions from High to Low, and switch S3-° transitions from Low to High. During Phase 2 (S1=High, S2=High, S3=Low, S3-°=High), the capacitive transimpedance amplifier 210 is connected to capacitors C1, C2, C3, and C4. Since the gain of the buffer amplifier 228 is equal to 1, the buffer amplifier 228 can drive large capacitances, and C4 can be made much larger than any of C1, C2, and C3. As a result, the bandwidth of the capacitive transimpedance amplifier 210 decreases due to the increased capacitance, especially when C4 is large. This can reduce readout noise in this phase. Furthermore, in Phase 2, switch S3 is opened, disconnecting the buffer amplifier 228. Thus, the offset voltage V of the buffer amplifier os Because V is removed, out1 =V out2 This is the result.

[0032] The operation of the circuit in Figure 2 in phases 3 and 4 is the same as in phases 1 and 2, respectively. The difference is that, as mentioned above, S1 is Low and the photocharge from photodiode 208 is transferred to the floating diffusion node 220 by the Tx gate 226. During phases 2 and 4, the buffer amplifier 228 may be turned off to save power. Towards the end of phase 4, as S2 changes from High to Low, the readout output is V out =V outp -V outm (2) (That is) it is given by the voltage difference between capacitors C1 and C2, as described above.

[0033] In relation to the column amplifier 200 in Figure 2, there are several drawbacks, particularly the persistent problem of high readout noise at higher readout frame rates. As mentioned above, maintaining a small C3 to achieve high bandwidth may be necessary for high frame rates, but it results in high readout noise during Phase 1. While using a large capacitor value for C4 can reduce readout noise in Phase 2, this reduces the bandwidth of the capacitive transimpedance amplifier 210, limiting the frame rate. Therefore, it may be necessary to keep C4 small for operation at high frame rates, resulting in still high readout noise.

[0034] Accordingly, the embodiments and designs address these drawbacks and provide a column readout amplifier that can operate with reduced readout noise compared to the column amplifier 200, particularly at high frame rates, at the same power consumption. Figure 4 is a circuit diagram of an example of a column readout amplifier 300 according to an embodiment of the present disclosure. For simplicity, elements of the column readout amplifier 300 that perform similar functions to those shown in Figure 2 for the column readout amplifier 200 are given the same reference numerals and will not be described in further detail. The signal timing of the column readout amplifier 300 is the same as that of the column readout amplifier 200 shown in Figure 3 and will therefore not be described further below.

[0035] Referring to Figure 4, as described above, a column readout amplifier 300 is shown, connected to the pixel sensor 202 and configured to read out the voltage corresponding to the photocharge accumulated by the pixel sensor 202. The column readout amplifier 300 includes a signal amplifier 302, which is a capacitive transimpedance amplifier in the illustrated example. The gain (G) of the signal amplifier 302 a) is greater than 1. The output of the signal amplifier is connected to the first terminal of the first capacitor 304 and, as in the configuration described above with reference to Figures 2 and 3, is switchably connected directly (when switch S3 is open and switch S3￣ is closed) or via buffer amplifier 308 (when switch S3 is closed and switch S3￣ is open) to the first terminal of the filter capacitor 306. The second terminals of capacitors 304 and 306 are connected to ground. Voltage V out2 As described above, the data is read out via analog memory (sample-and-hold circuit) by capacitors C1 and C2. In one example, as described above, the use of a pair of capacitors C1 and C2 for correlated double sampling (CDS) contributes to reducing low-frequency noise.

[0036] The buffer amplifier 308 may be a unitary gain amplifier (i.e., a gain G approximately equal to 1 within reasonable tolerances). b (having). Therefore, when the buffer amplifier 308 is connected to the output of the signal amplifier 302, as described above, the voltage V out2 Voltage V out1 To be continued. Voltage V out2 and voltage V out1 The difference is the noise from buffer amplifier 308 and the offset voltage V of the buffer amplifier. os This can also occur as a result of some slight difference in the gain of the buffer amplifier 308 relative to a gain of 1. Generally, the gain of the buffer amplifier 308 is set to substantially equal to 1. The amount by which the gain may differ from 1 depends on the degree of acceptable potential mismatch with respect to the filter capacitor 306. Any mismatch occurs when the voltage across the filter capacitor 306 after the switch S3 is opened is V out1 This may result in an increase in the time required to reach the target, and the amount of additional time generally depends on the specific application. The buffer amplifier 308 operates to accelerate the charging rate of the filter capacitor 306 during the readout phase when the buffer amplifier is connected to the output of the signal amplifier 302 (i.e., when switch S3 is closed and switch S3 is open).

[0037] In one example, the filter capacitor 306 may have a variable capacitance that can be increased or decreased depending on the application and current operating mode of the column readout amplifier 300. For example, in situations where the readout operation has a relatively low frame rate (e.g., about 30 fps), the bandwidth of the signal amplifier 302 can be reduced for the slow readout, so the capacitance of the filter capacitor 306 can be increased to reduce readout noise. As described above, the unit gain buffer amplifier 308 can drive high capacitances, so the capacitance value of the filter capacitor 306 can be significantly increased compared to that of C1, C2 and / or capacitor 304. In situations where the readout operation has a high frame rate and therefore a higher bandwidth is required for the signal amplifier 302, the capacitance of the filter capacitor 306 can be reduced. The variable capacitance value can be realized by implementing capacitor 306 with one or more variable capacitors and / or one or more switchable fixed-value capacitors that can be switchedly connected and disconnected to produce a desired combined capacitance value.

[0038] As mentioned above, in some examples, capacitor 304 may be selected to have a very small capacitance so that the signal amplifier 302 has a high bandwidth, which may be necessary for readout operations at high frame rates. Also, configuring capacitor 304 to have a very small capacitance value is possible when the amplifier gain is very high (for example, G a Even if it is approximately 32), the output voltage V from the signal amplifier 302 out1 This can contribute to faster settling. Faster settling time also makes it possible to perform readout operations at higher frame rates. However, as mentioned above, using a small capacitance capacitor 304 together with a small capacitance filter capacitor 306 for high frame rate readout operations can result in high readout noise.

[0039] To mitigate this problem, the column readout amplifier 300 includes a low-pass filter in the feedback path of the signal amplifier 302 (indicated by arrow 312). Figure 4 shows the input capacitor 214 (C) connected in series with the feedback path 312. in ) and capacitor 314(C f The gain G is given by the ratio of the capacities of ). a (G a =G in / C f The signal amplifier 302 is shown in high-gain mode at ). In one example, the gain G a This can be approximately 30, for example, 32. The low-pass filter includes a series resistor 316 connected in series with a capacitor 314, and a shunt capacitor 318 connected between the node between the series resistor 316 and the capacitor 314 and the ground point, as shown in the figure. By adding the low-pass filters 316, 318 in the feedback path, the total node 320 (V in Amplifier output voltage V for ) out1 The impact of noise is reduced. In other words, the low-pass filters 316 and 318 contribute to reducing the total noise at node 320, which in turn reduces the amplifier output V in the forward path. out1 This contributes to reducing noise in [the system].

[0040] In one example, in order to maintain the power consumption and amplifier slew rate of the signal amplifier 302, the capacitance of the shunt capacitor 318, which constitutes part of the low-pass filter, is much smaller than the capacitance of the filter capacitor 306. In one example, the capacitance of the shunt capacitor 318 is in the range of approximately 0.1 to 0.5 picofarads (pF), for example, 0.15pF, and the series resistor 316 has a resistance of approximately 200 kilohms (kΩ). The low-pass filters 316 and 318 have a readout frame rate of 120 fps (relative to the column readout amplifier 200) V out2 This can contribute to reducing readout noise by approximately 10%. At lower frame rates, the capacitance value of filter capacitor 306 can become very large as described above, so the voltage V out1 and V out2The noise level in can be lower. However, the addition of low-pass filters 316 and 318 still works to reduce noise in the column readout amplifier 200. For example, the low-pass filters 316 and 318 reduce noise in the V at a readout frame rate of 30 fps. out2 This can contribute to reducing readout noise by approximately 5% (compared to column readout amplifier 200). Simulations confirmed the reduction in readout noise of column readout amplifier 300 compared to column readout amplifier 200 under the same conditions.

[0041] Figure 5 is a graph showing the noise simulation results at 120 fps for an example of a column readout amplifier 200 (curve 502) and an example of a column readout amplifier 300 (curve 504) under the same conditions. It can be seen that the readout noise associated with the column readout amplifier 300 is reduced compared to the readout noise associated with the column amplifier 200.

[0042] Accordingly, the embodiments and models provide a column readout amplifier that contributes to reducing readout noise at high frame rates without increasing power consumption. Embodiments of the column readout amplifier 300 can be used as a column readout amplifier 120 in an image sensor 100 to enable the image sensor to operate with lower noise and therefore higher sensitivity, which can be advantageous in a number of applications, particularly in low-light imaging applications.

[0043] Exemplary computing platform Figure 6 shows an exemplary computing platform 600 that interfaces with an image sensor 100 configured according to one embodiment of the present disclosure. In some embodiments, the computing platform 600 may host or be incorporated into personal computers, workstations, server systems, laptop computers, ultralaptop computers, tablets, touchpads, portable computers, handheld computers, palmtop computers, personal digital assistants (PDAs), mobile phones, mobile phone and PDA combinations, smart devices (e.g., smartphones or smart tablets), mobile internet devices (MIDs), messaging devices, data communication devices, imaging devices, wearable devices, embedded systems, etc. Any combination of various devices may be used in a particular embodiment. The computing platform 600 may host a Controller Area Network (CAN) used in a vehicle. In some embodiments, the computing platform 600 represents one system in a network of systems interconnected via a CAN bus.

[0044] In some embodiments, the computing platform 600 may comprise any combination of a processor 602, memory 604, an image sensor 100 (as defined in the embodiment), a network interface 606, an input / output (I / O) system 608, a user interface 610, and a storage system 612. In some embodiments, one or more components of the image sensor 100 are implemented as part of the processor 602. As shown in Figure 6, buses and / or interconnects are also provided to enable communication between the various components listed above and / or other components not shown. The computing platform 600 is made connectable to a network 616 via the network interface 606 to enable communication with other computing devices, platforms, or resources. Other components and functions not reflected in the block diagram of Figure 6 should be obvious in light of this disclosure, and it should be clear that other embodiments are not limited to a specific hardware configuration.

[0045] The processor 602 may be any suitable processor and may include one or more coprocessors or controllers that assist in control and processing operations related to the computing platform 600. In some embodiments, the processor 602 may be implemented as any number of processor cores. The processor (or processor core) may be any type of processor, such as a microprocessor, embedded processor, digital signal processor (DSP), graphics processor (GPU), network processor, field-programmable gate array, or other device configured to execute code. The processor may be a multithreaded core that may include two or more hardware thread contexts (i.e., “logical processors”) per core. In some examples, the processor 602 may include or be part of the processor 140 described above.

[0046] Memory 604 can be implemented using any appropriate type of digital storage, such as flash memory and / or random access memory (RAM). In some embodiments, memory 604 may include various layers of memory hierarchy and / or memory cache, which are well known to those skilled in the art. Memory 604 may be implemented as a volatile memory device, such as RAM, dynamic RAM (DRAM), or static RAM (SRAM) devices, but is not limited to these. Storage system 612 may be implemented as a non-volatile storage device, such as one or more hard disk drives (HDDs), solid-state drives (SSDs), universal serial bus (USB) drives, optical disk drives, tape drives, internal storage devices, external storage devices, flash memory, battery-backed synchronous DRAM (SDRAM), and / or network-accessible storage devices, but is not limited to these. In some embodiments, storage system 612 may include techniques to enhance protection of valuable digital media by improving storage performance when multiple hard drives are included.

[0047] Processor 602 may be configured to run an operating system (OS) 614 which may include any appropriate operating system such as Google Android® (Google, Inc., Mountain View, California), Microsoft Windows® (Microsoft Corporation, Redmond, Washington), Apple OS X (Apple Inc., Cupertino, California), Linux®, or a Real-Time Operating System (RTOS). As can be seen in light of this disclosure, the technology provided herein is implementable regardless of the specific operating system provided in conjunction with the computing platform 600, and therefore may be implemented using any appropriate existing or subsequently developed platform.

[0048] The network interface 606 may be any suitable network chip or chipset that enables wired and / or wireless connections between the computing platform 600 and / or other components of the network 616, thereby enabling the computing platform 600 to communicate with other local and / or remote computing systems, servers, cloud-based servers and / or other resources. Wired communication may conform to existing (or undeveloped) standards such as Ethernet. Wireless communication may conform to existing (or undeveloped) standards such as LTE (Long-Term Evolution), Wireless Fidelity (Wi-Fi), Bluetooth and / or Near Field Communication (NFC). Illustrative wireless networks include, but are not limited to, wireless local area networks, wireless personal area networks, wireless metropolitan area networks, cellular networks and satellite networks.

[0049] The I / O system 608 may be configured to interface between various I / O devices of the computing platform 600 and other components. The I / O devices may include, but are not limited to, a user interface 610. The user interface 610 may include devices (not shown) such as a display element, touchpad, keyboard, mouse, and speaker. The I / O system 608 may include a graphics subsystem configured to perform image processing for rendering on the display element. The graphics subsystem may be, for example, a graphics processing unit or a visual processing unit (VPU). Analog or digital interfaces may be used to connect the graphics subsystem and the display element in a communicative manner. For example, the interface may be any of the following: High-Definition Multimedia Interface (HDMI®), DisplayPort, Wireless HDMI, and / or any other suitable interface using wireless high-definition technology. In some embodiments, the graphics subsystem may be integrated into the processor 602 or any chipset of the computing platform 600.

[0050] In some embodiments, it will be apparent that various components of the computing platform 600 may be combined or integrated into a system-on-a-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0051] In various embodiments, the computing platform 600 may be implemented as a wireless system, a wired system, or a combination of both. When implemented as a wireless system, the computing platform 600 may include components and interfaces suitable for communication over a wireless shared medium, such as one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, and control logic. Examples of a wireless shared medium may include a portion of the radio spectrum, such as the radio frequency spectrum. When implemented as a wired system, the computing platform 600 may include components and interfaces suitable for communication over a wired communication medium, such as input / output adapters, physical connectors connecting the input / output adapters to the corresponding wired communication medium, network interface cards (NICs), disk controllers, video controllers, and audio controllers. Examples of a wired communication medium may include wiring, cable metal leads, printed circuit boards (PCBs), backplanes, switch fabrics, semiconductor materials, twisted pair wires, coaxial cables, and fiber optics.

[0052] Unless otherwise specified, terms such as “process,” “computing,” “calculating,” and “determine / identify / decide” can be understood to mean the operation and / or processing of a computer or computer system or similar electronic computing device that manipulates and / or converts data represented as physical quantities (e.g., electronic quantities) in the registers and / or memory units of a computer system into other data similarly represented as physical quantities in the registers, memory units, or other such information storage and transmission units or displays of a computer system. Embodiments are not limited to this background.

[0053] In any embodiment, the terms “circuit” or “circuits” as used herein may include, for example, hardwired circuits, programmable circuits such as a computer processor having one or more individual instruction processing cores, state-machine circuits, and / or firmware that stores instructions executed by programmable circuits, either alone or in any combination. Circuits may include processors and / or controllers configured to execute one or more instructions that perform one or more of the operations described herein. Instructions may be implemented, for example, as applications, software, firmware, etc., configured to cause the circuits to perform any of the operations described herein. Software may be implemented as software packages, code, instructions, instruction sets, and / or data recorded in a computer-readable storage device. Software may be implemented or performed to include any number of operations, and operations may be implemented or performed to include any number of threads, etc., in a hierarchical manner. Firmware may be implemented as (e.g., non-volatile) code, instructions or instruction sets, and / or data hard encoded in a memory device. Circuits can be implemented collectively or individually as part of a larger system, such as integrated circuits (ICs), application-specific integrated circuits (ASICs), system-on-a-chip (SoCs), desktop computers, laptop computers, tablet computers, servers, and smartphones. Other embodiments can be implemented as software executed by a programmable control device. Various embodiments can be implemented using hardware elements, software elements, or any combination thereof, as described herein. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, and chipsets.

[0054] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, programmable logic devices, digital signal processors, FPGAs, GPUs, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The decision of whether an embodiment is implemented using hardware elements and / or software elements may depend on any number of factors, such as the desired computing speed, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints.

[0055] Additional examples Embodiment 1 is a column readout amplifier comprising: a signal amplifier having an amplifier output section, a first amplifier input section, and a second amplifier input section, wherein the second amplifier input terminal is connected to a reference voltage terminal; a filter capacitor having first and second terminals, wherein the second terminal is connected to a ground terminal; a buffer amplifier having a buffer amplifier input section and a buffer amplifier output section; a switching network configured to switchably connect the amplifier output section to the buffer amplifier input section and the buffer amplifier output section to the first terminal of the filter capacitor during a first period, and to switchably connect the amplifier output terminal directly to the first terminal of the filter capacitor during a second period; and a low-pass filter connected between the amplifier output section and the first amplifier input section in the feedback path of the signal amplifier, the low-pass filter including a series resistor and a capacitor.

[0056] Embodiment 2 includes the column readout amplifier of Embodiment 1, and further comprises a capacitor connected between the amplifier output section and the ground terminal.

[0057] Embodiment 3 includes a column readout amplifier of either Embodiment 1 or 2, and further comprises a feedback capacitor connected in series with the series resistor in the feedback path of the signal amplifier.

[0058] Example 4 includes the column readout amplifier of Example 3, wherein the signal amplifier comprises a capacitive transimpedance amplifier configured with a gain greater than 1.

[0059] Embodiment 5 includes one of the column readout amplifiers of Embodiments 3 and 4, wherein the capacitor is connected between the node between the series resistor and the feedback capacitor and the ground terminal.

[0060] Example 6 includes a column readout amplifier from any one of Examples 1 to 5, wherein the capacitance of the capacitor is less than the capacitance of the filter capacitor.

[0061] Example 7 includes the column readout amplifier of Example 6, wherein the capacitance of the filter capacitor is variable.

[0062] Example 8 includes a column readout amplifier from any one of Examples 1 to 7, wherein the buffer amplifier output is disconnected from the filter capacitor during the second period.

[0063] Example 9 includes a column readout amplifier from any one of Examples 1 to 8, wherein the buffer amplifier has a gain substantially equal to 1.

[0064] Example 10 includes a column readout amplifier from any one of Examples 1 to 9, and further comprises an input capacitor connected to the first input of the signal amplifier.

[0065] Embodiment 11 is an image sensor comprising: a bit line conductor; a pixel array having at least one row of addressable pixel sensors, each pixel sensor being connected to the bit line conductor in accordance with a word selection signal; and a column amplifier connected to the bit line conductor, the column amplifier comprising: a signal amplifier having an amplifier output section, a first amplifier input section, and a second amplifier input section, the second amplifier input section being connected to a reference voltage terminal; a filter capacitor having first and second terminals, the second terminal being connected to a ground terminal; a buffer amplifier having a buffer amplifier input section and a buffer amplifier output section; a switching network configured to switchably connect the amplifier output section to the buffer amplifier input section and the buffer amplifier output section to the first terminal of the filter capacitor during a first period, and to switchably connect the amplifier output section directly to the first terminal of the filter capacitor during a second period; and a low-pass filter connected between the amplifier output section and the first amplifier input section in the feedback path of the signal amplifier, the low-pass filter comprising a series resistor and a capacitor.

[0066] Example 12 includes the image sensor from Example 11 and further comprises a capacitor connected between the amplifier output section and the ground terminal.

[0067] Example 13 includes one of the image sensors from Examples 11 and 12, and further comprises a feedback capacitor connected in series with the series resistor in the feedback path of the signal amplifier.

[0068] Example 14 includes the image sensor of Example 13, and the signal amplifier comprises a capacitive transimpedance amplifier configured with a gain greater than 1.

[0069] Example 15 includes one of the image sensors from Examples 13 and 14, wherein the capacitor is connected between the node between the series resistor and the feedback capacitor and the ground terminal.

[0070] Example 16 includes one of the image sensors from Examples 11 to 15, wherein the capacitance of the capacitor is less than the capacitance of the filter capacitor.

[0071] Example 17 includes the image sensor from Example 16, and the capacitance of the filter capacitor is variable.

[0072] Example 18 includes one image sensor from any one of Examples 11 to 17, wherein the buffer amplifier output is disconnected from the filter capacitor during the second period.

[0073] Example 19 includes any one image sensor from Examples 11 to 18, wherein the buffer amplifier has a gain substantially equal to 1.

[0074] Example 20 includes an image sensor from any one of Examples 11 to 19, and further comprises an input capacitor connected to the first input of the signal amplifier.

[0075] While several aspects of at least one embodiment have been described, it should be understood that various changes, modifications, and improvements will be readily apparent to those skilled in the art. Such changes, modifications, and improvements will be part of the disclosure and will be within the scope of the invention. Accordingly, the above descriptions and drawings of various embodiments are presented for illustrative purposes only. These examples are not exclusive, nor do they limit the invention to the exact forms disclosed. The methods and apparatus are implementable in other embodiments and can be implemented or performed in various ways. Furthermore, the language and terminology used herein are for illustrative purposes only and should not be considered limiting. Any singular reference to an example, component, element, or operation / function of a system or method referred herein may include plural examples, and any plural reference to an example, component, element, or operation / function referred herein may include singular examples only. The singular or plural references do not limit the systems or methods, their components, operations / functions, or elements actually disclosed. The use of “includes,” “equips,” “possesses,” “contains,” “accompanies,” and their variations herein is intended to encompass the matters listed thereafter, their equivalents, and additional matters. References to “or / or” may be interpreted as inclusive, so that any term written using “or / or” may refer to one, two or more, or all of the terms written. The scope of the invention should be determined by the appropriate interpretation of the appended claims and their equivalents.

Claims

1. A column readout amplifier, A signal amplifier having an amplifier output section, a first amplifier input section, and a second amplifier input section, wherein the second amplifier input section is connected to a reference voltage terminal, A filter capacitor having a first terminal and a second terminal, wherein the second terminal is connected to a ground terminal, A buffer amplifier having a buffer amplifier input section and a buffer amplifier output section, A switching network configured such that, in the first period, the amplifier output section is switchably connected to the buffer amplifier input section, and the buffer amplifier output section is switchably connected to the first terminal of the filter capacitor, and in the second period, the amplifier output section is switchably connected directly to the first terminal of the filter capacitor, A low-pass filter connected between the amplifier output section and the first amplifier input section in the feedback path of the signal amplifier, the low-pass filter including a series resistor and a capacitor, A column readout amplifier equipped with the following features.

2. The column readout amplifier according to claim 1, further comprising a capacitor connected between the amplifier output section and the ground terminal.

3. The column readout amplifier according to claim 1, further comprising a feedback capacitor connected in series with the series resistor in the feedback path of the signal amplifier.

4. The column readout amplifier according to claim 3, wherein the signal amplifier comprises a capacitive transimpedance amplifier configured with a gain greater than 1.

5. The column readout amplifier according to claim 3, wherein the capacitor is connected between the node between the series resistor and the feedback capacitor and the ground terminal.

6. The column readout amplifier according to claim 1, wherein the capacitance of the capacitor is less than the capacitance of the filter capacitor.

7. The column readout amplifier according to claim 6, wherein the capacitance of the filter capacitor is variable.

8. The column readout amplifier according to claim 1, wherein the buffer amplifier output section is disconnected from the filter capacitor during the second period.

9. The column readout amplifier according to claim 1, wherein the buffer amplifier has a gain substantially equal to 1.

10. The column readout amplifier according to claim 1, further comprising an input capacitor connected to the first amplifier input of the signal amplifier.

11. Bitline conductor and, A pixel array having at least one row of addressable pixel sensors, wherein each pixel sensor is connected to the bit line conductor in accordance with a word selection signal, A column amplifier connected to the bit line conductor, Equipped with, The aforementioned column amplifier, A signal amplifier having an amplifier output section, a first amplifier input section, and a second amplifier input section, wherein the second amplifier input section is connected to a reference voltage terminal, A filter capacitor having a first terminal and a second terminal, wherein the second terminal is connected to a ground terminal, A buffer amplifier having a buffer amplifier input section and a buffer amplifier output section, A switching network configured such that, in the first period, the amplifier output section is switchably connected to the buffer amplifier input section, and the buffer amplifier output section is switchably connected to the first terminal of the filter capacitor, and in the second period, the amplifier output section is switchably connected directly to the first terminal of the filter capacitor, A low-pass filter connected between the amplifier output section and the first amplifier input section in the feedback path of the signal amplifier, the low-pass filter including a series resistor and a capacitor, An image sensor equipped with the following features.

12. The image sensor according to claim 11, further comprising a capacitor connected between the amplifier output section and the ground terminal.

13. The image sensor according to claim 11, further comprising a feedback capacitor connected in series with the series resistor in the feedback path of the signal amplifier.

14. The image sensor according to claim 13, wherein the signal amplifier comprises a capacitive transimpedance amplifier configured with a gain greater than 1.

15. The image sensor according to claim 13, wherein the capacitor is connected between the node between the series resistor and the feedback capacitor and the ground terminal.

16. The image sensor according to claim 11, wherein the capacitance of the capacitor is less than the capacitance of the filter capacitor.

17. The image sensor according to claim 16, wherein the capacitance of the filter capacitor is variable.

18. The image sensor according to claim 11, wherein the buffer amplifier output section is disconnected from the filter capacitor during the second period.

19. The image sensor according to claim 11, wherein the buffer amplifier has a gain substantially equal to 1.

20. The image sensor according to claim 11, further comprising an input capacitor connected to the first amplifier input section of the signal amplifier.

Images