Wiring board

Abstract

To provide a wiring board that has high adhesion between a board and a wiring.SOLUTION: A wiring board 100 includes: a substrate 102 containing a first element; a diffusion layer 106 in contact with the substrate and containing a first metal element; and a first metal film 104 in contact with the diffusion layer and containing a second metal element. The diffusion layer has a region containing at least the first element and the first metal element, and a region containing the first metal element and the second metal element. The concentration of the second metal element in the diffusion layer may decrease as it approaches the substrate in the thickness direction. The concentration of the first element in the diffusion layer may decrease as it approaches the first metal film in the thickness direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0004] , , , , , ,

[0005]

[0001] The present disclosure relates to a wiring board in which wirings are formed on a substrate, a method for manufacturing the wiring board, and a semiconductor device including the wiring board.

Background Art

[0002] Electronic devices usually use a basic structure including a substrate and wirings provided thereon (hereinafter referred to as a wiring board). Such a wiring board not only functions as a semiconductor device itself, but is also widely applied as a substrate for electrically connecting various electronic components or as a substrate (interposer) for mounting a semiconductor device on an electronic device. Various methods for providing wirings on a substrate have been developed. For example, in the methods disclosed in Patent Documents 1 and 2, a film containing a metal oxide is provided between an insulating substrate and the wirings, thereby improving the adhesion between the substrate and the wirings.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

[0006] One embodiment of the present disclosure is a method for manufacturing a wiring board. This manufacturing method includes forming a first intermediate layer containing an oxide of a first metal element on a substrate containing the first element, converting the first intermediate layer into a second intermediate layer by diffusing the first element into the first intermediate layer, forming a first metal film containing a second metal element on the second intermediate layer, and converting the second intermediate layer into a diffusion layer by diffusing the second metal element into the second intermediate layer. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic cross-sectional view of a wiring board according to one embodiment, and a schematic diagram of the density profile in the thickness direction of the wiring board. [Figure 2] A schematic diagram of the elemental concentration profile in the thickness direction of a wiring board according to one embodiment. [Figure 3] A schematic diagram of the elemental concentration profile in the thickness direction of a wiring board according to one embodiment. [Figure 4] A schematic diagram of the elemental concentration profile in the thickness direction of a wiring board according to one embodiment. [Figure 5] A schematic diagram of the elemental concentration profile in the thickness direction of a wiring board according to one embodiment. [Figure 6] A schematic cross-sectional view of a wiring board according to one embodiment. [Figure 7] A schematic cross-sectional view showing a method for manufacturing a wiring board according to one embodiment. [Figure 8] A schematic cross-sectional view showing a method for manufacturing a wiring board according to one embodiment. [Figure 9] A schematic cross-sectional view showing a method for manufacturing a wiring board according to one embodiment. [Figure 10] A schematic cross-sectional view showing a method for manufacturing a wiring board according to one embodiment. [Figure 11] A schematic cross-sectional view of a semiconductor device including a wiring board according to one embodiment. [Figure 12] A schematic cross-sectional view of a semiconductor device including a wiring board according to one embodiment. [Figure 13] A schematic cross-sectional view of a semiconductor device including a wiring board according to one embodiment. [Figure 14] Energy-dispersive X-ray analysis results of a wiring board according to one embodiment. [Modes for carrying out the invention]

[0008] The embodiments of this disclosure will be described below with reference to the drawings and other illustrations. However, this disclosure can be implemented in various ways without departing from its essence, and should not be construed as being limited to the embodiments described below.

[0009] While drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation, these are merely examples and do not limit the interpretation of this disclosure. In this specification and in each drawing, elements having the same function as those described in previously shown drawings are denoted by the same reference numerals, and redundant explanations may be omitted.

[0010] In this specification and the claims, when describing a configuration in which one structure is placed above or below another structure, unless otherwise specified, the terms "above" or "below" include both cases: one in which the other structure is placed directly above or below another structure so as to be in contact with it, and another in which the other structure is placed above or directly below another structure via yet another structure.

[0011] In this specification and the claims, the expression "a certain structure is exposed from another structure" means a mode in which a part of a certain structure is not covered by another structure, and the part not covered by this other structure also includes a mode in which it is covered by yet another structure.

[0012] (First Embodiment) In this embodiment, the wiring board 100 according to one of the embodiments of the present disclosure will be described.

[0013] 1. Basic Structure A cross-sectional schematic view of the wiring board 100 is shown in FIG. 1(A). The wiring board 100 includes a substrate 102, a diffusion layer 106 located on the substrate 102 and in contact with the substrate 102, and a first metal film 104 located on the diffusion layer 106 and in contact with the diffusion layer 106. The wiring board 100 may further include a second metal film 108 located on the first metal film 104 and in contact with the first metal film 104 in an arbitrary configuration.

[0014] The substrate 102 contains a first element. Here, the first element is selected from elements other than oxygen and is an element included in the main component of the substrate 102. In this specification and the claims, the main component of a certain configuration is a component that occupies 90% by weight or more of that configuration. Examples of the substrate 102 include a glass substrate, a quartz substrate, a semiconductor substrate including a semiconductor such as silicon, germanium, gallium arsenide, or gallium nitride, a ceramic substrate including a ceramic such as alumina or zirconia, and a substrate including a single crystal metal oxide such as a sapphire substrate. In the case of a substrate having glass as the main component, a resin may be compounded. When using the above-described substrates, the first element is selected from silicon, germanium, aluminum, zirconium, arsenic, nitrogen, and the like.

[0015] Among the above-described substrates, a glass substrate is preferably used when the wiring board 100 is used as an interposer of a semiconductor device because it can be obtained at a low cost and exhibits excellent insulation properties. Examples of the glass included in the glass substrate include soda-lime glass, fluoride glass, phosphate glass, and borate glass.

[0016] There are no restrictions on the surface roughness of the substrate 102; for example, it may be 0.1 nm or more, 1 nm or more, or 5 nm or more. The surface roughness of the substrate 102 may also be 200 nm or less, 100 nm or less, or 50 nm or less. The surface roughness of the substrate 102 may also be 0.1 nm to 200 nm, 1 nm to 100 nm, or 5 nm to 50 nm. The surface roughness can be measured, for example, using an optical interference microscope. When relatively thin wiring is provided on the substrate 102, the surface roughness of the substrate 102 is reflected on the surface of the wiring. However, by adjusting the surface roughness of the substrate 102 to the range described above, the increase in the surface roughness of the wiring is also suppressed. Therefore, when the wiring substrate 100 is applied to a high-frequency circuit board, transmission loss can be reduced. Furthermore, when the wiring is processed by photolithography, scattering of light from the exposure machine can be suppressed, preventing interference with the microfabrication of the wiring.

[0017] Here, surface roughness can be evaluated by the arithmetic mean roughness Ra, which is a parameter expressed by the following formula. In this formula, L is the measurement length on the substrate 102 being evaluated, and f(x) is the height when the measurement length direction is x. Ra is the absolute value of the height at the measurement length averaged over the measurement length.

number

[0018] An example of a method for measuring the arithmetic mean roughness Ra is as follows. First, select multiple arbitrary measurement areas on the substrate 102. The size of the measurement area can be, for example, a rectangle of 0.30 mm × 0.22 mm. For example, five locations on the substrate 102, the four corners and the center, can be selected as measurement areas. Next, set any two points in each of the multiple areas. The distance between these two points should be 0.1 mm, which corresponds to the measurement length L. Measure the arithmetic mean roughness Ra between these two points, and use the average of the arithmetic mean roughness Ra obtained from the multiple measurement areas as the surface roughness of the substrate 102. For example, if five locations on the substrate 102, the four corners and the center, are selected as measurement areas, the average of the five measurement results will be the surface roughness of the substrate 102. Alternatively, multiple measurements can be performed in each measurement area, and their average can be used as the arithmetic mean roughness Ra for a single measurement area. The arithmetic mean roughness Ra can be measured using a 3D optical profiler that employs a white light interferometer, for example (such as the Zygo New View5000 3D optical profiler from Zygo).

[0019] The first metal film 104 contains a zero-valent metal element (second metal element) and can function as wiring for the wiring substrate 100, or as a seed layer for forming the second metal film 108 or various wirings (not shown) provided on the wiring substrate 100 by electroplating. Examples of the second metal element include copper, titanium, chromium, nickel, and gold. There are no restrictions on the thickness of the first metal film 104; for example, it can be 0.5 μm or more, 1 μm or more, or 5 μm or more, and can be 50 μm or less, 30 μm or less, or 20 μm or less. The thickness of the first metal film 104 may be 0.5 μm or more and 50 μm or less, 1 μm or more and 30 μm or less, or 5 μm or more and 20 μm or less. By setting the thickness of the first metal film 104 within this range, it is possible to ensure sufficient conductivity as wiring. Furthermore, even when the first metal film 104 is formed by a plating method, for example, it can be formed in a short time, and even when the first metal film 104 is formed by photolithography, microfabrication can be easily performed.

[0020] The diffusion layer 106 has the function of firmly adhering the first metal film 104 to the substrate 102, and is therefore also called the adhesion layer. The diffusion layer 106 is formed by the interdiffusion of an intermediate layer provided between the first metal film 104 and the substrate 102. The intermediate layer contains a first metal element. For example, the intermediate layer contains an oxide or nitride of the first metal, and examples of the first metal include zinc, titanium, zirconium, aluminum, and tin. The region of the intermediate layer containing the first metal is defined as the diffusion layer 106. The thickness of the diffusion layer 106 may be 1 nm or more. This allows the diffusion layer 106 to follow the surface roughness of the substrate 102, ensuring high adhesion between the first metal film 104 and the substrate 102, and also allowing for microfabrication to be performed simultaneously with the first metal film 104. The thickness of the diffusion layer 106 may be 1 μm or less, 100 nm or less, 20 nm or less, or 10 nm or less. The thickness of the diffusion layer 106 may be 1 nm to 1 μm, 1 nm to 100 nm, 1 nm to 20 nm, or 1 nm to 10 nm. This allows the diffusion layer 106 to be formed in a short time, and ensures that no etching residue remains on the substrate 102 during processing such as etching, and provides reliable insulation between adjacent wirings. For example, if the arithmetic mean roughness Ra of the substrate 102 is 5 nm, the thickness of the diffusion layer 106 can be set in the range of 10 nm to 20 nm.

[0021] 2. Composition of the diffusion layer The diffusion layer 106 further contains, in addition to the first metal element, the first element contained in the substrate 102 and the second metal element contained in the first metal film 104. More specifically, the diffusion layer 106 includes at least one of the following regions: a region where the first element, the first metal element, and the second metal element coexist; a region where the first metal element and the first element coexist; and a region where the first metal element and the second metal element coexist. For example, the diffusion layer 106 may have a region containing the first metal element and the first element, and a region containing the first metal element and the second metal element.

[0022] Therefore, the thickness of the diffusion layer 106 does not necessarily coincide with the thickness of the intermediate layer, and can be defined as the thickness of the portion where at least one of the three regions described above exists. In this case, the thickness can be measured by energy-dispersive X-ray (EDX) analysis. Specifically, a sample in which at least the diffusion layer 106 and the first metal film 104 are arranged on the substrate 102 is processed using a focused ion beam (FIB) to expose the cross-section, and an electron beam is irradiated from the substrate 102 side so as to scan the interfaces between each layer, and characteristic X-rays are detected using a Si drift detector or the like. The atomic composition percentage (atomic%) of each element is obtained based on the intensity of the characteristic X-rays. This provides the elemental distribution in the depth direction, and the above regions are identified. The thickness of the diffusion layer 106 can be determined by calculating the thickness of the portion where at least one of these regions exists.

[0023] Figure 1(B) schematically shows the concentration profiles of the first element, the first metallic element, and the second metallic element in the thickness direction of the wiring substrate 100. In Figures 1(B) to 5(B) below, the vertical axis represents the normalized elemental concentration (i.e., the number of atoms of the first element, the first metallic element, and the second metallic element per unit volume), and the horizontal axis represents the depth of the wiring substrate 100. Depth is the distance from the top surface of the first metal film 104 in the direction toward the substrate 102, along the normal to the top surface of the first metal film 104.

[0024] As shown in Figure 1(B), the concentration 102a of the first element decreases in the thickness direction as it approaches the first metal film 104 from the interface 103 between the substrate 102 and the diffusion layer 106. Similarly, the concentration 104a of the second metal element decreases in the thickness direction as it approaches the substrate 102 from the interface 105 between the diffusion layer 106 and the first metal film 104. These concentration changes may be continuous. Here, interface 103 is the surface located between the region where the first metal element is absent or substantially undetectable and the region where the first metal element is present or detectable, and is closer to the substrate 102 than to the first metal film 104. Interface 105 is the surface located between the region where the first metal element is absent or substantially undetectable and the region where the first metal element is present or detectable, and is closer to the first metal film 104 than to the substrate 102 (see Figure 1(B)). The area between these interfaces 103 and 105 is a diffusion layer 106, and in the diffusion layer 106, the plot of the concentration 106a of the first metal element against depth gives at least one peak (Figure 1(B)).

[0025] Therefore, in the diffusion layer 106, the plot of the concentration 104a of the second metal element against the depth of the wiring substrate 100 (dotted line in Figure 1(B)) intersects with the plot of the first element against the depth (dashed line in Figure 1(B)). The concentrations 102a of the first element, 106a of the first metal element, and 104a of the second metal element can be measured, for example, by EDX analysis.

[0026] In the example shown in Figure 1(B), the concentration 104a of the second metal element decreases as it approaches the substrate 102 within the diffusion layer 106, becoming virtually undetectable at the interface 103. Similarly, the concentration 102a of the first element decreases as it approaches the first metal film 104 within the diffusion layer 106, becoming virtually undetectable at the interface 105. In other words, the first element, the first metal element, and the second metal element coexist throughout the diffusion layer 106.

[0027] The concentration profiles of the first element and the second metal element in the diffusion layer 106 are not limited to those shown in Figure 1(B). For example, as shown in Figure 2(A), the diffusion layer 106 may have a region 106b on the interface 105 side in which the first element is absent or substantially undetectable. Alternatively, as shown in Figure 2(B), the diffusion layer 106 may have a region 106c on the interface 103 side in which the second metal element is absent or substantially undetectable.

[0028] Alternatively, as shown in Figure 3(A), the second metal element may be contained not only in the diffusion layer 106 but also in the substrate 102. In this case, the concentration 104a of the second metal element in the substrate 102 decreases as you move away from the interface 103. Conversely, the first element may be contained not only in the diffusion layer 106 but also in the first metal film 104 (Figure 3(B)). In this case, the concentration 102a of the first element in the first metal film 104 decreases as you move away from the interface 105.

[0029] The diffusion layer 106 may be configured such that the concentration profiles described above are combined. For example, as shown in Figure 4(A), the diffusion layer 106 may have both region 106b and region 106c on the interface 105 side and 103 side, respectively. In this case, the region in the diffusion layer 106 where the first element, the first metal element, and the second metal element coexist is sandwiched between regions 106b and 106c.

[0030] Alternatively, as shown in Figure 4(B), the diffusion layer 106 may have a region 106c, and the first element may be contained not only in the diffusion layer 106 but also in the first metal film 104. Conversely, as shown in Figure 5(A), the diffusion layer 106 may have a region 106b, and the second metal element may be contained not only in the diffusion layer 106 but also in the substrate 102. Alternatively, as shown in Figure 5(B), the first element may be contained not only in the diffusion layer 106 but also in the first metal film 104, and the second metal element may be contained not only in the diffusion layer 106 but also in the substrate 102.

[0031] Regardless of the concentration profile, in the diffusion layer 106, the plot of the concentration 104a of the second metal element against the depth of the wiring substrate 100 intersects with the plot of the concentration of the first element against the depth. Therefore, in every region of the diffusion layer 106, in addition to the first metal element, at least one of the first and second metal elements is present, and there are no regions where the first metal element is present but neither the first nor the second metal element is present.

[0032] 3. Variant As shown in Figure 6(A), the substrate 102 of the wiring board 100 may have through holes 110. In this case, the diffusion layer 106 and the first metal film 104 are provided so as to cover the upper and lower surfaces of the substrate 102 and the side walls of the through holes 110. A second metal film 108, which is provided in an optional configuration, may also be arranged to cover the upper and lower surfaces of the substrate 102 and the side walls of the through holes 110. If the entire through hole 110 is not blocked by the first metal film 104 or the second metal film 108, a filler material 112 may be formed to fill the through hole 110. Examples of filler material 112 include organic compounds such as epoxy resin, acrylic resin, polyimide, polyamide, and polyester. Inorganic materials such as silicon dioxide may be mixed into the organic compound. Alternatively, as shown in Figure 6(B), the second metal film 108 or the first metal film 104 may be provided to block the through hole 110. As will be described later, the first metal film 104, or the lamination of the first metal film 104 and the second metal film 108, can function as through-wiring for electrically connecting various elements and semiconductor devices mounted on the substrate 102.

[0033] In the wiring substrate 100 having the above-described configuration, as experimentally demonstrated in the embodiment, a large adhesive force is obtained between the substrate 102 and the first metal film 104 due to the presence of the diffusion layer 106. Furthermore, since there are substantially no regions in the diffusion layer 106 where the oxide of the first element exists alone, the diffusion layer 106 has higher etching resistance compared to a film that has regions consisting substantially only of the oxide of the first element. For this reason, the diffusion layer 106 exhibits an etching rate similar to that of the first metal film 104, and etching of the diffusion layer 106 located beneath the first metal film 104 (side etching) is less likely to occur during etching of the first metal film 104. In particular, when the diffusion layer 106 has regions where the first element, the first metal element, and the second metal element coexist, there are no intermediate layers that exist alone, so such side etching is prevented and high adhesive force can be achieved. As a result, the phenomenon of the first metal film 104 peeling off from the substrate 102 can be effectively suppressed, and a highly reliable wiring substrate and a semiconductor device including the same can be provided.

[0034] (Second Embodiment) This embodiment describes the method for manufacturing the wiring board 100 as described in the first embodiment. Configurations that are the same as or similar to those described in the first embodiment may be omitted from the description.

[0035] First, a first intermediate layer 120, which will serve as a precursor for the diffusion layer 106, is formed on the substrate 102-1 (Figure 7, S1). The first intermediate layer 120 contains an oxide of a first element and is formed by sputtering, physical vapor deposition (PVP) methods such as electron beam deposition or vacuum deposition, or the sol-gel method. When using the sol-gel method, metal alkoxides such as tetraethylzinc, tetraethoxytitanium, or tetraethoxyzirconium are used as raw materials, and a solution or mixture containing these is applied to the substrate 102-1 by spin coating, dip coating, printing, etc., and then the first intermediate layer 120 is formed by hydrolysis of the metal alkoxide. The thickness of the first intermediate layer 120 can be 5 nm or more, and may be 20 nm or 15 nm or less. The thickness of the first intermediate layer 120 may be 5 nm or more and 20 nm or less, or 5 nm or more and 15 nm or less.

[0036] The thickness of the intermediate layer can be measured using the thin-film calibration curve method. Specifically, first, a metal thin film containing the metal included in the intermediate layer 120, with a known thickness, is used as a standard sample, and the fluorescence X-ray intensity obtained by irradiating it with X-rays is measured. Using multiple samples of different thicknesses, a calibration curve showing the relationship between thickness and fluorescence X-ray intensity is prepared. Next, the same measurement is performed on the intermediate layer 120 formed on the substrate 102, and the thickness is estimated from the obtained fluorescence X-ray intensity using the calibration curve. In this measurement as well, measurements are performed in multiple regions of the intermediate layer 120, and the value obtained by averaging the thicknesses obtained in each region can be adopted as the thickness of the intermediate layer 120. For example, five regions can be selected as the four corners and the center of the substrate 102.

[0037] An example of a measuring device is the Seiko Instruments SFT9450 X-ray fluorescence analyzer, which is equipped with both a semiconductor detector and a proportional counter as detectors, and a 0.1 mm diameter collimator. Using this device, the thickness of the intermediate layer 120 is measured according to the method described above, under conditions of a tube current of 1500 μA and a measurement time of 30 seconds.

[0038] Subsequently, the substrate 102-1 and the first intermediate layer 120 formed thereon are subjected to heat treatment to diffuse the first element contained in the substrate 102-1 into the first intermediate layer 120. The heat treatment can be performed at a temperature set from a range of, for example, 100°C or higher, 200°C or higher, 250°C or higher, or 350°C or higher, and 700°C or lower, 600°C or lower, or 550°C or lower. This temperature range may also be 100°C to 700°C, 200°C to 700°C, 250°C to 600°C, or 350°C to 550°C. Depending on the heating temperature, the heating time may be, for example, 10 minutes or more, 15 minutes or more, or 30 minutes or more, and 5 hours or less, or 2 hours or less. A typical heating time is 1 hour. The heating time may also be 10 minutes to 5 hours, 15 minutes to 5 hours, or 30 minutes to 2 hours. When heating the substrate 102 at a temperature higher than its heat resistance temperature (glass transition temperature, or melting point), it is preferable to perform the heat treatment for a short time, approximately 1 to 30 seconds. Through this heat treatment, the first intermediate layer 120 is converted into a first metal element and a second intermediate layer 122 containing the first element (Figure 7, S2). At least a portion of the first metal element exists as an oxide. The substrate 102-1 and the first intermediate layer 120 are converted into substrate 102-2 and the second intermediate layer 122, respectively, by mutual diffusion.

[0039] Next, the metal film 104-1 is formed on the second intermediate layer 122. The second intermediate layer 122 can be formed by methods such as electroless plating, sputtering, chemical vapor deposition (CVD) including metal-organic vapor deposition (MOCVD), or PVD methods such as vacuum deposition or electron beam deposition. The temperature at this time is room temperature (20°C to 25°C) or above room temperature, and can be 100°C or below, or 50°C or below (Figure 7, S3). The temperature during the formation of the metal film 104-1 may be above room temperature and below 100°C, or above room temperature and below 50°C.

[0040] After this, the metal film 104-1 is heated again to diffuse the first metal contained in the metal film 104-1 into the second intermediate layer 122. The temperature and time of the heating treatment can be appropriately selected from the range described above. At this time, the first element contained in the substrate 102 may further diffuse into the second intermediate layer 122. Through this heating treatment, the second intermediate layer 122 is converted into a diffusion layer 106 having the concentration profile described in the first embodiment (Figure 7, S4). The metal film 104-1 after interdiffusion with the second intermediate layer 122 is designated as the first metal film 104. Although not shown, a second metal film 108 may be formed on the first metal film 104. The second metal film 108 can be formed by sputtering, CVD, PVD, etc. Alternatively, the first metal film 104 may be used as a seed layer, and the second metal film 108 may be formed by supplying power to the first metal film 104.

[0041] When manufacturing a wiring board 100 having through holes 110, first, through holes 110 are made in the substrate 102 (Figure 8, S10). The through holes 110 can be formed by etching such as plasma etching or wet etching, laser irradiation, or mechanical processing such as sandblasting or ultrasonic drilling. If necessary, after forming the through holes 110, the substrate 102 may be treated with hydrofluoric acid to flatten the top and bottom surfaces of the substrate 102 and the side walls of the through holes 110.

[0042] After forming the through-hole 110, the first intermediate layer 120 is formed to cover the upper surface, lower surface, and side walls of the through-hole 110 of the substrate 102 (Figure 8, S11). Subsequently, the first intermediate layer 120 is converted into a second intermediate layer 122 by the heat treatment described above (Figure 8, S12), and a metal film 104-1 is formed on the second intermediate layer 122 (Figure 8, S13). After this, the second intermediate layer 122 is converted into a diffusion layer 106 by performing the heat treatment described above (Figure 9, S14).

[0043] Next, a second metal film 108 is formed on the upper and lower parts of the substrate 102. For example, as shown in S15 of Figure 9, a resist mask 124 is placed on the first metal film 104 so as to cover the area where the second metal film 108 is not provided. The resist mask 124 may be formed by applying and curing liquid resist, but since the substrate 102 has through holes 110, the resist mask 124 can be efficiently formed by attaching a film-like resist to the upper and lower surfaces of the substrate 102, and then performing exposure and development.

[0044] Next, power is supplied to the first metal film 104 to perform electroplating. This forms a second metal film 108 on the first metal film 104 exposed from the resist mask 124 (Figure 9, S16). After this, the resist mask 124 is removed (Figure 10, S17), and the first metal film 104 and diffusion layer 106 exposed from the second metal film 108 are removed by etching (Figure 10, S18). Etching can be performed using an etchant containing an acid such as sulfuric acid. Through the above process, a wiring board 100 having through holes 110 can be manufactured. A detailed explanation is omitted, but the through holes 110 may be formed after the first metal film 104 is formed, or after the second metal film 108 is formed.

[0045] As described above, the diffusion layer 106 of this disclosure exhibits an etching rate similar to that of the first metal film 104. Therefore, side etching of the diffusion layer 106 does not occur, or occurs very slowly, during the etching process (S18) of the first metal film 104. Consequently, a sufficient contact area can be provided between the first metal film 104 and the substrate 102 via the diffusion layer 106. As a result, peeling of the first metal film 104 and the second metal film 108 can be effectively prevented.

[0046] (Third embodiment) In this embodiment, a semiconductor device utilizing the wiring board 100 described in the first and second embodiments will be described. Here, a semiconductor device utilizing the wiring board 100 obtained in step S18 of Figure 10 will be described as a typical example.

[0047] The semiconductor device 130 shown in Figure 11 has a main substrate 132 and a plurality of wiring substrates 100 (wiring substrates 100-1, 100-2, 100-3) stacked on it. There is no limit to the number of wiring substrates 100, and it is determined according to the performance required of the semiconductor device 130. Various semiconductor chips (memory devices, central processing units) and semiconductor elements (micro-electromechanical systems (MEMS), etc.) are connected to the main substrate 132. Figure 11 shows an example in which a central processing unit 133 is installed on the main substrate 132. As described in the first embodiment, the wiring substrate 100 functions as through-wiring and has a second metal film 108 and a first metal film 104 (hereinafter collectively referred to as connecting wiring 134) provided on the upper and lower surfaces of the substrate 102, and the connecting wiring 134 contributes to the vertical electrical connection in the semiconductor device 130. The connection wiring 134 on the bottommost wiring board 100-1 is electrically connected to terminals 138 on the main board 132 via bumps 136-1 through via holes or wiring placed between the interlayer insulating layers 142, 142. The connection wiring 134 on the top of wiring board 100-1 is electrically connected to wiring board 100-2 via bumps 136-2 through via holes or wiring placed between the interlayer insulating layers 139, 140. Similarly, wiring boards 100-2 and 100-3 are also electrically connected via bumps 136-3. The bumps 136 include metals such as indium, copper, or gold, or alloys such as solder.

[0048] As shown in Figure 12, the stacked wiring boards 100 may differ in size and shape from one another, and the number of wiring boards 100 stacked on the main board 132 may also vary. In the example shown in Figure 12, two wiring boards 100-4 and 100-5 are stacked in some areas, and three wiring boards 100-1, 100-2, and 100-3 are stacked in other areas.

[0049] The semiconductor device 160 shown in Figure 13 has a structure in which multiple semiconductor chips 162-1 and 162-2 are stacked on a main substrate 132 via a wiring board 100. Terminals 164 and 166 are formed on semiconductor chips 162-1 and 162-2, respectively, and these are electrically connected to the connection wiring 134 of the wiring board 100-1 via bumps 168. Examples of semiconductor chips include semiconductor chip 162-1 as a driver chip and semiconductor chip 162-2 as a memory chip. In this way, semiconductor chips 162-1 and 162-2 are electrically connected to each other. Alternatively, semiconductor chip 162-2 and the main substrate 132 may be electrically connected by wire wiring 170. In Figures 11 to 13, the connection wiring 134 is shown to be directly connected to bumps 136 and 168, but other wiring such as lead wiring may be provided between the bumps 136 and 168 and the connection wiring 134. [Examples]

[0050] 1. Example 1 This embodiment describes the results of an analysis of the elements contained in the wiring board 100 manufactured according to the manufacturing method described in the second embodiment.

[0051] The structure of the wiring board 100 is shown in Figure 1(A), and the specific manufacturing method was as follows: A first intermediate layer 120 (thickness 15 nm) was formed by creating a film containing zinc oxide on a glass substrate (30 cm × 40 cm, thickness 0.5 mm, surface roughness 5 nm) using the sol-gel method. Then, the first intermediate layer 120 was converted into a second intermediate layer 122 by heating at 550°C for 1 hour. Subsequently, a copper film (thickness 0.5 μm) was formed on the second intermediate layer 122 as the first metal film 104 by applying an electroless plating method. Then, the second intermediate layer 122 was converted into a diffusion layer 106 by heating again at 450°C for 1 hour.

[0052] For comparative examples, samples were also prepared using three substrates with surface roughnesses of 5 nm, 200 nm, and 1 μm (1000 nm), in which the first metal film 104 was directly formed on the substrate without forming the first intermediate layer 120. These samples correspond to samples 8 to 10 in Table 1, described later, and are samples that do not have a diffusion layer 106.

[0053] Elemental analysis was performed by exposing the cross-section of the heated wiring board 100 by processing it using a FIB, and then performing elemental analysis from the substrate 102 side using EDX, scanning the interfaces between each layer. The obtained characteristic X-ray intensity was converted into atomic composition ratio, and the elemental distribution in the depth direction was evaluated. As the measurement device, a transmission electron microscope (Hitachi High-Technologies, model number: HD-2700) equipped with an elemental analyzer was used. An electron beam with a beam diameter of approximately 0.2 nm was irradiated onto the wiring board 100 with an acceleration voltage of 200 kV, and the generated characteristic X-rays were detected using a Si drift detector. The elemental analyzer used was a Horiba EMAX Evolution. The energy resolution was approximately 130 eV, the X-ray extraction angle was 24.8°, and the solid angle was 2.2 sr. The number of acquisition points was 100, and the acquisition time for each point was 1 second.

[0054] The EDX analysis results are shown in Figure 14. Figure 14 shows the changes in the concentrations of zinc, silicon, and copper with respect to the depth of the wiring substrate 100. As shown in Figure 14, zinc is virtually undetectable in the region from 0 nm to 35 nm and in the region deeper than 50 nm. Therefore, it can be seen that the interface 103 between the substrate 102 and the diffusion layer 106, and the interface 105 between the diffusion layer 106 and the first metal film 104 are located at depths of 35 nm and 50 nm, respectively. The plot of the zinc concentration contained in the diffusion layer 106 confirms that it shows a single peak in the diffusion layer 106.

[0055] Figure 14 shows that the concentration of silicon, the first element contained in the substrate 102, decreases as it approaches the first metal film 104 from the interface 103. Similarly, it can be seen that the concentration of copper contained in the first metal film 104 also decreases as it approaches the substrate 102 from the interface 105. From the above, it was confirmed that the diffusion layer 106 contains zinc, the first metal element, as well as silicon, the first element, and copper, the second metal element. Furthermore, in the diffusion layer 106, the concentration plots of silicon and copper against depth intersect each other. From this, it was found that in every region of the diffusion layer 106, in addition to the first metal element, at least one of the first and second metal elements is contained.

[0056] 2. Example 2 This embodiment shows the results of evaluating the effect of the diffusion layer 106 on the adhesive strength between the substrate 102 and the first metal film 104.

[0057] In Example 1, power was supplied to the first metal film 104 of the wiring board 100, and a copper film (3 μm thick) was formed as the second metal film 108 by electroplating. In this example, the thickness of the first intermediate layer 120 was set to 15 nm, and the heating temperature after the formation of the second metal film 108 was varied to evaluate the effect of the diffusion layer 106. Samples 8 to 10, i.e., wiring boards without the diffusion layer 106, were also evaluated as comparative examples.

[0058] The effect of the diffusion layer 106 on the adhesion between the first metal film 104 and the substrate 102 was evaluated by tape peel tests and etching tests. The former was evaluated by applying a polyimide-based adhesive tape (manufactured by Nitto Denko, model number: Heat-resistant insulating polyimide adhesive tape No. 360UL) to the second metal film 108, peeling off the adhesive tape, and visually observing the adhesive tape. The latter was performed by etching the wiring board 100 and visually checking for delamination of the first metal film 104 and the second metal film 108 during etching. Etching was performed using 1% ammonium persulfate as the etchant at 23°C for 1 minute.

[0059] The results are shown in Table 1. As shown in Table 1, when using the diffusion layer 106 having the structure shown in this disclosure, if the heating temperature after the formation of the second metal film 108 is 250°C or higher (samples 3 to 7), peeling was not observed in the tape peel test, and it was found that the first metal film 104 and the second metal film 108 remained on the substrate 102. Furthermore, if the heating temperature is 350°C or higher (samples 4 to 7), peeling was not observed in either the tape peel test or the etching test. On the other hand, in the comparative example without the diffusion layer 106 (sample 8), i.e., when the first intermediate layer 120 was not formed on the substrate 102, peeling was observed in the tape peel test even when the heating temperature after the formation of the second metal film 108 was 450°C. These results clearly demonstrate that, without the diffusion layer 106 of this disclosure, the adhesion between the first metal film 104 and the substrate 102 is weak, and the first metal film 104 and the second metal film 108 easily peel off from the substrate 102. In contrast, by providing the diffusion layer 106 of this disclosure, metal wiring can be formed on the substrate 102 with strong adhesive force.

[0060] Here, as the surface roughness of the substrate increases, an anchoring effect occurs, which usually improves adhesion with the metal film formed on it. However, even when the surface roughness of the substrate 102 was 200 nm, delamination was observed in the tape peel test (sample 9), and the results of sample 10 confirmed that a rough surface of 1000 nm is necessary when the diffusion layer 106 is not provided. However, when a diffusion layer 106 as thick as 1000 nm is provided, microfabrication becomes difficult as described above, and it becomes significantly disadvantageous, for example, when forming wiring with a line-space (L / S) of 10 μm / 10 μm. Therefore, by using the diffusion layer 106 of this disclosure, it becomes possible to form microfabricated wiring on a substrate with a surface roughness such that the anchoring effect is not expected, that is, on a substrate with extremely high surface flatness. This contributes to the manufacture of wiring substrates such as high-frequency circuit boards that require high flatness of wiring.

[0061] [Table 1]

[0062] The embodiments described above as embodiments of this disclosure may be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design modifications made by a person skilled in the art based on these embodiments are also included within the scope of this disclosure, as long as they retain the essence of this disclosure.

[0063] Furthermore, any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally understood to be brought about by this disclosure. [Explanation of Symbols]

[0064] 100: Wiring board, 100-1: Wiring board, 100-2: Wiring board, 100-3: Wiring board, 100-4: Wiring board, 100-5: Wiring board, 102: Substrate, 102-1: Substrate, 102-2: Substrate, 102a: Concentration of the first element, 103: Interface, 104: First metal film, 104-1: Metal film, 104a: Concentration of the second metal element, 105: Interface, 106: Diffusion layer, 106a: Concentration of the first metal element, 106b: Region, 106c: Region, 108: Second metal film, 110: Through hole, 112: Filling Material, 120: First intermediate layer, 122: Second intermediate layer, 124: Resist mask, 130: Semiconductor device, 132: Main board, 133: Central processing unit, 134: Connection wiring, 136: Bump, 136-1: Bump, 136-2: Bump, 136-3: Bump, 138: Terminal, 140: Interlayer insulating layer, 141: Interlayer insulating layer, 150: Semiconductor device, 160: Semiconductor device, 162-1: Semiconductor chip, 162-2: Semiconductor chip, 164: Terminal, 166: Terminal, 168: Bump, 170: Wire wiring

Claims

1. Silicon-containing substrate, A diffusion layer containing a first metal element is in contact with the substrate, and The first metal film, which is in contact with the diffusion layer and contains a second metal element, The diffusion layer comprises silicon, the first metal element, and the second metal element. The substrate has through holes, A portion of the upper surface of the substrate and / or a portion of the lower surface of the substrate are exposed from the diffusion layer and the first metal film. The diffusion layer and the first metal film are a wiring substrate that covers the side wall of the through hole.

2. The wiring substrate according to claim 1, wherein the first metallic element is titanium.

3. The present invention further comprises a second metal film located on the first metal film and in contact with the first metal film, The wiring board according to claim 1, wherein the second metal film covers the side wall of the through hole.

4. The wiring board according to claim 3, wherein a portion of the upper surface and / or a portion of the lower surface of the substrate are exposed from the second metal film.

5. The concentration of the second metal element in the diffusion layer decreases as it approaches the substrate in the thickness direction. The wiring substrate according to claim 1, wherein the concentration of silicon in the diffusion layer decreases as it approaches the first metal film in the thickness direction.

6. The wiring substrate according to claim 5, wherein in the diffusion layer, there exists a region where the plot of the concentration of the second metal element against the thickness of the diffusion layer intersects with the plot of the concentration of silicon against the thickness.

7. The wiring board according to claim 1, wherein the second metallic element is selected from copper, titanium, chromium, nickel, and gold.

8. The wiring substrate according to claim 1, wherein the first metal element exists as an oxide in the diffusion layer.

9. The wiring substrate according to claim 1, wherein the substrate is selected from a glass substrate, a quartz substrate, a semiconductor substrate, and a ceramic substrate.

10. The diffusion layer and the first metal film are located on the insulating layer and have openings that overlap with the through holes, and The wiring board according to claim 1, further comprising a first wiring located at the opening.

11. The wiring board according to claim 10, further comprising a second wiring that is electrically connected to the first wiring on the first wiring.

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